add IPL

IPL/Customer/Mobis/V4H_Cx_Loader/Makefile

@@ -0,0 +1,593 @@
+#*******************************************************************************
+# DISCLAIMER
+# This software is supplied by Renesas Electronics Corporation and is only
+# intended for use with Renesas products. No other uses are authorized. This
+# software is owned by Renesas Electronics Corporation and is protected under
+# all applicable laws, including copyright laws.
+# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+# Renesas reserves the right, without notice, to make changes to this software
+# and to discontinue the availability of this software. By using this software,
+# you agree to the additional terms and conditions found by accessing the
+# following link:
+# http://www.renesas.com/disclaimer
+# Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+#******************************************************************************/
+
+
+
+# ******************************************************************************
+# * DESCRIPTION   : makefile for Loader
+# ******************************************************************************
+# ******************************************************************************
+# * @file          Makefile
+# * - Version      : 0.14
+# * @brief
+# * .
+# ******************************************************************************
+# ******************************************************************************
+# * History : DD.MM.YYYY Version  Description
+# *         : 02.02.2022 0.01     First Release
+# *         : 17.02.2022 0.02     Support AArch32
+# *         : 23.03.2022 0.03     Removed unnecessary functions
+# *         : 09.05.2022 0.04     Used the standard library
+# *                               Renamed the image
+# *                               Added make option "LSI"
+# *                               Removed make option "AArch"
+# *                               Changed to make common things common in LSI
+# *         : 17.06.2022 0.05     Support secure boot for S4
+# *         : 02.08.2022 0.06     Support WDT
+# *         : 07.11.2022 0.07     Support DDR initialization/QOS initialization processing
+# *         : 14.12.2022 0.08     Fixed make option "EMMC_TRANS_MODE"
+# *                               Support MMU
+# *         : 15.12.2022 0.09     Support RegionID check
+# *                               Fixed "LSI" default settings
+# *         : 04.04.2023 0.10     Fixed not used standerd library.
+# *         : 21.08.2023 0.11     Add support for V4M.
+# *         : 04.09.2023 0.12     Add C4 power domain setting.
+# *         : 19.12.2024 0.13     Add build option "RTOS_LOAD_NUM"
+# *                               Add build option "ECM_ERROR_ENABLE"
+# *                               and "ECMERRTGTR_INTC".
+# *         : 26.05.2025 0.14     Add build option "OPTEE_LOAD_ENABLE"
+# ******************************************************************************
+
+###################################################
+# makefile
+###################################################
+
+define add_define
+DEFINES			+=	-D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+INCLUDE_DIR	=	-Iinclude
+
+OUTDIR		:=	build
+
+# LSI setting common define
+RCAR_S4:=0
+RCAR_V4H:=1
+RCAR_V4M:=2
+NORMAL:=0
+SECURE:=1
+HS400:=0
+HS200:=1
+HIGH_SPEED:=2
+NO_HIGH_SPEED:=3
+$(eval $(call add_define,RCAR_S4))
+$(eval $(call add_define,RCAR_V4H))
+$(eval $(call add_define,RCAR_V4M))
+$(eval $(call add_define,NORMAL))
+$(eval $(call add_define,SECURE))
+$(eval $(call add_define,HS400))
+$(eval $(call add_define,HS200))
+$(eval $(call add_define,HIGH_SPEED))
+$(eval $(call add_define,NO_HIGH_SPEED))
+ifneq ("$(FORCE_115200)", "")
+$(eval $(call add_define,FORCE_115200))
+endif
+$(eval $(call add_define,MOBIS_PRK3))
+
+#/* Select LSI("S4" or "V4H" or "V4M")***********************
+ifeq ("$(LSI)", "")
+LSI = S4
+endif
+
+ifeq (${LSI},S4)
+  RCAR_LSI:=${RCAR_S4}
+  #output file name
+  FILE_NAME	=	ca55_loader
+else ifeq (${LSI},V4H)
+  RCAR_LSI:=${RCAR_V4H}
+  #output file name
+  FILE_NAME	=	cr52_loader
+else ifeq (${LSI},V4M)
+  RCAR_LSI:=${RCAR_V4M}
+  #output file name
+  FILE_NAME	=	cr52_loader
+else
+  $(error "Error: ${LSI} is not supported.")
+endif
+$(eval $(call add_define,RCAR_LSI))
+
+ifndef BOOT_MODE
+  BOOT_MODE:=${NORMAL}
+else
+  ifeq (${BOOT_MODE},NORMAL)
+    BOOT_MODE:=${NORMAL}
+  else ifeq (${BOOT_MODE},SECURE)
+    BOOT_MODE:=${SECURE}
+    ifeq (${LSI},S4)
+      $(eval $(call add_define,TARGET_CORTEX_A))
+      $(eval $(call add_define,TARGET_DEVICE_S4X))
+      $(eval $(call add_define,AARCH64))
+    else ifeq (${LSI},V4H)
+      $(eval $(call add_define,TARGET_DEVICE_V4H))
+    else ifeq (${LSI},V4M)
+      $(eval $(call add_define,TARGET_DEVICE_V4M))
+    endif
+  else
+    $(error "Error: ${BOOT_MODE} is not supported.")
+  endif
+  $(eval $(call add_define,BOOT_MODE))
+endif
+
+ifndef EMMC_TRANS_MODE
+  EMMC_TRANS_MODE:=${HS400}
+else
+  ifeq (${EMMC_TRANS_MODE},HS400)
+    EMMC_TRANS_MODE:=${HS400}
+  else ifeq (${EMMC_TRANS_MODE},HS200)
+    EMMC_TRANS_MODE:=${HS200}
+  else ifeq (${EMMC_TRANS_MODE},HIGH_SPEED)
+    EMMC_TRANS_MODE:=${HIGH_SPEED}
+  else ifeq (${EMMC_TRANS_MODE},NO_HIGH_SPEED)
+    EMMC_TRANS_MODE:=${NO_HIGH_SPEED}
+  else
+    $(error "Error: ${EMMC_TRANS_MODE} is not supported.")
+  endif
+  $(eval $(call add_define,EMMC_TRANS_MODE))
+endif
+
+# Process RCAR_DRAM_SPLIT flag (V4H only)
+ifeq (${LSI},V4H)
+  ifndef RCAR_DRAM_SPLIT
+  RCAR_DRAM_SPLIT := 1
+  $(eval $(call add_define,RCAR_DRAM_SPLIT))
+  else
+    ifeq (${RCAR_DRAM_SPLIT},0)
+      $(eval $(call add_define,RCAR_DRAM_SPLIT))
+    else ifeq (${RCAR_DRAM_SPLIT},1)
+      $(eval $(call add_define,RCAR_DRAM_SPLIT))
+    else
+      $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.")
+    endif
+  endif
+else ifeq (${LSI},V4M)
+  ifndef RCAR_DRAM_SPLIT
+  RCAR_DRAM_SPLIT := 0
+  $(eval $(call add_define,RCAR_DRAM_SPLIT))
+  else
+    ifneq (${RCAR_DRAM_SPLIT},0)
+      $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.")
+    endif
+  endif
+endif
+
+# Process RCAR_PERIODIC_WRITE_TRAINING flag
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef RCAR_PERIODIC_WRITE_TRAINING
+  RCAR_PERIODIC_WRITE_TRAINING := 1
+  $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
+  else
+    ifeq (${RCAR_PERIODIC_WRITE_TRAINING},0)
+      $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
+    else ifeq (${RCAR_PERIODIC_WRITE_TRAINING},1)
+      $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
+    else
+      $(error "Error:RCAR_PERIODIC_WRITE_TRAINING=${RCAR_PERIODIC_WRITE_TRAINING} is not supported.")
+    endif
+  endif
+endif
+
+# Process RCAR_PERIODIC_READ_TRAINING flag
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef RCAR_PERIODIC_READ_TRAINING
+  RCAR_PERIODIC_READ_TRAINING := 1
+  $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
+  else
+    ifeq (${RCAR_PERIODIC_READ_TRAINING},0)
+      $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
+    else ifeq (${RCAR_PERIODIC_READ_TRAINING},1)
+      $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
+    else
+      $(error "Error:RCAR_PERIODIC_READ_TRAINING=${RCAR_PERIODIC_READ_TRAINING} is not supported.")
+    endif
+  endif
+endif
+
+# Process DBSC_REFINTS flag
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef DBSC_REFINTS
+  DBSC_REFINTS := 0
+  $(eval $(call add_define,DBSC_REFINTS))
+  else
+    ifeq (${DBSC_REFINTS},0)
+      $(eval $(call add_define,DBSC_REFINTS))
+    else ifeq (${DBSC_REFINTS},1)
+      $(eval $(call add_define,DBSC_REFINTS))
+    else
+      $(error "Error:DBSC_REFINTS=${DBSC_REFINTS} is not supported.")
+    endif
+  endif
+endif
+
+# Process RTVRAM_EXTEND flag
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef RTVRAM_EXTEND
+  RTVRAM_EXTEND := 1
+  $(eval $(call add_define,RTVRAM_EXTEND))
+  else
+    ifeq (${RTVRAM_EXTEND},0)
+      $(eval $(call add_define,RTVRAM_EXTEND))
+    else ifeq (${RTVRAM_EXTEND},1)
+      $(eval $(call add_define,RTVRAM_EXTEND))
+    else
+      $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.")
+    endif
+  endif
+endif
+
+# timing measurement
+ifeq ("$(MEASURE_TIME)", "")
+    MEASURE_TIME = 0
+else
+    $(eval $(call add_define,MEASURE_TIME))
+    # Set log level to Error, so we dont waste time with unnecessary prints
+    LOG_LEVEL := 1
+    OBJ_FILE	+= \
+		common/scmt_checkpoint.o    \
+		common/timer/scmt.o
+endif
+
+# Process BL2_LOAD_ENABLE flag
+ifeq (${LSI},V4H)
+  ifndef BL2_LOAD_ENABLE
+  BL2_LOAD_ENABLE := 1
+  $(eval $(call add_define,BL2_LOAD_ENABLE))
+  else
+    ifeq (${BL2_LOAD_ENABLE},0)
+      $(eval $(call add_define,BL2_LOAD_ENABLE))
+    else ifeq (${BL2_LOAD_ENABLE},1)
+      $(eval $(call add_define,BL2_LOAD_ENABLE))
+    else
+      $(error "Error:BL2_LOAD_ENABLE=${BL2_LOAD_ENABLE} is not supported.")
+    endif
+  endif
+endif
+
+# Process QNX_OS_LOAD_ENABLE flag
+ifeq (${LSI},V4H)
+  ifndef QNX_OS_LOAD_ENABLE
+  QNX_OS_LOAD_ENABLE := 1
+  $(eval $(call add_define,QNX_OS_LOAD_ENABLE))
+  else
+    ifeq (${QNX_OS_LOAD_ENABLE},0)
+      $(eval $(call add_define,QNX_OS_LOAD_ENABLE))
+    else ifeq (${QNX_OS_LOAD_ENABLE},1)
+      $(eval $(call add_define,QNX_OS_LOAD_ENABLE))
+    else
+      $(error "Error:QNX_OS_LOAD_ENABLE=${QNX_OS_LOAD_ENABLE} is not supported.")
+    endif
+  endif
+endif
+
+# Process RTOS_LOAD_NUM flag
+# 1:RTOS#0 only 3:RTOS#0,#1,#2
+ifndef RTOS_LOAD_NUM
+  RTOS_LOAD_NUM := 1
+  $(eval $(call add_define,RTOS_LOAD_NUM))
+else
+  ifeq (${RTOS_LOAD_NUM},1)
+    $(eval $(call add_define,RTOS_LOAD_NUM))
+  else ifeq (${RTOS_LOAD_NUM},3)
+      $(eval $(call add_define,RTOS_LOAD_NUM))
+  else
+    $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.")
+  endif
+endif
+
+# Process OPTEE_LOAD_ENABLE flag
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef OPTEE_LOAD_ENABLE
+  OPTEE_LOAD_ENABLE := 1
+  $(eval $(call add_define,OPTEE_LOAD_ENABLE))
+  else
+    ifeq (${OPTEE_LOAD_ENABLE},0)
+      $(eval $(call add_define,OPTEE_LOAD_ENABLE))
+    else ifeq (${OPTEE_LOAD_ENABLE},1)
+      $(eval $(call add_define,OPTEE_LOAD_ENABLE))
+    else
+      $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
+    endif
+  endif
+endif
+
+OUTPUT_FILE	=	$(FILE_NAME).elf
+
+# object file name
+OBJ_FILE	+=	common/string.o  \
+      common/log/log.o	\
+			common/log/scif.o		\
+			common/timer/generic_timer.o	\
+			image_load/image_load.o	\
+			ip/ip_control.o			\
+			ip/emmc/emmc_boot.o		\
+			ip/emmc/emmc_cmd.o		\
+			ip/emmc/emmc_init.o		\
+			ip/emmc/emmc_interrupt.o	\
+			ip/emmc/emmc_mount.o	\
+			ip/emmc/emmc_multiboot.o	\
+			ip/emmc/emmc_read.o		\
+			ip/emmc/emmc_utility.o	\
+			loader/stack.o			\
+			loader/loader_main.o    \
+            ip/interrupt.o
+
+ifeq (${BOOT_MODE},SECURE)
+OBJ_FILE	+=	secure/secure_boot.o	\
+            secure/src/comm_drv/icum_d_comm_pe.o  \
+            secure/src/icumif_lib/r_icumif.o      \
+            secure/shared/src/mem_info_def.o      \
+            secure/user_api/user_icumif_api.o
+
+INCLUDE_DIR	+=	-Isecure/src/comm_drv -Isecure/src/icumif_lib -Isecure/icumif -Isecure/include -Isecure/user_api -Isecure/shared/src
+
+endif
+
+ifeq (${LSI},S4)
+  OBJ_FILE += \
+            loader/loader_s4.o      \
+			ip/swdt/swdt.o          \
+			loader/loader_mmu_table.o             \
+            loader/loader_exceptions.o
+  #linker script name
+  MEMORY_DEF = loader/loader_s4.ld
+else ifeq (${LSI},V4H)
+  OBJ_FILE += \
+            cpu_on/cpu_on.o        \
+            ip/qos/qos.o           \
+            cnf_tbl/cnf_tbl_v4h.o  \
+            ip/rtvram/rtvram.o     \
+            loader/loader_v4h.o    \
+            loader/loader_main_common.o           \
+            protect/region_id/region_id.o         \
+            cnf_tbl/rgidcnf_tbl_v4h.o             \
+            ip/ddr/v4h/lpddr5/ecc_enable_v4h.o    \
+            ip/ddr/v4h/lpddr5/ecm_enable_v4h.o
+  #linker script name
+  MEMORY_DEF = loader/loader_v4h.ld
+
+  INCLUDE_DIR	+=	-Iip/ddr
+else ifeq (${LSI},V4M)
+  OBJ_FILE += \
+            cpu_on/cpu_on.o        \
+            ip/qos/qos.o           \
+            cnf_tbl/cnf_tbl_v4m.o  \
+            ip/rtvram/rtvram.o     \
+            loader/loader_v4m.o    \
+            loader/loader_main_common.o           \
+            protect/region_id/region_id.o         \
+            cnf_tbl/rgidcnf_tbl_v4m.o             \
+            ip/ddr/v4m/lpddr5/ecc_enable_v4m.o    \
+            ip/ddr/v4m/lpddr5/ecm_enable_v4m.o
+  #linker script name
+  MEMORY_DEF = loader/loader_v4m.ld
+
+  INCLUDE_DIR	+=	-Iip/ddr
+
+endif
+
+###################################################
+# Process access protection flag
+# 0:Disable 1:Enable
+ifndef ACC_PROT_ENABLE
+ACC_PROT_ENABLE := 0
+$(eval $(call add_define,ACC_PROT_ENABLE))
+else
+  ifeq (${ACC_PROT_ENABLE},0)
+    $(eval $(call add_define,ACC_PROT_ENABLE))
+  else ifeq (${ACC_PROT_ENABLE},1)
+    $(eval $(call add_define,ACC_PROT_ENABLE))
+  else
+    $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.")
+  endif
+endif
+
+# Debug build
+DEBUG:=0
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+  $(eval $(call add_define,NDEBUG))
+else
+  CFLAGS			+= 	-g
+  ASFLAGS			+= 	-g -Wa,--gdwarf-2
+endif
+
+# booting performance check
+ifeq ("$(BOOT_TIME_CHECK)", "")
+BOOT_TIME_CHECK = 0
+endif
+$(eval $(call add_define,BOOT_TIME_CHECK))
+ifneq (${BOOT_TIME_CHECK},0)
+OBJ_FILE	+=	ip/gpio/gpio.o
+endif
+
+# Process LOG_LEVEL
+ifndef LOG_LEVEL
+LOG_LEVEL := 2
+endif
+$(eval $(call add_define,LOG_LEVEL))
+
+# Process ECC_ENABLE
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  ifndef ECC_ENABLE
+    ECC_ENABLE:= 0
+    $(eval $(call add_define,ECC_ENABLE))
+  else
+    ifeq (${ECC_ENABLE},0)
+      $(eval $(call add_define,ECC_ENABLE))
+    else ifeq (${ECC_ENABLE},1)
+      $(eval $(call add_define,ECC_ENABLE))
+    else
+      $(error "Error: ECC_ENABLE=${ECC_ENABLE} is not supported.")
+    endif
+  endif
+endif
+
+# Process ECM_ERROR_ENABLE flag
+ifndef ECM_ERROR_ENABLE
+  ECM_ERROR_ENABLE := 1
+  $(eval $(call add_define,ECM_ERROR_ENABLE))
+else
+  ifeq (${ECM_ERROR_ENABLE},0)
+    $(eval $(call add_define,ECM_ERROR_ENABLE))
+  else ifeq (${ECM_ERROR_ENABLE},1)
+      $(eval $(call add_define,ECM_ERROR_ENABLE))
+  else
+    $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.")
+  endif
+endif
+
+# Process ECMERRTGTR_INTC flag
+ifndef ECMERRTGTR_INTC
+  ECMERRTGTR_INTC := 1
+  $(eval $(call add_define,ECMERRTGTR_INTC))
+else
+  ifeq (${ECMERRTGTR_INTC},0)
+    $(eval $(call add_define,ECMERRTGTR_INTC))
+  else ifeq (${ECMERRTGTR_INTC},1)
+      $(eval $(call add_define,ECMERRTGTR_INTC))
+  else
+    $(error "Error:ECMERRTGTR_INTC=${ECMERRTGTR_INTC} is not supported.")
+  endif
+endif
+
+ifeq ($(filter ${LSI},V4H V4M),${LSI})
+  include ip/ddr/ddr.mk
+endif
+
+# Process DBSC HUNGUP WA
+ifndef WA_OTLINT5579
+  WA_OTLINT5579:= 1
+endif
+$(eval $(call add_define,WA_OTLINT5579))
+
+# Private Option for QoS and DBSC
+RCAR_PERIODIC_TRAINING_SEPARATE_MODE:= 0
+$(eval $(call add_define,RCAR_PERIODIC_TRAINING_SEPARATE_MODE))
+
+###################################################
+
+OUTDIR_REL			:= $(OUTDIR)/release
+OUTDIR_OBJ			:= $(OUTDIR)/obj
+
+OBJ_FILE			:= $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
+
+CC			= $(CROSS_COMPILE)gcc
+CPP			= ${CROSS_COMPILE}cpp
+AS			= ${CROSS_COMPILE}gcc
+AR			= ${CROSS_COMPILE}ar
+LD			= $(CROSS_COMPILE)ld
+OC			= ${CROSS_COMPILE}objcopy
+OD			= ${CROSS_COMPILE}objdump
+
+ifeq (${LSI},S4)
+ASFLAGS		+=	-march=armv8.2-a
+CFLAGS		+=	-march=armv8.2-a \
+			-O0
+else ifeq ($(filter ${LSI},V4H V4M),${LSI})
+ASFLAGS		+=	-march=armv8-r
+CFLAGS		+=	-march=armv8-r   \
+			-O2
+endif
+
+ASFLAGS     += -ffreestanding -Wa,--fatal-warnings	\
+			-Wmissing-include-dirs			\
+			 -c -D__ASSEMBLY				\
+			$(INCLUDE_DIR) $(DEFINES)
+
+CFLAGS		+= -ffreestanding -Wall			\
+			-Wmissing-include-dirs			\
+			-std=c99 -c					\
+			-D__CX_IPL__ \
+			$(INCLUDE_DIR) $(DEFINES)
+
+#LDFLAGS		=	--fatal-warnings -O1 -nostdlib
+LDFLAGS		=	--fatal-warnings -O1 -lm
+
+BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
+
+LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc
+LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc
+
+###################################################
+.SUFFIXES : .s .c .o
+
+###################################################
+# command
+
+.PHONY: all
+all: $(OUTPUT_FILE)
+
+###################################################
+# Linker
+###################################################
+$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
+	@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \
+		$(CC) $(CFLAGS) -xc - -o $(OUTDIR_OBJ)/build_message.o
+	@if [ ! -e "$(OUTDIR_REL)" ]; then mkdir "$(OUTDIR_REL)"; fi
+
+	$(V)$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o	\
+	  -T $(MEMORY_DEF)		\
+	  -o $(OUTDIR_REL)/$(OUTPUT_FILE)	\
+	  $(LDFLAGS)	\
+	  -Map $(OUTDIR_REL)/$(FILE_NAME).map	\
+	  $(LIBS)
+
+	$(V)$(OC) -O srec --srec-forceS3  $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).srec
+	$(V)$(OC) -O binary $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).bin
+	$(V)$(OD) -dx $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
+
+	@chmod 644 $(OUTDIR_REL)/$(FILE_NAME).*
+ifneq ("$(V)", "")
+	@echo "Build complete: $(OUTPUT_FILE)"
+	@echo "Output files:"
+	@echo "  - $(OUTDIR_REL)/$(FILE_NAME).srec"
+endif
+
+###################################################
+# Compile
+###################################################
+
+$(OUTDIR_OBJ)/%.o:%.c
+	@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
+	$(V)$(CC) $(CFLAGS) -o $@ -c $<
+
+$(OUTDIR_OBJ)/%.o:%.S
+	@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
+	$(V)$(AS) $(ASFLAGS) -o $@ -c $<
+
+
+.PHONY: clean
+clean:
+	@rm -rf $(OUTDIR)

IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c

@@ -0,0 +1,323 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Configuration table
+ ******************************************************************************/
+/******************************************************************************
+ * @file          cnf_tbl.c
+ * - Version      : 0.04
+ * @brief         Configuration table for V4H.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 28.07.2021 0.01     First Release
+ *         : 23.05.2022 0.02     Integration of S4 and V4H
+ *                               Renamed from conf_tbl.c to cnf_tbl_v4h.c.
+ *         : 22.05.2023 0.03     Update the qos config table for response to past
+ *                               follow back.
+ *         : 08.06.2023 0.04     Update the qos config table for ISP and VSPX.
+ *****************************************************************************/
+
+#include <stdint.h>
+#if defined(__RH850G3K__)
+#include <cpg_register.h>
+#endif
+#include <cnf_tbl.h>
+
+#if defined(__RH850G3K__)
+#pragma ghs section rodata=".qosbw_tbl"
+#else
+__attribute__ ((section(".qoswt_tbl")))
+#endif
+const QOS_SETTING_TABLE g_qosbw_tbl[] = {
+    [0]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [1]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [2]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [3]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [4]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [5]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [6]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [7]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [8]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [9]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [10]  = {0x000C04010000FFFFULL,  0x0000000000000000ULL},
+    [11]  = {0x000C04080000FFFFULL,  0x00200030004FFC01ULL},
+    [12]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [13]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [14]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [15]  = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [16]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [17]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [18]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [19]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [20]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [21]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [22]  = {0x000C04100000FFFFULL,  0x0000000000000000ULL},
+    [23]  = {0x000C08140000FFFFULL,  0x00100030004FFC01ULL},
+    [24]  = {0x000C08140000FFFFULL,  0x00100030004FFC01ULL},
+    [25]  = {0x000000000000FFF0ULL,  0x0000000000000000ULL},
+    [26]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [27]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [28]  = {0x000C04100000FFFFULL,  0x0000000000000000ULL},
+    [29]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [30]  = {0x000C08140000FFFFULL,  0x00100030004FFC01ULL},
+    [31]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [32]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [33]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [34]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [35]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [36]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [37]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [38]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [39]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [40]  = {0x000C04010000FFFFULL,  0x001000F0004FFC01ULL},
+    [41]  = {0x000C04010000FFFFULL,  0x001000F0004FFC01ULL},
+    [42]  = {0x000C04010000FFFFULL,  0x002000F0004FFC01ULL},
+    [43]  = {0x000C04010000FFFFULL,  0x002000F0004FFC01ULL},
+    [44]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [45]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [46]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [47]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [48]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [49]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [50]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [51]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [52]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [53]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [54]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [55]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [56]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [57]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [58]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [59]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [60]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [61]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [62]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [63]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [64]  = {0x000C04200000FFFFULL,  0x00100030004FFC01ULL},
+    [65]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [66]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [67]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [68]  = {0x000C0C4F0000FFFFULL,  0x00100030004FFC01ULL},
+    [69]  = {0x000C0C4F0000FFFFULL,  0x00100030004FFC01ULL},
+    [70]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [71]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [72]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [73]  = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [74]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [75]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [76]  = {0x000C149E0000FFFFULL,  0x00100030004FFC01ULL},
+    [77]  = {0x000C149E0000FFFFULL,  0x00100030004FFC01ULL},
+    [78]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [79]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [80]  = {0x00140C050000FFFFULL,  0x00100030004FFC01ULL},
+    [81]  = {0x0014450E0000FFFFULL,  0x00100030004FFC01ULL},
+    [82]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [83]  = {0x0014289E0000FFFFULL,  0x00000000000FFC00ULL},
+    [84]  = {0x0014289E0000FFFFULL,  0x00000000000FFC00ULL},
+    [85]  = {0x0014149E0000FFFFULL,  0x0000000000000000ULL},
+    [86]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [87]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [88]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [89]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [90]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [91]  = {0x000C00000000FFFFULL,  0x001000F0004FFC01ULL},
+    [92]  = {0x000C00000000FFFFULL,  0x001000F0004FFC01ULL},
+    [93]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [94]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [95]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [96]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [97]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [98]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [99]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [100] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [101] = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [102] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [103] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [104] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [105] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [106] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [107] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [108] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [109] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [110] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [111] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [112] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [113] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [114] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [115] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [116] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [117] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [118] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [119] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [120] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [121] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [122] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [123] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [124] = {0x001404010000FFFFULL,  0x00100030004FFC01ULL}
+};
+
+
+/* Now go back to default rules */
+#if defined(__RH850G3K__)
+#pragma ghs section rodata=default
+
+#pragma ghs section rodata=".qoswt_tbl"
+#else
+__attribute__ ((section(".qosbw_tbl")))
+#endif
+const QOS_SETTING_TABLE g_qoswt_tbl[] = {
+    [0]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [1]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [2]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [3]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [4]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [5]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [6]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [7]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [8]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [9]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [10]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [11]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [12]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [13]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [14]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [15]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [16]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [17]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [18]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [19]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [20]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [21]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [22]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [23]  = {0x000C04050000FFFFULL,  0x0000000000000000ULL},
+    [24]  = {0x000C080C0000FFFFULL,  0x0000000000000000ULL},
+    [25]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [26]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [27]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [28]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [29]  = {0x000C04050000C001ULL,  0x0000000000000000ULL},
+    [30]  = {0x000C080C0000C001ULL,  0x0000000000000000ULL},
+    [31]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [32]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [33]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [34]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [35]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [36]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [37]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [38]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [39]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [40]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [41]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [42]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [43]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [44]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [45]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [46]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [47]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [48]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [49]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [50]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [51]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [52]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [53]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [54]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [55]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [56]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [57]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [58]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [59]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [60]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [61]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [62]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [63]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [64]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [65]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [66]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [67]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [68]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [69]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [70]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [71]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [72]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [73]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [74]  = {0x001424870000C001ULL,  0x0000000000000000ULL},
+    [75]  = {0x001424870000C001ULL,  0x0000000000000000ULL},
+    [76]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [77]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [78]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [79]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [80]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [81]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [82]  = {0x001424870000FFFFULL,  0x0000000000000000ULL},
+    [83]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [84]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [85]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [86]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [87]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [88]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [89]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [90]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [91]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [92]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [93]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [94]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [95]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [96]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [97]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [98]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [99]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [100] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [101] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [102] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [103] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [104] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [105] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [106] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [107] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [108] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [109] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [110] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [111] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [112] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [113] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [114] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [115] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [116] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [117] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [118] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [119] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [120] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [121] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [122] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [123] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [124] = {0x0000000000000000ULL,  0x0000000000000000ULL}
+};
+
+
+#if defined(__RH850G3K__)
+/* Now go back to default rules */
+#pragma ghs section rodata=default
+#endif

IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c

@@ -0,0 +1,318 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Configuration table
+ ******************************************************************************/
+/******************************************************************************
+ * @file          cnf_tbl_v4m.c
+ * - Version      : 0.01
+ * @brief         Configuration table for V4M.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 21.08.2023 0.01     First Release
+ *****************************************************************************/
+
+#include <stdint.h>
+#if defined(__RH850G3K__)
+#include <cpg_register.h>
+#endif
+#include <cnf_tbl.h>
+
+#if defined(__RH850G3K__)
+#pragma ghs section rodata=".qosbw_tbl"
+#else
+__attribute__ ((section(".qoswt_tbl")))
+#endif
+const QOS_SETTING_TABLE g_qosbw_tbl[] = {
+    [0]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [1]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [2]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [3]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [4]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [5]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [6]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [7]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [8]   = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [9]   = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [10]  = {0x000C04010000FFFFULL,  0x0000000000000000ULL},
+    [11]  = {0x000C04080000FFFFULL,  0x00200030004FFC01ULL},
+    [12]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [13]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [14]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [15]  = {0x000C04010000FFFFULL,  0x00200030004FFC01ULL},
+    [16]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [17]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [18]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [19]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [20]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [21]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [22]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [23]  = {0x000C08140000FFFFULL,  0x00100030004FFC01ULL},
+    [24]  = {0x0000000000000000ULL,  0x00100030004FFC01ULL},
+    [25]  = {0x000000000000FFF0ULL,  0x0000000000000000ULL},
+    [26]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [27]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [28]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [29]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [30]  = {0x000C08140000FFFFULL,  0x00100030004FFC01ULL},
+    [31]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [32]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [33]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [34]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [35]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [36]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [37]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [38]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [39]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [40]  = {0x000C04010000FFFFULL,  0x001000F0004FFC01ULL},
+    [41]  = {0x000C04010000FFFFULL,  0x001000F0004FFC01ULL},
+    [42]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [43]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [44]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [45]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [46]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [47]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [48]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [49]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [50]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [51]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [52]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [53]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [54]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [55]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [56]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [57]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [58]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [59]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [60]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [61]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [62]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [63]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [64]  = {0x000C04200000FFFFULL,  0x00100030004FFC01ULL},
+    [65]  = {0x000C04100000FFFFULL,  0x00100030004FFC01ULL},
+    [66]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [67]  = {0x000C144F0000FFFFULL,  0x00100030004FFC01ULL},
+    [68]  = {0x000C0C4F0000FFFFULL,  0x00100030004FFC01ULL},
+    [69]  = {0x000C0C4F0000FFFFULL,  0x00100030004FFC01ULL},
+    [70]  = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [71]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [72]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [73]  = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [74]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [75]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [76]  = {0x000C149E0000FFFFULL,  0x00100030004FFC01ULL},
+    [77]  = {0x000C149E0000FFFFULL,  0x00100030004FFC01ULL},
+    [78]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [79]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [80]  = {0x00140C050000FFFFULL,  0x00100030004FFC01ULL},
+    [81]  = {0x0014450E0000FFFFULL,  0x00100030004FFC01ULL},
+    [82]  = {0x001424870000FFFFULL,  0x00100030004FFC01ULL},
+    [83]  = {0x0014289E0000FFFFULL,  0x00000000000FFC00ULL},
+    [84]  = {0x0014289E0000FFFFULL,  0x00000000000FFC00ULL},
+    [85]  = {0x0014149E0000FFFFULL,  0x0000000000000000ULL},
+    [86]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [87]  = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [88]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [89]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [90]  = {0x001004080000FFFFULL,  0x0000000000000000ULL},
+    [91]  = {0x000C00000000FFFFULL,  0x001000F0004FFC01ULL},
+    [92]  = {0x000C00000000FFFFULL,  0x001000F0004FFC01ULL},
+    [93]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [94]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [95]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [96]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [97]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [98]  = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [99]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [100] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [101] = {0x001404080000FFFFULL,  0x00100030004FFC01ULL},
+    [102] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [103] = {0x000C04080000FFFFULL,  0x00100030004FFC01ULL},
+    [104] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [105] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [106] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [107] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [108] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [109] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [110] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [111] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [112] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [113] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [114] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [115] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [116] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [117] = {0x000000000000FFFFULL,  0x0000000000000000ULL},
+    [118] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [119] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [120] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [121] = {0x000C04010000FFFFULL,  0x001001D0004FFC01ULL},
+    [122] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [123] = {0x000C04010000FFFFULL,  0x00100030004FFC01ULL},
+    [124] = {0x001404010000FFFFULL,  0x00100030004FFC01ULL}
+};
+
+
+/* Now go back to default rules */
+#if defined(__RH850G3K__)
+#pragma ghs section rodata=default
+
+#pragma ghs section rodata=".qoswt_tbl"
+#else
+__attribute__ ((section(".qosbw_tbl")))
+#endif
+const QOS_SETTING_TABLE g_qoswt_tbl[] = {
+    [0]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [1]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [2]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [3]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [4]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [5]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [6]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [7]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [8]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [9]   = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [10]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [11]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [12]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [13]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [14]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [15]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [16]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [17]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [18]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [19]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [20]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [21]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [22]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [23]  = {0x000C04050000FFFFULL,  0x0000000000000000ULL},
+    [24]  = {0x000C080C0000FFFFULL,  0x0000000000000000ULL},
+    [25]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [26]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [27]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [28]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [29]  = {0x000C04050000C001ULL,  0x0000000000000000ULL},
+    [30]  = {0x000C080C0000C001ULL,  0x0000000000000000ULL},
+    [31]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [32]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [33]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [34]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [35]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [36]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [37]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [38]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [39]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [40]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [41]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [42]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [43]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [44]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [45]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [46]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [47]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [48]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [49]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [50]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [51]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [52]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [53]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [54]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [55]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [56]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [57]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [58]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [59]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [60]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [61]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [62]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [63]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [64]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [65]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [66]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [67]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [68]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [69]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [70]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [71]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [72]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [73]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [74]  = {0x001424870000C001ULL,  0x0000000000000000ULL},
+    [75]  = {0x001424870000C001ULL,  0x0000000000000000ULL},
+    [76]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [77]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [78]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [79]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [80]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [81]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [82]  = {0x001424870000FFFFULL,  0x0000000000000000ULL},
+    [83]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [84]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [85]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [86]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [87]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [88]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [89]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [90]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [91]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [92]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [93]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [94]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [95]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [96]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [97]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [98]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [99]  = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [100] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [101] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [102] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [103] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [104] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [105] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [106] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [107] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [108] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [109] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [110] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [111] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [112] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [113] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [114] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [115] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [116] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [117] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [118] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [119] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [120] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [121] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [122] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [123] = {0x0000000000000000ULL,  0x0000000000000000ULL},
+    [124] = {0x0000000000000000ULL,  0x0000000000000000ULL}
+};
+
+
+#if defined(__RH850G3K__)
+/* Now go back to default rules */
+#pragma ghs section rodata=default
+#endif

IPL/Customer/Mobis/V4H_Cx_Loader/common/crc32.c

@@ -0,0 +1,273 @@
+/*
+ * This file is derived from crc32.c from the zlib-1.1.3 distribution
+ * by Jean-loup Gailly and Mark Adler.
+ */
+
+/* crc32.c -- compute the CRC-32 of a data stream
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#ifdef USE_HOSTCC
+#include <arpa/inet.h>
+#include <u-boot/crc.h>
+#else
+// #include <common.h>
+#include <string.h>
+#endif
+// #include <compiler.h>
+#include <stddef.h>
+/* from u-boot's compiler_types.h */
+#define __inline__ inline
+
+/* from u-boot's linux/types.h */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+# define __force	__attribute__((force))
+#else
+#define __bitwise__
+# define __force
+#endif
+
+/* from u-boot's compiler.h */
+# define cpu_to_le32(x)		(x)
+# define le32_to_cpu(x)		(x)
+
+#include <stdint.h>
+/* from u-boot's asm-generic/int-ll64.h */
+typedef unsigned int __u32;
+
+/* from u-boot's linux/types.h */
+// typedef __u32 __bitwise __be32;
+#define __be32  __u32
+
+/* from u-boot's linux/byteorder/swab.h */
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+
+/* from u-boot's linux/byteorder/little_endian.h */
+#define __cpu_to_be32(x) ((__force __be32)__swab32((x)))
+
+/* from u-boot's generic.h */
+#undef htonl
+#define ___htonl(x) __cpu_to_be32(x)
+#define htonl(x) ___htonl(x)
+
+// #include <u-boot/crc.h>
+#include <crc.h>
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#include <watchdog.h>
+#endif
+
+#define tole(x) cpu_to_le32(x)
+
+#ifdef CONFIG_DYNAMIC_CRC_TABLE
+
+static int crc_table_empty = 1;
+static uint32_t crc_table[256];
+static void make_crc_table OF((void));
+
+/*
+  Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
+  x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
+
+  Polynomials over GF(2) are represented in binary, one bit per coefficient,
+  with the lowest powers in the most significant bit.  Then adding polynomials
+  is just exclusive-or, and multiplying a polynomial by x is a right shift by
+  one.  If we call the above polynomial p, and represent a byte as the
+  polynomial q, also with the lowest power in the most significant bit (so the
+  byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p,
+  where a mod b means the remainder after dividing a by b.
+
+  This calculation is done using the shift-register method of multiplying and
+  taking the remainder.  The register is initialized to zero, and for each
+  incoming bit, x^32 is added mod p to the register if the bit is a one (where
+  x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by
+  x (which is shifting right by one and adding x^32 mod p if the bit shifted
+  out is a one).  We start with the highest power (least significant bit) of
+  q and repeat for all eight bits of q.
+
+  The table is simply the CRC of all possible eight bit values.  This is all
+  the information needed to generate CRC's on data a byte at a time for all
+  combinations of CRC register values and incoming bytes.
+*/
+static void make_crc_table(void)
+{
+  uint32_t c;
+  int n, k;
+  uLong poly;		/* polynomial exclusive-or pattern */
+  /* terms of polynomial defining this crc (except x^32): */
+  static uint8_t p[] = {
+		0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
+
+  /* make exclusive-or pattern from polynomial (0xedb88320L) */
+  poly = 0L;
+  for (n = 0; n < sizeof(p)/sizeof(uint8_t); n++)
+    poly |= 1L << (31 - p[n]);
+
+  for (n = 0; n < 256; n++)
+  {
+    c = (uLong)n;
+    for (k = 0; k < 8; k++)
+      c = c & 1 ? poly ^ (c >> 1) : c >> 1;
+    crc_table[n] = tole(c);
+  }
+  crc_table_empty = 0;
+}
+#elif !defined(CONFIG_ARM64_CRC32)
+/* ========================================================================
+ * Table of CRC-32's of all single-byte values (made by make_crc_table)
+ */
+
+static const uint32_t crc_table[256] = {
+tole(0x00000000L), tole(0x77073096L), tole(0xee0e612cL), tole(0x990951baL),
+tole(0x076dc419L), tole(0x706af48fL), tole(0xe963a535L), tole(0x9e6495a3L),
+tole(0x0edb8832L), tole(0x79dcb8a4L), tole(0xe0d5e91eL), tole(0x97d2d988L),
+tole(0x09b64c2bL), tole(0x7eb17cbdL), tole(0xe7b82d07L), tole(0x90bf1d91L),
+tole(0x1db71064L), tole(0x6ab020f2L), tole(0xf3b97148L), tole(0x84be41deL),
+tole(0x1adad47dL), tole(0x6ddde4ebL), tole(0xf4d4b551L), tole(0x83d385c7L),
+tole(0x136c9856L), tole(0x646ba8c0L), tole(0xfd62f97aL), tole(0x8a65c9ecL),
+tole(0x14015c4fL), tole(0x63066cd9L), tole(0xfa0f3d63L), tole(0x8d080df5L),
+tole(0x3b6e20c8L), tole(0x4c69105eL), tole(0xd56041e4L), tole(0xa2677172L),
+tole(0x3c03e4d1L), tole(0x4b04d447L), tole(0xd20d85fdL), tole(0xa50ab56bL),
+tole(0x35b5a8faL), tole(0x42b2986cL), tole(0xdbbbc9d6L), tole(0xacbcf940L),
+tole(0x32d86ce3L), tole(0x45df5c75L), tole(0xdcd60dcfL), tole(0xabd13d59L),
+tole(0x26d930acL), tole(0x51de003aL), tole(0xc8d75180L), tole(0xbfd06116L),
+tole(0x21b4f4b5L), tole(0x56b3c423L), tole(0xcfba9599L), tole(0xb8bda50fL),
+tole(0x2802b89eL), tole(0x5f058808L), tole(0xc60cd9b2L), tole(0xb10be924L),
+tole(0x2f6f7c87L), tole(0x58684c11L), tole(0xc1611dabL), tole(0xb6662d3dL),
+tole(0x76dc4190L), tole(0x01db7106L), tole(0x98d220bcL), tole(0xefd5102aL),
+tole(0x71b18589L), tole(0x06b6b51fL), tole(0x9fbfe4a5L), tole(0xe8b8d433L),
+tole(0x7807c9a2L), tole(0x0f00f934L), tole(0x9609a88eL), tole(0xe10e9818L),
+tole(0x7f6a0dbbL), tole(0x086d3d2dL), tole(0x91646c97L), tole(0xe6635c01L),
+tole(0x6b6b51f4L), tole(0x1c6c6162L), tole(0x856530d8L), tole(0xf262004eL),
+tole(0x6c0695edL), tole(0x1b01a57bL), tole(0x8208f4c1L), tole(0xf50fc457L),
+tole(0x65b0d9c6L), tole(0x12b7e950L), tole(0x8bbeb8eaL), tole(0xfcb9887cL),
+tole(0x62dd1ddfL), tole(0x15da2d49L), tole(0x8cd37cf3L), tole(0xfbd44c65L),
+tole(0x4db26158L), tole(0x3ab551ceL), tole(0xa3bc0074L), tole(0xd4bb30e2L),
+tole(0x4adfa541L), tole(0x3dd895d7L), tole(0xa4d1c46dL), tole(0xd3d6f4fbL),
+tole(0x4369e96aL), tole(0x346ed9fcL), tole(0xad678846L), tole(0xda60b8d0L),
+tole(0x44042d73L), tole(0x33031de5L), tole(0xaa0a4c5fL), tole(0xdd0d7cc9L),
+tole(0x5005713cL), tole(0x270241aaL), tole(0xbe0b1010L), tole(0xc90c2086L),
+tole(0x5768b525L), tole(0x206f85b3L), tole(0xb966d409L), tole(0xce61e49fL),
+tole(0x5edef90eL), tole(0x29d9c998L), tole(0xb0d09822L), tole(0xc7d7a8b4L),
+tole(0x59b33d17L), tole(0x2eb40d81L), tole(0xb7bd5c3bL), tole(0xc0ba6cadL),
+tole(0xedb88320L), tole(0x9abfb3b6L), tole(0x03b6e20cL), tole(0x74b1d29aL),
+tole(0xead54739L), tole(0x9dd277afL), tole(0x04db2615L), tole(0x73dc1683L),
+tole(0xe3630b12L), tole(0x94643b84L), tole(0x0d6d6a3eL), tole(0x7a6a5aa8L),
+tole(0xe40ecf0bL), tole(0x9309ff9dL), tole(0x0a00ae27L), tole(0x7d079eb1L),
+tole(0xf00f9344L), tole(0x8708a3d2L), tole(0x1e01f268L), tole(0x6906c2feL),
+tole(0xf762575dL), tole(0x806567cbL), tole(0x196c3671L), tole(0x6e6b06e7L),
+tole(0xfed41b76L), tole(0x89d32be0L), tole(0x10da7a5aL), tole(0x67dd4accL),
+tole(0xf9b9df6fL), tole(0x8ebeeff9L), tole(0x17b7be43L), tole(0x60b08ed5L),
+tole(0xd6d6a3e8L), tole(0xa1d1937eL), tole(0x38d8c2c4L), tole(0x4fdff252L),
+tole(0xd1bb67f1L), tole(0xa6bc5767L), tole(0x3fb506ddL), tole(0x48b2364bL),
+tole(0xd80d2bdaL), tole(0xaf0a1b4cL), tole(0x36034af6L), tole(0x41047a60L),
+tole(0xdf60efc3L), tole(0xa867df55L), tole(0x316e8eefL), tole(0x4669be79L),
+tole(0xcb61b38cL), tole(0xbc66831aL), tole(0x256fd2a0L), tole(0x5268e236L),
+tole(0xcc0c7795L), tole(0xbb0b4703L), tole(0x220216b9L), tole(0x5505262fL),
+tole(0xc5ba3bbeL), tole(0xb2bd0b28L), tole(0x2bb45a92L), tole(0x5cb36a04L),
+tole(0xc2d7ffa7L), tole(0xb5d0cf31L), tole(0x2cd99e8bL), tole(0x5bdeae1dL),
+tole(0x9b64c2b0L), tole(0xec63f226L), tole(0x756aa39cL), tole(0x026d930aL),
+tole(0x9c0906a9L), tole(0xeb0e363fL), tole(0x72076785L), tole(0x05005713L),
+tole(0x95bf4a82L), tole(0xe2b87a14L), tole(0x7bb12baeL), tole(0x0cb61b38L),
+tole(0x92d28e9bL), tole(0xe5d5be0dL), tole(0x7cdcefb7L), tole(0x0bdbdf21L),
+tole(0x86d3d2d4L), tole(0xf1d4e242L), tole(0x68ddb3f8L), tole(0x1fda836eL),
+tole(0x81be16cdL), tole(0xf6b9265bL), tole(0x6fb077e1L), tole(0x18b74777L),
+tole(0x88085ae6L), tole(0xff0f6a70L), tole(0x66063bcaL), tole(0x11010b5cL),
+tole(0x8f659effL), tole(0xf862ae69L), tole(0x616bffd3L), tole(0x166ccf45L),
+tole(0xa00ae278L), tole(0xd70dd2eeL), tole(0x4e048354L), tole(0x3903b3c2L),
+tole(0xa7672661L), tole(0xd06016f7L), tole(0x4969474dL), tole(0x3e6e77dbL),
+tole(0xaed16a4aL), tole(0xd9d65adcL), tole(0x40df0b66L), tole(0x37d83bf0L),
+tole(0xa9bcae53L), tole(0xdebb9ec5L), tole(0x47b2cf7fL), tole(0x30b5ffe9L),
+tole(0xbdbdf21cL), tole(0xcabac28aL), tole(0x53b39330L), tole(0x24b4a3a6L),
+tole(0xbad03605L), tole(0xcdd70693L), tole(0x54de5729L), tole(0x23d967bfL),
+tole(0xb3667a2eL), tole(0xc4614ab8L), tole(0x5d681b02L), tole(0x2a6f2b94L),
+tole(0xb40bbe37L), tole(0xc30c8ea1L), tole(0x5a05df1bL), tole(0x2d02ef8dL)
+};
+#endif
+
+/* ========================================================================= */
+// # if __BYTE_ORDER == __LITTLE_ENDIAN
+#  define DO_CRC(x) crc = tab[(crc ^ (x)) & 255] ^ (crc >> 8)
+// # else
+// #  define DO_CRC(x) crc = tab[((crc >> 24) ^ (x)) & 255] ^ (crc << 8)
+// # endif
+
+/* ========================================================================= */
+
+/* No ones complement version. JFFS2 (and other things ?)
+ * don't use ones compliment in their CRC calculations.
+ */
+uint32_t crc32_no_comp(uint32_t crc, const unsigned char *buf, uint len)
+{
+#ifdef CONFIG_ARM64_CRC32
+    crc = cpu_to_le32(crc);
+    while (len--)
+        crc = __builtin_aarch64_crc32b(crc, *buf++);
+    return le32_to_cpu(crc);
+#else
+    const uint32_t *tab = crc_table;
+    const uint32_t *b =(const uint32_t *)buf;
+    size_t rem_len;
+#ifdef CONFIG_DYNAMIC_CRC_TABLE
+    if (crc_table_empty)
+      make_crc_table();
+#endif
+    crc = cpu_to_le32(crc);
+    /* Align it */
+    if (((long)b) & 3 && len) {
+	 uint8_t *p = (uint8_t *)b;
+	 do {
+	      DO_CRC(*p++);
+	 } while ((--len) && ((long)p)&3);
+	 b = (uint32_t *)p;
+    }
+
+    rem_len = len & 3;
+    len = len >> 2;
+    for (--b; len; --len) {
+	 /* load data 32 bits wide, xor data 32 bits wide. */
+	 crc ^= *++b; /* use pre increment for speed */
+	 DO_CRC(0);
+	 DO_CRC(0);
+	 DO_CRC(0);
+	 DO_CRC(0);
+    }
+    len = rem_len;
+    /* And the last few bytes */
+    if (len) {
+	 uint8_t *p = (uint8_t *)(b + 1) - 1;
+	 do {
+	      DO_CRC(*++p); /* use pre increment for speed */
+	 } while (--len);
+    }
+
+    return le32_to_cpu(crc);
+#endif
+}
+#undef DO_CRC
+
+uint32_t crc32(uint32_t crc, const unsigned char *p, uint len)
+{
+     return crc32_no_comp(crc ^ 0xffffffffL, p, len) ^ 0xffffffffL;
+}

IPL/Customer/Mobis/V4H_Cx_Loader/common/log/log.c

@@ -0,0 +1,264 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+/*******************************************************************************
+ * DESCRIPTION   : log
+ ******************************************************************************/
+/******************************************************************************
+ * @file          log.c
+ * - Version      : 0.04
+ * @brief         Access protection setting driver.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 03.07.2020 0.01     First Release
+ *         : 16.06.2022 0.02     Change log output
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 04.04.2023 0.04     Removed sprintf.
+ *****************************************************************************/
+
+#include "stdarg.h"
+#include "stdint.h"
+#include "math.h"
+#include "log.h"
+#include "scif.h"
+
+#define NULL_CHAR	'\0'
+
+/***********************************************************
+ * log_printf
+ ***********************************************************/
+
+#define DOUBLE_PRINT_RES (0.001)
+static uint32_t double_print(double num)
+{
+	uint8_t  num_buf[10];
+	uint32_t count = 0U;
+	uint32_t i = 0U;
+	uint32_t rem;
+	double   unum;
+	double   res = 1/DOUBLE_PRINT_RES;
+
+	if (num < 0) {
+		(void)console_putc((uint8_t)'-');
+		count = 1U;
+		unum = -num;
+	} else {
+		unum = num;
+	}
+
+	unum /= (DOUBLE_PRINT_RES);
+
+	while (1) {
+		if (i == 0) {
+			rem = 	fmin(9, round( fmod(unum, 10.0) ) ); //last digit is rounded to correctly handle hidden digits. (last digit is processed first)
+		} else {
+			rem = 	fmod(unum, 10.0);
+		}
+		num_buf[i] = (uint8_t)('0' + rem);
+
+		i++;
+		unum = unum / 10.0;
+		res  = res / 10.0;
+		if ( (res <= 5.0) && (res > 0.5) ) {
+			num_buf[i] = (uint8_t)('.');
+			i++;
+		}
+
+		if ( (unum < 1.0) && (res < 1.0) ) {
+			break;
+		}
+	}
+
+	while (i != 0U) {
+		i--;
+		(void)console_putc(num_buf[i]);
+		count++;
+	};
+
+	return count;
+}
+
+static uint32_t uint32_print(uint32_t num)
+{
+	uint8_t  num_buf[10];
+	uint32_t count = 0U;
+	uint32_t i = 0U;
+	uint32_t rem;
+	uint32_t unum = num;
+
+	while (1) {
+		rem = unum % 10U;
+		num_buf[i] = (uint8_t)('0' + rem);
+
+		i++;
+		unum = unum / 10U;
+		if (unum < 1U) {
+			break;
+		}
+	}
+
+	while (i != 0U) {
+		i--;
+		(void)console_putc(num_buf[i]);
+		count++;
+	};
+
+	return count;
+}
+
+
+static uint32_t int32_print(int32_t num)
+{
+	uint32_t unum;
+	uint32_t count = 0U;
+
+	if (num < 0) {
+		(void)console_putc((uint8_t)'-');
+		count = 1U;
+		unum = (uint32_t)-num;
+	} else {
+		unum = (uint32_t)num;
+	}
+
+	count += uint32_print(unum);
+
+	return count;
+}
+
+
+static uint32_t uint32_hex_print(uint32_t num)
+{
+	uint32_t i;
+	uint32_t count = 0U;
+	uint8_t  c;
+
+	for (i = 0U; i < 8U; i++) {
+		/* 0-F */
+		c = (uint8_t)((num >> ((7U - i) * 4U)) & 0x0FU);
+		if (c >= 0x0AU) {
+			/* A-F */
+			c += (uint8_t)('a' - 0x0AU);
+		} else {
+			/* 0-9 */
+			c += (uint8_t)'0';
+		}
+		(void)console_putc(c);
+		count++;
+	}
+
+	return count;
+}
+
+
+static uint32_t uint8_hex_print(uint8_t num)
+{
+	uint32_t i;
+	uint32_t count = 0U;
+	uint8_t  c;
+
+	for (i = 0U; i < 2U; i++) {
+		/* 0-F */
+		c = ((num >> ((1U - i) * 4U)) & 0x0FU);
+		if (c >= 0x0AU) {
+			/* A-F */
+			c += (uint8_t)('a' - 0x0AU);
+		} else {
+			/* 0-9 */
+			c += (uint8_t)'0';
+		}
+		(void)console_putc(c);
+		count++;
+	}
+
+	return count;
+}
+
+
+static uint32_t str_print(const char *str)
+{
+	uint32_t count = 0;
+
+	while (*str != NULL_CHAR) {
+		(void)console_putc((uint8_t)*str);
+		str++;
+		count++;
+	}
+
+	return count;
+}
+
+
+void log_printf(const char *fmt, ...)
+{
+	va_list  args;
+	double   dnum;
+	int32_t  num;
+	uint32_t unum;
+	char     *str;
+	uint32_t count = 0U;
+
+	va_start(args, fmt);
+	while (*fmt != NULL_CHAR) {
+		if (*fmt == '%') {
+			fmt++;
+			switch (*fmt) {
+			case 'i':
+				/* No break */
+			case 'd':
+				num = va_arg(args, int32_t);
+				count += int32_print(num);
+				break;
+			case 's':
+				str = va_arg(args, char *);
+				count += str_print(str);
+				break;
+			case 'x':
+				unum = va_arg(args, uint32_t);
+				count += uint32_hex_print(unum);
+				break;
+			case 'b':
+				unum = (uint8_t)va_arg(args, uint32_t);
+				count += uint8_hex_print(unum);
+				break;
+			case 'u':
+				unum = va_arg(args, uint32_t);
+				count += uint32_print(unum);
+				break;
+			case 'f':
+				dnum = va_arg(args, double);
+				count += double_print(dnum);
+				break;
+			default:
+				break;
+			}
+		} else {
+			(void)console_putc((uint8_t)*fmt);
+			count++;
+		}
+		fmt++;
+	}
+	va_end(args);
+}

IPL/Customer/Mobis/V4H_Cx_Loader/common/log/scif.c

@@ -0,0 +1,172 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+ * DESCRIPTION   : SCIF driver
+ ******************************************************************************/
+/******************************************************************************
+ * @file          scif.c
+ * - Version      : 0.07
+ * @brief         1. Initial setting of SCIF.
+ *                2. Initial setting of HSCIF.
+ *                3. Log output function.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 28.07.2021 0.01     First Release
+ *         : 03.09.2021 0.02     Modify the timing of MODEMR judgement.
+ *         : 15.10.2021 0.03     Modify register access to read modify write.
+ *         : 03.12.2021 0.04     Fix incorrect configuration process.
+ *         : 06.01.2022 0.05     Static analysis support
+ *         : 16.06.2022 0.06     Change line feed code
+ *         : 31.10.2022 0.07     License notation change.
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <types.h>
+#include <scif.h>
+#include <mem_io.h>
+#include <rst_register.h>
+
+/* Define  */
+#define SCIF_SCFSR_TEND         (uint16_t)((uint16_t)1U << 6U)
+#define SCIF_SCFSR_TDFE         (uint16_t)((uint16_t)1U << 5U)
+#define TRANS_END_CHECK         (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
+
+
+static void (*rcar_putc)(uint8_t outchar);
+
+static void scif_console_init(uint32_t modemr);
+static void scif_console_putc(uint8_t outchar);
+static void hscif_console_putc(uint8_t outchar);
+
+
+static void scif_console_init(uint32_t modemr)
+{
+    switch(modemr)
+    {
+        case MODEMR_HSCIF_DLMODE_3000000:
+        {
+            /* Set the pointer to a function that outputs one character. */
+            rcar_putc = hscif_console_putc;
+            break;
+        }
+        case MODEMR_HSCIF_DLMODE_1843200:
+        {
+            /* Set the pointer to a function that outputs one character. */
+            rcar_putc = hscif_console_putc;
+            break;
+        }
+        case MODEMR_HSCIF_DLMODE_921600:
+        {
+            /* Set the pointer to a function that outputs one character. */
+            rcar_putc = hscif_console_putc;
+            break;
+        }
+        case MODEMR_SCIF_DLMODE:
+        default:
+        {
+            /* Set the pointer to a function that outputs one character. */
+            rcar_putc = scif_console_putc;
+            break;
+        }
+    }
+}
+/* End of function scif_console_init(void) */
+
+void scif_init(void)
+{
+    uint32_t modemr;
+
+#ifdef FORCE_115200  /* force to serial speed to 115200 bps */
+#define _MODE31     (0xEB22FFF0)      /* Gen4_ICUMX_loader at RT-VRAM */
+#define _MODE_115200 0x00115200
+	modemr = mem_read32(_MODE31);
+	if (modemr == _MODE_115200)
+		modemr = MODEMR_SCIF_DLMODE;
+	else
+#endif
+	{
+    modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U);
+    modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
+	}
+    scif_console_init(modemr);
+}
+/* End of function scif_init(void) */
+
+void console_putc(uint8_t outchar)
+{
+    if (outchar == 0x0A)   /* \n */
+    {
+        rcar_putc( 0x0D ); /* \r */
+    }
+    rcar_putc(outchar);
+}
+/* End of function console_putc(void) */
+
+
+static void scif_console_putc(uint8_t outchar)
+{
+    uint16_t reg;
+
+    /* Check that transfer of SCIF0 is completed */
+    while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
+    {
+        ;
+    }
+
+    mem_write8(SCIF_SCFTDR, outchar);   /* Transfer one character */
+    reg = mem_read16(SCIF_SCFSR);
+    reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
+    mem_write16(SCIF_SCFSR, reg);
+
+    /* Check that transfer of SCIF0 is completed */
+    while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
+    {
+        ;
+    }
+}
+/* End of function scif_console_putc(uint8_t outchar) */
+
+static void hscif_console_putc(uint8_t outchar)
+{
+    uint16_t reg;
+
+    /* Check that transfer of SCIF0 is completed */
+    while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
+    {
+        ;
+    }
+
+    mem_write8(HSCIF_HSFTDR, outchar);  /* Transfer one character */
+    reg = mem_read16(HSCIF_HSFSR);
+    reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
+    mem_write16(HSCIF_HSFSR, reg);
+
+    /* Check that transfer of SCIF0 is completed */
+    while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
+    {
+        ;
+    }
+}
+/* End of function hscif_console_putc(uint8_t outchar) */

IPL/Customer/Mobis/V4H_Cx_Loader/common/string.c

@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Standard library
+ ******************************************************************************/
+/******************************************************************************
+ * @file          string.c
+ * - Version      : 0.01
+ * @brief         standard library.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 04.04.2023 0.01     First Release
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+
+void *memcpy(void *dst, const void *src, size_t len)
+{
+    uint8_t *p1 = (uint8_t *)dst;
+    const uint8_t *p2 = (const uint8_t *)src;
+    while(len > 0U)
+    {
+        *(p1++) = *(p2++);
+        len--;
+    }
+    return dst;
+}
+/* End of function memcpy( void* dst, const void* src, size_t n ) */
+
+void *memset(void *dst, int val, size_t len)
+{
+    uint8_t *p = (uint8_t *)dst;
+    const uint8_t uc = (uint8_t)val;
+
+    while (len > 0U)
+    {
+        *p++ = uc;
+        len--;
+    }
+    return (dst);
+}
+/* End of function memset(void *dst, int val, size_t len) */
+
+/**
+ * memcmp - Compare two areas of memory
+ * @cs: One area of memory
+ * @ct: Another area of memory
+ * @count: The size of the area.
+ */
+int memcmp(const void * cs, const void * ct, size_t count)
+{
+	const unsigned char *su1, *su2;
+	int res = 0;
+
+	for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+		if ((res = *su1 - *su2) != 0)
+			break;
+	return res;
+}

IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/generic_timer.c

@@ -0,0 +1,177 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+/*******************************************************************************
+ * DESCRIPTION   : generic timer
+ ******************************************************************************/
+/******************************************************************************
+ * @file          generic_timer.c
+ * - Version      : 0.08
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 19.01.2022 0.01     First Release
+ *         : 17.02.2022 0.02     Support AArch32
+ *         : 09.05.2022 0.03     Supports argument check of micro_wait()
+ *                               Moved the definition of the define value
+ *                               Removed __ARM_ARCH_8R__ and __ARM_ARCH_8A__
+ *                               Change macro to inline function
+ *                               Added initial settings
+ *                               Remove unnecessary casts
+ *                               Change the value of RCAR_CNTC_EXTAL
+ *         : 16.06.2022 0.04     Change the value of RCAR_CNTC_EXTAL
+ *         : 16.06.2022 0.05     Change log output
+ *         : 31.10.2022 0.06     License notation change.
+ *         : 04.04.2023 0.07     Removed stdio.h.
+ *         : 21.08.2023 0.08     Add support for V4M.
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <mem_io.h>
+#include <timer.h>
+#include <log.h>
+
+#if (RCAR_LSI == RCAR_S4)
+#define RCAR_CNTC_EXTAL (16666666U) /* 16.666666MHz */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define RCAR_CNTC_EXTAL (16666600U) /* 16.666600MHz */
+#endif /* RCAR_LSI == RCAR_S4 */
+#define CNTFID_OFF          (0x0020U)
+#define CNTCR_OFF           (0x0000U)
+#define CNTCR_EN            ((1U) << 0U)
+#define RCAR_CNTC_BASE      (0xE6080000U)
+#define RCAR_CONV_MICROSEC  (1000000U)
+#define RCAR_MAX_WAITTIME   (10000000U)
+#define RCAR_MIN_WAITTIME   (0U)
+
+#ifdef __aarch64__
+static inline uint64_t get_cntfrq(void)
+{
+    uint64_t    freq;
+    __asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq));
+
+    return(freq);
+}
+
+static inline void set_cntfrq(uint64_t reg_cntfid)
+{
+    __asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid));
+}
+
+static inline uint64_t get_cntpct(void)
+{
+    uint64_t    base_count;
+    __asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count));
+
+    return(base_count);
+}
+
+#elif __arm__
+static inline uint32_t get_cntfrq(void)
+{
+    uint32_t    freq;
+    __asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+    return(freq);
+}
+
+static inline void set_cntfrq(uint32_t reg_cntfid)
+{
+    __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid));
+}
+
+static inline uint64_t get_cntpct(void)
+{
+    uint64_t    base_count;
+    __asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count));
+
+    return(base_count);
+}
+#endif /* __aarch64__ */
+
+void generic_timer_init(void)
+{
+    /* Update memory mapped and register based freqency */
+    /* AArch64:cntfrq_el0 */
+    /* AArch32:cntfrq */
+    set_cntfrq(RCAR_CNTC_EXTAL);
+
+    mem_write32(RCAR_CNTC_BASE + CNTFID_OFF, RCAR_CNTC_EXTAL);
+
+    /* Enable counter */
+    mem_bitset32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_EN);
+}
+/* End of function generic_timer_init(void) */
+
+void micro_wait(uint64_t micro_sec)
+{
+    uint64_t base_count = 0U;
+    uint64_t get_count  = 0U;
+    uint64_t wait_time  = 0U;
+#ifdef __aarch64__
+    uint64_t freq       = 0U;
+#elif __arm__
+    uint32_t freq       = 0U;
+#endif /* __aarch64__ */
+
+
+    if((micro_sec > RCAR_MIN_WAITTIME) && (micro_sec <= RCAR_MAX_WAITTIME))
+    {
+        /* AArch64:cntfrq_el0 */
+        /* AArch32:cntfrq */
+        freq = get_cntfrq();
+        /* AArch64:cntpct_el0 */
+        /* AArch32:cntpct */
+        base_count = get_cntpct();
+
+        micro_sec *= freq;
+        while (micro_sec > wait_time)
+        {
+            /* cntpct */
+            get_count = get_cntpct();
+
+            /* INT30-C Pre confirmation */
+            if (get_count < base_count)
+            {
+                ERROR("micro_wait(Timer value error!!).\n");
+                panic;
+            }
+            else
+            {
+                wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC);
+            }
+        }
+    }
+    else
+    {
+        ERROR("micro_wait(wait time)\n");
+        ERROR("wait time = 0x%x\n", (unsigned int)micro_sec);
+        panic;
+    }
+
+}
+/* End of function micro_wait(uint64_t micro_sec) */
+

IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c

@@ -0,0 +1,304 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Power management driver
+ ******************************************************************************/
+/******************************************************************************
+ * @file          cpu_on.c
+ * - Version      : 0.12
+ * @brief         1. Boot process of ARM CPU core.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 17.02.2022 0.01     First Release
+ *         : 25.02.2022 0.02     Changed to boot Cortex-R on Core 0.
+ *         : 23.03.2022 0.03     Removed unnecessary header file inclusions
+ *         : 09.05.2022 0.04     Removed unnecessary processing
+ *                               Removed unnecessary cast
+ *         : 31.10.2022 0.05     License notation change.
+ *         : 21.08.2023 0.06     Add support for V4M.
+ *         : 16.11.2023 0.07     Changed not to execute ASPREG setting
+ *                               in case of V4M.
+ *         : 10.09.2024 0.08     Updated Region ID and RAM protection setting
+ *                               for QNX.
+ *         : 11.10.2024 0.09     Updated Region ID and RAM protection setting
+ *                               for QNX for V4M.
+ *         : 09.12.2024 0.10     Updated OTP_MEM_OTPMONITOR60 register to
+ *                               OTP_MEM_OTPMONITOR17 register for V4M.
+ *                               And Improve the adj_ca_variant_freq function.
+ *         : 19.12.2024 0.11     Add support for booting CR52 core2.
+ *         : 18.03.2025 0.12     Add INTC initialization process.
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <mem_io.h>
+#include <cpu_on.h>
+#include <rst_register.h>
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#include "access_protection.h"
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+#include <log.h>
+
+
+/* ARM */
+#define CA_CORE0_WUP_REQ      (0x00000001U)
+#define CA_CORE0_VLD_RVBARP   (0x00000001U)
+#define CR_BTMD_RBAR          (0x00000000U)
+#define CR_VLD_BARP           (0x00000001U << 0U)
+#define CR_BAREN_VALID        (0x00000001U << 4U)
+#define CRRST                 (0x00000000U)
+
+#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1    (0x00000001U << 1U)
+#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0    (0x00000001U << 0U)
+#define AP_CORE_APSREG_CCI500_AUX_ACTDIS            (0x00000001U << 0U)
+#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM          (0x00000001U << 1U)
+
+/* APMU */
+#define APMU_BASE           (BASE_APMU_ADDR)
+#define CORTEX_R_CORE       (0U)                                               /* Target Cortex R52 cores (0 to 2)  */
+#define APMU_CRRSTCTRL(n)   (APMU_BASE + ((n) * 0x40U) + 0x0304U)   /* Cortex-R Reset Control Register    */
+#define APMU_CRBARP(n)      (APMU_BASE + ((n) * 0x40U) + 0x033CU)   /* Cortex-R Boot Address Register Protected   */
+
+#define APMU_PWRCTRLC0      (APMU_BASE + 0x0800U)   /* Power Control Register for Core 0    */
+#define APMU_RVBARPLC0      (APMU_BASE + 0x0838U)   /* Reset Vector Base Address Register Protected Low for Core 0  */
+#define APMU_RVBARPHC0      (APMU_BASE + 0x083CU)   /* Reset Vector Base Address Register Protected High for Core 0 */
+
+#define AP_CORE_BASE        (BASE_AP_CORE_ADDR)     /* 0xE6280000 */
+
+#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U))
+#define AP_CORE_APSREG_CCI500_AUX           (AP_CORE_BASE + 0x00009010U)
+#define AP_CORE_APSREG_P_CCI500_AUX         (AP_CORE_BASE + 0x00029010U)
+
+#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT       (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0)
+
+#if (RCAR_LSI == RCAR_V4H)
+#define V4H_5_NI_CA           (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
+#define V4H_3_NI_CA           (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
+#elif (RCAR_LSI == RCAR_V4M)
+#define V4M_5_NI_CA           (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
+#define V4M_3_NI_CA           (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
+#define V4M_2_NI_CA           (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
+#endif /* RCAR_LSI == RCAR_V4H */
+
+#define CPG_PLL2CR0_KICK_BIT  (0x80000000U)
+#define CPG_PLLECR_PLL2ST_BIT (0x00000200U)
+
+#if (RCAR_LSI == RCAR_V4M)
+#define CPG_BASE              (BASE_CPG_ADDR)
+#define CPG_SRSTCLR5          (CPG_BASE + 0x2C94U)
+#define CPG_SRSTCLR11         (CPG_BASE + 0x2CACU)
+#define CPG_MSTPCR5           (CPG_BASE + 0x2D14U)
+#define CPG_SRSTCLR5_VAL      (0x80000000U)
+#define CPG_SRSTCLR11_VAL     (0x00080000U)
+#define CPG_MSTPCR5_VAL       (0x80000000U)
+
+static void intc_init(void);
+#endif /* RCAR_LSI == RCAR_V4M */
+
+static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr, int n)
+{
+    if(RCAR_PWR_TARGET_CR == target)
+    {
+        /* CR Boot address set */
+        mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP));
+        mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
+    }
+    else
+    {
+        /* CA Boot address set */
+        mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+        mem_write32(APMU_RVBARPHC0, 0x00000020U);   /* CA boot address 0x20_XXXXXXXX */
+#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
+        mem_write32(APMU_RVBARPHC0, 0x00000000U);
+#endif
+#else
+        mem_write32(APMU_RVBARPHC0, 0x00000000U);
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+    }
+}
+/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
+
+void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id)
+{
+    uint32_t res_data;
+
+    if(RCAR_PWR_TARGET_CR == target)
+    {
+        if (core_id < 0)
+            core_id = CORTEX_R_CORE;
+
+        NOTICE("enable CR-52 core %d\n", core_id);
+
+        /* CR Boot address set. */
+        arm_cpu_set_address(target, boot_addr, core_id);
+
+        /* CR reset. */
+        mem_write32(APMU_CRRSTCTRL(core_id), CRRST);
+    }
+    else
+    {
+#if (RCAR_LSI == RCAR_V4M)
+        /* For the initial setting flow of INTC, see Section 15.4.5 in
+         * "R-Car Series, V4M Series User's Manual".
+         */
+        /* INTC initialize */
+        intc_init();
+#endif /* RCAR_LSI == RCAR_V4M */
+
+        /* CA Boot address set. */
+        arm_cpu_set_address(target, boot_addr, 0);
+        
+#if (RCAR_LSI == RCAR_V4H)
+        /*
+         * In case of V4M, doesn't execute following process at Cx 2nd IPL.
+         * Because following register setting is needed to execute before C4 power on.
+         */
+        /* AP-System core initialize */
+        res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U));
+        res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
+        mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data);
+        
+        res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
+        res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
+        mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
+        /* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */
+        res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
+        res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
+        mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
+#endif /* RCAR_LSI == RCAR_V4H */
+    	/* CA core0 wake up sequence. */
+        mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ);
+        /* Wait until CA core0 wake up sequence finished. */
+        do
+        {
+            res_data = mem_read32(APMU_PWRCTRLC0);
+        }while(CA_CORE0_WUP_REQ & res_data);
+    }
+}
+/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
+
+void adj_ca_variant_freq(void)
+{
+    uint32_t product   = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
+    uint32_t pll2_freq = mem_read32(CPG_PLL2CR0);
+
+#if (RCAR_LSI == RCAR_V4H)
+    /* Set the CPU frequency division ratio according to the type of variant. */
+    switch (product)
+    {
+    case VARIANT_V4H_7:
+        /* Default value, do nothing */;
+        break;
+    case VARIANT_V4H_5:
+        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
+        pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U));
+        break;
+    case VARIANT_V4H_3:
+        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
+        pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U));
+        break;
+    default:
+        ; /* Do nothing */
+        break;
+    }
+
+    if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
+    {
+        /* Write Division value to FRQCRC0 register */
+        mem_write32(CPG_CPGWPR,  ~(pll2_freq));
+        mem_write32(CPG_PLL2CR0, pll2_freq);
+
+        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
+        mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
+
+        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
+        {
+            ;
+        }
+    }
+#elif (RCAR_LSI == RCAR_V4M)
+    /* Set the CPU frequency division ratio according to the type of variant. */
+    switch (product)
+    {
+    case VARIANT_V4M_7:
+        /* Default value, do nothing */;
+        break;
+    case VARIANT_V4M_5:
+        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
+        pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U));
+        break;
+    case VARIANT_V4M_3:
+        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
+        pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U));
+        break;
+    case VARIANT_V4M_2:
+        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
+        pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U));
+        break;
+    default:
+        ; /* Do nothing */
+        break;
+    }
+
+    if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
+    {
+        /* Write Division value to FRQCRC0 register */
+        mem_write32(CPG_CPGWPR,  ~(pll2_freq));
+        mem_write32(CPG_PLL2CR0, pll2_freq);
+
+        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
+        mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
+
+        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
+        {
+            ;
+        }
+    }
+#endif /* RCAR_LSI == RCAR_V4H */
+}
+/* End of function adj_cpu_variant_freq(void) */
+
+#if (RCAR_LSI == RCAR_V4M)
+static void intc_init(void)
+{
+    uint32_t reg;
+
+    mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL));
+    mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL);
+
+    mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL));
+    mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL);
+
+    mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL));
+    reg = mem_read32(CPG_MSTPCR5);
+    reg |= CPG_MSTPCR5_VAL;
+    mem_write32(CPG_MSTPCR5, reg);
+}
+/* End of function intc_init(void) */
+#endif /* RCAR_LSI == RCAR_V4M */

IPL/Customer/Mobis/V4H_Cx_Loader/image_load/android_ab.c

@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+// #include <common.h>
+#include <android_ab.h>
+#include <android_bootloader_message.h>
+// #include <blk.h>
+#include <log.h>
+// #include <malloc.h>
+#include <string.h>
+// #include <part.h>
+// #include <memalign.h>
+// #include <linux/err.h>
+#include <errno.h>
+// #include <u-boot/crc.h>
+#include <crc.h>
+
+#include <emmc_multiboot.h>
+#include <image_load_emmc.h>
+#include <mem_io.h>
+typedef unsigned long int	ulong;
+typedef uint32_t	u32;
+#define typeof(x)	__typeof__(x)
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+#define ARRAY_SIZE(x)		(sizeof(x) / sizeof((x)[0]))
+
+volatile uint8_t *_disk_buffer = (volatile uint8_t *)DISK_BUFFER_ADDR;
+
+/**
+ * Compute the CRC-32 of the bootloader control struct.
+ *
+ * Only the bytes up to the crc32_le field are considered for the CRC-32
+ * calculation.
+ *
+ * @param[in] abc bootloader control block
+ *
+ * @return crc32 sum
+ */
+static uint32_t ab_control_compute_crc(struct bootloader_control *abc)
+{
+	return crc32(0, (void *)abc, offsetof(typeof(*abc), crc32_le));
+}
+
+/**
+ * Initialize bootloader_control to the default value.
+ *
+ * It allows us to boot all slots in order from the first one. This value
+ * should be used when the bootloader message is corrupted, but not when
+ * a valid message indicates that all slots are unbootable.
+ *
+ * @param[in] abc bootloader control block
+ *
+ * @return 0 on success and a negative on error
+ */
+static int ab_control_default(struct bootloader_control *abc)
+{
+	int i;
+	const struct slot_metadata metadata = {
+		.priority = 15,
+		.tries_remaining = 7,
+		.successful_boot = 0,
+		.verity_corrupted = 0,
+		.reserved = 0
+	};
+
+	if (!abc)
+		return -EFAULT;
+
+	memcpy(abc->slot_suffix, "a\0\0\0", 4);
+	abc->magic = BOOT_CTRL_MAGIC;
+	abc->version = BOOT_CTRL_VERSION;
+	abc->nb_slot = NUM_SLOTS;
+	memset(abc->reserved0, 0, sizeof(abc->reserved0));
+	for (i = 0; i < abc->nb_slot; ++i)
+		abc->slot_info[i] = metadata;
+
+	memset(abc->reserved1, 0, sizeof(abc->reserved1));
+	abc->crc32_le = ab_control_compute_crc(abc);
+
+	return 0;
+}
+
+/**
+ * Load the boot_control struct from disk into newly allocated memory.
+ *
+ * This function allocates and returns an integer number of disk blocks,
+ * based on the block size of the passed device to help performing a
+ * read-modify-write operation on the boot_control struct.
+ * The boot_control struct offset (2 KiB) must be a multiple of the device
+ * block size, for simplicity.
+ *
+ * @param[in] dev_desc Device where to read the boot_control struct from
+ * @param[in] part_info Partition in 'dev_desc' where to read from, normally
+ *			the "misc" partition should be used
+ * @param[out] pointer to pointer to bootloader_control data
+ * @return 0 on success and a negative on error
+ */
+static int ab_control_create_from_disk(
+				    //    struct blk_desc *dev_desc,
+				    //    const struct disk_partition *part_info,
+				       struct bootloader_control **abc)
+{
+	// ulong abc_offset, abc_blocks, ret;
+
+	// abc_offset = offsetof(struct bootloader_message_ab, slot_suffix);
+	// if (abc_offset % CX_EMMC_SECTOR_SIZE) {
+	// 	ERROR("Boot control block not block aligned.\n");
+	// 	return -EINVAL;
+	// }
+	// abc_offset /= CX_EMMC_SECTOR_SIZE;
+
+	// abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control),
+	// 			  CX_EMMC_SECTOR_SIZE);
+	// if (abc_offset + abc_blocks > part_info->size) {
+	// 	ERROR("boot control partition too small. Need at"
+	// 		" least %lu blocks but have %lu blocks.\n",
+	// 		abc_offset + abc_blocks, part_info->size);
+	// 	return -EINVAL;
+	// }
+	// *abc = malloc_cache_aligned(abc_blocks * CX_EMMC_SECTOR_SIZE);
+	// if (!*abc)
+	// 	return -ENOMEM;
+
+	// [ab_control_create_from_disk:112] start 0x3f800(260096), abc_offset(0x4,4), blocks 1
+	// ret = blk_dread(dev_desc, part_info->start + abc_offset, abc_blocks,
+	// 		*abc);
+    uint32_t rtn_val = EMMC_DEV_ERR;
+
+#define CX_EMMC_MISC_PART	0			// user partition
+#define CX_EMMC_MISC_START	0x3F800		// 127MB in user partition
+#define CX_EMMC_AB_CONTROL	(CX_EMMC_MISC_START + 4)
+#define CX_EMMC_AB_SIZE		(1)
+	rtn_val = emmc_trans_data(CX_EMMC_MISC_PART, (uintptr_t)(CX_EMMC_AB_CONTROL), 
+                    (uintptr_t)_disk_buffer, CX_EMMC_AB_SIZE);
+    if(EMMC_DEV_OK != rtn_val)
+	{
+		ERROR("Could not read from boot ctrl partition\n");
+		*abc = NULL;
+		return -EIO;
+	}
+
+	*abc = (struct bootloader_control *)_disk_buffer;
+	return 0;
+}
+
+/**
+ * Store the loaded boot_control block.
+ *
+ * Store back to the same location it was read from with
+ * ab_control_create_from_misc().
+ *
+ * @param[in] dev_desc Device where we should write the boot_control struct
+ * @param[in] part_info Partition on the 'dev_desc' where to write
+ * @param[in] abc Pointer to the boot control struct and the extra bytes after
+ *                it up to the nearest block boundary
+ * @return 0 on success and a negative on error
+ */
+// static int ab_control_store(struct blk_desc *dev_desc,
+// 			    const struct disk_partition *part_info,
+// 			    struct bootloader_control *abc)
+// {
+// 	ulong abc_offset, abc_blocks, ret;
+
+// 	abc_offset = offsetof(struct bootloader_message_ab, slot_suffix) /
+// 		     part_info->blksz;
+// 	abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control),
+// 				  part_info->blksz);
+// 	ret = blk_dwrite(dev_desc, part_info->start + abc_offset, abc_blocks,
+// 			 abc);
+// 	if (IS_ERR_VALUE(ret)) {
+// 		log_err("ANDROID: Could not write back the misc partition\n");
+// 		return -EIO;
+// 	}
+
+// 	return 0;
+// }
+
+/**
+ * Compare two slots.
+ *
+ * The function determines slot which is should we boot from among the two.
+ *
+ * @param[in] a The first bootable slot metadata
+ * @param[in] b The second bootable slot metadata
+ * @return Negative if the slot "a" is better, positive of the slot "b" is
+ *         better or 0 if they are equally good.
+ */
+static int ab_compare_slots(const struct slot_metadata *a,
+			    const struct slot_metadata *b)
+{
+	/* Higher priority is better */
+	if (a->priority != b->priority)
+		return b->priority - a->priority;
+
+	/* Higher successful_boot value is better, in case of same priority */
+	if (a->successful_boot != b->successful_boot)
+		return b->successful_boot - a->successful_boot;
+
+	/* Higher tries_remaining is better to ensure round-robin */
+	if (a->tries_remaining != b->tries_remaining)
+		return b->tries_remaining - a->tries_remaining;
+
+	return 0;
+}
+
+int ab_select_slot(
+	// struct blk_desc *dev_desc, struct disk_partition *part_info
+	void
+)
+{
+	struct bootloader_control *abc = NULL;
+	u32 crc32_le;
+	int slot, i, ret;
+	bool store_needed = false;
+	char slot_suffix[4];
+
+	mem_write32(AB_INFO_FLAG_ADDR, AB_INFO_FLAG_INIT);
+	ret = ab_control_create_from_disk(/*dev_desc, part_info,*/ &abc);
+	if (ret < 0) {
+		/*
+		 * This condition represents an actual problem with the code or
+		 * the board setup, like an invalid partition information.
+		 * Signal a repair mode and do not try to boot from either slot.
+		 */
+		return ret;
+	}
+
+	crc32_le = ab_control_compute_crc(abc);
+	if (abc->crc32_le != crc32_le) {
+		ERROR("Invalid CRC-32 (expected %.8x, found %.8x),"
+				"re-initializing A/B metadata.\n", crc32_le, abc->crc32_le);
+
+		ret = ab_control_default(abc);
+		if (ret < 0) {
+			// free(abc);
+			return -ENODATA;
+		}
+		store_needed = true;
+	}
+
+	if (abc->magic != BOOT_CTRL_MAGIC) {
+		ERROR("Unknown A/B metadata: %.8x\n", abc->magic);
+		// free(abc);
+		return -ENODATA;
+	}
+
+	if (abc->version > BOOT_CTRL_VERSION) {
+		ERROR("Unsupported A/B metadata version: %.8x\n", abc->version);
+		// free(abc);
+		return -ENODATA;
+	}
+
+	/*
+	 * At this point a valid boot control metadata is stored in abc,
+	 * followed by other reserved data in the same block. We select a with
+	 * the higher priority slot that
+	 *  - is not marked as corrupted and
+	 *  - either has tries_remaining > 0 or successful_boot is true.
+	 * If the selected slot has a false successful_boot, we also decrement
+	 * the tries_remaining until it eventually becomes unbootable because
+	 * tries_remaining reaches 0. This mechanism produces a bootloader
+	 * induced rollback, typically right after a failed update.
+	 */
+
+	/* Safety check: limit the number of slots. */
+	if (abc->nb_slot > ARRAY_SIZE(abc->slot_info)) {
+		abc->nb_slot = ARRAY_SIZE(abc->slot_info);
+		NOTICE("[%s:%d] abc->nb_slot > ARRAY_SIZE(abc->slot_info)\n", __func__, __LINE__);
+		store_needed = true;
+	}
+
+	slot = -1;
+	for (i = 0; i < abc->nb_slot; ++i) {
+		if (abc->slot_info[i].verity_corrupted ||
+		    !abc->slot_info[i].tries_remaining) {
+			NOTICE("unbootable slot %d tries: %d, corrupt: %d\n",
+				  i, abc->slot_info[i].tries_remaining,
+				  abc->slot_info[i].verity_corrupted);
+			continue;
+		}
+		NOTICE("bootable slot %d pri: %d, tries: %d, "
+				"corrupt: %d, successful: %d\n",
+			  i, abc->slot_info[i].priority,
+			  abc->slot_info[i].tries_remaining,
+			  abc->slot_info[i].verity_corrupted,
+			  abc->slot_info[i].successful_boot);
+
+		if (slot < 0 ||
+		    ab_compare_slots(&abc->slot_info[i],
+				     &abc->slot_info[slot]) < 0) {
+			slot = i;
+		}
+	}
+
+	if (slot >= 0 && !abc->slot_info[slot].successful_boot) {
+		ERROR("Attempting slot %d, tries remaining %d\n",
+			slot, abc->slot_info[slot].tries_remaining);
+		abc->slot_info[slot].tries_remaining--;
+		store_needed = true;
+	}
+
+	if (slot >= 0) {
+		/*
+		 * Legacy user-space requires this field to be set in the BCB.
+		 * Newer releases load this slot suffix from the command line
+		 * or the device tree.
+		 */
+		memset(slot_suffix, 0, sizeof(slot_suffix));
+		slot_suffix[0] = BOOT_SLOT_NAME(slot);
+		if (memcmp(abc->slot_suffix, slot_suffix,
+			   sizeof(slot_suffix))) {
+			memcpy(abc->slot_suffix, slot_suffix,
+			       sizeof(slot_suffix));
+			NOTICE("[%s:%d] slot_suffix is differ\n", __func__, __LINE__);
+			store_needed = true;
+		}
+	}
+
+	if (store_needed) {
+		abc->crc32_le = ab_control_compute_crc(abc);
+		// ab_control_store(dev_desc, part_info, abc);
+		crc32_le = AB_INFO_FLAG_STORE;
+	}
+	else
+		crc32_le = AB_INFO_FLAG_OK;
+	// free(abc);
+	if (slot == 1)
+		crc32_le |= AB_INFO_SELECT_2nd;
+	mem_write32(AB_INFO_FLAG_ADDR, crc32_le);
+
+	if (slot < 0)
+		return -EINVAL;
+
+	return slot;
+}

IPL/Customer/Mobis/V4H_Cx_Loader/image_load/image_load.c

@@ -0,0 +1,494 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Image load function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          image_load.c
+ * - Version      : 0.11
+ * @brief         Access protection setting driver.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 29.11.2021 0.01     First Release
+ *         : 10.02.2022 0.02     Updated eMMC driver
+ *                               Removed the comment
+ *                               Change the line feed code of log output
+ *                               Change the number of CA programs
+ *         : 17.02.2022 0.03     Support AArch32
+ *         : 22.03.2022 0.04     Support for GSCE[3.3b]
+ *         : 11.05.2022 0.05     Used the standard library
+ *                               Integrated LOAD_INFO
+ *                               Changed image_name table
+ *                               Changed check_load_area
+ *                               - Change RAM check process
+ *                               - Change address check process
+ *                               - Add Image check process
+ *                               - Processing integration
+ *                               Changed to processing for each device
+ *                               Change structure member name
+ *                               Added function return value judgment
+ *                               Changed LOGICAL_CONTENT_CERT_ADDR to
+ *                                 get_logic_cont_cert_addr
+ *                               Changed uint32_t to uintptr_t
+ *                               Change log output
+ *                               Add argument of load_init()
+ *                               Change to error when key information is invalid
+ *                               Remove unnecessary type conversion
+ *         : 11.07.2022 0.06     Change log output
+ *                               Support secure boot for S4
+ *                               Change load start processing other than 512byte align
+ *         : 02.09.2022 0.07     Added 512byte boundary check
+ *         : 31.10.2022 0.08     License notation change.
+ *         : 21.08.2023 0.09     Add support for V4M.
+ *         : 19.12.2024 0.10     Add support for RTOS#1 and RTOS#2.
+ *         : 26.05.2025 0.11     Change key cert address of [CA_OPTIONAL_ID+2].
+*****************************************************************************/
+/* indelude */
+#include <stdint.h>
+#include <image_load.h>
+#include <mem_io.h>
+#include <log.h>
+
+#include <image_load_emmc.h>
+#include <emmc_multiboot.h>
+
+#define KEY_SIZE_FLG_MSK            (0x00000003U)
+#define KEY_SIZE_BIT_SHIFT          (21U)
+#define CERT_INFO_FLG_OFFSET        (0x0000000CU)
+#define KEY_SIZE_4096               (0x00000002U)
+#define KEY_SIZE_3072               (0x00000001U)
+#define KEY_SIZE_2048               (0x00000000U)
+#define WORD_TO_BYTE                (4U)
+#define NOT_OVERLAP_FLAG            (0U)
+#define OVERLAP_FLAG                (1U)
+#define RAM_RANGE_OK                (0U)
+#define RAM_RANGE_NG                (1U)
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
+#define RAM_MAX                     (4U)
+#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+#define RAM_MAX                     (5U)    /* ++ SRAM in RT-VRAM (0xE2000000 - 0xE200FFFF) */
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+#define ADDRESS_RANGE_512           (512U)
+
+static void check_load_area(LOAD_INFO* li);
+static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
+    uint32_t *dest_addr);
+
+void load_image(LOAD_INFO* li)
+{
+    /* log output of load image for information */
+    load_image_info_print_for_emmc(li);
+
+	/* Check transfer range of image. */
+    check_load_area(li);
+
+    /* Image load start. */
+    load_start(li);
+}
+/* End of function load_image(LOAD_INFO* li) */
+
+void load_init(LOAD_INFO* li, uint32_t num)
+{
+    uint32_t  loop;
+    uintptr_t buf;
+    
+    const char *image_name[MAX_PLACED]  = {
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+        [RTOS_ID]           = "RTOS",
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+#ifdef MOBIS_PRK3
+        [CA_OPTIONAL_ID]     = "BL31",
+        [CA_OPTIONAL_ID + 1] = "u-boot",
+        [CA_OPTIONAL_ID + 2] = "tee OS",
+        [CA_OPTIONAL_ID + 3] = "BL2",
+        [CA_OPTIONAL_ID + 4] = "QNX OS",
+#else
+        [CA_OPTIONAL_ID]     = "CA Program #1",
+        [CA_OPTIONAL_ID + 1] = "CA Program #2",
+        [CA_OPTIONAL_ID + 2] = "CA Program #3",
+        [CA_OPTIONAL_ID + 3] = "CA Program #4",
+        [CA_OPTIONAL_ID + 4] = "CA Program #5",
+#endif
+        [CA_OPTIONAL_ID + 5] = "CA Program #6",
+        [CA_OPTIONAL_ID + 6] = "CA Program #7",
+        [CA_OPTIONAL_ID + 7] = "CA Program #8",
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+        [RTOS1_ID]           = "RTOS#1",
+        [RTOS2_ID]           = "RTOS#2",
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+    };
+
+    const uint32_t key_cert[MAX_PLACED]  = {
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+        [RTOS_ID]                  = TFMV_KEY_CERT_ADDR,
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+        [CA_OPTIONAL_ID]           = TFMV_KEY_CERT_ADDR,    /* bl31 */
+#if (RCAR_LSI == RCAR_S4)
+        [CA_OPTIONAL_ID + 1]       = TFMV_KEY_CERT_ADDR,
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+        [CA_OPTIONAL_ID + 1]       = NTFMV_KEY_CERT_ADDR,   /* u-boot */
+#endif
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+        [CA_OPTIONAL_ID + 2]       = NTFMV_KEY_CERT_ADDR,
+#else
+        [CA_OPTIONAL_ID + 2]       = TFMV_KEY_CERT_ADDR,    /* tee OS */
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+#if (BL2_LOAD_ENABLE == BL2_DISABLE)
+        [CA_OPTIONAL_ID + 3]       = NTFMV_KEY_CERT_ADDR,
+#else
+        [CA_OPTIONAL_ID + 3]       = TFMV_KEY_CERT_ADDR,    /* ca76-loader */
+#endif /* BL2_LOAD_ENABLE == BL2_DISABLE */
+        [CA_OPTIONAL_ID + 4]       = NTFMV_KEY_CERT_ADDR,   /* qnx OS */
+        [CA_OPTIONAL_ID + 5]       = NTFMV_KEY_CERT_ADDR,
+        [CA_OPTIONAL_ID + 6]       = NTFMV_KEY_CERT_ADDR,
+        [CA_OPTIONAL_ID + 7]       = NTFMV_KEY_CERT_ADDR,
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+        [RTOS1_ID]                 = TFMV_KEY_CERT_ADDR,
+        [RTOS2_ID]                 = TFMV_KEY_CERT_ADDR,
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+    };
+
+
+    if (num >= 1U && num <= 8U)
+    {
+        /* Set Load info parameter */
+        for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++)
+        {
+            li[loop].name          = image_name[loop];
+            li[loop].key_cert_addr = key_cert[loop];
+            li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
+            get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
+            buf                    = get_src_addr_offset_in_cert(loop);
+            li[loop].src_addr      = (SRC_TOP + mem_read32(buf));
+            buf                    = get_part_num_in_cert(loop);
+            li[loop].part_num      = mem_read32(buf);
+            li[loop].load_id       = loop;
+        }
+    }
+    else
+    {
+        ERROR("load_init(CA program num error).\n");
+        panic;
+    }
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+    li[RTOS_ID].name       = image_name[RTOS_ID];
+    li[RTOS_ID].key_cert_addr  = key_cert[RTOS_ID];
+    li[RTOS_ID].cnt_cert_addr  = get_logic_cont_cert_addr(RTOS_ID);
+    get_info_from_cert(li[RTOS_ID].cnt_cert_addr, &li[RTOS_ID].image_size, &li[RTOS_ID].boot_addr);
+    buf                    = get_src_addr_offset_in_cert(RTOS_ID);
+    li[RTOS_ID].src_addr   = (SRC_TOP + mem_read32(buf));
+    buf                    = get_part_num_in_cert(RTOS_ID);
+    li[RTOS_ID].part_num   = mem_read32(buf);
+    li[RTOS_ID].load_id       = RTOS_ID;
+
+ #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+    /* Set Load info parameter for RTOS#1 and RTOS#2 */
+    for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++)
+    {
+        li[loop].name          = image_name[loop];
+        li[loop].key_cert_addr = key_cert[loop];
+        li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
+        get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
+        buf                    = get_src_addr_offset_in_cert(loop);
+        li[loop].src_addr      = (SRC_TOP + mem_read32(buf));
+        buf                    = get_part_num_in_cert(loop);
+        li[loop].part_num      = mem_read32(buf);
+        li[loop].load_id       = loop;
+    }
+ #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+
+}/* End of function load_init(LOAD_INFO* li) */
+
+void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot)
+{
+    uint32_t  loop;
+
+    /* Set Load info parameter */
+    for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++)
+    {
+        li[loop].part_num      = (slot == 1) ? 2 : 1;
+    }
+    li[RTOS_ID].part_num   = (slot == 1) ? 2 : 1;
+}
+
+static void check_load_area(LOAD_INFO* li)
+{
+    uint32_t src;
+    uint32_t dst;
+    uint32_t len;
+    uint32_t dst_end;
+    uint32_t overlap;
+    uint32_t loop;
+    uint32_t rge_chk_flg;
+    static uint32_t s_num = 1U;
+
+    /* The memory range of destination. */
+    const ADDRESS_RANGE add_list[RAM_MAX] = {
+        [TARGET_MEM_DRAM]   = {DRAM_BASE, DRAM_END},
+        [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END},
+        [TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END},
+        [TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END},
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+        [TARGET_MEM_SRAM_IN_RTVRAM] = {RTVRAM_SRAM_TOP, RTVRAM_SRAM_END},
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+    };
+
+	    /* The image range check */
+    const IMAGE_RANGE size_list[CA_IMAGESIZECHK_DEF] = {
+        { CA_PROGRAM1_ID, CA_PROGRAM1_ADR, CA_PROGRAM1_SIZE},
+        { CA_PROGRAM2_ID, CA_PROGRAM2_ADR, CA_PROGRAM2_SIZE},
+#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
+        { CA_PROGRAM3_ID, CA_PROGRAM3_ADR, CA_PROGRAM3_SIZE},
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
+#if (BL2_LOAD_ENABLE == BL2_ENABLE)
+        { CA_PROGRAM4_ID, CA_PROGRAM4_ADR, CA_PROGRAM4_SIZE},
+#endif  /* BL2_LOAD_ENABLE == BL2_ENABLE */
+#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE)
+        { CA_PROGRAM5_ID, CA_PROGRAM5_ADR, CA_PROGRAM5_SIZE},
+#endif  /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */
+    };
+
+    static ADDRESS_RANGE s_placed_image[MAX_PLACED] = {
+        [0] = {IPL_TOP, IPL_END}
+    };
+
+    
+    src = li->src_addr;
+    dst = li->boot_addr;
+    len = li->image_size;
+    
+    /* Check image size */
+    if (len == 0U)
+    {
+        ERROR("image size error\n");
+        panic;
+    }
+
+    /* Check whether source is overflow */
+    /* INT30-C Pre confirmation */
+    if (src > (UINT32_MAX - len))
+    {
+        ERROR("1:overflow is occurred at source\n");
+        ERROR("1:source address = 0x%x image size = 0x%x\n", (unsigned int)src, (unsigned int)len);
+        panic;
+    }
+
+    /* Check whether destination is overflow */
+    /* INT30-C Pre confirmation */
+    if (dst > (UINT32_MAX - len))
+    {
+        ERROR("1:overflow is occurred at destination\n");
+        ERROR("1:destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
+            (unsigned int)len);
+        panic;
+    }
+    else
+    {
+        dst_end = dst + len - 1U;
+    }
+
+    /* Check source address range. */
+    /* No error check is performed because it is detected by the eMMC device */
+
+    /* Check destination address range. */
+
+    /* 512byte boundary check */
+    if (0U != (dst % ADDRESS_RANGE_512))
+    {
+        ERROR("check_load_area (destination address)\n");
+        ERROR("destination address = 0x%x \n", (unsigned int)dst);
+        panic;
+    }
+
+    /* range check */
+    rge_chk_flg = RAM_RANGE_NG;
+
+    for(loop = 0U; loop < RAM_MAX; loop++)
+    {
+        if (add_list[loop].cx_topadd <= dst)
+        {
+            if(dst_end <= add_list[loop].cx_endadd)
+            {
+                rge_chk_flg = RAM_RANGE_OK;
+                break;
+            }
+        }
+    }
+
+    if(rge_chk_flg != RAM_RANGE_OK)
+    {
+        ERROR("check_load_area (destination address)\n");
+        ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
+        (unsigned int)len);
+        panic;
+    }
+
+    /* Check whether destination is overflow */
+    for (loop = 0U; loop < CA_IMAGESIZECHK_DEF; loop++)
+    {
+        if (li->load_id == size_list[loop].load_id)
+        {
+            if ((size_list[loop].image_adr != 0U) && (dst != size_list[loop].image_adr))
+            {
+                ERROR("check load area.(outside secure area)\n");
+                ERROR("destination address = 0x%x(0x%x) image size = 0x%x\n", (unsigned int)dst,
+                (unsigned int)(size_list[loop].image_adr), (unsigned int)len);
+                panic;
+            }
+            if ((size_list[loop].image_size != 0U) && (len > size_list[loop].image_size))
+            {
+                ERROR("check load area.(outside secure area)\n");
+                ERROR("destination address = 0x%x image size = 0x%x(0x%x)\n", (unsigned int)dst,
+                (unsigned int)len, (unsigned int)(size_list[loop].image_size));
+                panic;
+            }
+       }
+    }
+
+    /* Check there are no overlaps the image that will be loaded and
+       the images that have already loaded.             */
+    overlap = NOT_OVERLAP_FLAG;
+    loop = 0U;
+    do
+    {
+        /* check overlap */
+        if ((dst >= s_placed_image[loop].cx_topadd)
+            && (dst <= s_placed_image[loop].cx_endadd))
+        {
+            overlap = OVERLAP_FLAG;
+        }
+        else if ((dst_end >= s_placed_image[loop].cx_topadd)
+            && (dst_end <= s_placed_image[loop].cx_endadd))
+        {
+            overlap = OVERLAP_FLAG;
+        }
+        else if ((dst < s_placed_image[loop].cx_topadd)
+            && (s_placed_image[loop].cx_endadd < dst_end))
+        {
+            overlap = OVERLAP_FLAG;
+        }
+        else
+        {
+            loop++;
+        }
+    } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG));
+
+    /* Check the overlap flag.
+       Parameter error if overwrite occurred.
+       Otherwise, add parameters of the image to be loaded into
+       Placed_image.                    */
+    if (overlap == NOT_OVERLAP_FLAG)
+    {
+        s_placed_image[s_num].cx_topadd = dst;
+        s_placed_image[s_num].cx_endadd = dst_end;
+        s_num++;
+    }
+    else
+    {
+        ERROR("check load area (overlap)\n");
+        ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, (unsigned int)len);
+        ERROR("overlapped image is [%u]\n", (unsigned int)loop);
+        ERROR("top address = 0x%x end address = 0x%x\n",
+            (unsigned int)s_placed_image[loop].cx_topadd, (unsigned int)s_placed_image[loop].cx_endadd);
+        panic;
+    }
+}
+/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */
+
+static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
+    uint32_t *dest_addr)
+{
+    uint32_t    val;
+    uint32_t    certInfo1;
+    uintptr_t   pSize;
+    uintptr_t   pDestL;
+
+    /* Get key length of content certificate. */
+    val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET);
+    certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK;
+
+    /* Get the transfer address and transfer size from
+       the certificate in accordance with the key length.   */
+    if (KEY_SIZE_4096 == certInfo1)  /* key size = 4096 */
+    {
+        pSize = cert_addr + CERT_INFO_SIZE_OFFSET2;
+        *size = mem_read32(pSize) * WORD_TO_BYTE;
+        pDestL = cert_addr + CERT_INFO_DST_OFFSET2;
+        *dest_addr = mem_read32(pDestL);
+    }
+    else if (KEY_SIZE_3072 == certInfo1)    /* key size = 3072 */
+    {
+        pSize = cert_addr + CERT_INFO_SIZE_OFFSET1;
+        *size = mem_read32(pSize) * WORD_TO_BYTE;
+        pDestL = cert_addr + CERT_INFO_DST_OFFSET1;
+        *dest_addr = mem_read32(pDestL);
+    }
+    else if (KEY_SIZE_2048 == certInfo1)    /* key size = 2048 */
+    {
+        pSize = cert_addr + CERT_INFO_SIZE_OFFSET;
+        *size = mem_read32(pSize) * WORD_TO_BYTE;
+        pDestL = cert_addr + CERT_INFO_DST_OFFSET;
+        *dest_addr = mem_read32(pDestL);
+    }
+    else
+    {
+        ERROR("get_info_from_cert key size error.\n");
+        panic;
+    }
+}
+/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */
+
+void load_start(LOAD_INFO* li)
+{
+    uint32_t rtn_val = EMMC_DEV_ERR;
+    uint32_t sector_count;
+    uint32_t fraction;
+
+    /* Converted to number of sectors transferred. */
+    sector_count = li->image_size >> CX_EMMC_SECTOR_SIZE_SHIFT;
+
+    fraction = li->image_size % CX_EMMC_SECTOR_SIZE;
+    /* Add 1 if there is a fraction */
+    if(0U != fraction)
+    {
+        sector_count += 1U;
+    }
+
+    rtn_val = emmc_trans_data(li->part_num, (uintptr_t)(li->src_addr >> CX_EMMC_SECTOR_SIZE_SHIFT), 
+                    (uintptr_t)li->boot_addr, sector_count);
+
+    if(EMMC_DEV_OK != rtn_val)
+    {
+        ERROR("load_start(emmc_trans_data error).\n");
+        panic;
+    }
+}
+/* End of function load_start(LOAD_INFO* li) */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/access_protection.h

@@ -0,0 +1,37 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2022-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Region ID function header
+ ******************************************************************************/
+
+#ifndef REGION_ID_H__
+#define REGION_ID_H__
+
+#define PROTECTION_DISABLE (0U)
+#define PROTECTION_ENABLE  (1U)
+
+void rgid_protection_check(void);
+void ram_protection_check(void);
+
+#endif	/* REGION_ID_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/android_ab.h

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+
+#ifndef __ANDROID_AB_H
+#define __ANDROID_AB_H
+
+// struct blk_desc;
+// struct disk_partition;
+
+/* Android standard boot slot names are 'a', 'b', 'c', ... */
+#define BOOT_SLOT_NAME(slot_num) ('a' + (slot_num))
+
+/* Number of slots */
+#define NUM_SLOTS 2
+
+/* CX_EMMC_AB_CONTROL from icumx_IPL */
+#define DISK_BUFFER__IPL	(0xEB22E000U)
+#define DISK_BUFFER_ADDR	(0x41DFE000U)
+
+/* pass ab info from Cx_IPL to BL2 */
+#define AB_INFO_FLAG__IPL	(0xEB22FFFCU)
+#define AB_INFO_FLAG_ADDR	(0x41DFFFFCU)
+#define AB_INFO_FLAG_INIT	(0xDEADBEEFU)
+#define AB_INFO_SELECT_1st	(0x00000000U)
+#define AB_INFO_SELECT_2nd	(0x10000000U)
+#define AB_INFO_FLAG_STORE	(0x0BADF00DU)
+#define AB_INFO_FLAG_OK		(0x00FACADEU)
+
+/**
+ * Select the slot where to boot from.
+ *
+ * On Android devices with more than one boot slot (multiple copies of the
+ * kernel and system images) selects which slot should be used to boot from and
+ * registers the boot attempt. This is used in by the new A/B update model where
+ * one slot is updated in the background while running from the other slot. If
+ * the selected slot did not successfully boot in the past, a boot attempt is
+ * registered before returning from this function so it isn't selected
+ * indefinitely.
+ *
+ * @param[in] dev_desc Place to store the device description pointer
+ * @param[in] part_info Place to store the partition information
+ * @return The slot number (>= 0) on success, or a negative on error
+ */
+int ab_select_slot(
+    // struct blk_desc *dev_desc, struct disk_partition *part_info
+    void
+);
+
+#endif /* __ANDROID_AB_H */

IPL/Customer/Mobis/V4H_Cx_Loader/include/android_bootloader_message.h

@@ -0,0 +1,256 @@
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/bootable/recovery
+ * File: bootloader_message/include/bootloader_message/bootloader_message.h
+ * Commit: See U-Boot commit description
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ANDROID_BOOTLOADER_MESSAGE_H
+#define __ANDROID_BOOTLOADER_MESSAGE_H
+
+#ifndef __UBOOT__
+#include <assert.h>
+#include <stddef.h>
+#include <stdint.h>
+#else
+/* compiler.h defines the types that otherwise are included from stdint.h and
+ * stddef.h
+ */
+#include <compiler.h>
+#endif
+
+// Spaces used by misc partition are as below:
+// 0   - 2K     For bootloader_message
+// 2K  - 16K    Used by Vendor's bootloader (the 2K - 4K range may be optionally used
+//              as bootloader_message_ab struct)
+// 16K - 64K    Used by uncrypt and recovery to store wipe_package for A/B devices
+// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
+// are not configurable without changing all of them.
+static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
+static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
+
+/* Bootloader Message (2-KiB)
+ *
+ * This structure describes the content of a block in flash
+ * that is used for recovery and the bootloader to talk to
+ * each other.
+ *
+ * The command field is updated by linux when it wants to
+ * reboot into recovery or to update radio or bootloader firmware.
+ * It is also updated by the bootloader when firmware update
+ * is complete (to boot into recovery for any final cleanup)
+ *
+ * The status field was used by the bootloader after the completion
+ * of an "update-radio" or "update-hboot" command, which has been
+ * deprecated since Froyo.
+ *
+ * The recovery field is only written by linux and used
+ * for the system to send a message to recovery or the
+ * other way around.
+ *
+ * The stage field is written by packages which restart themselves
+ * multiple times, so that the UI can reflect which invocation of the
+ * package it is.  If the value is of the format "#/#" (eg, "1/3"),
+ * the UI will add a simple indicator of that status.
+ *
+ * We used to have slot_suffix field for A/B boot control metadata in
+ * this struct, which gets unintentionally cleared by recovery or
+ * uncrypt. Move it into struct bootloader_message_ab to avoid the
+ * issue.
+ */
+struct bootloader_message {
+    char command[32];
+    char status[32];
+    char recovery[768];
+
+    // The 'recovery' field used to be 1024 bytes.  It has only ever
+    // been used to store the recovery command line, so 768 bytes
+    // should be plenty.  We carve off the last 256 bytes to store the
+    // stage string (for multistage packages) and possible future
+    // expansion.
+    char stage[32];
+
+    // The 'reserved' field used to be 224 bytes when it was initially
+    // carved off from the 1024-byte recovery field. Bump it up to
+    // 1184-byte so that the entire bootloader_message struct rounds up
+    // to 2048-byte.
+    char reserved[1184];
+};
+
+/**
+ * We must be cautious when changing the bootloader_message struct size,
+ * because A/B-specific fields may end up with different offsets.
+ */
+#ifndef __UBOOT__
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message) == 2048,
+              "struct bootloader_message size changes, which may break A/B devices");
+#endif
+#endif /* __UBOOT__ */
+
+/**
+ * The A/B-specific bootloader message structure (4-KiB).
+ *
+ * We separate A/B boot control metadata from the regular bootloader
+ * message struct and keep it here. Everything that's A/B-specific
+ * stays after struct bootloader_message, which should be managed by
+ * the A/B-bootloader or boot control HAL.
+ *
+ * The slot_suffix field is used for A/B implementations where the
+ * bootloader does not set the androidboot.ro.boot.slot_suffix kernel
+ * commandline parameter. This is used by fs_mgr to mount /system and
+ * other partitions with the slotselect flag set in fstab. A/B
+ * implementations are free to use all 32 bytes and may store private
+ * data past the first NUL-byte in this field. It is encouraged, but
+ * not mandatory, to use 'struct bootloader_control' described below.
+ *
+ * The update_channel field is used to store the Omaha update channel
+ * if update_engine is compiled with Omaha support.
+ */
+struct bootloader_message_ab {
+    struct bootloader_message message;
+    char slot_suffix[32];
+    char update_channel[128];
+
+    // Round up the entire struct to 4096-byte.
+    char reserved[1888];
+};
+
+/**
+ * Be cautious about the struct size change, in case we put anything post
+ * bootloader_message_ab struct (b/29159185).
+ */
+#ifndef __UBOOT__
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message_ab) == 4096,
+              "struct bootloader_message_ab size changes");
+#endif
+#endif /* __UBOOT__ */
+
+#define BOOT_CTRL_MAGIC   0x42414342 /* Bootloader Control AB */
+#define BOOT_CTRL_VERSION 1
+
+struct slot_metadata {
+    // Slot priority with 15 meaning highest priority, 1 lowest
+    // priority and 0 the slot is unbootable.
+    uint8_t priority : 4;
+    // Number of times left attempting to boot this slot.
+    uint8_t tries_remaining : 3;
+    // 1 if this slot has booted successfully, 0 otherwise.
+    uint8_t successful_boot : 1;
+    // 1 if this slot is corrupted from a dm-verity corruption, 0
+    // otherwise.
+    uint8_t verity_corrupted : 1;
+    // Reserved for further use.
+    uint8_t reserved : 7;
+} __attribute__((packed));
+
+/* Bootloader Control AB
+ *
+ * This struct can be used to manage A/B metadata. It is designed to
+ * be put in the 'slot_suffix' field of the 'bootloader_message'
+ * structure described above. It is encouraged to use the
+ * 'bootloader_control' structure to store the A/B metadata, but not
+ * mandatory.
+ */
+struct bootloader_control {
+    // NUL terminated active slot suffix.
+    char slot_suffix[4];
+    // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC).
+    uint32_t magic;
+    // Version of struct being used (see BOOT_CTRL_VERSION).
+    uint8_t version;
+    // Number of slots being managed.
+    uint8_t nb_slot : 3;
+    // Number of times left attempting to boot recovery.
+    uint8_t recovery_tries_remaining : 3;
+    // Ensure 4-bytes alignment for slot_info field.
+    uint8_t reserved0[2];
+    // Per-slot information.  Up to 4 slots.
+    struct slot_metadata slot_info[4];
+    // Reserved for further use.
+    uint8_t reserved1[8];
+    // CRC32 of all 28 bytes preceding this field (little endian
+    // format).
+    uint32_t crc32_le;
+} __attribute__((packed));
+
+#ifndef __UBOOT__
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_control) ==
+              sizeof(((struct bootloader_message_ab *)0)->slot_suffix),
+              "struct bootloader_control has wrong size");
+#endif
+#endif /* __UBOOT__ */
+
+#ifndef __UBOOT__
+#ifdef __cplusplus
+
+#include <string>
+#include <vector>
+
+// Return the block device name for the bootloader message partition and waits
+// for the device for up to 10 seconds. In case of error returns the empty
+// string.
+std::string get_bootloader_message_blk_device(std::string* err);
+
+// Read bootloader message into boot. Error message will be set in err.
+bool read_bootloader_message(bootloader_message* boot, std::string* err);
+
+// Read bootloader message from the specified misc device into boot.
+bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device,
+                                  std::string* err);
+
+// Write bootloader message to BCB.
+bool write_bootloader_message(const bootloader_message& boot, std::string* err);
+
+// Write bootloader message to the specified BCB device.
+bool write_bootloader_message_to(const bootloader_message& boot,
+                                 const std::string& misc_blk_device, std::string* err);
+
+// Write bootloader message (boots into recovery with the options) to BCB. Will
+// set the command and recovery fields, and reset the rest.
+bool write_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+// Write bootloader message (boots into recovery with the options) to the specific BCB device. Will
+// set the command and recovery fields, and reset the rest.
+bool write_bootloader_message_to(const std::vector<std::string>& options,
+                                 const std::string& misc_blk_device, std::string* err);
+
+// Update bootloader message (boots into recovery with the options) to BCB. Will
+// only update the command and recovery fields.
+bool update_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+// Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update
+// the command and recovery fields.
+bool update_bootloader_message_in_struct(bootloader_message* boot,
+                                         const std::vector<std::string>& options);
+
+// Clear BCB.
+bool clear_bootloader_message(std::string* err);
+
+// Writes the reboot-bootloader reboot reason to the bootloader_message.
+bool write_reboot_bootloader(std::string* err);
+
+// Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC).
+bool read_wipe_package(std::string* package_data, size_t size, std::string* err);
+
+// Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC).
+bool write_wipe_package(const std::string& package_data, std::string* err);
+
+#else
+
+#include <stdbool.h>
+
+// C Interface.
+bool write_bootloader_message(const char* options);
+bool write_reboot_bootloader(void);
+
+#endif  // ifdef __cplusplus
+#endif  /* __UBOOT__ */
+
+#endif  /* __ANDROID_BOOTLOADER_MESSAGE_H */

IPL/Customer/Mobis/V4H_Cx_Loader/include/axmm_register.h

@@ -0,0 +1,73 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2024 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : AXMM register header
+ ******************************************************************************/
+
+#ifndef AXMM_REGISTER_H__
+#define AXMM_REGISTER_H__
+
+#include <stdint.h>
+
+/* System RAM / SDRAM register base address */
+#define AXMM_BASE           (0xE6780000U)
+
+#define AXMM_DPTDIVCR       (AXMM_BASE + 0x6000U)
+#define AXMM_DPTRGNCR       (AXMM_BASE + 0x6100U)
+#define AXMM_DPTSECCR       (AXMM_BASE + 0x6200U)
+#define AXMM_SPTDIVCR       (AXMM_BASE + 0x6300U)
+#define AXMM_SPTRGNCR       (AXMM_BASE + 0x6400U)
+#define AXMM_SPTSECCR       (AXMM_BASE + 0x6500U)
+
+static inline uint32_t get_dptdivcr_addr(uint32_t num)
+{
+    return ((AXMM_DPTDIVCR + (num * 4U)));
+}
+
+static inline uint32_t get_dptrgncr_addr(uint32_t num)
+{
+    return ((AXMM_DPTRGNCR + (num * 4U)));
+}
+
+static inline uint32_t get_dptseccr_addr(uint32_t num)
+{
+    return ((AXMM_DPTSECCR + (num * 4U)));
+}
+
+static inline uint32_t get_sptdivcr_addr(uint32_t num)
+{
+    return ((AXMM_SPTDIVCR + (num * 4U)));
+}
+
+static inline uint32_t get_sptrgncr_addr(uint32_t num)
+{
+    return ((AXMM_SPTRGNCR + (num * 4U)));
+}
+
+static inline uint32_t get_sptseccr_addr(uint32_t num)
+{
+    return ((AXMM_SPTSECCR + (num * 4U)));
+}
+
+#endif  /* AXMM_REGISTER_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h

@@ -0,0 +1,126 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Configuration table header
+ ******************************************************************************/
+
+#ifndef CNF_TBL_H_
+#define CNF_TBL_H_
+
+#include <stdint.h>
+
+typedef struct{
+    uint64_t fix;
+    uint64_t be;
+} QOS_SETTING_TABLE;
+
+typedef struct{
+    uint32_t phys_addr; /* Physical address of Region ID registers. */
+    uint32_t value;     /* setting value of Region ID registers. */
+} REGION_ID_SETTING_TABLE;
+
+/* For RAM protection table */
+typedef struct {
+    uint32_t rw_val;
+    uint32_t sec_val;
+}RAM_PROTECTION_VALUE_FORMAT;
+
+typedef struct {
+    uint32_t read_val;
+    uint32_t write_val;
+}RTRAM_PROTECTION_VALUE_FORMAT;
+
+typedef struct {
+    uint32_t addr;
+    RTRAM_PROTECTION_VALUE_FORMAT setting_value;
+}RTRAM_PROTECTION_STRUCTUR;
+
+typedef struct {
+    uint32_t addr;
+    RAM_PROTECTION_VALUE_FORMAT setting_value;
+}SYSTEM_RAM_PROTECTION_STRUCTUR;
+
+typedef struct {
+    uint64_t addr;
+    RAM_PROTECTION_VALUE_FORMAT setting_value;
+}DRAM_PROTECTION_STRUCTUR;
+
+
+#if (RCAR_LSI == RCAR_S4)
+#define QOS_TBL_MAX     (48U)   /* Max setting number of QoS Bank registers. */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define QOS_TBL_MAX     (125U)  /* Max setting number of QoS Bank registers. */
+#endif /* RCAR_LSI == RCAR_S4 */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define RGID_MASTER_MAX (77U)   /* Max number of Region registers. (Master) */
+#define RGID_READ_MAX   (908U)  /* Max number of Region registers. (Read)   */
+#define RGID_WRITE_MAX  (907U)  /* Max number of Region registers. (Write)  */
+#define RGID_SEC_MAX    (957U)  /* Max number of Region registers. (Secure) */
+#define RGID_AXI_MAX    (98U)   /* Max number of Region registers. (Read/Write for AXI-bus)  */
+#elif (RCAR_LSI == RCAR_V4M)
+#define RGID_MASTER_MAX (85U)   /* Max number of Region registers. (Master) */
+#define RGID_READ_MAX   (805U)  /* Max number of Region registers. (Read)   */
+#define RGID_WRITE_MAX  (804U)  /* Max number of Region registers. (Write)  */
+#define RGID_SEC_MAX    (819U)  /* Max number of Region registers. (Secure) */
+#define RGID_AXI_MAX    (90U)   /* Max number of Region registers. (Read/Write for AXI-bus)  */
+#endif /* RCAR_LSI == RCAR_V4H */
+
+#define RAM_PROTECTION_MAX       (16U)   /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */
+#define DRAM_PROTECTION_MAX      (64U)   /* Max number of RAM Protection registers. (SDRAM) */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define IMP_MASTER_MAX  (19U)
+#define IMP_SLAVE_MAX   (38U)
+#endif /* (RCAR_LSI == RCAR_V4H) */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define IPMMU_RGID_MAX  (11U)
+#elif (RCAR_LSI == RCAR_V4M)
+#define IPMMU_RGID_MAX  (10U)
+#endif /* (RCAR_LSI == RCAR_V4H) */
+
+extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX];
+extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX];
+
+extern const REGION_ID_SETTING_TABLE g_rgid_master_tbl[RGID_MASTER_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_read_tbl[RGID_READ_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_write_tbl[RGID_WRITE_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX];
+#if (RCAR_LSI == RCAR_V4H)
+extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX];
+extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX];
+#endif /* (RCAR_LSI == RCAR_V4H) */
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX];
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX];
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX];
+
+/* For RAM protection */
+extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX];
+extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX];
+extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX];
+extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX];
+
+#endif /* CNF_TBL_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/cpu_on.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : cpu on function header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          cpu_on.h
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 17.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *         : 09.12.2024 0.03     Remove OTP_MEM_OTPMONITOR60 register.
+ *         : 19.12.2024 0.04     Add definition for booting CR52 core 2.
+*****************************************************************************/
+
+#ifndef CPU_ON_H__
+#define CPU_ON_H__
+
+#define RCAR_PWR_TARGET_CR    (0U)
+#define RCAR_PWR_TARGET_CA    (1U)
+
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id);
+void adj_ca_variant_freq(void);
+
+#define OTP_MEM_1_BASE               (0xE61BF000U)
+#define OTP_MEM_OTPMONITOR17         (OTP_MEM_1_BASE + 0x0144U)
+#define OTP_MEM_PRODUCT_MASK         (0x000000FFU)
+#if (RCAR_LSI == RCAR_V4H)
+#define VARIANT_V4H_7                (0x00U)
+#define VARIANT_V4H_5                (0x01U)
+#define VARIANT_V4H_3                (0x02U)
+#elif (RCAR_LSI == RCAR_V4M)
+#define VARIANT_V4M_7                (0x00U)
+#define VARIANT_V4M_5                (0x01U)
+#define VARIANT_V4M_3                (0x02U)
+#define VARIANT_V4M_2                (0x04U)
+#endif /* RCAR_LSI == RCAR_V4H */
+
+#endif /* CPU_ON_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/crc.h

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _UBOOT_CRC_H
+#define _UBOOT_CRC_H
+
+// #include <compiler.h> /* 'uint*' definitions */
+typedef unsigned int	uint;
+
+/**
+ * crc32 - Calculate the CRC32 for a block of data
+ *
+ * @crc: Input crc to chain from a previous calculution (use 0 to start a new
+ *	calculation)
+ * @buf: Bytes to checksum
+ * @len: Number of bytes to checksum
+ * @return checksum value
+ */
+uint32_t crc32(uint32_t crc, const unsigned char *buf, uint len);
+
+/**
+ * crc32_no_comp - Calculate the CRC32 for a block of data (no one's compliment)
+ *
+ * This version uses a different algorithm which doesn't use one's compliment.
+ * JFFS2 (and other things?) use this.
+ *
+ * @crc: Input crc to chain from a previous calculution (use 0 to start a new
+ *	calculation)
+ * @buf: Bytes to checksum
+ * @len: Number of bytes to checksum
+ * @return checksum value
+ */
+uint32_t crc32_no_comp(uint32_t crc, const unsigned char *buf, uint len);
+
+#endif /* _UBOOT_CRC_H */

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_boot.h

@@ -0,0 +1,46 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc boot header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_boot.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_BOOT_
+#define EMMC_BOOT_
+
+void emmc_initialize( void );
+
+#endif /* EMMC_BOOT_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_config.h

@@ -0,0 +1,68 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc config header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_config.h
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 18.03.2022 0.02     Delete unnecessary define
+ *                               Delete unnecessary include file
+ *         : 31.10.2022 0.03     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_CONFIG_H__
+#define EMMC_CONFIG_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/* MMC driver config */
+#define EMMC_RCA                        (1U)                /* RCA  */
+#define EMMC_RW_DATA_TIMEOUT            (0x40U)             /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17)  */
+#define EMMC_CMD_MAX                    (60U)               /* Don't change. */
+
+/* etc */
+#define LOADIMAGE_FLAGS_DMA_ENABLE      (0x00000001U)
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif  /* #ifndef EMMC_CONFIG_H__ */
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_def.h

@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc def header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_def.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_DEF_H__
+#define EMMC_DEF_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include "emmc_std.h"
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+extern st_mmc_base mmc_drv_obj;
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* eMMC driver API */
+EMMC_ERROR_CODE emmc_init(void);
+void import_mmc_drv_obj(void);
+void export_mmc_drv_obj(void);
+EMMC_ERROR_CODE emmc_terminate(void);
+EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode);
+EMMC_ERROR_CODE emmc_mount(void);
+EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq);
+EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg);
+EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id);
+EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags);
+uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom);
+
+
+/* interrupt service */
+uint32_t emmc_interrupt(void);
+
+
+/* send command API */
+EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response);
+void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg);
+void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual,
+            uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
+EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg);
+
+/* ********************************* CODE ********************************** */
+
+#endif /* #define EMMC_DEF_H__ */
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_hal.h

@@ -0,0 +1,175 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc HW Layer header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_hal.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_HAL_H__
+#define EMMC_HAL_H__
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include <types.h>
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+/* Memory card response types  */
+#define HAL_MEMCARD_COMMAND_INDEX_MASK      (0x0003fU)
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* memory access operation */
+typedef enum
+{
+    HAL_MEMCARD_READ    = 0U,    /**< read */
+    HAL_MEMCARD_WRITE   = 1U     /**< write */
+} HAL_MEMCARD_OPERATION;
+
+/* Type of data width on memorycard bus */
+typedef enum
+{
+    HAL_MEMCARD_DATA_WIDTH_1_BIT    = 0U,
+    HAL_MEMCARD_DATA_WIDTH_4_BIT    = 1U,
+    HAL_MEMCARD_DATA_WIDTH_8_BIT    = 2U
+} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
+
+/* mode of data transfer */
+typedef enum
+{
+    HAL_MEMCARD_DMA         = 0U,
+    HAL_MEMCARD_NOT_DMA     = 1U
+} HAL_MEMCARD_DATA_TRANSFER_MODE;
+
+
+/* Memory card response types. */
+typedef enum hal_memcard_response_type
+{
+    HAL_MEMCARD_RESPONSE_NONE       = 0x00000U,
+    HAL_MEMCARD_RESPONSE_R1         = 0x00100U,
+    HAL_MEMCARD_RESPONSE_R1b        = 0x00200U,
+    HAL_MEMCARD_RESPONSE_R2         = 0x00300U,
+    HAL_MEMCARD_RESPONSE_R3         = 0x00400U,
+    HAL_MEMCARD_RESPONSE_R4         = 0x00500U,
+    HAL_MEMCARD_RESPONSE_R5         = 0x00600U,
+    HAL_MEMCARD_RESPONSE_R6         = 0x00700U,
+    HAL_MEMCARD_RESPONSE_R7         = 0x00800U,
+    HAL_MEMCARD_RESPONSE_TYPE_MASK  = 0x00f00U
+} HAL_MEMCARD_RESPONSE_TYPE;
+
+
+/* Memory card command types. */
+typedef enum hal_memcard_command_type
+{
+    HAL_MEMCARD_COMMAND_TYPE_BC         = 0x00000U,
+    HAL_MEMCARD_COMMAND_TYPE_BCR        = 0x01000U,
+    HAL_MEMCARD_COMMAND_TYPE_AC         = 0x02000U,
+    HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
+    HAL_MEMCARD_COMMAND_TYPE_ADTC_READ  = 0x04000U,
+    HAL_MEMCARD_COMMAND_TYPE_MASK       = 0x07000U
+} HAL_MEMCARD_COMMAND_TYPE;
+
+/* Type of memory card */
+typedef enum hal_memcard_command_card_type
+{
+    HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON    = 0x00000U,
+    HAL_MEMCARD_COMMAND_CARD_TYPE_MMC       = 0x08000U,
+    HAL_MEMCARD_COMMAND_CARD_TYPE_SD        = 0x10000U,
+    HAL_MEMCARD_COMMAND_CARD_TYPE_MASK      = 0x18000U
+} HAL_MEMCARD_COMMAND_CARD_TYPE;
+
+/* Memory card application command. */
+typedef enum hal_memcard_command_app_norm
+{
+HAL_MEMCARD_COMMAND_NORMAL          = 0x00000U,
+HAL_MEMCARD_COMMAND_APP             = 0x20000U,
+HAL_MEMCARD_COMMAND_APP_NORM_MASK   = 0x20000U
+} HAL_MEMCARD_COMMAND_APP_NORM;
+
+
+/* Memory card command codes. */
+typedef enum
+{
+/* class 0 and class 1 */
+    CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
+    CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
+    CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
+    CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+    CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
+    CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+    CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
+    CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
+    CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
+    CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+    ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+    CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
+    CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
+    CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
+    CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
+    CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+    CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
+    CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
+    CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
+    CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
+    CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */
+    CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
+    ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+    CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
+    CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
+
+/* class 2 */
+    CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
+    CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
+    CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
+    CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
+/* class 3 */
+    CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
+    CMD21 = 21, /* CMD21 */
+    CMD22 = 22, /* CMD22 */
+    ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+
+/* class 4 */
+    CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */
+
+} HAL_MEMCARD_COMMAND;
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif  /* EMMC_HAL_H__ */
+
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_multiboot.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc multi boot header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_multiboot.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_MULTIBOOT_H_
+#define EMMC_MULTIBOOT_H_
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+/* EMMC */
+#define EMMC_DEV_OK                         (0x525F4F4BU)       /* "R_OK" */
+#define EMMC_DEV_ERR                        (0xFFFFFFFFU)
+#define EMMC_DEV_ERR_HW                     (0x00000004U)
+#define EMMC_DEV_ERR_FAULT_INJECTION        (0x00000005U)
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize);
+/* ******************************** END ************************************ */
+#endif /* #ifndef EMMC_MULTIBOOT_H_*/

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h

@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc register header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_register.h
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 24.10.2022 0.02     SDIF_MODE register to support HS200/400
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 07.06.2024 0.04     Modify the transfer end bit of DMAC channel.
+ *****************************************************************************/
+
+#ifndef EMMC_REGISTERS_H__
+#define EMMC_REGISTERS_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include <rcar_register.h>
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+/* MMC0 channel */
+#define MMC0_SD_BASE        (BASE_MMC0_ADDR)            /* reg addr is 0xEE140000U */
+
+#define SD_CMD              (MMC0_SD_BASE + 0x0000U)
+#define SD_ARG              (MMC0_SD_BASE + 0x0010U)
+#define SD_STOP             (MMC0_SD_BASE + 0x0020U)
+#define SD_SECCNT           (MMC0_SD_BASE + 0x0028U)
+#define SD_RSP10            (MMC0_SD_BASE + 0x0030U)
+#define SD_RSP32            (MMC0_SD_BASE + 0x0040U)
+#define SD_RSP54            (MMC0_SD_BASE + 0x0050U)
+#define SD_RSP76            (MMC0_SD_BASE + 0x0060U)
+#define SD_INFO1            (MMC0_SD_BASE + 0x0070U)
+#define SD_INFO2            (MMC0_SD_BASE + 0x0078U)
+#define SD_INFO1_MASK       (MMC0_SD_BASE + 0x0080U)
+#define SD_INFO2_MASK       (MMC0_SD_BASE + 0x0088U)
+#define SD_CLK_CTRL         (MMC0_SD_BASE + 0x0090U)
+#define SD_SIZE             (MMC0_SD_BASE + 0x0098U)
+#define SD_OPTION           (MMC0_SD_BASE + 0x00A0U)
+#define SD_ERR_STS1         (MMC0_SD_BASE + 0x00B0U)
+#define SD_ERR_STS2         (MMC0_SD_BASE + 0x00B8U)
+#define SD_BUF0             (MMC0_SD_BASE + 0x00C0U)
+#define CC_EXT_MODE         (MMC0_SD_BASE + 0x0360U)
+#define SOFT_RST            (MMC0_SD_BASE + 0x0380U)
+#define HOST_MODE           (MMC0_SD_BASE + 0x0390U)
+#define SDIF_MODE           (MMC0_SD_BASE + 0x0398U)
+#define DM_CM_DTRAN_MODE    (MMC0_SD_BASE + 0x0820U)
+#define DM_CM_DTRAN_CTRL    (MMC0_SD_BASE + 0x0828U)
+#define DM_CM_INFO1         (MMC0_SD_BASE + 0x0840U)
+#define DM_CM_INFO1_MASK    (MMC0_SD_BASE + 0x0848U)
+#define DM_CM_INFO2         (MMC0_SD_BASE + 0x0850U)
+#define DM_CM_INFO2_MASK    (MMC0_SD_BASE + 0x0858U)
+#define DM_DTRAN_ADDR       (MMC0_SD_BASE + 0x0880U)
+#define SCC_DTCNTL          (MMC0_SD_BASE + 0x1000U)
+#define SCC_TAPSET          (MMC0_SD_BASE + 0x1008U)
+#define SCC_DT2FF           (MMC0_SD_BASE + 0x1010U)
+#define SCC_CKSEL           (MMC0_SD_BASE + 0x1018U)
+#define SCC_SMPCMP          (MMC0_SD_BASE + 0x1030U)
+#define SCC_TMPPORT2        (MMC0_SD_BASE + 0x1038U)
+
+/* SD_INFO1 Registers */
+#define SD_INFO1_INFO2              (0x00000004U)       /* Access end*/
+#define SD_INFO1_INFO0              (0x00000001U)       /* Response end*/
+
+/* SD_INFO2 Registers */
+#define SD_INFO2_CBSY               (0x00004000U)       /* Command Type Register Busy*/
+#define SD_INFO2_BWE                (0x00000200U)       /* SD_BUF Write Enable*/
+#define SD_INFO2_BRE                (0x00000100U)       /* SD_BUF Read Enable*/
+#define SD_INFO2_DAT0               (0x00000080U)       /* SDDAT0*/
+#define SD_INFO2_ALL_ERR            (0x0000807FU)
+#define SD_INFO2_CLEAR              (0x00000800U)       /* BIT11 The write value should always be 1. HWM_0003 */
+
+/* DM_INFO1 Registers */
+#define DM_CM_INFO_DTRANEND0        (0x00010000U)       /* DMAC Channel 0 Transfer End */
+#define DM_CM_INFO_DTRANEND1        (0x00100000U)       /* DMAC Channel 1 Transfer End */
+
+/* DM_INFO2 Registers */
+#define DM_CM_INFO2_DTRANEND0        (0x00010000U)       /* DMAC Channel 0 Error */
+#define DM_CM_INFO2_DTRANEND1        (0x00020000U)       /* DMAC Channel 1 Error */
+
+/* SOFT_RST */
+#define SOFT_RST_SDRST              (0x00000001U)
+
+/* SD_CLK_CTRL */
+#define SD_CLK_CTRL_CLKDIV_MASK     (0x000000FFU)
+#define SD_CLK_WRITE_MASK           (0x000003FFU)
+
+/* SD_OPTION */
+#define SD_OPTION_WIDTH             (0x00008000U)
+#define SD_OPTION_WIDTH8            (0x00002000U)
+#define SD_OPTION_TIMEOUT_CNT_MASK  (0x000000F0U)
+
+
+/* MMC Clock Frequency
+* 200MHz * 1/x = output clock
+*/
+#define MMC_400KHZ                  (512U)              /* 200MHz * 1/512 = 390 KHz */
+#define MMC_20MHZ                   (16U)               /* 200MHz * 1/16  = 12.5 MHz Normal speed mode*/
+#define MMC_26MHZ                   (8U)                /* 200MHz * 1/8   = 25 MHz High speed mode 26Mhz*/
+#define MMC_52MHZ                   (4U)                /* 200MHz * 1/4   = 50 MHz High speed mode 52Mhz*/
+#define MMC_200MHZ                  (1U)                /* 200MHz * 1/1   = 200 MHz HS200/HS400 mode 200Mhz*/
+
+#define MMC_FREQ_52MHZ              (52000000U)
+#define MMC_FREQ_26MHZ              (26000000U)
+#define MMC_FREQ_20MHZ              (20000000U)
+
+/* MMC Clock DIV */
+#define MMC_SD_CLK_START            (0x00000100U)       /* CLOCK On     */
+#define MMC_SD_CLK_STOP             (~0x00000100UL)     /* CLOCK stop   */
+
+/* DM_CM_DTRAN_MODE */
+#define DM_CM_DTRAN_MODE_CH0        (0x00000000U)       /* CH0 : downstream*/
+#define DM_CM_DTRAN_MODE_CH1        (0x00010000U)       /* CH1 : upstream*/
+#define DM_CM_DTRAN_MODE_BIT_WIDTH  (0x00000030U)
+
+/* CC_EXT_MODE */
+#define CC_EXT_MODE_DMASDRW_ENABLE  (0x00000002U)       /* SD_BUF Read/Write DMA Transfer */
+#define CC_EXT_MODE_CLEAR           (0x00001010U)       /* BIT 12 & 4 always 1. */
+
+/* DM_CM_INFO_MASK */
+#define DM_CM_INFO_MASK_CLEAR       (0xFFEEFEFEU)
+#define DM_CM_INFO_CH0_ENABLE       (0x00010001U)
+#define DM_CM_INFO_CH1_ENABLE       (0x00100001U)
+
+/* DM_CM_INFO2_MASK */
+#define DM_CM_INFO2_MASK_CLEAR      (0xFFFCFFFEU)
+#define DM_CM_INFO2_CH0_ENABLE      (0x00010001U)
+#define DM_CM_INFO2_CH1_ENABLE      (0x00020001U)
+
+/* DM_DTRAN_ADDR */
+#define DM_DTRAN_ADDR_WRITE_MASK    (0xFFFFFFF8U)
+
+/*DM_CM_DTRAN_CTRL */
+#define DM_CM_DTRAN_CTRL_START      (0x00000001U)
+
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif /* EMMC_REGISTERS_H__ */
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h

@@ -0,0 +1,312 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc std header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_std.h
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 24.10.2022 0.02     Add supports for HS200/400
+ *         : 31.10.2022 0.03     License notation change.
+ *****************************************************************************/
+
+#ifndef EMMC_STD_H__
+#define EMMC_STD_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/*CSD register Macros */
+#define EMMC_CSD_SPEC_VARS()        (emmc_bit_field(mmc_drv_obj.csd_data, 125,122))
+#define EMMC_CSD_TRAN_SPEED()       (emmc_bit_field(mmc_drv_obj.csd_data, 103,96))
+
+/* for sector access */
+#define EMMC_SECTOR_SIZE_SHIFT      (9U)        /* 512 = 2^9 */
+#define EMMC_SECTOR_PADD_MASK       ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U)
+#define EMMC_SECTOR_SIZE            (512U)
+#define EMMC_BLOCK_LENGTH           (512U)
+#define EMMC_BLOCK_LENGTH_DW        (128U)
+
+/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
+typedef enum
+{
+    EMMC_ERR                    = 0U,           /**< unknown error */
+    EMMC_SUCCESS                ,               /**< OK */
+    EMMC_ERR_FROM_DMAC          ,               /**< DMAC allocation error */
+    EMMC_ERR_FROM_DMAC_TRANSFER ,               /**< DMAC transfer error */
+    EMMC_ERR_CARD_STATUS_BIT    ,               /**< card status error. Non-masked error bit was set in the card status */
+    EMMC_ERR_CMD_TIMEOUT        ,               /**< command timeout error */
+    EMMC_ERR_DATA_TIMEOUT       ,               /**< data timeout error */
+    EMMC_ERR_CMD_CRC            ,               /**< command CRC error */
+    EMMC_ERR_DATA_CRC           ,               /**< data CRC error */
+    EMMC_ERR_PARAM              ,               /**< parameter error */
+    EMMC_ERR_RESPONSE           ,               /**< response error */
+    EMMC_ERR_RESPONSE_BUSY      ,               /**< response busy error */
+    EMMC_ERR_TRANSFER           ,               /**< data transfer error */
+    EMMC_ERR_READ_SECTOR        ,               /**< read sector error */
+    EMMC_ERR_WRITE_SECTOR       ,               /**< write sector error */
+    EMMC_ERR_STATE              ,               /**< state error */
+    EMMC_ERR_TIMEOUT            ,               /**< timeout error */
+    EMMC_ERR_ILLEGAL_CARD       ,               /**< illegal card */
+    EMMC_ERR_CARD_BUSY          ,               /**< Busy state */
+    EMMC_ERR_CARD_STATE         ,               /**< card state error */
+    EMMC_ERR_SET_TRACE          ,               /**< trace information error */
+    EMMC_ERR_FROM_TIMER         ,               /**< Timer error */
+    EMMC_ERR_FORCE_TERMINATE    ,               /**< Force terminate */
+    EMMC_ERR_CARD_POWER         ,               /**< card power fail */
+    EMMC_ERR_ERASE_SECTOR       ,               /**< erase sector error */
+    EMMC_ERR_INFO2              ,               /**< exec cmd error info2 */
+    RCAR_ERR                                    /**< Error judged by R-Car register */
+
+} EMMC_ERROR_CODE;
+
+/* Error code judged by R-car register or eMMC return*/
+#define EMMC_TUNING_FAIL                    (0U)                /* Fail judged by eMMC return*/
+#define TUNING_SUCCESS                      (1U)                /* Tuning success */
+#define RCAR_TUNING_FAIL                    (2U)                /* Fail judged by R-car register*/
+
+/* Response */
+/** R1 */
+#define EMMC_R1_ERROR_MASK                  (0xFDBFE080U)        /* Type 'E' bit and bit14(must be 0). ignore bit22 */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC      (0xFD3FE080U)        /* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_STATE_MASK                  (0x00001E00U)        /* [12:9] */
+#define EMMC_R1_READY                       (0x00000100U)        /* bit8 */
+#define EMMC_R1_STATE_SHIFT                 (9U)
+
+/** R4 */
+#define EMMC_R4_STATUS                      (0x00008000U)
+
+/** CSD */
+#define EMMC_TRANSPEED_FREQ_UNIT_MASK       (0x07U)             /* bit[2:0] */
+#define EMMC_TRANSPEED_MULT_MASK            (0x78U)             /* bit[6:3] */
+#define EMMC_TRANSPEED_MULT_SHIFT           (3U)
+
+/** OCR */
+#define EMMC_HOST_OCR_VALUE                 (0x40FF8080U)
+#define EMMC_OCR_STATUS_BIT                 (0x80000000U)       /* Card power up status bit */
+#define EMMC_OCR_ACCESS_MODE_MASK           (0x60000000U)       /* bit[30:29] */
+#define EMMC_OCR_ACCESS_MODE_SECT           (0x40000000U)
+
+/** EXT_CSD */
+#define EMMC_EXT_CSD_CARD_TYPE              (196U)
+#define EMMC_EXT_CSD_PARTITION_CONFIG       (179U)
+#define EMMC_EXT_CSD_PWR_CL_DDR_200_360     (253U)              /* Power class for 200MHz, DDR at VCC= 3.6V */
+#define EMMC_EXT_CSD_PWR_CL_200_195         (237U)              /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */
+#define EMMC_EXT_CSD_PWR_CL_26_195          (201U)              /* Power class for 26MHz at 1.95V 1 R */
+#define EMMC_EXT_CSD_PWR_CL_52_195          (200U)              /* Power class for 52MHz at 1.95V 1 R */
+
+#define EMMC_EXT_CSD_CARD_TYPE_26MHZ        (0x01U)
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ        (0x02U)
+#define EMMC_EXT_CSD_CARD_TYPE_200MHZ       (0x10U)
+#define EMMC_EXT_CSD_CARD_TYPE_400MHZ       (0x40U)
+
+/** SWITCH (CMD6) argument */
+#define EXTCSD_ACCESS_BYTE              (0x03000000U)           /* H'03000000 */
+
+#define BUS_WIDTH_ADD                   (183U<<16U)             /* H'00b70000 */
+#define HS_TIMING_ADD                   (185U<<16U)             /* H'00b90000 */
+#define POW_CLASS_ADD                   (187U<<16U)             /* H'00bb0000 */
+
+#define BUS_WIDTH_1                     (0U<<8U)                /* H'00000000 */
+#define BUS_WIDTH_8                     (2U<<8U)                /* H'00000200 */
+#define BUS_WIDTH_8_DDR                 (6U<<8U)                /* H'00000400 */
+
+#define HS_TIMING_1                     (1U<<8U)                /* H'00000100 */
+#define HS_TIMING_HS200                 (2U<<8U)                /* H'00000200 */
+#define HS_TIMING_HS400                 (3U<<8U)                /* H'00000300 */
+
+#define EMMC_SWITCH_HS_TIMING           (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1)          /**< H'03b90100 */
+#define EMMC_SWITCH_HS200               (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200)      /**< H'03b90200 */
+#define EMMC_SWITCH_HS400               (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400)      /**< H'03b90300 */
+
+#define EMMC_SWITCH_BUS_WIDTH_1         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1)          /**< H'03b70000 */
+#define EMMC_SWITCH_BUS_WIDTH_8_DDR     (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR)      /**< H'03b70600 */
+
+
+#define EMMC_SWITCH_PARTITION_CONFIG    (0x03B30000UL)          /**< Partition config = 0x00 */
+
+/** for st_mmc_base */
+#define EMMC_MAX_RESPONSE_LENGTH        (17U)
+#define EMMC_MAX_CID_LENGTH             (16U)
+#define EMMC_MAX_CSD_LENGTH             (16U)
+#define EMMC_MAX_EXT_CSD_LENGTH         (512U)
+
+/* speed mode */
+#define TIMING_HIGH_SPEED_OFF           (0U)
+#define TIMING_HIGH_SPEED               (1U)
+#define TIMING_HS200                    (2U)
+#define TIMING_HS400                    (3U)
+
+/* MMC Clock Frequency */
+/* 200MHz * 1/x = output clock */
+#define HS400_50MHZ                     (8U)                /* 400MHz * 1/8   = 50MHz */
+#define HS400_200MHZ                    (2U)                /* 400MHz * 1/2   = 200MHz */
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* Partition id */
+typedef enum
+{
+    PARTITION_ID_USER   = 0x0,                          /**< User Area */
+    PARTITION_ID_BOOT_1 = 0x1,                          /**< boot partition 1 */
+    PARTITION_ID_BOOT_2 = 0x2,                          /**< boot partition 2 */
+    PARTITION_ID_RPMB   = 0x3,                          /**< Replay Protected Memory Block */
+    PARTITION_ID_GP_1   = 0x4,                          /**< General Purpose partition 1 */
+    PARTITION_ID_GP_2   = 0x5,                          /**< General Purpose partition 2 */
+    PARTITION_ID_GP_3   = 0x6,                          /**< General Purpose partition 3 */
+    PARTITION_ID_GP_4   = 0x7,                          /**< General Purpose partition 4 */
+    PARTITION_ID_MASK   = 0x7                           /**< [2:0] */
+} EMMC_PARTITION_ID;
+
+/* card state in R1 response [12:9] */
+typedef enum
+{
+    EMMC_R1_STATE_IDLE  = 0,
+    EMMC_R1_STATE_READY,
+    EMMC_R1_STATE_IDENT,
+    EMMC_R1_STATE_STBY,
+    EMMC_R1_STATE_TRAN,
+    EMMC_R1_STATE_DATA,
+    EMMC_R1_STATE_RCV,
+    EMMC_R1_STATE_PRG,
+    EMMC_R1_STATE_DIS,
+    EMMC_R1_STATE_BTST,
+    EMMC_R1_STATE_SLEP
+} EMMC_R1_STATE;
+
+typedef enum{
+    ESTATE_BEGIN = 0,
+    ESTATE_ISSUE_CMD,
+    ESTATE_NON_RESP_CMD,
+    ESTATE_RCV_RESP,
+    ESTATE_RCV_RESPONSE_BUSY,
+    ESTATE_CHECK_RESPONSE_COMPLETE,
+    ESTATE_DATA_TRANSFER,
+    ESTATE_DATA_TRANSFER_COMPLETE,
+    ESTATE_ACCESS_END,
+    ESTATE_TRANSFER_ERROR,
+    ESTATE_ERROR,
+    ESTATE_END
+}EMMC_INT_STATE;
+
+/* eMMC boot driver error information */
+typedef struct
+{
+    volatile uint32_t info1;                                /**< SD_INFO1 register value. (hardware dependence) */
+    volatile uint32_t info2;                                /**< SD_INFO2 register value. (hardware dependence) */
+    volatile uint32_t status1;                              /**< SD_ERR_STS1 register value. (hardware dependence) */
+    volatile uint32_t status2;                              /**< SD_ERR_STS2 register value. (hardware dependence) */
+    volatile uint32_t dm_info1;                             /**< DM_CM_INFO1 register value. (hardware dependence) */
+    volatile uint32_t dm_info2;                             /**< DM_CM_INFO2 register value. (hardware dependence) */
+} st_error_info;
+
+
+/* Command information */
+typedef struct
+{
+    HAL_MEMCARD_COMMAND cmd;                                /**< Command information */
+    uint32_t arg;                                           /**< argument */
+    HAL_MEMCARD_OPERATION dir;                              /**< direction */
+    uint32_t hw;                                            /**< H/W dependence. SD_CMD register value. */
+} st_command_info;
+
+
+/* MMC driver base */
+typedef struct
+{
+    st_error_info error_info;                               /**< error information */
+    st_command_info cmd_info;                               /**< command information */
+
+    /* for data transfer */
+    uint32_t *buff_address_virtual;                         /**< Dest or Src buff */
+    uint32_t *buff_address_physical;                        /**< Dest or Src buff */
+    HAL_MEMCARD_DATA_WIDTH bus_width;                       /**< bus width */
+    uint32_t trans_size;                                    /**< transfer size for this command */
+    uint32_t remain_size;                                   /**< remain size for this command */
+    uint32_t response_length;                               /**< response length for this command */
+
+    /* clock */
+    uint32_t max_freq;                                      /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
+    uint32_t current_freq;                                  /**< current MMC clock[Hz] (the closest frequency supported by HW) */
+    uint32_t set_freq;                                      /**< Frequency to be set. */
+
+    /* state flag */
+    uint32_t card_power_enable;                             /**< True : Power ON */
+    uint32_t clock_enable;                                  /**< True : Clock ON */
+    uint32_t initialize;                                    /**< True : initialize complete. */
+    uint32_t mount;                                         /**< True : mount complete. */
+    uint32_t selected;                                      /**< True : selected card. */
+    HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;           /**< 0: DMA, 1:PIO */
+    EMMC_R1_STATE current_state;                            /**< card state */
+    volatile uint32_t during_transfer;                      /**< True : during transfer */
+    volatile uint32_t during_dma_transfer;                  /**< True : during transfer (DMA)*/
+    volatile uint32_t dma_error_flag;                       /**< True : occurred DMAC error */
+    volatile uint32_t force_terminate;                      /**< force terminate flag */
+    volatile uint32_t state_machine_blocking;               /**< state machine blocking flag : True or False */
+
+    /* timeout */
+    uint32_t data_timeout;                                  /**< read and write data timeout.*/
+
+    /* interrupt */
+    volatile uint32_t int_event1;                           /**< interrupt SD_INFO1 Event */
+    volatile uint32_t int_event2;                           /**< interrupt SD_INFO2 Event */
+    volatile uint32_t dm_event1;                            /**< interrupt DM_CM_INFO1 Event */
+    volatile uint32_t dm_event2;                            /**< interrupt DM_CM_INFO2 Event */
+
+    /* response */
+    uint32_t *response;                                     /**< pointer to buffer for executing command. */
+    uint32_t r1_card_status;                                /**< R1 response data */
+    uint32_t r3_ocr;                                        /**< R3 response data */
+    uint32_t r4_resp;                                       /**< R4 response data */
+    uint32_t r5_resp;                                       /**< R5 response data */
+
+    /* Card registers (4byte align) */
+    uint8_t csd_data[EMMC_MAX_CSD_LENGTH];                  /**< CSD */
+    uint8_t cid_data[EMMC_MAX_CID_LENGTH];                  /**< CID */
+    uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH];          /**< EXT_CSD */
+    uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH];        /**< other response */
+
+    /* SDHI base address */
+    uintptr_t base_address;
+} st_mmc_base;
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+/* ******************************** END ************************************ */
+#endif  /* EMMC_STD_H__ */
+/* EMMC_STD_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/gic.h

@@ -0,0 +1,417 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : GIC Control Function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          gic.h
+ * - Version      : 0.04
+ * @brief         Controls GIC-600 registers and interrupts.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.08.2022 0.01     First Release
+ *         : 20.09.2022 0.02     Set ChildrenAsleep of GICR_WAKER to 1 and end processing
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 04.04.2023 0.04     Removed stdio.h.
+ *****************************************************************************/
+
+#ifndef GIC_H
+#define GIC_H
+
+/*******************************************************************************
+**                      Include Section                                       **
+*******************************************************************************/
+#include <stdint.h>
+
+/*******************************************************************************
+**                      Version Information                                   **
+*******************************************************************************/
+
+/*******************************************************************************
+**                      Global Symbols                                        **
+*******************************************************************************/
+/* GIC base */
+#define GICD_BASE    (0xF1000000UL)
+#define GICR_BASE    (GICD_BASE + 0x60000U)
+
+/* Generic Interrupt Controller Distributor (GICD) */
+#define GICD_CTLR              *((volatile uint32_t *)(GICD_BASE + 0x000U))
+#define GICD_IGROUPR(n)        *((volatile uint32_t *)(GICD_BASE + 0x080U + 4U*(n)))
+#define GICD_ISENABLER(n)      *((volatile uint32_t *)(GICD_BASE + 0x100U + 4U*(n)))
+#define GICD_ICENABLER(n)      *((volatile uint32_t *)(GICD_BASE + 0x180U + 4U*(n)))
+#define GICD_ISPENDR(n)        *((volatile uint32_t *)(GICD_BASE + 0x200U + 4U*(n)))
+#define GICD_ICPENDR(n)        *((volatile uint32_t *)(GICD_BASE + 0x280U + 4U*(n)))
+#define GICD_IPRIORITYR(n)     *((volatile uint32_t *)(GICD_BASE + 0x400U + 4U*(n)))
+#define GICD_ICFGR(n)          *((volatile uint32_t *)(GICD_BASE + 0xC00U + 4U*(n)))
+#define GICD_IGRPMODR(n)       *((volatile uint32_t *)(GICD_BASE + 0xD00U + 4U*(n)))
+#define GICD_IROUTER(n)        *((volatile uint64_t *)(GICD_BASE + 0x6000U + 8U*(n)))
+
+/* Generic Interrupt Controller Redistributor (GICR) */
+#define GICR_CTLR              *((volatile uint32_t *)(GICR_BASE + 0x0000U))
+#define GICR_WAKER             *((volatile uint32_t *)(GICR_BASE + 0x0014U))
+#define GICR_PWRR              *((volatile uint32_t *)(GICR_BASE + 0x0024U))
+
+#define CHILDREN_ASLEEP        (1U << 2U)
+#define PROCESSOR_SLEEP        (1U << 1U)
+#define RDPOWER_DOWN           (1U << 0U)
+
+/*******************************************************************************
+**                      Global Data Types                                     **
+*******************************************************************************/
+
+/*******************************************************************************
+**                      Function Prototypes                                   **
+*******************************************************************************/
+
+/*******************************************************************************
+**                      Macro                                                 **
+*******************************************************************************/
+
+/*******************************************************************************
+ * Definitions for CPU system register interface to GICv3
+ ******************************************************************************/
+/* ICC_SRE_EL3 */
+#define ICC_SRE_EN_BIT     (8U)
+#define ICC_SRE_DIB_BIT    (4U)
+#define ICC_SRE_DFB_BIT    (2U)
+#define ICC_SRE_SRE_BIT    (1U)
+
+/* SCR_EL3 */
+#define SCR_NS_BIT         (1U)
+
+/* Affinity Leve mask value */
+#define AFFINITY0_MASK     (0xFFU)
+#define AFFINITY1_MASK     (0xFF00U)
+#define AFFINITY2_MASK     (0xFF0000U)
+#define AFFINITY3_MASK     (0xFF00000000U)
+#define IRM_OFF            (0x80000000U)
+
+/* Get ICC_IAR0 */
+static inline uint64_t get_ICC_IAR0(void)
+{
+    uint64_t value = 0U;
+    __asm__ volatile("mrs %0, S3_0_c12_c8_0" : "=r" (value));
+    return value;
+}
+
+/* Set ICC_PMR */
+static inline void set_ICC_PMR(uint64_t value)
+{
+    __asm__ volatile ("msr S3_0_C4_C6_0, %0" :: "r" (value));
+}
+
+/* Set ICC_IGRPEN0 */
+static inline void set_ICC_IGRPEN0(uint64_t value)
+{
+    __asm__ volatile ("msr S3_0_c12_c12_6, %0" :: "r" (value));
+}
+
+/* Set ICC_SRE_EL1 */
+static inline void set_ICC_SRE_EL1(uint64_t value)
+{
+    __asm__ volatile ("msr S3_0_C12_C12_5, %0" :: "r" (value));
+}
+
+/* Get ICC_SRE_EL3 */
+static inline uint64_t get_ICC_SRE_EL3(void)
+{
+    uint64_t value = 0U;
+    __asm__ volatile("mrs %0, S3_6_C12_C12_5" : "=r" (value));
+    return value;
+}
+
+/* Set ICC_SRE_EL3 */
+static inline void set_ICC_SRE_EL3(uint64_t value)
+{
+    __asm__ volatile ("msr S3_6_C12_C12_5, %0" :: "r" (value));
+}
+
+/* Get MPIDR_EL1 */
+static inline uint64_t get_MPIDR_EL1(void)
+{
+    uint64_t value = 0U;
+    __asm__ volatile("mrs %0, mpidr_el1" : "=r" (value));
+    return value;
+}
+
+/* ISB */
+static inline void GIC_isb(void)
+{
+    __asm__ volatile ("isb");
+}
+
+/*  Enable the interrupt distributor using the GIC's CTLR register */
+static inline void GIC_EnableDistributor(void)
+{
+    GICD_CTLR |= 0x31U;
+}
+
+/* Disable the interrupt distributor using the GIC's CTLR register */
+static inline void GIC_DisableDistributor(void)
+{
+    GICD_CTLR &= 0xFFFFFFFEU;
+}
+
+/* Set the interrupt enable from the GIC's ISENABLER register */
+static inline void GIC_SetEnable(uint32_t intid, uint32_t value)
+{
+    uint32_t reg     = GICD_ISENABLER(intid / 32U);
+    uint32_t shift   = (intid % 32U);
+
+    reg &= (~(1U          << shift));
+    reg |= ( (value & 1U) << shift);
+
+    GICD_ISENABLER(intid / 32U) = reg;
+}
+
+/* Set the interrupt disable from the GIC's ICENABLER register */
+static inline void GIC_SetClearEnable(uint32_t intid, uint32_t value)
+{
+    uint32_t reg     = GICD_ICENABLER(intid / 32U);
+    uint32_t shift   = (intid % 32U);
+
+    reg &= (~(1U          << shift));
+    reg |= ( (value & 1U) << shift);
+
+    GICD_ICENABLER(intid / 32U) = reg;
+}
+
+/* Sets the interrupt configuration using GIC's ICFGR register */
+static inline void GIC_SetConfiguration(uint32_t intid, uint32_t int_config)
+{
+    uint32_t icfgr = GICD_ICFGR(intid / 16U);
+    uint32_t shift = (intid % 16U) << 1U;
+
+    icfgr &= (~(3U         << shift));
+    icfgr |= (  int_config << shift);
+
+    GICD_ICFGR(intid / 16U) = icfgr;
+}
+
+/* Set the priority for the given interrupt in the GIC's IPRIORITYR register */
+static inline void GIC_SetPriority(uint32_t intid, uint32_t priority)
+{
+    uint32_t mask  = GICD_IPRIORITYR(intid / 4U);
+	uint32_t shift = ((intid % 4U) * 8U);
+
+    mask &= (~(0xFFU          << shift));
+    mask |= ( (priority & 0xFFU) << shift);
+
+    GICD_IPRIORITYR(intid / 4U) = mask;
+}
+
+/* Set the interrupt group from the GIC's IGROUPR register */
+static inline void GIC_SetGroup(uint32_t intid, uint32_t group)
+{
+    uint32_t igroupr = GICD_IGROUPR(intid / 32U);
+    uint32_t shift   = (intid % 32U);
+
+    igroupr &= (~(1U          << shift));
+    igroupr |= ( (group & 1U) << shift);
+
+    GICD_IGROUPR(intid / 32U) = igroupr;
+}
+
+/* Set the interrupt group from the GIC's IGRPMODR register */
+static inline void GIC_SetGrpMode(uint32_t intid, uint32_t mode)
+{
+    uint32_t imode   = GICD_IGRPMODR(intid / 32U);
+    uint32_t shift   = (intid % 32U);
+
+    imode &= (~(1U          << shift));
+    imode |= ( (mode & 1U) << shift);
+
+    GICD_IGRPMODR(intid / 32U) = imode;
+}
+
+/* Set the interrupt routing from the GIC's IROUTER register */
+static inline void GIC_SetRouter(uint32_t intid)
+{
+    uint64_t affinity = 0U;
+
+    /* Get Affinity level */
+    affinity = get_MPIDR_EL1();
+    affinity &= (AFFINITY0_MASK | AFFINITY1_MASK | AFFINITY2_MASK | AFFINITY3_MASK);
+    /* Interrupt routing mode bit OFF */
+	affinity &= (~(IRM_OFF));
+
+    GICD_IROUTER(intid) = affinity;
+}
+
+/* Get power register value from the GIC's GICR_PWRR register */
+static inline uint32_t GIC_Getpwwr(void)
+{
+    return (GICR_PWRR);
+}
+
+/* Set power register value from the GIC's GICR_PWRR register */
+static inline void GIC_Setpwwr(uint32_t set_value)
+{
+    GICR_PWRR = set_value;
+}
+
+/* Get power management cotrol register from the GIC's GICR_WAKER register */
+static inline uint32_t GIC_Getwaker(void)
+{
+    return (GICR_WAKER);
+}
+
+/* Set power management cotrol register from the GIC's GICR_WAKER register */
+static inline void GIC_Setwaker(uint32_t set_value)
+{
+    GICR_WAKER = set_value;
+}
+
+/* Enables the given interrupt using GIC's ISENABLER register */
+static inline void GIC_EnableFIQ(uint32_t intid)
+{
+
+    /* Disable interrupt forwarding */
+    GIC_DisableDistributor();
+
+    /* Set level-sensitive */
+    GIC_SetConfiguration(intid, 0U);
+
+    /* Set priority */
+    GIC_SetPriority(intid, 0U);
+
+    /* Set group 0 (secure) */
+    GIC_SetGroup(intid, 0U);
+
+    /* Set group 0 (secure) */
+    GIC_SetGrpMode(intid, 0U);
+
+    /* Enable distributor */
+    GIC_EnableDistributor();
+
+    /* Enable the SPI interrupt */
+    GIC_SetEnable(intid, 1U);
+
+    /* Set the interrupt routing */
+    GIC_SetRouter(intid);
+}
+
+/*  Enable the interrupt redistributor wakeup */
+static inline void GIC_WakeupRedistributor(void)
+{
+    uint32_t    get_value = 0U;
+    uint32_t    set_value = 0U;
+
+    get_value = GIC_Getpwwr();
+	set_value = get_value & ~(RDPOWER_DOWN);
+    GIC_Setpwwr(set_value);
+
+    get_value = GIC_Getwaker();
+    set_value = get_value & ~(PROCESSOR_SLEEP);
+    GIC_Setwaker(set_value);
+
+    do 
+    {
+        get_value = GIC_Getwaker();
+    }while((get_value & CHILDREN_ASLEEP) == CHILDREN_ASLEEP);
+}
+
+/* Enable the CPU's interrupt interface */
+static inline void GIC_EnableInterface(void)
+{
+    uint64_t reg = 0U;
+    uint64_t icc_sre_el3 = 0U;
+
+    /* Disable the legacy interrupt bypass */
+    icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
+
+    reg = get_ICC_SRE_EL3();
+    set_ICC_SRE_EL3(reg | icc_sre_el3);
+
+    set_ICC_SRE_EL1(ICC_SRE_SRE_BIT);
+    GIC_isb();
+
+    set_ICC_IGRPEN0(1U); /* enable interface grp0 */
+    GIC_isb();
+}
+
+/* Disable the CPU's interrupt interface */
+static inline void GIC_DisableInterface(uint32_t intid)
+{
+    uint32_t    get_value = 0U;
+    uint32_t    set_value = 0U;
+
+    /* Clear Enable the SPI interrupt */
+    GIC_SetClearEnable(intid, 1U);
+
+    /* Set ChildrenAsleep of GICR_WAKER to 1 and end processing */
+    get_value = GIC_Getwaker();
+    set_value = get_value | PROCESSOR_SLEEP;
+    GIC_Setwaker(set_value);
+
+    do
+    {
+        get_value = GIC_Getwaker();
+    }while((get_value & CHILDREN_ASLEEP) != CHILDREN_ASLEEP);
+
+}
+
+/* Read the CPU's IAR register */
+static inline uint32_t GIC_AcknowledgePending(void)
+{
+    return (uint32_t)(get_ICC_IAR0());
+}
+
+/* Set the interrupt priority mask using CPU's PMR register */
+static inline void GIC_SetInterfacePriorityMask(uint64_t priority)
+{
+    /* Specify F8. 32 priority levels are bit0-2 invalid */
+    set_ICC_PMR(priority << 3U);
+}
+
+/* Initialize and enable the GIC */
+static inline void GIC_Enable(void)
+{
+    GIC_WakeupRedistributor();
+    /* Enable interface */
+    GIC_EnableInterface();
+    /* Set priority mask */
+    GIC_SetInterfacePriorityMask(0xFFUL);
+}
+
+/*******************************************************************************
+**                      Function                                              **
+*******************************************************************************/
+/* Interrupt configuration */
+#define Interrupt_Config(void)              GIC_Enable(void)
+
+/* Enable */
+#define Interrupt_Enable(intid)             GIC_EnableFIQ((uint32_t)intid)
+
+/* Disable */
+#define Interrupt_Disable(intid)            GIC_DisableInterface((uint32_t)intid)
+
+#endif /* GIC_H */
+/*******************************************************************************
+**                      End of File                                           **
+*******************************************************************************/

IPL/Customer/Mobis/V4H_Cx_Loader/include/hscif_register.h

@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : HSCIF register header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          hscif_register.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef HSCIF_REGISTER_H_
+#define HSCIF_REGISTER_H_
+
+#include <rcar_register.h>
+
+/* HSCIF0 base address */
+/* 0xE6540000U */
+#define HSCIF0_BASE     (BASE_HSCIF_ADDR)
+
+#define HSCIF_HSSMR     (HSCIF0_BASE + 0x0000U) /*  16  Serial mode register */
+#define HSCIF_HSBRR     (HSCIF0_BASE + 0x0004U) /*  8   Bit rate register */
+#define HSCIF_HSSCR     (HSCIF0_BASE + 0x0008U) /*  16  Serial control register */
+#define HSCIF_HSFTDR    (HSCIF0_BASE + 0x000CU) /*  8   Transmit FIFO data register */
+#define HSCIF_HSFSR     (HSCIF0_BASE + 0x0010U) /*  16  Serial status register */
+#define HSCIF_HSFCR     (HSCIF0_BASE + 0x0018U) /*  16  FIFO control register */
+#define HSCIF_HSLSR     (HSCIF0_BASE + 0x0024U) /*  16  Line status register */
+#define HSCIF_DL        (HSCIF0_BASE + 0x0030U) /*  16  Frequency division register */
+#define HSCIF_CKS       (HSCIF0_BASE + 0x0034U) /*  16  Clock Select register */
+#define HSCIF_HSSRR     (HSCIF0_BASE + 0x0040U) /*  16  Sampling rate register */
+
+#endif /* HSCIF_REGISTER_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load.h

@@ -0,0 +1,272 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Image load function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          image_load.h
+ * - Version      : 0.09
+ * @brief         Access protection setting driver.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 10.02.2022 0.02     Change the number of CA programs
+ *         : 17.02.2022 0.03     Support AArch32
+ *         : 18.05.2022 0.04     Integrated LOAD_INFO
+ *                               Defined value integration
+ *                               Remove unused define values
+ *                               Changed to processing for each device
+ *                               Change structure member name
+ *                               Remove LOGICAL_CONTENT_CERT_ADDR
+ *                               Add get_logic_cont_cert_addr
+ *                               Change the argument type of get_src_addr_offset_in_cert
+ *                               Added argument check
+ *                               Remove unnecessary macros
+ *                               Add argument of load_init()
+ *                               Change for memory map update
+ *         : 16.06.2022 0.05     Change log output
+ *                               Support secure boot for S4
+ *         : 31.10.2022 0.06     License notation change.
+ *         : 21.08.2023 0.07     Add support for V4M.
+ *         : 19.12.2024 0.08     Add definitions for RTOS#1 and RTOS#2.
+ *         : 26.05.2025 0.09     Change address and size of CA program2.
+ *****************************************************************************/
+
+#ifndef LOAD_IMAGE_H_
+#define LOAD_IMAGE_H_
+
+#include "log.h"
+
+/* define */
+/* For Build Option RTOS_LOAD_NUM */
+#define RTOS_LOAD_NUM_1     (1U)    /* RTOS is RTOS#0 only. */
+#define RTOS_LOAD_NUM_3     (3U)    /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
+
+/* For Build Option OPTEE_LOAD_ENABLE */
+#define OPTEE_DISABLE       (0U)    /* Load OP-TEE image disable. */
+#define OPTEE_ENABLE        (1U)    /* Load OP-TEE image enable. */
+
+/* For Build Option BL2_LOAD_ENABLE */
+#define BL2_DISABLE         (0U)    /* Load BL2 image disable. */
+#define BL2_ENABLE          (1U)    /* Load BL2 image enable. */
+
+/* For Build Option QNX_OS_LOAD_ENABLE */
+#define QNX_OS_DISABLE       (0U)    /* Load QNX_OS image disable. */
+#define QNX_OS_ENABLE        (1U)    /* Load QNX_OS image enable. */
+
+/* DRAM address */
+#define DRAM_BASE       (0x40000000U)
+#define DRAM_SIZE       (0x80000000U)
+#define DRAM_END        ((DRAM_BASE + DRAM_SIZE) - 1U)
+
+/* RT-SRAM */
+/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */
+#define RTSRAM_BASE     (0xEB200000U)
+#define RTSRAM_SIZE     ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */
+#define RTSRAM_END      ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
+
+/* RT-VRAM */
+/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */
+#define RTVRAM_BASE     (0xE2000000U)
+#define RTVRAM_SIZE     (1024U * 1024U)     /* 1MB */
+#define RTVRAM_VBUF_28M         (28U)       /* 28MB */
+#define RTVRAM_VBUF_SIZE        ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U)   /* 3MB to 27MB (The first 1MB is actual RAM.) */
+#define RTVRAM_VBUF_TOP         (RTVRAM_BASE + RTVRAM_SIZE)   /* 0xE2100000 */
+#define RTVRAM_VBUF_END         ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U)
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+#define RTVRAM_8WAY_28M_SRAM_SIZE   (0x00010000U)   /* 64KiB */
+#define RTVRAM_SRAM_TOP         (RTVRAM_BASE)
+#define RTVRAM_SRAM_END         (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U)  /* 0xE2000000 - 0xE200FFFF */
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+
+/* System RAM */
+#define SYSRAM_BASE (0xE6300000U)
+#if (RCAR_LSI == RCAR_S4)
+#define SYSRAM_SIZE (384U * 1024U)   /* 384KB */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define SYSRAM_SIZE (1024U * 1024U)  /* 1MB */
+#endif /* RCAR_LSI == RCAR_S4 */
+#define SYSRAM_END  ((SYSRAM_BASE + SYSRAM_SIZE) - 1U)
+
+/* Cx Loader */
+#define IPL_TOP         (0xE6300000U)
+#define IPL_SIZE        (0x00030000U) /* 192KiB */
+#define IPL_END         ((IPL_TOP +IPL_SIZE) - 1U)
+
+/* Certificate size */
+#define CONTENT_CERT_OFFSET         (0x00006000U)   /* certificate top offset */
+#define CONTENT_CERT_INFO_SIZE      (0x00001000U)   /* Content cert header area size(4KiB) */
+#define CONTENT_CERT_DST_SIZE       (0x00000800U)   /* content cert dst size */
+#define KEY_CERT_SIZE               (0x00002000U)   /* Key cert area size(8KiB) */
+
+/* Load ID */
+#define RTOS_ID             (1U)
+#define CA_PROGRAM_ID       (2U)
+#define CA_OPTIONAL_ID      (6U)
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+#define RTOS1_ID            (16U)   /* 16:RTOS#1 */
+#define RTOS2_ID            (17U)   /* 17:RTOS#2 */
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+
+/* Number of Max loading image */
+#define CA_MAX_IMAGE        (8U)        /* CA Load program MAX image num */
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
+#define MAX_PLACED          (16U)       /* Load program MAX image num */
+#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+#define MAX_PLACED          (18U)       /* Load program MAX image num */
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */
+
+#define TARGET_MEM_DRAM     (0U)
+#define TARGET_MEM_RTSRAM   (1U)
+#define TARGET_MEM_RTVRAM   (2U)
+#define TARGET_MEM_SYSRAM   (3U)
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+#define TARGET_MEM_SRAM_IN_RTVRAM  (4U)
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+
+/* get info from cert address offset */
+#define CERT_INFO_SIZE_OFFSET   (0x00000264U)   /* Offset Type1 */
+#define CERT_INFO_DST_OFFSET    (0x00000154U)   /* Offset Type1 */
+#define CERT_INFO_SIZE_OFFSET1  (0x00000364U)   /* Offset Type2 */
+#define CERT_INFO_DST_OFFSET1   (0x000001D4U)   /* Offset Type2 */
+#define CERT_INFO_SIZE_OFFSET2  (0x00000464U)   /* Offset Type2 */
+#define CERT_INFO_DST_OFFSET2   (0x00000254U)   /* Offset Type2 */
+
+/* Certificate logical address */
+#define CONTENT_CERT_DEST_ADDR    (0xEB230000U)
+#define CONTENT_CERT_DEST_SIZE    (0x00008000U) /* 32KB */
+
+/* BL31/BL32(S4), BL31/tee-OS/u-boot(V4H) check */
+/* check image num */
+#ifdef MOBIS_PRK3
+  #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+  #error "OPTEE_LOAD_ENABLE==1 should be for PRK3"
+  #endif
+  #if (BL2_LOAD_ENABLE == BL2_DISABLE)
+  #error "BL2_LOAD_ENABLE==1 should be for PRK3"
+  #endif
+  #if (QNX_OS_LOAD_ENABLE == QNX_OS_DISABLE)
+  #error "QNX_OS_LOAD_ENABLE==1 should be for PRK3"
+  #endif
+#define CA_IMAGESIZECHK_DEF (5U)
+#else
+#define CA_IMAGESIZECHK_DEF (2U)
+#endif
+/* load_id */
+#define CA_PROGRAM1_ID      (6U)    /* bl31 */
+#define CA_PROGRAM2_ID      (7U)    /* u-boot */
+#define CA_PROGRAM3_ID      (8U)    /* tee-os */
+#define CA_PROGRAM4_ID      (9U)    /* ca76-loader */
+#define CA_PROGRAM5_ID      (10U)   /* qnx OS */
+#define CA_BL2_ID           CA_PROGRAM4_ID
+#define CA_QNX_OS_ID        CA_PROGRAM5_ID
+
+#define CA_PROGRAM1_ADR     (0x46400000U)
+#define CA_PROGRAM1_SIZE    (0x00022000U)
+#if (RCAR_LSI == RCAR_S4)
+#define CA_PROGRAM2_ADR     (0x44100000U)
+#define CA_PROGRAM2_SIZE    (0x00100000U)
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define CA_PROGRAM2_ADR     (0x00000000U)
+#define CA_PROGRAM2_SIZE    (0x00000000U)
+#endif /* RCAR_LSI == RCAR_S4 */
+#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
+#define CA_PROGRAM3_ADR     (0x44100000U)
+#define CA_PROGRAM3_SIZE    (0x00100000U)
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
+#if (BL2_LOAD_ENABLE == BL2_ENABLE)
+#define CA_PROGRAM4_ADR     (0x41D00000U)
+#define CA_PROGRAM4_SIZE    (0x00020000U)   /* 128KB */
+#endif  /* BL2_LOAD_ENABLE == BL2_ENABLE */
+#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE)
+#define CA_PROGRAM5_ADR     (0x50100000U)
+#define CA_PROGRAM5_SIZE    (0x00800000U)   /* 8MB */
+#endif  /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */
+
+/* key cert address */
+#define TFMV_KEY_CERT_ADDR  (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */
+#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE)              /* 0xEB233000 */
+
+/* struct */
+/* load image range */
+typedef struct {
+    uint32_t load_id;
+    uint32_t image_adr;
+    uint32_t image_size;
+} IMAGE_RANGE;
+
+/* load address range */
+typedef struct {
+    uint32_t    cx_topadd;
+    uint32_t    cx_endadd;
+} ADDRESS_RANGE;
+
+/* load info */
+typedef struct{
+    const char *name;       /* store load image name */
+    uint32_t image_size;    /* store image size */
+    uint32_t boot_addr;     /* store boot address of image */
+    uint32_t key_cert_addr; /* store key cert address */
+    uint32_t cnt_cert_addr; /* store content cert address */
+    uint32_t src_addr;      /* store source address */
+    uint32_t part_num;      /* store eMMC partition number */
+    uint32_t load_id;       /* store Load ID */
+    uint32_t cmac[4U];      /* store cmac */
+
+} LOAD_INFO;
+
+static inline uint32_t get_src_addr_offset_in_cert(uint32_t id)
+{
+    /* INT30-C Pre confirmation */
+    if (id > UINT32_MAX / 0x10U)
+    {
+        ERROR("get_src_addr_offset_in_cert id error.\n");
+        panic;
+    }
+
+    return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U));
+}
+
+static inline uint32_t get_logic_cont_cert_addr(uint32_t num)
+{
+    /* INT30-C Pre confirmation */
+    if (num > UINT32_MAX / 0x10U)
+    {
+        ERROR("get_logic_cont_cert_addr num error.\n");
+        panic;
+    }
+    return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE));
+}
+
+/* Prototype */
+void load_image(LOAD_INFO* li);
+void load_init(LOAD_INFO* li, uint32_t num);
+void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot);
+void load_start(LOAD_INFO* li);
+#endif /* LOAD_IMAGE_H_ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load_emmc.h

@@ -0,0 +1,113 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Image load function for eMMC header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          image_load_emmc.h
+ * - Version      : 0.05
+ * @brief         Access protection setting driver.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 17.02.2022 0.02     Support AArch32
+ *         : 10.05.2022 0.03     Defined value integration
+ *                               Change the argument type of get_part_num_in_cert
+ *                               Added argument check
+ *                               Changed define name
+ *                               Change log output
+ *                               Change the direct value reference
+ *                               Remove Prototype
+ *         : 08.07.2022 0.04     Change log output
+ *                               Adds the defined used in the emmc_trans_data argument
+ *         : 31.10.2022 0.05     License notation change.
+ *****************************************************************************/
+
+#ifndef LOAD_IMAGE_EMMC_H_
+#define LOAD_IMAGE_EMMC_H_
+
+#include <image_load.h>
+#include <log.h>
+
+/* define */
+/* eMMC */
+#define CX_EMMC_TOP            (0x00000000U)
+#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U)    /* 31MB */
+#define CX_EMMC_END            ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U)
+#define SRC_TOP (CX_EMMC_TOP)
+
+/* For eMMC */
+#define CX_EMMC_SECTOR_SIZE_SHIFT           (9U)           /* 512 = 2^9 */
+#define CX_EMMC_SECTOR_SIZE                 (512U)
+#define CX_EMMC_CONTENT_CERT_ADDR           (0x00240000U)
+#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER  (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT)
+
+/* A side certificate setting */
+/* RT-SRAM Offset */
+#define SEC_BOOT_KEY_CERT_OFFSET	(0x00001000U)
+#define SEC_DEBUG_SEC_CERT_OFFSET		(0x00006000U)
+
+/* A side RT-SRAM physical address */
+/* RT-SRAM(0xEB200000) + CERT_OFFSET */
+#define SEC_BOOT_KEY_CERT_ADDR		(ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET)
+
+/* A/B side certificate setting */
+/* Boot side Offset */
+#define CERT_OFFSET_2ND			(0x8000U)
+	
+/* A/B side RT-SRAM physical address */
+/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/
+#define GET_SEC_BOOT_KEY_CERT_ADDR(a)	((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a)))
+
+#define SEC_DEBUG_CERT_SIZE		(6396U)
+
+
+static inline void load_image_info_print_for_emmc(LOAD_INFO* li)
+{
+
+    NOTICE("======== %s image load info ========\n", li->name);
+    NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n"
+        "source address \t= (p:%u)0x%x\n",
+        (unsigned int)li->boot_addr, (unsigned int)(li->image_size),
+        (unsigned int)li->part_num, (unsigned int)li->src_addr );
+}
+
+static inline uint32_t get_part_num_in_cert(uint32_t id)
+{
+    /* INT30-C Pre confirmation */
+    if (UINT32_MAX - id < 1U)
+    {
+        ERROR("get_part_num_in_cert id error.\n");
+        panic;
+    }
+
+    return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U));
+}
+
+#endif /* LOAD_IMAGE_EMMC_H_ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/inline_asm.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : inline asm func header
+ ******************************************************************************/
+
+#ifndef INLINE_ASM_H__
+#define INLINE_ASM_H__
+
+#if defined(__RH850G3K__)
+static inline void syncm(void)
+{
+    __asm__ __volatile__ ("SYNCM");
+}
+
+static inline void synci(void)
+{
+    __asm__ __volatile__ ("SYNCI");
+}
+#else
+static inline void syncm(void)
+{
+    __asm__ volatile ("dsb");
+}
+
+static inline void synci(void)
+{
+    __asm__ volatile ("dsb");
+    __asm__ volatile ("isb");
+}
+
+#endif
+
+#endif  /* INLINE_ASM_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/interrupt.h

@@ -0,0 +1,56 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : INTC header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          interrupt.h
+ * - Version      : 0.05
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *         : 15.12.2022 0.03     V4H interrupt support.
+ *         : 27.12.2022 0.04     Change argument of pabort_error.
+ *         : 21.08.2023 0.05     Add support for V4M.
+ *****************************************************************************/
+#ifndef INTERRUPT_H_
+#define INTERRUPT_H_
+
+/* Prototype */
+#if (RCAR_LSI == RCAR_S4)
+extern void handler_fiq(void);
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar);
+void pabort_error(uint32_t ifsr, uint32_t ifar);
+void Undefined_error(uint32_t occ_add);
+#endif /* RCAR_LSI == RCAR_S4 */
+extern void handler_error(uint32_t ex_type);
+
+#endif /* INTERRUPT_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/ip_control.h

@@ -0,0 +1,51 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : IP's control header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ip_control.h
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 02.08.2022 0.02     Added define value
+ *         : 31.10.2022 0.03     License notation change.
+ *****************************************************************************/
+
+#ifndef IP_CONTROL_H_
+#define IP_CONTROL_H_
+
+#define INTC_SPI_SWDT      (548U)
+
+/* Prototype */
+void ip_init(void);
+void ip_release(void);
+
+#endif /* IP_CONTROL_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main.h

@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Loader main header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          loader_main.h
+ * - Version      : 0.34
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 18.02.2022 0.02     Updated IPL_VERSION 0.7.0
+ *         : 22.03.2022 0.03     Updated IPL_VERSION 0.8.0
+ *         : 20.05.2022 0.04     Updated IPL_VERSION 0.9.0
+ *         : 12.07.2022 0.05     Updated IPL_VERSION 0.11.0
+ *         : 22.08.2022 0.06     Updated IPL_VERSION 0.12.0
+ *         : 03.10.2022 0.07     Updated IPL_VERSION 0.13.0
+ *         : 27.10.2022 0.08     Updated IPL_VERSION 0.14.0
+ *         : 31.10.2022 0.09     License notation change.
+ *         : 07.11.2022 0.10     Removed unnecessary define values.
+ *         : 14.12.2022 0.11     Updated IPL_VERSION 0.15.0
+ *         : 08.02.2023 0.12     Updated IPL_VERSION 0.17.0
+ *         : 17.02.2023 0.13     Updated IPL_VERSION 0.17.1
+ *         : 24.04.2023 0.14     Updated IPL_VERSION 0.18.0
+ *         : 22.05.2023 0.15     Updated IPL_VERSION 0.19.0
+ *         : 19.06.2023 0.16     Updated IPL_VERSION 0.21.0
+ *         : 22.08.2023 0.17     Updated IPL_VERSION 1.25.0
+ *         : 19.09.2023 0.18     Updated IPL_VERSION 1.30.0
+ *         : 23.10.2023 0.19     Updated IPL_VERSION 1.31.0
+ *         : 17.11.2023 0.20     Updated IPL_VERSION 1.41.0
+ *         : 26.01.2024 0.21     Updated IPL_VERSION 1.42.0
+ *         : 07.02.2024 0.22     Updated IPL_VERSION 1.44.0
+ *         : 05.04.2024 0.23     Updated IPL_VERSION 1.45.0
+ *         : 11.06.2024 0.24     Updated IPL_VERSION 1.48.0
+ *         : 19.08.2024 0.25     Updated IPL_VERSION 1.50.0
+ *         : 19.09.2024 0.26     Updated IPL_VERSION 1.51.2
+ *         : 22.10.2024 0.27     Updated IPL_VERSION 1.52.0
+ *         : 23.10.2024 0.28     Updated IPL_VERSION 1.53.0
+ *         : 28.10.2024 0.29     Updated IPL_VERSION 1.53.1
+ *         : 28.10.2024 0.30     Updated IPL_VERSION 1.54.0
+ *         : 05.12.2024 0.31     Updated IPL_VERSION 1.55.0
+ *         : 08.01.2025 0.32     Updated IPL_VERSION 1.56.0
+ *         : 09.04.2025 0.33     Updated IPL_VERSION 1.57.0
+ *         : 26.05.2025 0.34     Updated IPL_VERSION 1.58.0
+ *****************************************************************************/
+
+#ifndef LOADER_MAIN_H_
+#define LOADER_MAIN_H_
+
+/* define */
+#define IPL_VERSION "1.58.0"
+
+/* Global */
+extern const char build_message[];
+
+/* prototype */
+uint32_t loader_main(void);
+
+#endif /* LOAD_MAIN_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main_common.h

@@ -0,0 +1,43 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Loader main common header
+ ******************************************************************************/
+
+#ifndef LOADER_MAIN_COMMON_H_
+#define LOADER_MAIN_COMMON_H_
+
+#include <image_load.h>
+
+/* prototype */
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+ void smoni_set_param(uintptr_t smoni_entry_point,
+                     uintptr_t uboot_entry_point);
+#else
+void smoni_set_param(uintptr_t smoni_entry_point,
+                    uintptr_t uboot_entry_point,
+                    uintptr_t tee_entry_point);
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+
+#endif /* LOADER_MAIN_COMMON_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_mmu_table.h

@@ -0,0 +1,80 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Definitions used by the MMU.
+ ******************************************************************************/
+/******************************************************************************
+ * @file          loader_mmu_table.h
+ * - Version      : 0.01
+ * @brief         MMU define.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 14.12.2022 0.01     First Release
+*****************************************************************************/
+
+#ifndef MMU_TABLE_H_
+#define MMU_TABLE_H_
+
+#include <stdint.h>		/* for uint32_t */
+
+/* b[1:0] Block and Table descriptors */
+#define MMU_TBL_TYPE_TABLE		(3UL << 0)
+#define MMU_TBL_TYPE_BLOCK		(1UL << 0)
+#define MMU_TBL_TYPE_PAGE		(3UL << 0)
+
+/* Lower attributes:SH[1:0] unused */
+#define MMU_TBL_BLOCK_OUTER_SHARE	(2ULL << 8)
+#define MMU_TBL_BLOCK_INNER_SHARE	(3ULL << 8)
+
+/* Lower attributes:AF[10] */
+#define MMU_TBL_BLOCK_AF		(1UL << 10)
+
+/* Lower attributes:AP[2:1] access permissions model */
+#define MMU_TBL_AP_APP_RW		(1UL << 6)
+#define MMU_TBL_AP_APP_R		(3UL << 6)
+
+/* Lower attributes:AttrIndx[2:0]  */
+#define MMU_TBL_ATTRINDX0		(0UL << 2)	/* Device-nGnRnE memory */
+#define MMU_TBL_ATTRINDX1		(1UL << 2)	/* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
+#define MMU_TBL_ATTRINDX2		(2UL << 2)	/* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
+
+/* Upper attributes:Block descriptors */
+#define MMU_TBL_BLOCK_XN		(1UL << 54)
+
+#define MMU_TBL_BLOCK_NOEXEC_DEVICE	  (MMU_TBL_BLOCK_XN  | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
+#define MMU_TBL_BLOCK_EXECREAD_MEMORY (                    MMU_TBL_AP_APP_R  | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
+#define MMU_TBL_BLOCK_NOEXEC_MEMORY   (MMU_TBL_BLOCK_XN  | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
+/* Level 3 */
+#define MMU_TBL_PAGE_NOEXEC_DEVICE	  (MMU_TBL_BLOCK_XN  | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
+#define MMU_TBL_PAGE_EXECREAD_MEMORY  (                    MMU_TBL_AP_APP_R  | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
+#define MMU_TBL_PAGE_NOEXEC_MEMORY	  (MMU_TBL_BLOCK_XN  | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
+
+extern const uint64_t g_loader_level1_table[];
+extern const uint64_t g_loader_level2_table[];
+extern const uint64_t g_loader_level3_table[];
+
+#endif	 /* MMU_TABLE_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/log.h

@@ -0,0 +1,101 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : log header file
+ ******************************************************************************/
+/******************************************************************************
+ * @file          log.h
+ * - Version      : 0.06
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 12.05.2022 0.02     Changed __LOG_H__ to LOG_H_
+ *                               Changed panic (Static analysis)
+ *         : 16.06.2022 0.03     Change log output
+ *         : 31.10.2022 0.04     License notation change.
+ *         : 07.11.2022 0.05     Change log macro.
+ *         : 04.04.2023 0.06     Removed stdio.h.
+ *****************************************************************************/
+#ifndef LOG_H_
+#define LOG_H_
+
+#include <stdbool.h>
+
+#define LOG_NONE    (0)
+#define LOG_ERROR   (1)
+#define LOG_NOTICE  (2)
+#define LOG_WARNING (3)
+#define LOG_INFO    (4)
+#define LOG_VERBOSE (5)
+
+
+#if LOG_LEVEL >= LOG_NOTICE
+# define NOTICE(...)	log_printf("N:" __VA_ARGS__)
+#else
+# define NOTICE(...)
+#endif
+
+#if LOG_LEVEL >= LOG_ERROR
+# define ERROR(...)	    log_printf("E:" __VA_ARGS__)
+#else
+# define ERROR(...)
+#endif
+
+#if LOG_LEVEL >= LOG_WARNING
+# define WARN(...)	    log_printf("W:" __VA_ARGS__)
+#else
+# define WARN(...)
+#endif
+
+#if LOG_LEVEL >= LOG_INFO
+# define INFO(...)	    log_printf("I:" __VA_ARGS__)
+#else
+# define INFO(...)
+#endif
+
+#if LOG_LEVEL >= LOG_VERBOSE
+# define VERBOSE(...)	log_printf("V:" __VA_ARGS__)
+#else
+# define VERBOSE(...)
+#endif
+
+
+#define panic                               \
+    do {                                    \
+        log_printf("P:%s\n", __func__);     \
+        while(true){}                       \
+    } while (false)
+
+
+void log_printf(const char *fmt, ...);
+
+void gpio_N1307(int set);
+void gpio_N1305(int set);
+
+#endif /* LOG_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/mem_io.h

@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Memory access driver header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          mem_io.h
+ * - Version      : 0.05
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 17.02.2022 0.02     Change the return type of mem_read64
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 07.11.2022 0.04     Added to convert mmio.
+ *         : 21.08.2023 0.05     Add support for V4M.
+ *****************************************************************************/
+#ifndef MEM_IO_H_
+#define MEM_IO_H_
+
+#include <stdint.h>
+
+static inline void mem_write8(uintptr_t addr, uint8_t data)
+{
+    *(volatile uint8_t*)addr = data;
+}
+
+static inline uint8_t mem_read8(uintptr_t addr)
+{
+    return (*(volatile uint8_t*)addr);
+}
+
+static inline void mem_write16(uintptr_t addr, uint16_t data)
+{
+    *(volatile uint16_t*)addr = data;
+}
+
+static inline uint16_t mem_read16(uintptr_t addr)
+{
+    return (*(volatile uint16_t*)addr);
+}
+
+static inline void mem_write32(uintptr_t addr, uint32_t data)
+{
+    *(volatile uint32_t*)addr = data;
+}
+
+static inline uint32_t mem_read32(uintptr_t addr)
+{
+    return (*(volatile uint32_t*)addr);
+}
+
+static inline void mem_write64(uintptr_t addr, uint64_t data)
+{
+    *(volatile uint64_t*)addr = data;
+}
+
+static inline uint64_t mem_read64(uintptr_t addr)
+{
+    return (*(volatile uint64_t*)addr);
+}
+
+static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
+{
+    mem_write32(addr, (mem_read32(addr) & ~clr) | set);
+}
+
+static inline void mem_bitset32(uintptr_t addr, uint32_t set)
+{
+    mem_write32(addr, (mem_read32(addr) | set) );
+}
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define mmio_write_32(a,b)          mem_write32(a,b)
+#define mmio_read_32(a)             mem_read32(a)
+#define mmio_clrsetbits_32(a,b,c)   mem_bitclrset32(a,b,c)
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+
+#endif /* MEM_IO_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/qos.h

@@ -0,0 +1,33 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : QoS driver header
+ ******************************************************************************/
+
+#ifndef QOS_INIT_H_
+#define QOS_INIT_H_
+
+extern void qos_init(void);
+
+#endif /* QOS_INIT_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/ram_protection.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2024-2025 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : RAM protection driver header
+ ******************************************************************************/
+#ifndef RAM_PROTECTION_H_
+#define RAM_PROTECTION_H_
+
+#include <stdint.h>
+#include <image_load.h>
+
+#define RTVRAM0_AREA1_TOP            (0xE0040000U)
+#define RTVRAM0_ADDR_END             (0xE0100000U)
+
+#define RTVRAM1_AREA1_TOP            (0xE2010000U)
+#define RTVRAM1_AREA2_TOP            (0xE2100000U)
+#define RTVRAM1_ADDR_END             (0xE3C00000U)
+
+#define SYSTEM_RAM_AREA1_TOP        (0xE635E000U)
+#define SYSTEM_RAM_AREA2_TOP        (0xE6360000U)
+#define SYSTEM_RAM_ADDR_END         (0xE6400000U)
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define DRAM_ADDR_AREA1             (0x0401C00000ULL)
+#define DRAM_ADDR_AREA2             (0x0401D00000ULL)
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+#define DRAM_ADDR_AREA3             (0x0406400000ULL)
+#define DRAM_ADDR_AREA4             (0x0406440000ULL)
+#define DRAM_ADDR_AREA5             (0x0407FC0000ULL)
+#define DRAM_ADDR_AREA6             (0x0408000000ULL)
+#define DRAM_ADDR_AREA7             (0x041DC00000ULL)
+#define DRAM_ADDR_AREA8             (0x0420000000ULL)
+#define DRAM_ADDR_AREA9             (0x0440000000ULL)
+#define DRAM_ADDR_AREA10            (0x0460000000ULL)
+#define DRAM_ADDR_AREA11            (0x0480000000ULL)
+#define DRAM_ADDR_AREA12            (0x0500000000ULL)
+#define DRAM_ADDR_AREA13            (0x0600000000ULL)
+#else
+#define DRAM_ADDR_AREA3             (0x0404100000ULL)
+#define DRAM_ADDR_AREA4             (0x0406400000ULL)
+#define DRAM_ADDR_AREA5             (0x0406440000ULL)
+#define DRAM_ADDR_AREA6             (0x0407E00000ULL)
+#define DRAM_ADDR_AREA7             (0x0407F00000ULL)
+#define DRAM_ADDR_AREA8             (0x0407FC0000ULL)
+#define DRAM_ADDR_AREA9             (0x0408000000ULL)
+#define DRAM_ADDR_AREA10            (0x041DC00000ULL)
+#define DRAM_ADDR_AREA11            (0x0420000000ULL)
+#define DRAM_ADDR_AREA12            (0x0440000000ULL)
+#define DRAM_ADDR_AREA13            (0x0460000000ULL)
+#define DRAM_ADDR_AREA14            (0x0480000000ULL)
+#define DRAM_ADDR_AREA15            (0x0500000000ULL)
+#define DRAM_ADDR_AREA16            (0x0600000000ULL)
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+
+#else
+#define DRAM_ADDR_AREA1             (0x0401C00000ULL)
+#define DRAM_ADDR_AREA2             (0x0406400000ULL)
+#define DRAM_ADDR_AREA3             (0x0406440000ULL)
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+#define DRAM_ADDR_END               (0x0700000000ULL)
+
+#define NOT_USED_VALUE              (0x00000000U)
+
+/* RAM DIVISION AREA ID */
+/* RT-SRAM */
+#define RTVRAM0_ICUMX_IPL_AREA      (0U)    /* 0xEB200000 -- 0xEB23FFFF */
+#define RTVRAM0_ICUMX_FW_AREA       (1U)    /* 0xEB240000 -- 0xEB2FFFFF */
+/* RT-VRAM */
+#define RTVRAM1_BLANK_AREA			(0U)    /* 0xE2000000 -- 0xE200FFFF */
+#define RTVRAM1_EXTEND_CACHE_AREA   (1U)    /* 0xE2010000 -- 0xE20FFFFF */
+#define RTVRAM1_RTOS_AREA           (2U)    /* 0xE2100000 -- 0xE3BFFFFF */
+/* System RAM */
+#define SYSTEM_RAM_CX_2ND_IPL       (0U)    /* 0xE6300000 -- 0xE635DFFF */
+#define SYSTEM_RAM_SHARED_MEM       (1U)    /* 0xE635E000 -- 0xE635FFFF */
+/* SDRAM */
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define RTVRAM1_EXTEND_AREA         (0U)    /* 0x04_00000000 -- 0x04_01BFFFFF */
+#define CR_FW_SHARED_AREA           (1U)    /* 0x04_01C00000 -- 0x04_01CFFFFF */
+#define SDRAM_BLANK_AREA            (2U)    /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF
+                                             * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */
+#define SDRAM_PROTECT_AREA          (3U)    /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF
+                                             * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+#define SDRAM_PUBLIC_AREA           (4U)    /* 0x04_06440000 -- 0x04_07FBFFFF */
+#define ICCOM_USED_AREA             (5U)    /* 0x04_07FC0000 -- 0x04_07FFFFFF */
+#define LINUX_USED_AREA             (6U)    /* 0x04_08000000 -- 0x04_1DBFFFFF */
+#define CAAREA2_USED_AREA           (7U)    /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
+#define CR52_USED_AREA              (8U)    /* 0x04_20000000 -- 0x04_3FFFFFFF */
+#define CAAREA3_USED_AREA           (9U)    /* 0x04_40000000 -- 0x04_5FFFFFFF */
+#define CAAREA2_USED_AREA2          (10U)   /* 0x04_60000000 -- 0x04_7FFFFFFF */
+#define CAAREA1_USED_AREA           (11U)   /* 0x04_80000000 -- 0x04_FFFFFFFF */
+#else
+#define SDRAM_PROTECT_AREA2         (4U)    /* 0x04_06400000 -- 0x04_0643FFFF */
+#define SDRAM_BLANK_AREA2           (5U)    /* 0x04_06440000 -- 0x04_07DFFFFF */
+#define OPTEE_SHARED_AREA           (6U)    /* 0x04_07E00000 -- 0x04_07EFFFFF */
+#define SDRAM_BLANK_AREA3           (7U)    /* 0x04_07F00000 -- 0x04_07FBFFFF */
+#define ICCOM_USED_AREA             (8U)    /* 0x04_07FC0000 -- 0x04_07FFFFFF */
+#define LINUX_USED_AREA             (9U)    /* 0x04_08000000 -- 0x04_1DBFFFFF */
+#define CAAREA2_USED_AREA           (10U)   /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
+#define CR52_USED_AREA              (11U)   /* 0x04_20000000 -- 0x04_3FFFFFFF */
+#define CAAREA3_USED_AREA           (12U)   /* 0x04_40000000 -- 0x04_5FFFFFFF */
+#define CAAREA2_USED_AREA2          (13U)   /* 0x04_60000000 -- 0x04_7FFFFFFF */
+#define CAAREA1_USED_AREA           (14U)   /* 0x04_80000000 -- 0x04_FFFFFFFF */
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+#if (RCAR_LSI == RCAR_V4H)
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+#define RESERVERD_AREA              (12U)   /* 0x05_00000000 -- 0x05_FFFFFFFF */
+#define CAAREA1_USED_AREA2          (13U)   /* 0x06_00000000 -- 0x06_FFFFFFFF */
+#else
+#define RESERVERD_AREA              (15U)   /* 0x05_00000000 -- 0x05_FFFFFFFF */
+#define CAAREA1_USED_AREA2          (16U)   /* 0x06_00000000 -- 0x06_FFFFFFFF */
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+#elif (RCAR_LSI == RCAR_V4M)
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+#define CAAREA1_USED_AREA2          (12U)   /* 0x05_00000000 -- 0x05_FFFFFFFF */
+#define RESERVERD_AREA              (13U)   /* 0x06_00000000 -- 0x06_FFFFFFFF */
+#else
+#define CAAREA1_USED_AREA2          (15U)   /* 0x05_00000000 -- 0x05_FFFFFFFF */
+#define RESERVERD_AREA              (16U)   /* 0x06_00000000 -- 0x06_FFFFFFFF */
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+#endif /* RCAR_LSI == RCAR_V4H */
+#else
+#define RTVRAM1_EXTEND_AREA         (0U)    /* 0x04_00000000 -- 0x04_01BFFFFF */
+#define SDRAM_BLANK_AREA            (1U)    /* 0x04_01C00000 -- 0x04_063FFFFF */
+#define SDRAM_PROTECT_AREA          (2U)    /* 0x04_06400000 -- 0x04_0643FFFF */
+#define SDRAM_PUBLIC_AREA           (3U)    /* 0x04_06440000 -- 0x06_FFFFFFFF */
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+
+#endif /* RAM_PROTECTION_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_def.h

@@ -0,0 +1,66 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : R-Car common header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          rcar_def.h
+ * - Version      : 0.05
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 17.02.2022 0.02     Support V4H
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 23.05.2023 0.04     Add the define "PRR_PRODUCT_21" for V4H v2.1.
+ *         : 21.08.2023 0.05     Add support for V4M.
+ *****************************************************************************/
+
+#ifndef RCAR_DEF_H_
+#define RCAR_DEF_H_
+
+/* Product Register */
+#define PRR                 (0xFFF00044U)   /* PRR register */
+#define PRR_PRODUCT_MASK    (0x00007F00U)   /* Product mask */
+#define PRR_CUT_MASK        (0x000000FFU)   /* Cut Number bit mask */
+#define PRR_MAJOR_MASK      (0x000000F0U)   /* Major bit mask */
+#define PRR_MINOR_MASK      (0x0000000FU)   /* Minor bit mask */
+#define PRR_MAJOR_SHIFT     (4U)            /* Major bit shift */
+#define PRR_MAJOR_OFFSET    (1U)
+
+#define PRR_PRODUCT_S4      (0x00005A00U)   /* R-Car S4 */
+#define PRR_PRODUCT_V4H     (0x00005C00U)   /* R-Car V4H */
+#define PRR_PRODUCT_V4M     (0x00005D00U)   /* R-Car V4M */
+
+#define PRR_PRODUCT_10		    (0x00000000U)   /*   ver 1.0 */
+#define PRR_PRODUCT_11		    (0x00000001U)   /*   ver 1.1 */
+#define PRR_PRODUCT_20		    (0x00000010U)	/*   ver 2.0 */
+#define PRR_PRODUCT_21		    (0x00000011U)	/*   ver 2.1 */
+#define PRR_PRODUCT_22		    (0x00000012U)	/*   ver 2.2 */
+#endif /* RCAR_DEF_H_ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h

@@ -0,0 +1,157 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : rcar register header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          rcar_register.h
+ * - Version      : 0.07
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 17.02.2022 0.02     Add APMU
+ *                               Support AArch32
+ *         : 09.05.2022 0.03     Changed to processing for each device
+ *         : 24.10.2022 0.04     Add supports for HS200/400
+ *         : 31.10.2022 0.05     License notation change.
+ *         : 07.11.2022 0.06     Added QOS and RTVRAM related registers.
+ *         : 21.08.2023 0.07     Add support for V4M.
+ *****************************************************************************/
+
+#ifndef RCAR_REGISTER_H_
+#define RCAR_REGISTER_H_
+
+#include <stdint.h>
+
+#define BASE_ADDR_PFC           (0xE6000000U)   /* PFC,GPIO,LIFC,CPGA,RESET */
+#define BASE_ADDR_RPC           (0xEE200000U)   /* RPC */
+#if (RCAR_LSI == RCAR_S4)
+#define BASE_ADDR_SCIF          (0xE6C00000U)   /* SCIF */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define BASE_ADDR_SCIF          (0xE6E00000U)   /* SCIF */
+#endif /* RCAR_LSI == RCAR_S4 */
+#define BASE_ADDR_MMC           (0xEE000000U)   /* MMC */
+#define BASE_ADDR_HSCIF         (0xE6400000U)   /* HSCIF */
+#define BASE_AP_CORE_ADDR       (0xE6280000U)   /* ECM */
+
+/* Base address offset of each register */
+/* CPGA */
+#define OFFSET_CPGA             (0x00150000U)
+/* RESET */
+#define OFFSET_RESET            (0x00160000U)
+/* APMU */
+#define OFFSET_APMU             (0x00170000U)
+
+/*RPC*/
+#define OFFSET_RPC              (0x00000000U)
+
+/*SCIF*/
+#if (RCAR_LSI == RCAR_S4)
+#define OFFSET_SCIF3            (0x00050000U)
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define OFFSET_SCIF0            (0x00060000U)
+#endif /* RCAR_LSI == RCAR_S4 */
+
+/* SDHI2/MMC0 */
+#define OFFSET_SDHI             (0x00140000U)
+
+/* HSCIF */
+#define OFFSET_HSCIF0           (0x00140000U)
+
+/* PFC0 */
+#define OFFSET_PFC0             (0x00050000U)
+
+/* PFC1 */
+#if (RCAR_LSI == RCAR_S4)
+#define OFFSET_PFC1             (0x00051000U)
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define OFFSET_PFC1             (0x00058000U)
+#endif /* RCAR_LSI == RCAR_S4 */
+
+/* Port Group */
+#define OFFSET_PORTGR           (0x00000800U)
+
+/* CPGWPR */
+#define OFFSET_CPG_CPGWPR   	(0x00000000U)
+
+/* SD0CKCR */
+#define OFFSET_CPG_SD0CKCR      (0x00000870U)
+
+/* PLL2CR0 */
+#define OFFSET_CPG_PLL2CR0      (0x00000834U)
+
+/* PLLECR */
+#define OFFSET_CPG_PLLECR       (0x00000820U)
+
+/* QOS */
+#define ICU_CC                  (0xE6600000U)   /* CC63S,I2C,AXMM,QoS */
+#define ICU_OFFSET_CCI          (0x001a0000U)   /* (0xE67A0000U) */
+#define BASE_CCI_ADDR           (ICU_CC + ICU_OFFSET_CCI)
+
+/* RTVRAM */
+#define SDRAM_40BIT_ADDR_TOP    (0x0400000000ULL)
+#define RTVRAM_VBUF_AREA_SIZE   (4U * 1024U * 1024U)    /* 4MB */
+
+#define BASE_CPG_ADDR           (BASE_ADDR_PFC + OFFSET_CPGA)
+#define BASE_RESET_ADDR         (BASE_ADDR_PFC + OFFSET_RESET)
+#define BASE_APMU_ADDR          (BASE_ADDR_PFC + OFFSET_APMU)
+#define BASE_RPC_ADDR           (BASE_ADDR_RPC + OFFSET_RPC)
+#if (RCAR_LSI == RCAR_S4)
+#define BASE_SCIF_ADDR          (BASE_ADDR_SCIF + OFFSET_SCIF3)
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define BASE_SCIF_ADDR          (BASE_ADDR_SCIF + OFFSET_SCIF0)
+#endif /* RCAR_LSI == RCAR_S4 */
+#define BASE_MMC0_ADDR          (BASE_ADDR_MMC + OFFSET_SDHI)
+#define BASE_HSCIF_ADDR         (BASE_ADDR_HSCIF + OFFSET_HSCIF0)
+#define BASE_PFC0_ADDR          (BASE_ADDR_PFC + OFFSET_PFC0)
+#define BASE_PFC1_ADDR          (BASE_ADDR_PFC + OFFSET_PFC1)
+#define BASE_CPG_ADDR           (BASE_ADDR_PFC + OFFSET_CPGA)
+#define PFC_GP1_BASE			(BASE_PFC0_ADDR + OFFSET_PORTGR)
+#define PFC_GP3_BASE			(BASE_PFC1_ADDR + OFFSET_PORTGR)
+#define CPG_CPGWPR				(BASE_CPG_ADDR + OFFSET_CPG_CPGWPR)
+#define CPG_PLL2CR0				(BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0)
+#define CPG_PLLECR              (BASE_CPG_ADDR + OFFSET_CPG_PLLECR)
+#define CPG_SD0CKCR				(BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR)
+#define CPG_FRQCRC0             (BASE_CPG_ADDR  + OFFSET_CPG_FRQCRC0 0x0808U)
+
+#define OFFSET_PFC_DRV0CTRL		(0x00000080U)
+#define OFFSET_PFC_DRV1CTRL     (0x00000084U)
+#define OFFSET_PFC_DRV2CTRL     (0x00000088U)
+
+#if (RCAR_LSI == RCAR_S4)
+#define	PFC_DRVCTRL1_GP1_DM0	(PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL)	// R/W	32	POC control register0 PortGroup 3
+#define	PFC_DRVCTRL2_GP1_DM0	(PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL)	// R/W	32	POC control register1 PortGroup 3
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define	PFC_DRVCTRL0_GP3_DM0	(PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL)	// R/W	32	POC control register0 PortGroup 3
+#define	PFC_DRVCTRL1_GP3_DM0	(PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL)	// R/W	32	POC control register1 PortGroup 3
+#endif /* RCAR_LSI == RCAR_S4 */
+
+#define	PFC_PMMR(addr)			((addr) & (uintptr_t)0xFFFFF800U)	// R/W	32	LSI Multiplexed Pin Setting Mask Register
+
+#endif /* RCAR_REGISTER_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/rst_register.h

@@ -0,0 +1,65 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : RST register header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          rst_register.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef RST_REGISTER_H_
+#define RST_REGISTER_H_
+
+#include <rcar_register.h>
+
+#define RST_BASE        (BASE_RESET_ADDR)   /* 0xE6160000 */
+
+#define RST_MODEMR0         (RST_BASE + 0x0000U)    /* Mode pin register0 */
+#define RST_MODEMR1         (RST_BASE + 0x0004U)    /* Mode pin register1 */
+#define RST_MODEMR0_MD31    (1U << 31U)
+#define RST_MODEMR1_MD32    (1U << 0U)
+
+#define RST_MODEMR0_BOOT_DEV_MASK           (0x0000001EU)
+#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160  (0x00000004U)
+#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80   (0x00000006U)
+#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40   (0x00000008U)
+#define RST_MODEMR0_BOOT_DEV_EMMC_50X8      (0x0000001AU)
+
+/* SCIF / HSCIF clock speed */
+#define MODEMR_SCIF_DLMODE          (0x00000000U)
+#define MODEMR_HSCIF_DLMODE_921600  (0x00000001U)
+#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
+#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
+
+#endif /* RST_REGISTER_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram.h

@@ -0,0 +1,35 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : RT-VRAM driver header
+ ******************************************************************************/
+
+#ifndef RTVRAM_H_
+#define RTVRAM_H_
+
+#include <rtvram_register.h>
+
+void rtvram_extendmode(void);
+
+#endif /* RTVRAM_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram_register.h

@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : RT-VRAM register header
+ ******************************************************************************/
+
+#ifndef RTVRAM_REGISTER_H__
+#define RTVRAM_REGISTER_H__
+
+#include <stdint.h>
+
+/* RT-VRAM register base address */
+#define RTVRAM_REG_BASE    (0xFFEC0000U)
+
+#define RTVRAM_SECDIVD     (RTVRAM_REG_BASE + 0x0000U)
+#define RTVRAM_SECCTRRD    (RTVRAM_REG_BASE + 0x0040U)
+#define RTVRAM_SECCTRWD    (RTVRAM_REG_BASE + 0x0340U)
+#define RTVRAM_EXT_MODE    (RTVRAM_REG_BASE + 0x8500U)
+#define RTVRAM_VBUF_CFG    (RTVRAM_REG_BASE + 0x6504U)
+#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U)
+#define RTVRAM_VBUF_BADDR  (RTVRAM_REG_BASE + 0xC580U)
+
+/* RT-VRAM0 register base address */
+#define RTVRAM0_REG_BASE    (0xFFE90000U)
+/* RT-VRAM1 register base address */
+#define RTVRAM1_REG_BASE    (0xFFEC0000U)
+
+#define RTVRAM0_SECDIVD     (RTVRAM0_REG_BASE + 0x0000U)
+#define RTVRAM0_SECCTRRD    (RTVRAM0_REG_BASE + 0x0040U)
+#define RTVRAM0_SECCTRWD    (RTVRAM0_REG_BASE + 0x0340U)
+
+#define RTVRAM1_SECDIVD     (RTVRAM1_REG_BASE + 0x0000U)
+#define RTVRAM1_SECCTRRD    (RTVRAM1_REG_BASE + 0x0040U)
+#define RTVRAM1_SECCTRWD    (RTVRAM1_REG_BASE + 0x0340U)
+
+static inline uint32_t get_rtvram0_secdivd_addr(uint32_t num)
+{
+    return ((RTVRAM0_SECDIVD + (num * 4U)));
+}
+
+static inline uint32_t get_rtvram0_secctrrd_addr(uint32_t num)
+{
+    return ((RTVRAM0_SECCTRRD + (num * 4U)));
+}
+
+static inline uint32_t get_rtvram0_secctrwd_addr(uint32_t num)
+{
+    return ((RTVRAM0_SECCTRWD + (num * 4U)));
+}
+
+static inline uint32_t get_rtvram1_secdivd_addr(uint32_t num)
+{
+    return ((RTVRAM1_SECDIVD + (num * 4U)));
+}
+
+static inline uint32_t get_rtvram1_secctrrd_addr(uint32_t num)
+{
+    return ((RTVRAM1_SECCTRRD + (num * 4U)));
+}
+
+static inline uint32_t get_rtvram1_secctrwd_addr(uint32_t num)
+{
+    return ((RTVRAM1_SECCTRWD + (num * 4U)));
+}
+
+static inline uint32_t get_vbuf_baddr_addr(uint32_t num)
+{
+    return ((RTVRAM_VBUF_BADDR + (num * 4U)));
+}
+
+#endif  /* RTVRAM_REGISTER_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/scif.h

@@ -0,0 +1,51 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : SCIF driver header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          scif.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+#ifndef SCIF_H_
+#define SCIF_H_
+
+#include <scif_register.h>
+#include <hscif_register.h>
+
+/* Prototype */
+void scif_init(void);
+void console_putc(uint8_t outchar);
+
+#endif /* SCIF_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/scif_register.h

@@ -0,0 +1,60 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : SCIF register header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          scif_register.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+
+#ifndef SCIF_REGISTER_H_
+#define SCIF_REGISTER_H_
+
+#include <rcar_register.h>
+
+/* SCIF3 base address */
+/* 0xE6C50000 */
+#define SCIF_BASE   (BASE_SCIF_ADDR)
+
+#define SCIF_SCSMR  (SCIF_BASE + 0x0000U)   /*  16  Serial mode register */
+#define SCIF_SCBRR  (SCIF_BASE + 0x0004U)   /*  8   Bit rate register */
+#define SCIF_SCSCR  (SCIF_BASE + 0x0008U)   /*  16  Serial control register */
+#define SCIF_SCFTDR (SCIF_BASE + 0x000CU)   /*  8   Transmit FIFO data register */
+#define SCIF_SCFSR  (SCIF_BASE + 0x0010U)   /*  16  Serial status register */
+#define SCIF_SCFCR  (SCIF_BASE + 0x0018U)   /*  16  FIFO control register */
+#define SCIF_SCLSR  (SCIF_BASE + 0x0024U)   /*  16  Line status register */
+#define SCIF_CKS    (SCIF_BASE + 0x0034U)   /*  16  Clock Select register */
+
+#endif /* SCIF_REGISTER_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_config.h

@@ -0,0 +1,80 @@
+#ifndef SCMT_CONFIG_H_
+#define SCMT_CONFIG_H_
+
+/* Activate measurement functions. Provide dummy functions otherwise */
+#ifndef MEASURE_TIME
+#define MEASURE_TIME (0)
+#endif
+
+/* Replace printing by dummy function. This will keep timer init, but removes impact of printing on system performance */
+#ifndef MEASURE_TIME_NOPRINT
+#define MEASURE_TIME_NOPRINT (0)
+#endif
+
+/* Only first IPL should init the timer.
+   In case of bus access issues, you can check addresses and register values with SCMT_DEBUG.
+   (Dont forget to add a call to scmt_module_start then and set debug level to NOTICE(2). ) */
+#define SCMT_INIT   (0)
+#define SCMT_DEBUG  (0)
+
+/* SCMT base address */
+/* V4H:0xE6040000 */
+/* V4H-ICUMX:  0xFC000000 + (13*0x00200000) + 0x00040000 = 0xFDA40000 */
+#define SCMT_BASE   (0xE6040000)
+
+/* For boot time measurement, you can signal the start of SCMT by GPIO pin toggle */
+/* See code for adaption of toggled pin */
+#define SCMT_TOGGLE_GPIO (0)
+
+/* SCMT is counting with OSCCLK = 131.57 kHz */
+/* Tick = 7.6 µs*/
+/* Full 32-bit wrap around therefore: 32643 seconds == 9.07 hours */
+/* NOTE: WRAPAROUND HANDLING NOT IMPLEMENTED! */
+#define SCMT_MS2TICKS(ms) ((ms)*131.579)
+
+/* If the startup time until start of SCMT is known, we can set it as start value of the timer to see absolute time right away */
+//#define SCMT_START_VALUE (0)    /* No offset, add offset using your spreadsheet program */
+//#define SCMT_START_VALUE (2750) /* 20.9ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 160MHz, Unsecure Boot */
+//#define SCMT_START_VALUE (2842) /* 21.6ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 80MHz, Unsecure Boot */
+//#define SCMT_START_VALUE (2974) /* 22.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 133MHz QuadIO, Unsecure Boot */
+//#define SCMT_START_VALUE (3237) /* 24.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 80MHz QuadIO, Unsecure Boot */
+#define SCMT_START_VALUE (7184) /* 54.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 40MHz, Unsecure Boot */
+
+/* Start a little self-test routine to check Timer-Frequency against baudrate */
+/* #define TIMER_TEST_VS_BAUD (921600) */
+#define TIMER_TEST_VS_BAUD (0)
+
+/* SCMT frequency slightly depends on MD-Pin settings!! See V4H UM Table 8.1.4e Note 5 */
+#define TIMER_FREQ (131578.9)
+
+/* Module name show in log output */
+#define MODULE "Cx:"
+
+/* Arry size for time checkpoints */
+#define TIME_CHECKPOINTS_MAX (20)
+
+/* Print additional infos about compiler or MODEMR register */
+#define PRINT_INFO (0)
+
+/* Calculates milliseconds from timer ticks. May be disabled if compiler is currently not prepared to handle floats */
+#define PRINT_FLOAT (1)
+
+/* PRINTING
+   You need to configure a way to hook into the systems print functionality
+*/
+
+/* Uses the ERROR macro defined by log.h - Works for ICUMX and CR Core */
+#include <log.h>          /* Access to ERROR() print function */
+#define PRINTFN(args...) ERROR(args)
+
+/* Uses facilities provided by Dummy_CA76 application */
+// #define USE_LOG_PRINTF (1)
+// void log_printf(const char *fmt, ...); /* Provided by scmt_checkpoint_log.c */
+// int32_t PutChar(char outChar);         /* Provided by devdrv.c */
+// #define PRINTFN(args...) {log_printf(args);}
+// #define PUTFN(outChar) PutChar(outChar)
+
+
+
+
+#endif

IPL/Customer/Mobis/V4H_Cx_Loader/include/secure_boot.h

@@ -0,0 +1,60 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+/*******************************************************************************
+ * DESCRIPTION   : ICUMIF control function header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          secure_boot.h
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 17.06.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *         : 16.02.2023 0.03     Added prototype declaration of final_hash_cmp.
+ *****************************************************************************/
+
+#ifndef SECURE_BOOT_H_
+#define SECURE_BOOT_H_
+
+#define SECURE_BOOT (0x0U)
+#define NORMAL_BOOT (0x211883DFU)
+
+#define ROMAPI_OK                           (0x00000000U)
+#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU)
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void secureboot_init(void);
+uint32_t judge_bootmode(void);
+void secureboot_verify(LOAD_INFO* li, uint32_t start, uint32_t end);
+int secureboot_image(LOAD_INFO* li, int do_panic);
+void final_hash_cmp(void);
+
+#endif /* SECURE_BOOT_H_ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/include/string.h

@@ -0,0 +1,52 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   :  string function header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          string.h
+ * - Version      : 0.01
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 06.04.2023 0.01     First Release
+*****************************************************************************/
+
+#ifndef STRING_H__
+#define STRING_H__
+
+#include <stddef.h>
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void *memcpy(void *dst, const void *src, size_t len);
+void *memset(void *dst, int val, size_t len);
+int memcmp(const void * cs, const void * ct, size_t count);
+
+#endif /* STRING_H__ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/swdt.h

@@ -0,0 +1,105 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : swdt header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          swdt.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 12.08.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+#ifndef SWDT_H_
+#define SWDT_H_
+
+#include <stdint.h>
+#include "mem_io.h"
+#include "rst_register.h"
+
+#define SWDT_BASE              (0xE6030000U)
+#define SWDT_WTCNT             (SWDT_BASE + 0x0000U)
+#define SWDT_WTCSRA            (SWDT_BASE + 0x0004U)
+#define SWDT_WTCSRB            (SWDT_BASE + 0x0008U)
+
+#define WTCNT_UPPER_BYTE       (0x5A5A0000U)
+#define WTCSRA_UPPER_BYTE      (0xA5A5A500U)
+#define WTCSRB_UPPER_BYTE      (0xA5A5A500U)
+#define WTCNT_RESET_VALUE      (0xF488U)
+#define WTCSRA_BIT_CKS         (0x0007U)
+#define WTCSRB_BIT_CKS         (0x003FU)
+#define SWDT_RSTMSK            (0U << 1U)
+#define WTCSRA_WOVFE           (1U << 3U)
+#define WTCSRA_WRFLG           (1U << 5U)
+#define WTCSRA_TME             (1U << 7U)
+
+#define WDTRSTCR_MASK_ALL      (0x0000FFFFU)
+#define WTCSRA_MASK_ALL        (0x000000FFU)
+#define WTCNT_INIT_DATA        (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
+#define WTCSRA_INIT_DATA       (WTCSRA_UPPER_BYTE + 0x0FU)
+#define WTCSRB_INIT_DATA       (WTCSRB_UPPER_BYTE + 0x21U)
+
+/* CKS0 setting */
+#define OSCCLK_32              (32U)          /* 011:OSCCLK/32 */
+#define WTCSRA_CKS0_OSCCLK     (0x00000003U)
+
+/* WDT Timeout Setting */
+/* OSCCLK */
+#define OSCCLK_133330HZ        (133330U)      /* MD13=0 MD14=0*/
+#define OSCCLK_131570HZ        (131570U)      /* MD13=H MD14=L*/
+
+/* clock */
+/* (micro sec / (Hz / RPhi) */
+#define CLK_133330HZ           ((uint32_t)((1U * 1000U * 1000U) \
+                               / (OSCCLK_133330HZ / OSCCLK_32)))
+#define CLK_131570HZ           ((uint32_t)((1U * 1000U * 1000U) \
+                               / (OSCCLK_131570HZ / OSCCLK_32)))
+
+#define SWDT_COUNT_SEC         (10U)           /* set param(1--10sec) */
+
+/* SWDT over flow sec need count*/
+#define SWDT_COUNT_133330HZ    ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \
+                               / CLK_133330HZ))
+#define SWDT_COUNT_131570HZ    ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \
+                               / CLK_131570HZ))
+
+#define SWDTCNT_133330HZ       (0x10000U - SWDT_COUNT_133330HZ)
+#define SWDTCNT_131570HZ       (0x10000U - SWDT_COUNT_131570HZ)
+
+#define MD14_MD13_TYPE_0       (0x00000000U)   /* MD14=0 MD13=0 */
+#define MD14_MD13_TYPE_1       (0x00002000U)   /* MD14=0 MD13=1 */
+#define MD14_MD13_TYPE_3       (0x00006000U)   /* MD14=1 MD13=1 */
+#define CHECK_MD13_MD14        (0x00006000U)
+
+/* Prototype */
+void swdt_init(void);
+void swdt_exec(void);
+void swdt_release(void);
+#endif /* SWDT_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/timer.h

@@ -0,0 +1,51 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : timer header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          timer.h
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 09.05.2022 0.02     Moved the definition of the define value
+ *         : 31.10.2022 0.03     License notation change.
+ *****************************************************************************/
+#ifndef TIMER_H_
+#define TIMER_H_
+
+#include <stdint.h>
+#include <mem_io.h>
+
+/* Prototype */
+void generic_timer_init(void);
+void micro_wait(uint64_t micro_sec);
+
+#endif /* TIMER_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/include/types.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Type header
+ ******************************************************************************/
+/******************************************************************************
+ * @file          types.h
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+
+#ifndef TYPES_H
+#define TYPES_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * File Name: types.h
+ * Contents : Types Define
+ ****************************************************************************/
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef FALSE
+#define FALSE       (0U)
+#endif
+
+#ifndef TRUE
+#define TRUE        (1U)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h

@@ -0,0 +1,36 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#ifndef	BOOT_INIT_DRAM
+#define	BOOT_INIT_DRAM
+
+extern uint32_t R_DRAM_Init(void);
+#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U)
+void r_set_pi_rdlvl_interval(void);
+#endif
+
+#define INITDRAM_OK (0)
+#define INITDRAM_NG (0xFFFFFFFFU)
+#define INITDRAM_ERR_I (0xFFFFFFFFU)
+
+#endif /* BOOT_INIT_DRAM */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk

@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2015-2023, Renesas Electronics Corporation All rights reserved.
+#
+
+ifeq (${LSI},V4H)
+  OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram.o
+  OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram_config.o
+else ifeq (${LSI},V4M)
+  OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram.o
+  OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram_config.o
+endif
+OBJ_FILE += ip/ddr/dram_sub_func.o

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c

@@ -0,0 +1,36 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#include <stdint.h>
+#include "dram_sub_func.h"
+
+void R_DRAM_Get_Boot_Status(uint32_t *status)
+{
+	*status = DRAM_BOOT_STATUS_COLD;
+}
+
+uint32_t R_DRAM_Update_Boot_Status(uint32_t status)
+{
+	uint32_t ret = 0U;
+	return ret;
+}

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h

@@ -0,0 +1,33 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#ifndef DRAM_SUB_FUNC
+#define DRAM_SUB_FUNC
+
+#define DRAM_BOOT_STATUS_COLD	(0U)
+#define DRAM_BOOT_STATUS_WARM	(1U)
+
+void R_DRAM_Get_Boot_Status(uint32_t *status);
+uint32_t R_DRAM_Update_Boot_Status(uint32_t status);
+
+#endif /* DRAM_SUB_FUNC_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c

@@ -0,0 +1,194 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#include <stdint.h>
+#if defined(__RH850G3K__)
+#include "mem_io.h"
+#include "log.h"
+#else
+#include "mem_io.h"
+#include "log.h"
+#endif
+#include "boot_init_dram_config.h"
+#include "boot_init_dram_regdef.h"
+
+/*******************************************************************************
+ *    PLEASE SET board number or board judge function
+ ******************************************************************************/
+// #define BOARD_JUDGE_AUTO
+#ifdef BOARD_JUDGE_AUTO
+static uint32_t r_board_judge(void);
+uint32_t r_boardcnf_get_brd_type(void)
+{
+    return r_board_judge();
+}
+#else /* BOARD_JUDGE_AUTO */
+uint32_t r_boardcnf_get_brd_type(void)
+{
+        return (2);
+}
+#endif /* BOARD_JUDGE_AUTO */
+
+/**
+* RENESAS WHITE HAWK BOARD EXAMPLE
+* @par TraceID Cover_SW_UD:Cover_HW_DD
+* V4H-LPDDR5-DDR-SW-UD-01-02:V4H-LPDDR5-DDR-HW-DD-01-04-01
+* @param[in] brd Argument for dummy read
+* @param[in] clk The pointer which indicate the clock frequency
+* @param[in] div The pointer which indicate the clock frequency division
+* @details judged by md14/md13\n
+* 16.66MHz CLK,DIV= 50,3  (md14,md13==0,0)
+* 20.00MHz CLK,DIV= 60,3  (md14,md13==0,1)
+* 33.33MHz CLK,DIV=100,3  (md14,md13==1,1)
+*/
+void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
+{
+    uint32_t md;
+
+    md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
+    switch (md)
+    {
+        case 0x0U   : *clk =  50U; *clk_div = 3U;           break;  /*  50 / 3 = 16.66MHz */
+        case 0x1U   : *clk =  60U; *clk_div = 3U;           break;  /*  60 / 3 = 20.00MHz */
+        case 0x2U   : NOTICE("MD14/MD13 is invalid!!\n");   panic;  /*  Not supported     */
+        case 0x3U   : *clk = 100U; *clk_div = 3U;           break;  /* 100 / 3 = 33.33MHz */
+        default     : /* nop */                             break;
+    }
+    (void)brd;
+}
+
+/*******************************************************************************
+ *  DDR MBPS TARGET
+ *  PLEASE DEFINE HOW TO JUDGE DDR BPS
+ ******************************************************************************/
+/**
+* DDRxxxx (judge by md19, md17) : Mbps
+* @par TraceID Cover_SW_UD:Cover_HW_DD
+* V4H-LPDDR5-DDR-SW-UD-01-03:V4H-LPDDR5-DDR-HW-DD-01-04-02
+* @param[in] brd Argument for dummy read
+* @param[in] mbps The pointer which indicate the ddr frequency
+* @param[in] div  The pointer which indicate the ddr frequency division
+* @details SSCG enable / disable for PLL1 (judge by md37/md36)
+* According to Bit[17] of RST_MODEMR0 and Bit[5:4] of RST_MODEMR1,
+* determine the value of ddr mbps and mbps division.
+*/
+void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg)
+{
+    uint32_t md;
+    uint32_t product;
+
+    md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
+    md = (md | (md >> 1)) & 0x03U;
+    *sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U;
+    product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
+
+    if (product == 0x01U)
+    {
+        /* V4H-5 */
+        switch (md)
+        {
+            case 0x0U : *mbps =   5000U; *mbps_div = 1U; break;    /* 5000Mbps */
+            case 0x1U : *mbps =   5000U; *mbps_div = 1U; break;    /* 5000Mbps */
+            case 0x2U : *mbps =   5000U; *mbps_div = 1U; break;    /* 5000Mbps */
+            case 0x3U : *mbps =   4800U; *mbps_div = 1U; break;    /* 4800Mbps */
+            default   : /* Nothing */                    break;
+        }
+    }
+    else if (product == 0x02U)
+    {
+        /* V4H-3 */
+        switch (md)
+        {
+            case 0x0U : *mbps =   4800U; *mbps_div = 1U; break;    /* 4800Mbps */
+            case 0x1U : *mbps =   4800U; *mbps_div = 1U; break;    /* 4800Mbps */
+            case 0x2U : *mbps =   4800U; *mbps_div = 1U; break;    /* 4800Mbps */
+            case 0x3U : *mbps =   4800U; *mbps_div = 1U; break;    /* 4800Mbps */
+            default   : /* Nothing */                    break;
+        }
+    }
+    else
+    {
+        /* V4H-7 */
+        switch (*sscg)
+        {
+            case 0x0U :
+                switch (md)
+                {
+                    case 0x0U   :   *mbps =  6400U; *mbps_div = 1U; break;  /* 6400Mbps */
+                    case 0x1U   :   *mbps =  6000U; *mbps_div = 1U; break;  /* 6000Mbps */
+                    case 0x2U   :   *mbps =  5500U; *mbps_div = 1U; break;  /* 5500Mbps */
+                    case 0x3U   :   *mbps =  4800U; *mbps_div = 1U; break;  /* 4800Mbps */
+                    default     :   /* nop */                       break;
+                }
+                break;
+            case 0x1U :
+                switch (md)
+                {
+                    case 0x0U   :   *mbps = 19000U; *mbps_div = 3U; break;  /* 6333Mbps */
+                    case 0x1U   :   *mbps =  6000U; *mbps_div = 1U; break;  /* 6000Mbps */
+                    case 0x2U   :   *mbps =  5500U; *mbps_div = 1U; break;  /* 5500Mbps */
+                    case 0x3U   :   *mbps =  4800U; *mbps_div = 1U; break;  /* 4800Mbps */
+                    default     :   /* nop */                       break;
+                }
+                break;
+            case 0x2U :                                                     /* Not supported  */
+                NOTICE("This MD37/MD36 value is invalid!!\n");panic;
+            case 0x3U :
+                switch (md)
+                {
+                    case 0x0U   :   *mbps = 19000U; *mbps_div = 3U;  break;  /* 6333Mbps */
+                    case 0x1U   :   *mbps =  6000U; *mbps_div = 1U;  break;  /* 6000Mbps */
+                    case 0x2U   :   *mbps =  5500U; *mbps_div = 1U;  break;  /* 5500Mbps */
+                    case 0x3U   :   *mbps =  4800U; *mbps_div = 1U;  break;  /* 4800Mbps */
+                    default     :   /* nop */                        break;
+                }
+                break;
+            default :
+                /* nop */
+                break;
+        }
+    }
+    (void)brd;
+}
+
+#ifdef BOARD_JUDGE_AUTO
+/*******************************************************************************
+ *  SAMPLE board detect function
+ ******************************************************************************/
+/**
+* Select the setting parameters about the Spieder board you use.
+* @par TraceID Cover_SW_UD:Cover_HW_DD
+* V4H-LPDDR5-DDR-SW-UD-10:V4H-LPDDR5-DDR-HW-DD-01-03-02
+* @return uint32_t Selected table index, this is sample value 0.
+* @details Pass the return value from the r_board_judge function.
+* In case that "BOARD_JUDGE_AUTO" is not defined, Another process will be called.\n\n
+*/
+static uint32_t r_board_judge(void)
+{
+    uint32_t brd;
+
+    brd = 0U;    /* white hawk (64Gbit 1rank)*/
+
+    return brd;
+}
+#endif

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h

@@ -0,0 +1,282 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#ifndef BOOT_INIT_DRAM_CONFIG
+#define BOOT_INIT_DRAM_CONFIG
+
+#include "boot_init_dram_regdef.h"
+
+//! @details DRAM Param setting
+#define JS2_DERATE                  0U
+//! @details Average periodic refresh interval/Average Refresh Interval [ns]
+#define DBSC_REFINT                 1920U
+#ifndef DBSC_REFINTS
+//! 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT.
+#define DBSC_REFINTS                0U
+#endif
+//! @details Periodic-WriteDQ/ReadDQ Training Interval [us]
+#define PERIODIC_TRAINING_INTERVAL  20000U
+
+/*******************************************************************************
+ *  NUMBER OF BOARD CONFIGRATION
+ *  PLEASE DEFINE
+ ******************************************************************************/
+//! @details Add User platform BOARD
+#define BOARDNUM    3U
+
+/*******************************************************************************
+ * BOARD CONFIGRATION
+ * PLEASE DEFINE boardcnfs[]
+ ******************************************************************************/
+uint32_t r_boardcnf_get_brd_type(void);
+void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
+void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg);
+
+/*******************************************************************************
+ *    BOARD CONFIGRATION
+ *    PLEASE DEFINE boardcnfs[]
+ ******************************************************************************/
+typedef struct{
+    /*
+     0x00...0000B:  4Gb dual channel die /  2Gb single channel die
+     0x01...0001B:  6Gb dual channel die /  3Gb single channel die
+     0x02...0010B:  8Gb dual channel die /  4Gb single channel die
+     0x03...0011B: 12Gb dual channel die /  6Gb single channel die
+     0x04...0100B: 16Gb dual channel die /  8Gb single channel die
+     0x05...0101B: 24Gb dual channel die / 12Gb single channel die
+     0x06...0110B: 32Gb dual channel die / 16Gb single channel die
+     0x07...0111B: 24Gb single channel die
+     0x08...1000B: 32Gb single channel die
+     0xFF...NO_MEMORY
+    */
+    uint8_t bdcfg_ddr_density[CS_CNT];
+    /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+    uint32_t bdcfg_ca_swap;
+    /* SoC dqsX([1][0]) -> MEM dqsY: */
+    uint8_t bdcfg_dqs_swap;
+    /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
+    uint32_t bdcfg_dq_swap[SLICE_CNT];
+    /* SoC dm -> MEM dqY/dm:  (8 means DM) */
+    uint8_t bdcfg_dm_swap[SLICE_CNT];
+    /* SoC ckeX([1][0]) -> MEM csY */
+    uint8_t bdcfg_cs_swap;
+}st_boardcnf_ch_t;
+
+typedef struct {
+
+    /* ch in use */
+    uint8_t bdcfg_phyvalid;
+    /* Read vref (SoC) training range         : [23:16]step  / [15:8]stop  / [7:0]start,  0x00000000 = default val */
+    uint32_t bdcfg_vref_r;
+    /* Write vref (MR14, MR15) training range : [15:8]stop   / [7:0]start,  0x0000 = default val */
+    uint16_t bdcfg_vref_w;
+    /* CA vref (MR12) training range          : [15:8]stop   / [7:0]start,  0x0000 = default val */
+    uint16_t bdcfg_vref_ca;
+    /* RFM required check                     : 0x01 = check enable, 0x00 = check disable */
+    uint8_t bdcfg_rfm_chk;
+    //! @details Board parameter about channels
+    st_boardcnf_ch_t ch[4];
+}st_boardcnf_t;
+
+static const st_boardcnf_t boardcnfs[BOARDNUM] = {
+/*
+ * boardcnf[0] RENESAS V4H White Hawk (64Gbit 1rank)
+ */
+{
+    0x0FU,                /* bdcfg_phyvalid */
+    0x00000000U,          /* bdcfg_vref_r */
+    0x0000U,              /* bdcfg_vref_w */
+    0x0000U,              /* bdcfg_vref_ca */
+    0x01U,                /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x04506132U,
+/* bdcfg_dqs_swap */           0x01U,
+/* bdcfg_dq_swap[] */        { 0x26147085U, 0x12306845U },
+/* bdcfg_dm_swap[] */        { 0x03U, 0x07U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x02341065U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x56782314U, 0x71048365U },
+/* bdcfg_dm_swap[] */        { 0x00U, 0x02U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[2] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x02150643U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x58264071U, 0x41207536U },
+/* bdcfg_dm_swap[] */        { 0x03U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[3] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x01546230U,
+/* bdcfg_dqs_swap */           0x01U,
+/* bdcfg_dq_swap[] */        { 0x45761328U, 0x62801745U },
+/* bdcfg_dm_swap[] */        { 0x00U, 0x03U },
+/* bdcfg_cs_swap */            0x10U
+        }
+    }
+},
+#if 0   // added from v3.33.3, not used
+ /*
+ * boardcnf[1] RENESAS V4H White Hawk (64Gbit 2rank)
+ */
+{
+    0x0FU,                /* bdcfg_phyvalid */
+    0x00000000U,          /* bdcfg_vref_r */
+    0x0000U,              /* bdcfg_vref_w */
+    0x0000U,              /* bdcfg_vref_ca */
+    0x01U,                /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */    { 0x04U, 0x04U },
+/* bdcfg_ca_swap */            0x04506132U,
+/* bdcfg_dqs_swap */           0x01U,
+/* bdcfg_dq_swap[] */        { 0x26147085U, 0x12306845U },
+/* bdcfg_dm_swap[] */        { 0x03U, 0x07U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */    { 0x04U, 0x04U },
+/* bdcfg_ca_swap */            0x02341065U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x56782314U, 0x71048365U },
+/* bdcfg_dm_swap[] */        { 0x00U, 0x02U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[2] */    {
+/* bdcfg_ddr_density[] */    { 0x04U, 0x04U },
+/* bdcfg_ca_swap */            0x02150643U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x58264071U, 0x41207536U },
+/* bdcfg_dm_swap[] */        { 0x03U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[3] */    {
+/* bdcfg_ddr_density[] */    { 0x04U, 0x04U },
+/* bdcfg_ca_swap */            0x01546230U,
+/* bdcfg_dqs_swap */           0x01U,
+/* bdcfg_dq_swap[] */        { 0x45761328U, 0x62801745U },
+/* bdcfg_dm_swap[] */        { 0x00U, 0x03U },
+/* bdcfg_cs_swap */            0x10U
+        }
+    }
+},
+#endif
+/*
+ * boardcnf[1] RENESAS V4H (4ch)
+ */
+{
+    0x0FU,                /* bdcfg_phyvalid */
+    0x00000000U,          /* bdcfg_vref_r */
+    0x0000U,              /* bdcfg_vref_w */
+    0x0000U,              /* bdcfg_vref_ca */
+    0x01U,                /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[2] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[3] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0xFFU },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        }
+    }
+},
+/*
+ * boardcnf[2]MOBIS Proto1 20240717
+ */
+{
+    0x0FU,                /* bdcfg_phyvalid */
+    0x00000000U,          /* bdcfg_vref_r */
+    0x0000U,              /* bdcfg_vref_w */
+    0x0000U,              /* bdcfg_vref_ca */
+    0x01U,                /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
+/* bdcfg_ca_swap */0x04506132U,
+/* bdcfg_dqs_swap */0x01U,
+/* bdcfg_dq_swap[] */{ 0x26147085U, 0x12306845U },
+/* bdcfg_dm_swap[] */{ 0x03U, 0x07U },
+/* bdcfg_cs_swap */0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
+/* bdcfg_ca_swap */0x02341065U,
+/* bdcfg_dqs_swap */0x10U,
+/* bdcfg_dq_swap[] */{ 0x58762314U, 0x71048365U },
+/* bdcfg_dm_swap[] */{ 0x00U, 0x02U },
+/* bdcfg_cs_swap */0x10U
+        },
+/* ch[2] */    {
+/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
+/* bdcfg_ca_swap */0x02150643U,
+/* bdcfg_dqs_swap */0x10U,
+/* bdcfg_dq_swap[] */{ 0x58264071U, 0x41207536U },
+/* bdcfg_dm_swap[] */{ 0x03U, 0x08U },
+/* bdcfg_cs_swap */0x10U
+        },
+/* ch[3] */    {
+/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
+/* bdcfg_ca_swap */0x01546230U,
+/* bdcfg_dqs_swap */0x01U,
+/* bdcfg_dq_swap[] */{ 0x48761325U, 0x62801745U },
+/* bdcfg_dm_swap[] */{ 0x00U, 0x03U },
+/* bdcfg_cs_swap */0x10U
+        }
+    }
+}
+
+};
+#endif /* BOOT_INIT_DRAM_CONFIG */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h

@@ -0,0 +1,203 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#ifndef BOOT_INIT_DRAM_REGDEF
+#define BOOT_INIT_DRAM_REGDEF
+
+#if defined(__RH850G3K__)
+#include "remap_register.h"
+#endif
+
+//! @details The version of DDR code
+#define RCAR_DDR_VERSION           "rev.1.10"
+//! @details The number of channels V4H has
+#define DRAM_CH_CNT                 0x04U
+//! @details The number of slices V4H has
+#define SLICE_CNT                   0x02U
+//! @details The number of chip select V4H has
+#define CS_CNT                      0x02U
+
+//! @details for pll setting
+#define CLK_DIV(a, diva, b, divb)   (((a) * (divb)) / ((b) * (diva)))
+
+//! @details for ddr density setting
+#define DBMEMCONF_REG(d3, row, BG, bank, col, dw)   (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
+//! @details for 16bit value
+#define DBMEMCONF_REGD(density)     (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U))   /* 16bit */
+
+//! @details Kick bit setting CPG PLL3 division
+#define CPG_FRQCRD_KICK_BIT         (1U << 31)
+//! @details Kick bit to reflect setting CPG PLL3 value
+#define CPG_PLL3CR0_KICK_BIT        (1U << 31)
+//! @details Status bit to check CPG PLL3 works normally
+#define CPG_PLLECR_PLL3ST_BIT       (1U << 11)
+
+#if defined(__RH850G3K__)
+//! @details If this bin is processed by RH850G3K, address will be remapped.
+#define CPG_BASE    (BASE_CPG_ADDR)
+#else
+//! @details If this bin is processed by Arm core, address will be "0xE6150000U".
+#define CPG_BASE                    (0xE6150000U)
+#endif
+//! @details 32-bit readable/writable register
+#define CPG_CPGWPR                  (CPG_BASE + 0x0000U)
+//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency
+#define CPG_FRQCRD0                 (CPG_BASE + 0x080CU)
+//! @details PLL Enable Control Register
+#define CPG_PLLECR                  (CPG_BASE + 0x0820U)
+//! @details The register specifies the integer multiplication ratio
+#define CPG_PLL3CR0                 (CPG_BASE + 0x083CU)
+//! @details The register specifies the fractional multiplication
+#define CPG_PLL3CR1                 (CPG_BASE + 0x08C0U)
+//! @details Functional Safety Reset Check Clear Register
+#define CPG_FSRCHKCLRR4             (CPG_BASE + 0x0590U)
+//! @details Functional Safety Reset Check Set Register
+#define CPG_FSRCHKSETR4             (CPG_BASE + 0x0510U)
+//! @details Functional Safety Reset Check Register A
+#define CPG_FSRCHKRA4               (CPG_BASE + 0x0410U)
+//! @details Software Reset Status Register
+#define CPG_SRCR4                   (CPG_BASE + 0x2C10U)
+//! @details Software Reset Clearing Register
+#define CPG_SRSTCLR4                (CPG_BASE + 0x2C90U)
+
+#if defined(__RH850G3K__)
+//! @details If this bin is processed by RH850G3K, address will be remapped.
+#define RST_BASE    (BASE_RESET_ADDR)
+#else
+//! @details If this bin is processed by Arm core, address will be 0xE6160000U.
+#define RST_BASE                    (0xE6160000U)
+#endif
+//! @details 32-bit read-only register, which is initialized only by POR.
+#define RST_MODEMR0                 (RST_BASE + 0x0000U)
+//! @details 32-bit read-only register, which is initialized only by POR.
+#define RST_MODEMR1                 (RST_BASE + 0x0004U)
+
+#if defined(__RH850G3K__)
+#define OTP_MEM_1_BASE               (BASE_OTP_MEM_ADDR)
+#else
+#define OTP_MEM_1_BASE               (0xE61BF000U)
+#endif
+#define OTP_MEM_OTPMONITOR17         (OTP_MEM_1_BASE + 0x0144U)
+#define OTP_MEM_PRODUCT_MASK         (0x000000FFU)
+
+/* Product Register */
+#define PRR                         (0xFFF00044U)
+#define PRR_PRODUCT_MASK            (0x00007F00U)
+#define PRR_CUT_MASK                (0x000000FFU)
+
+#define PRR_PRODUCT_V4H             (0x00005C00U)   /* R-Car V4H */
+
+#define PRR_PRODUCT_30              (0x00000020U)    /* ver 3.0 */
+
+/* DBSC registers */
+#if defined(__RH850G3K__)
+//! @details If this bin is processed by RH850G3K, address will be remapped.
+#define DBSC_D_BASE                 (BASE_DBSC_ADDR + 0x14000U)    /* forV4H DBSC0 clk_dbsc region    DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE                 (BASE_DBSC_ADDR)            /* forV4H DBSC0 clk_axim region    DBSC1_A_BASE = 0xE6798000U */
+#else
+//! @details If this bin is processed by RH850G3K, address will be remapped.
+#define DBSC_D_BASE                 (0xE67A4000U)   /* forV4H DBSC0 clk_dbsc region    DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE                 (0xE6790000U)   /* forV4H DBSC0 clk_axim region    DBSC1_A_BASE = 0xE6798000U */
+#endif
+//! @details DBSC4 System Configuration Register 0
+#define DBSC_DBSYSCONF0         (DBSC_A_BASE + 0x0000U)
+//! @details DBSC4 System Configuration Register 1(for DFI domain)
+#define DBSC_DBSYSCONF1         (DBSC_D_BASE + 0x0000U)
+//! @details DBSC4 System Configuration Register 1(for AXI domain)
+#define DBSC_DBSYSCONF1A        (DBSC_A_BASE + 0x0004U)
+//! @details DBSC4 System Configuration Register 2
+#define DBSC_DBSYSCONF2         (DBSC_D_BASE + 0x0004U)
+//! @details PHY type Configuration Register
+#define DBSC_DBPHYCONF0         (DBSC_D_BASE + 0x0008U)
+//! @details PHY type Configuration Register 2A
+#define DBSC_DBSYSCONF2A        (DBSC_A_BASE + 0x0008U)
+//! @details Memory Type register (for DFI domain)
+#define DBSC_DBMEMKIND          (DBSC_D_BASE + 0x0020U)
+//! @details Memory Type register (for AXI domain)
+#define DBSC_DBMEMKINDA         (DBSC_A_BASE + 0x0020U)
+//! @details SDRAM Configuration setting Register (for DFI domain)
+#define DBSC_DBMEMCONF(ch,cs)   (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
+//! @details SDRAM Configuration setting Register (for AXI domain)
+#define DBSC_DBMEMCONFA(ch,cs)  (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
+//! @details DBSC System Register 0(For DFI Domain)
+#define DBSC_DBSYSCNT0          (DBSC_D_BASE + 0x0100U)
+//! @details DBSC System Register 0(For AXI Domain)
+#define DBSC_DBSYSCNT0A         (DBSC_A_BASE + 0x0100U)
+//! @details SDRAM Access Enable Register
+#define DBSC_DBACEN             (DBSC_A_BASE + 0x0200U)
+//! @details Auto-Refresh Enable Register
+#define DBSC_DBRFEN             (DBSC_D_BASE + 0x0204U)
+//! @details Manual Command-Issuing Register
+#define DBSC_DBCMD              (DBSC_D_BASE + 0x0208U)
+//! @details Operation Complition Waiting Register
+#define DBSC_DBWAIT             (DBSC_D_BASE + 0x0210U)
+//! @details SDRAM Operation Setting Register(for DFI domain)
+#define DBSC_DBBL               (DBSC_D_BASE + 0x0400U)
+//! @details SDRAM Operation Setting Register(for AXI domain)
+#define DBSC_DBBLA              (DBSC_A_BASE + 0x0400U)
+//! @details Refresh Configuration Register 1
+#define DBSC_DBRFCNF1           (DBSC_D_BASE + 0x0414U)
+//! @details Refresh Configuration Register 2
+#define DBSC_DBRFCNF2           (DBSC_D_BASE + 0x0418U)
+//! @details SDRAM Callibration Configuration Register
+#define DBSC_DBCALCNF           (DBSC_D_BASE + 0x0424U)
+//! @details DBI Configuration Register
+#define DBSC_DBDBICNT           (DBSC_D_BASE + 0x0518U)
+//! @details DFI PHY Master Control Register
+#define DBSC_DBDFIPMSTRCNF      (DBSC_D_BASE + 0x0520U)
+//! @details DFI Control Update Configuration Register
+#define DBSC_DBDFICUPDCNF       (DBSC_D_BASE + 0x0540U)
+//! @details CAM Unit Operation Setting Register
+#define DBSC_DBBCAMDIS          (DBSC_A_BASE + 0x09FCU)
+//! @details Read/Write Scheduling Setting Register 1
+#define DBSC_DBSCHRW1           (DBSC_A_BASE + 0x1024U)
+//! @details Data Transfer Cycle Setting
+#define DBSC_DBSCHTR0           (DBSC_A_BASE + 0x1030U)
+//! @details SDRAM Timing Register X
+#define DBSC_DBTR(x)            (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
+//! @details Multirank Operation Setting Register x
+#define DBSC_DBRNK(x)           (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
+//! @details DFI Status Interface Input Regiser
+#define DBSC_DBDFISTAT(ch)      (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details DFI Status Interface Output Regiser
+#define DBSC_DBDFICNT(ch)       (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Unit Control Register 02
+#define DBSC_DBPDCNT2(ch)       (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Unit Lock register
+#define DBSC_DBPDLK(ch)         (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Unit register address
+#define DBSC_DBPDRGA(ch)        (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Unit register access
+#define DBSC_DBPDRGD(ch)        (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Unit Registers Mask for channel
+#define DBSC_DBPDRGM(ch)        (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Status Register0 ch
+#define DBSC_DBPDSTAT0(ch)      (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details PHY Status Register1 ch
+#define DBSC_DBPDSTAT1(ch)      (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+//! @details Interval Setting for scheduler 
+#define DBSC_DBSCHFCTST0        (DBSC_A_BASE + 0x1040U)
+//! @details Interval Setting for scheduler 
+#define DBSC_DBSCHFCTST1        (DBSC_A_BASE + 0x1044U)
+
+#endif /* BOOT_INIT_DRAM_REGDEF */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h

@@ -0,0 +1,269 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+#ifndef DDR_REGDEF
+#define DDR_REGDEF
+
+#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL                        0x10031000U
+#define PHY_PER_CS_TRAINING_MULTICAST_EN                    0x10011006U
+#define PHY_VREF_INITIAL_STEPSIZE                           0x1808100DU
+#define PHY_RDLVL_BEST_THRSHLD                              0x0004100EU
+#define PHY_RDLVL_VREF_OUTLIER                              0x1003100EU
+#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT                       0x1005102CU
+#define PHY_CALVL_VREF_DRIVING_SLICE                        0x18011030U
+#define PHY_WRLVL_HARD0_DELAY_OBS                           0x000A1038U
+#define PHY_WRLVL_HARD1_DELAY_OBS                           0x100A1038U
+#define PHY_WRLVL_STATUS_OBS                                0x001C1039U
+#define PHY_WRLVL_ERROR_OBS                                 0x0010103BU
+#define PHY_GTLVL_STATUS_OBS                                0x0012103DU
+#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                       0x1009103EU
+#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                       0x0009103FU
+#define PHY_WDQLVL_STATUS_OBS                               0x00201043U
+#define PHY_DATA_DC_CAL_START                               0x1801104DU
+#define PHY_SLV_DLY_CTRL_GATE_DISABLE                       0x1001104EU
+#define PHY_REGULATOR_EN_CNT                                0x18061050U
+#define PHY_VREF_INITIAL_START_POINT                        0x00091055U
+#define PHY_VREF_INITIAL_STOP_POINT                         0x10091055U
+#define PHY_VREF_TRAINING_CTRL                              0x00021056U
+#define PHY_RDDQ0_SLAVE_DELAY                               0x0009105DU
+#define PHY_RDDQ1_SLAVE_DELAY                               0x1009105DU
+#define PHY_RDDQ2_SLAVE_DELAY                               0x0009105EU
+#define PHY_RDDQ3_SLAVE_DELAY                               0x1009105EU
+#define PHY_RDDQ4_SLAVE_DELAY                               0x0009105FU
+#define PHY_RDDQ5_SLAVE_DELAY                               0x1009105FU
+#define PHY_RDDQ6_SLAVE_DELAY                               0x00091060U
+#define PHY_RDDQ7_SLAVE_DELAY                               0x10091060U
+#define PHY_RDDM_SLAVE_DELAY                                0x00091061U
+#define PHY_RX_CAL_ALL_DLY                                  0x18061061U
+#define PHY_RX_PCLK_CLK_SEL                                 0x00031062U
+#define PHY_DATA_DC_CAL_CLK_SEL                             0x18031063U
+#define PHY_PAD_VREF_CTRL_DQ                                0x000E1067U
+#define PHY_PER_CS_TRAINING_EN                              0x00011068U
+#define PHY_RDDATA_EN_TSEL_DLY                              0x18051069U
+#define PHY_RDDATA_EN_OE_DLY                                0x0005106AU
+#define PHY_RPTR_UPDATE                                     0x1004106CU
+#define PHY_WRLVL_RESP_WAIT_CNT                             0x0806106DU
+#define PHY_RDLVL_DLY_STEP                                  0x08041070U
+#define PHY_RDLVL_MAX_EDGE                                  0x00091071U
+#define PHY_RDDATA_EN_DLY                                   0x10051076U
+#define PHY_DQ_DM_SWIZZLE0                                  0x00201077U
+#define PHY_DQ_DM_SWIZZLE1                                  0x00041078U
+#define PHY_CLK_WRDQS_SLAVE_DELAY                           0x0009107EU
+#define PHY_WRITE_PATH_LAT_DEC                              0x1001107EU
+#define PHY_RDDQS_GATE_SLAVE_DELAY                          0x00091088U
+#define PHY_RDDQS_LATENCY_ADJUST                            0x10051088U
+#define PHY_WRITE_PATH_LAT_ADD                              0x18031088U
+#define PHY_WRITE_PATH_LAT_FRAC                             0x00081089U
+#define PHY_GTLVL_LAT_ADJ_START                             0x0005108AU
+#define PHY_ADR_CALVL_SWIZZLE0                              0x00201202U
+#define PHY_ADR_MEAS_DLY_STEP_ENABLE                        0x10011203U
+#define PHY_ADR_CALVL_RANK_CTRL                             0x18021205U
+#define PHY_ADR_CALVL_OBS1                                  0x0020120AU
+#define PHY_ADR_CALVL_OBS2                                  0x0020120BU
+#define PHY_ADR_CALVL_DLY_STEP                              0x00041210U
+#define PHY_CS_ACS_ALLOCATION_BIT2_2                        0x08021215U
+#define PHY_CS_ACS_ALLOCATION_BIT3_2                        0x10021215U
+#define PHY_CSLVL_OBS1                                      0x00201221U
+#define PHY_CLK_DC_CAL_CLK_SEL                              0x0803123AU
+#define PHY_FREQ_SEL_MULTICAST_EN                           0x08011301U
+#define PHY_FREQ_SEL_INDEX                                  0x10021301U
+#define SC_PHY_MANUAL_UPDATE                                0x18011304U
+#define PHY_SET_DFI_INPUT_RST_PAD                           0x18011311U
+#define PHY_CAL_MODE_0                                      0x000D132CU
+#define PHY_CAL_INTERVAL_COUNT_0                            0x0020132DU
+#define PHY_DATA_BYTE_ORDER_SEL                             0x0020133EU
+#define PHY_PAD_ACS_RX_PCLK_CLK_SEL                         0x10031348U
+#define PHY_PLL_CTRL                                        0x000E134BU
+#define PHY_PLL_CTRL_8X                                     0x100E134BU
+#define PHY_CAL_CLK_SELECT_0                                0x00031360U
+#define SC_PHY_WCK_CALC                                     0x1801101AU
+#define PI_START                                            0x00010800U
+#define PI_TRAIN_ALL_FREQ_REQ                               0x18010802U
+#define PI_CS_MAP                                           0x08020813U
+#define PI_WRLVL_REQ                                        0x1001081CU
+#define PI_WRLVL_CS_SW                                      0x1802081CU
+#define PI_RDLVL_REQ                                        0x18010824U
+#define PI_RDLVL_GATE_REQ                                   0x00010825U
+#define PI_RDLVL_CS_SW                                      0x08020825U
+#define PI_DRAMDCA_FLIP_MASK                                0x0802083BU
+#define PI_DRAMDCA_LVL_REQ                                  0x1001083DU
+#define PI_DCMLVL_CS_SW                                     0x1802083DU
+#define PI_WRDCM_LVL_EN_F1                                  0x0002083FU
+#define PI_DRAMDCA_LVL_EN_F1                                0x0802083FU
+#define PI_WRDCM_LVL_EN_F2                                  0x1802083FU
+#define PI_DRAMDCA_LVL_EN_F2                                0x00020840U
+#define PI_TCKCKEL_F2                                       0x1804089DU
+#define PI_INT_STATUS                                       0x00200900U
+#define PI_INT_ACK_0                                        0x00200902U
+#define PI_INT_ACK_1                                        0x00030903U
+#define PI_ADDR_MUX_0                                       0x00030910U
+#define PI_ADDR_MUX_1                                       0x08030910U
+#define PI_ADDR_MUX_2                                       0x10030910U
+#define PI_ADDR_MUX_3                                       0x18030910U
+#define PI_ADDR_MUX_4                                       0x00030911U
+#define PI_ADDR_MUX_5                                       0x08030911U
+#define PI_ADDR_MUX_6                                       0x10030911U
+#define PI_DATA_BYTE_SWAP_EN                                0x18010911U
+#define PI_DATA_BYTE_SWAP_SLICE0                            0x00010912U
+#define PI_DATA_BYTE_SWAP_SLICE1                            0x08010912U
+#define PI_TDELAY_RDWR_2_BUS_IDLE_F2                        0x00080964U
+#define PI_WRLAT_F2                                         0x1007096AU
+#define PI_TWCKENL_WR_ADJ_F2                                0x1806096AU
+#define PI_TWCKENL_RD_ADJ_F2                                0x0006096BU
+#define PI_TWCKPRE_STATIC_F2                                0x0806096BU
+#define PI_TWCKPRE_TOGGLE_RD_F2                             0x1806096BU
+#define PI_TWCKENL_FS_ADJ_F2                                0x0006096CU
+#define PI_CASLAT_F2                                        0x0807096CU
+#define PI_TRFC_F2                                          0x000A0971U
+#define PI_TREF_F2                                          0x00140972U
+#define PI_TDFI_WRLVL_WW_F0                                 0x000A0974U
+#define PI_TDFI_WRLVL_WW_F1                                 0x000A0975U
+#define PI_WRLVL_EN_F2                                      0x18020975U
+#define PI_TDFI_WRLVL_WW_F2                                 0x000A0976U
+#define PI_WRLVL_WCKOFF_F2                                  0x10080976U
+#define PI_RDLVL_EN_F2                                      0x1802097AU
+#define PI_RDLVL_GATE_EN_F2                                 0x0002097BU
+#define PI_RDLVL_VREF_EN_F0                                 0x1004097BU
+#define PI_RDLVL_VREF_EN_F1                                 0x0004097DU
+#define PI_RDLVL_VREF_EN_F2                                 0x1004097EU
+#define PI_RDLAT_ADJ_F2                                     0x00090981U
+#define PI_WRLAT_ADJ_F2                                     0x00070982U
+#define PI_TDFI_CALVL_CC_F2                                 0x000A0985U
+#define PI_TDFI_CALVL_CAPTURE_F2                            0x100A0985U
+#define PI_CALVL_EN_F2                                      0x10020986U
+#define PI_TCAENT_F2                                        0x000E0989U
+#define PI_TVREF_SHORT_F2                                   0x000A098FU
+#define PI_TVREF_LONG_F2                                    0x100A098FU
+#define PI_TVRCG_ENABLE_F2                                  0x000A0990U
+#define PI_TVRCG_DISABLE_F2                                 0x100A0990U
+#define PI_CALVL_VREF_INITIAL_START_POINT_F0                0x00070991U
+#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0                 0x08070991U
+#define PI_CALVL_VREF_INITIAL_START_POINT_F1                0x18070991U
+#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1                 0x00070992U
+#define PI_CALVL_VREF_INITIAL_START_POINT_F2                0x10070992U
+#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2                 0x18070992U
+#define PI_TDFI_CALVL_STROBE_F2                             0x08040995U
+#define PI_TXP_F2                                           0x10050995U
+#define PI_TMRWCKEL_F2                                      0x18080995U
+#define PI_TCKEHDQS_F2                                      0x1006099DU
+#define PI_TFC_F2                                           0x000A099EU
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0               0x100709A0U
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0                0x180709A0U
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1               0x000709A4U
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1                0x080709A4U
+#define PI_TDFI_WDQLVL_WR_F2                                0x000A09A6U
+#define PI_TDFI_WDQLVL_RW_F2                                0x100A09A6U
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2               0x000709A7U
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2                0x080709A7U
+#define PI_WDQLVL_EN_F2                                     0x180209A7U
+#define PI_MBIST_RDLAT_ADJ_F2                               0x080909A8U
+#define PI_MBIST_TWCKENL_RD_ADJ_F2                          0x180609A8U
+#define PI_TRTP_F2                                          0x180809B3U
+#define PI_TRP_F2                                           0x000809B4U
+#define PI_TRCD_F2                                          0x080809B4U
+#define PI_TWTR_S_F2                                        0x180609B4U
+#define PI_TWTR_L_F2                                        0x000609B5U
+#define PI_TWTR_F2                                          0x100609B5U
+#define PI_TWR_F2                                           0x180809B5U
+#define PI_TRAS_MIN_F2                                      0x100909B6U
+#define PI_TDQSCK_MAX_F2                                    0x000409B7U
+#define PI_TSR_F2                                           0x100809B7U
+#define PI_TMRD_F2                                          0x180809B7U
+#define PI_TDFI_CTRLUPD_MAX_F2                              0x001509BCU
+#define PI_TDFI_CTRLUPD_INTERVAL_F2                         0x002009BDU
+#define PI_TINIT_F2                                         0x001809CCU
+#define PI_TINIT1_F2                                        0x001809CDU
+#define PI_TINIT3_F2                                        0x001809CEU
+#define PI_TINIT4_F2                                        0x001809CFU
+#define PI_TINIT5_F2                                        0x001809D0U
+#define PI_TXSNR_F2                                         0x001009D1U
+#define PI_TZQCAL_F2                                        0x100C09D6U
+#define PI_TZQLAT_F2                                        0x000709D7U
+#define PI_ZQRESET_F2                                       0x100C09D8U
+#define PI_TDQ72DQ_F2                                       0x100A09DDU
+#define PI_TCBTRTW_F2                                       0x000609DEU
+#define PI_MC_TRFC_F2                                       0x000A09E1U
+#define PI_CKE_MUX_0                                        0x000309E6U
+#define PI_CKE_MUX_1                                        0x080309E6U
+#define PI_SEQ_DEC_SW_CS                                    0x00020A4EU
+#define PI_SW_SEQ_START                                     0x10010A4EU
+#define PI_SW_SEQ_0                                         0x001B0BF1U
+#define PI_SW_SEQ_1                                         0x001B0BF2U
+#define PI_DFS_ENTRY_SEQ_0                                  0x001D0BFBU
+#define PI_DFS_INITIALIZATION_SEQ_1                         0x001D0C24U
+#define PI_DFS_INITIALIZATION_SEQ_9                         0x001D0C2CU
+#define PI_DFS_INITIALIZATION_SEQ_10                        0x001D0C2DU
+#define PI_SEQ_WAIT_16_F2                                   0x00180C77U
+#define PI_SEQ_WAIT_17_F2                                   0x00180C7AU
+#define PI_SEQ_WAIT_18_F2                                   0x00180C7DU
+#define PI_SEQ_WAIT_19_F2                                   0x00180C80U
+#define PI_SEQ_WAIT_20_F2                                   0x00180C83U
+#define PI_SEQ_WAIT_21_F2                                   0x00180C86U
+#define PI_SEQ_WAIT_22_F2                                   0x00180C89U
+#define PI_SEQ_WAIT_23_F2                                   0x00180C8CU
+#define PI_SEQ_WAIT_24_F2                                   0x00180C8FU
+#define PI_SEQ_WAIT_25_F2                                   0x00180C92U
+#define PI_SEQ_WAIT_26_F2                                   0x00180C95U
+#define PI_SEQ_WAIT_30_F2                                   0x00180CA1U
+#define PI_DARRAY3_0_CS0_F0                                 0x00080D0BU
+#define PI_DARRAY3_1_CS0_F0                                 0x08080D0BU
+#define PI_DARRAY3_0_CS0_F1                                 0x00080D15U
+#define PI_DARRAY3_1_CS0_F1                                 0x08080D15U
+#define PI_DARRAY3_0_CS0_F2                                 0x00080D1FU
+#define PI_DARRAY3_1_CS0_F2                                 0x08080D1FU
+#define PI_DARRAY3_4_CS0_F2                                 0x00080D20U
+#define PI_DARRAY3_20_CS0_F2                                0x00080D24U
+#define PI_DARRAY3_0_CS1_F0                                 0x00080D29U
+#define PI_DARRAY3_1_CS1_F0                                 0x08080D29U
+#define PI_DARRAY3_0_CS1_F1                                 0x00080D33U
+#define PI_DARRAY3_1_CS1_F1                                 0x08080D33U
+#define PI_DARRAY3_0_CS1_F2                                 0x00080D3DU
+#define PI_DARRAY3_1_CS1_F2                                 0x08080D3DU
+#define PI_DARRAY3_4_CS1_F2                                 0x00080D3EU
+#define PI_DARRAY3_20_CS1_F2                                0x00080D42U
+#define PI_DLL_RST                                          0x00010941U
+#define PI_PWRUP_SREFRESH_EXIT                              0x1801093DU
+#define PI_PWRUP_SREFRESH_EXIT                              0x1801093DU
+#define PI_RDLVL_TRAIN_SEQ_1                                0x001B0C42U
+#define PI_RDLVL_TRAIN_SEQ_2                                0x001B0C43U
+#define PI_RDLVL_TRAIN_SEQ_3                                0x001B0C44U
+#define PI_RDLVL_TRAIN_SEQ_4                                0x001B0C45U
+#define PI_RDLVL_TRAIN_SEQ_5                                0x001B0C46U
+#define PI_WDQLVL_VREF_EN                                   0x0804089EU
+#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2                         0x001B0868U
+#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3                         0x001B0869U
+#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4                         0x001B086AU
+#define PHY_PER_CS_TRAINING_INDEX                           0x18011006U
+#define PHY_DATA_DC_DQS_CLK_ADJUST                          0x0008108CU
+#define PHY_DATA_DC_WDQLVL_ENABLE                           0x08021075U
+#define PI_WDQLVL_PERIODIC                                  0x000108A0U
+#define PHY_MEAS_DLY_STEP_ENABLE                            0x08061076U
+#define PI_RDLVL_PERIODIC                                   0x0801082EU
+#define PI_LONG_COUNT_MASK                                  0x1005090FU
+#define PI_WDQLVL_INTERVAL                                  0x001008A4U
+#define PI_RDLVL_INTERVAL                                   0x08100835U
+#define DDR_REGDEF_ADR(regdef)  ((regdef)        & 0xFFFFU)
+#define DDR_REGDEF_LEN(regdef)  (((regdef) >> 16)  & 0xFFU)
+#define DDR_REGDEF_LSB(regdef)  (((regdef) >> 24)  & 0xFFU)
+
+#endif /* DDR_REGDEF */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c

@@ -0,0 +1,183 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECC initialize function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ecc_enable_v4h.c
+ * - Version      : 0.06
+ * @brief         Enable setting process of ECC for DRAM.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 09.08.2022 0.01     First Release
+ *         : 16.11.2022 0.02     Change ecc_enable to ecc_sdram_enable
+ *         : 04.04.2023 0.03     Removed stdio.h and string.h.
+ *         : 20.09.2023 0.04     Update the ecc_sdram_enable function according to HWSAN rev0.82.
+ *         : 13.06.2024 0.05     Fix register setting for EDC_CFG, and revise
+ *         :                     the ecm_lock()/ecm_unlock() process.
+ *         : 27.01.2025 0.06     Remove unused functions.
+ *****************************************************************************/
+
+#include <stdint.h>
+
+#if (ECC_ENABLE == 1)
+#include "ecc_enable_v4h.h"
+#include "ecm_enable_v4h.h"
+#include "mem_io.h"
+#include "v4h/lpddr5/boot_init_dram_regdef.h"
+
+/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
+void ecc_sdram_enable(void)
+{
+    NOTICE("ECC for DRAM is enable.\n");
+
+    uint32_t ecm_tmp;
+
+    /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
+    After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
+    mem_write32(DB0SYSCNT0, 0x00001234U);
+    mem_write32(DB1SYSCNT0, 0x00001234U);
+    mem_write32(DB0SYSCNT0A, 0x00001234U);
+    mem_write32(DB1SYSCNT0A, 0x00001234U);
+
+    /* (A) Setting ECM */
+    /* Unlock the write protect of ECM registers */
+    ecm_unlock();
+
+    /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
+                to inform the external device of the error via the ERROROUT# pin. */
+    /* Set bit 3, 1 of ECMERRTGTR0 to 0 and bit 3, 1 of ECMERRCTLR0 to 1.  */
+    ecm_tmp = mem_read32(ECMERRTGTR0);
+    ecm_tmp &= ~(0xAU);
+    ecm_write(ECMERRTGTR0, ecm_tmp);
+
+    ecm_tmp = mem_read32(ECMERRCTLR0);
+    ecm_tmp |= (0xAU);
+    ecm_write(ECMERRCTLR0, ecm_tmp);
+
+    /* (B) Setting ECC protection area */
+    /* Set the bottom row address of the ECC protection area */
+    mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
+    mem_write32(DB1FSDRAMECCAREA00, ECC_PROT_SIZE10);
+
+    /* (C) Initialization for DRAM */
+    mem_write32(DBSC_DB0ACEN, 0x00000000U);
+    mem_write32(DBSC_DB1ACEN, 0x00000000U);
+
+    /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
+    /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
+    mem_write32(DB0FSCONF00A, 0x0U);
+
+    /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
+    mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
+
+    /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
+    mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
+
+    /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
+    mem_write32(DB0FSCTRL01A, 0x01U);
+
+    /*** Initialization for DRAM connected to DBS1 Initialize RANK0 in according with the following procedure.***/
+    /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB1FSCONF00A[1:0]. */
+    mem_write32(DB1FSCONF00A, 0x0U);
+
+    /* [Step2] Set the start row address of the initialization area in DB1FSCONF01A[31:0]. */
+    mem_write32(DB1FSCONF01A, START_ECC_INIT_AREA10);
+
+    /* [Step3] Set the end row address of the initialization area in DB1FSCONF02A[31:0]. */
+    mem_write32(DB1FSCONF02A, END_ECC_INIT_AREA10);
+
+    /* [Step4] Set 0x1 to DB1FSCTRL01A[0] to start initialization. */
+    mem_write32(DB1FSCTRL01A, 0x01U);
+
+    /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
+    /* [Step5] When DB1FSSTAT01A[0] is set to 0x1, DBS1/RANK0 initialization is complete.*/
+    NOTICE("DRAM rank 0 of DBSC0/1 is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB0FSSTAT01A);
+        ecm_tmp &= mem_read32(DB1FSSTAT01A);
+    } while ((ecm_tmp & 0x01U) != 0x01U);
+
+    /* (D) Setting ECC protection enable */
+    /* Enable ECC protection for dbs0/rank0 by setting 0x1 in DB0FSCONFAXI0[8]. */
+    ecm_tmp = mem_read32(DB0FSCONFAXI0);
+    ecm_tmp |= (0x1U << 8U);
+    mem_write32(DB0FSCONFAXI0, ecm_tmp);
+
+    /* Enable ECC protection for dbs1/rank0 by setting 0x1 in DB1FSCONFAXI0[8]. */
+    ecm_tmp = mem_read32(DB1FSCONFAXI0);
+    ecm_tmp |= (0x1U << 8U);
+    mem_write32(DB1FSCONFAXI0, ecm_tmp);
+
+    /* (E) System RAM initialization */
+    NOTICE("System RAM of DBSC0 is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB0FSSTAT00A);
+    } while (ecm_tmp != 0x1U);
+
+    NOTICE("System RAM of DBSC1 is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB1FSSTAT00A);
+    } while (ecm_tmp != 0x1U);
+
+    /* (F) Setting for ECC error interrupt */
+    /* (1) Set the ECC error interrupt for read data. */
+    mem_write32(DB0FSINTENB02A, 0xFF00U);
+    mem_write32(DB1FSINTENB02A, 0xFF00U);
+
+    /* (2) Set the ECC error interrupt during RMW operation for System RAM. */
+    ecm_tmp = mem_read32(DB0FSINTENB02A);
+    ecm_tmp |= 0xFF000000U;
+    mem_write32(DB0FSINTENB02A, ecm_tmp);
+    ecm_tmp = mem_read32(DB1FSINTENB02A);
+    ecm_tmp |= 0xFF000000U;
+    mem_write32(DB1FSINTENB02A, ecm_tmp);
+
+    /* (3) Set the ECC error interrupt during RMW operation for DRAM. */
+    mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
+    mem_write32(DB1FSINTENB04A, 0xFFFFFFFFU);
+
+    /* Lock the ECM registers */
+    ecm_lock();
+
+    /* Enable the write protect of ECM registers */
+    mem_write32(DBSC_DB0ACEN, 0x00000001U);
+    mem_write32(DBSC_DB1ACEN, 0x00000001U);
+
+    /* Enable the access protect for DBSC registers */
+    mem_write32(DB0SYSCNT0, 0x00000000U);
+    mem_write32(DB1SYSCNT0, 0x00000000U);
+    mem_write32(DB0SYSCNT0A, 0x00000000U);
+    mem_write32(DB1SYSCNT0A, 0x00000000U);
+}
+#endif /* ECC_ENABLE == 1 */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h

@@ -0,0 +1,111 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECC driver header
+ ******************************************************************************/
+
+#ifndef ECC_PROTECT
+#define ECC_PROTECT
+/* DBSC registers */
+#if defined(__RH850G3K__)
+#include "remap_register.h"
+#include "mem_io.h"
+#include "log.h"
+#define DBSC_D_BASE			  (BASE_DBSC_ADDR + 0x14000U)	/* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE			  (BASE_DBSC_ADDR)	            /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
+#define ECM_BASE              (BASE_ECC_ADDR)
+#else
+#if (ECC_ENABLE == 1)
+#include "mem_io.h"
+#include "log.h"
+#define DBSC_D_BASE			  (0xE67A4000U)	                /* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE			  (0xE6790000U)	                /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
+#endif /* ECC_ENABLE == 1 */
+#define ECM_BASE              (0xE6250000U)
+#endif/* defined(__RH850G3K__) */
+
+#if (ECC_ENABLE == 1)
+void ecc_sdram_enable(void);
+
+#define DB0SYSCNT0            (DBSC_D_BASE + 0x0100U)
+#define DB0SYSCNT0A           (DBSC_A_BASE + 0x0100U)
+#define DB1SYSCNT0            (DB0SYSCNT0 +  0x4000U)
+#define DB1SYSCNT0A           (DB0SYSCNT0A + 0x8000U)
+
+#define	DBSC_DB0ACEN		  (DBSC_A_BASE + 0x0200U)
+#define	DBSC_DB1ACEN		  (DBSC_DB0ACEN + 0x8000U)
+#endif /* ECC_ENABLE == 1 */
+
+#define ECMWACNTR             (ECM_BASE + 0x0A04U)
+#define ECMWPCNTR             (ECM_BASE + 0x0A00U)
+#if (ECC_ENABLE == 1)
+#define ECMERRTGTR0           (ECM_BASE + 0x0200U)
+#define ECMERRCTLR0           (ECM_BASE + 0x0000U)
+#define DB0FSCONF00A          (DBSC_A_BASE    + 0x7640U)
+#define DB1FSCONF00A          (DB0FSCONF00A   + 0x8000U)
+#define DB0FSCONF01A          (DBSC_A_BASE    + 0x7644U)
+#define DB1FSCONF01A          (DB0FSCONF01A   + 0x8000U)
+#define DB0FSCONF02A          (DBSC_A_BASE    + 0x7648U)
+#define DB1FSCONF02A          (DB0FSCONF02A   + 0x8000U)
+#define DB0FSCTRL01A          (DBSC_A_BASE    + 0x7604U)
+#define DB1FSCTRL01A          (DB0FSCTRL01A   + 0x8000U)
+#define DB0FSSTAT01A          (DBSC_A_BASE    + 0x7684U)
+#define DB1FSSTAT01A          (DB0FSSTAT01A   + 0x8000U)
+#define DB0FSSTAT00A          (DBSC_A_BASE    + 0x7680U)
+#define DB1FSSTAT00A          (DB0FSSTAT00A   + 0x8000U)
+#define DB0FSINTENB02A        (DBSC_A_BASE    + 0x7088U)
+#define DB1FSINTENB02A        (DB0FSINTENB02A + 0x8000U)
+#define DB0FSINTENB04A        (DBSC_A_BASE    + 0x7090U)
+#define DB1FSINTENB04A        (DB0FSINTENB04A + 0x8000U)
+
+#define DB0FSDRAMECCAREA00    (DBSC_A_BASE + 0x7450U)
+#define DB0FSDRAMECCAREA01    (DBSC_A_BASE + 0x7454U)
+#define DB1FSDRAMECCAREA00    (DB0FSDRAMECCAREA00 + 0x8000U)
+#define DB1FSDRAMECCAREA01    (DB0FSDRAMECCAREA01 + 0x8000U)
+
+#define DB0FSCONFAXI0        (DBSC_A_BASE   + 0x7400U)
+#define DB1FSCONFAXI0        (DB0FSCONFAXI0 + 0x8000U)
+
+/********************* Set by the user *********************/
+/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
+#define ECC_PROT_SIZE00        (0xCCCCU)
+#define ECC_PROT_SIZE01        (0xCCCCU)
+#define ECC_PROT_SIZE10        (0xCCCCU)
+#define ECC_PROT_SIZE11        (0xCCCCU)
+
+/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
+#define START_ECC_INIT_AREA00   (0x00000000U)
+#define START_ECC_INIT_AREA10   (0x00000000U)
+#define END_ECC_INIT_AREA00     (0x0000CCCBU)
+#define END_ECC_INIT_AREA10     (0x0000CCCBU)
+
+/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
+#define START_ECC_INIT_AREA01   (0x00000000U)
+#define START_ECC_INIT_AREA11   (0x00000000U)
+#define END_ECC_INIT_AREA01     (0x0000CCCBU)
+#define END_ECC_INIT_AREA11     (0x0000CCCBU)
+/***********  Other settings cannot be changed ***************/
+#endif /* ECC_ENABLE == 1 */
+
+#endif/* ECC_PROTECT */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c

@@ -0,0 +1,260 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECM initialize function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ecm_enable_v4h.c
+ * - Version      : 0.01
+ * @brief         ECM setting.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 29.01.2025 0.01     First Release
+ *****************************************************************************/
+
+#include <stdint.h>
+#include "ecm_enable_v4h.h"
+
+#if (ECM_ERROR_ENABLE == 1)
+#include "log.h"
+#endif /* ECM_ERROR_ENABLE == 1 */
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+#include "ecc_enable_v4h.h"
+#include "mem_io.h"
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+#define ECM_ERR_REG_MAX     (40U)
+
+typedef struct{
+    uint32_t phys_addr; /* Physical address of ECM registers. */
+    uint32_t value;     /* Setting value of ECM registers. */
+} ECM_ERROR_TABLE;
+#endif /* ECM_ERROR_ENABLE == 1 */
+
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+void ecm_unlock(void)
+{
+    mem_write32(ECMWPCNTR, 0xACCE0001U);
+}
+
+void ecm_write(uint32_t adr, uint32_t val)
+{
+    mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
+    mem_write32(adr, val);
+}
+
+void ecm_lock(void)
+{
+    mem_write32(ECMWPCNTR, 0xACCE0000U);
+}
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+void ecm_error_enable(void)
+{
+    uint32_t reg;
+    uint32_t loop;
+
+    const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250000U, 0xFFFFF00FU}, /* ECMERRCTLR0 */
+    [1]   =     {0xE6250004U, 0xFFF8C000U}, /* ECMERRCTLR1 */
+    [2]   =     {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
+    [3]   =     {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
+    [4]   =     {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
+    [5]   =     {0xE6250014U, 0xFFFFFFFFU}, /* ECMERRCTLR5 */
+    [6]   =     {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
+    [7]   =     {0xE625001CU, 0x6F980FFFU}, /* ECMERRCTLR7 */
+    [8]   =     {0xE6250020U, 0xFFF00000U}, /* ECMERRCTLR8 */
+    [9]   =     {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
+    [10]  =     {0xE6250028U, 0x557D554FU}, /* ECMERRCTLR10 */
+    [11]  =     {0xE625002CU, 0xFFFC1555U}, /* ECMERRCTLR11 */
+    [12]  =     {0xE6250030U, 0x5557FFFFU}, /* ECMERRCTLR12 */
+    [13]  =     {0xE6250034U, 0x00000055U}, /* ECMERRCTLR13 */
+        /* Skip ECMERRCTLR14 setting */
+        /* Skip ECMERRCTLR15 setting */
+    [14]  =     {0xE6250040U, 0x3FFFFFFFU}, /* ECMERRCTLR16 */
+    [15]  =     {0xE6250044U, 0x2FFF8CE0U}, /* ECMERRCTLR17 */
+    [16]  =     {0xE6250048U, 0x0EC03FFFU}, /* ECMERRCTLR18 */
+    [17]  =     {0xE625004CU, 0xFFFFFFF9U}, /* ECMERRCTLR19 */
+    [18]  =     {0xE6250050U, 0xFE66667EU}, /* ECMERRCTLR20 */
+    [19]  =     {0xE6250054U, 0xBFE3BE0FU}, /* ECMERRCTLR21 */
+    [20]  =     {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
+    [21]  =     {0xE625005CU, 0x7EF3C008U}, /* ECMERRCTLR23 */
+    [22]  =     {0xE6250060U, 0x7FFE8ADBU}, /* ECMERRCTLR24 */
+    [23]  =     {0xE6250064U, 0xCF807FFFU}, /* ECMERRCTLR25 */
+    [24]  =     {0xE6250068U, 0x7EF3C008U}, /* ECMERRCTLR26 */
+    [25]  =     {0xE625006CU, 0x7FFE8ADBU}, /* ECMERRCTLR27 */
+    [26]  =     {0xE6250070U, 0xCF807FFFU}, /* ECMERRCTLR28 */
+    [27]  =     {0xE6250074U, 0x0073C008U}, /* ECMERRCTLR29 */
+    [28]  =     {0xE6250078U, 0x7FE68A9BU}, /* ECMERRCTLR30 */
+    [29]  =     {0xE625007CU, 0x8C007E00U}, /* ECMERRCTLR31 */
+    [30]  =     {0xE6250080U, 0xCFFFFFFFU}, /* ECMERRCTLR32 */
+    [31]  =     {0xE6250084U, 0x0FFFFFFFU}, /* ECMERRCTLR33 */
+    [32]  =     {0xE6250088U, 0x000003FFU}, /* ECMERRCTLR34 */
+    [33]  =     {0xE625008CU, 0xFFFFFFC0U}, /* ECMERRCTLR35 */
+    [34]  =     {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
+        /* Skip ECMERRCTLR37 setting */
+    [35]  =     {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
+    [36]  =     {0xE625009CU, 0x1FFF0000U}, /* ECMERRCTLR39 */
+    [37]  =     {0xE62500A0U, 0x1FFC7FFFU}, /* ECMERRCTLR40 */
+    [38]  =     {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
+    [39]  =     {0xE62500A8U, 0x3FBFFDFFU}, /* ECMERRCTLR42 */
+    };
+
+#if (ECMERRTGTR_INTC == 1)
+    const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250200U, 0xFFFFF00FU}, /* ECMERRTGTR0 */
+    [1]   =     {0xE6250204U, 0xFFF8C000U}, /* ECMERRTGTR1 */
+    [2]   =     {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
+    [3]   =     {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
+    [4]   =     {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
+    [5]   =     {0xE6250214U, 0xFFFFFFFFU}, /* ECMERRTGTR5 */
+    [6]   =     {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
+    [7]   =     {0xE625021CU, 0x6F980FFFU}, /* ECMERRTGTR7 */
+    [8]   =     {0xE6250220U, 0xFFF00000U}, /* ECMERRTGTR8 */
+    [9]   =     {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
+    [10]  =     {0xE6250228U, 0x557D554FU}, /* ECMERRTGTR10 */
+    [11]  =     {0xE625022CU, 0xFFFC1555U}, /* ECMERRTGTR11 */
+    [12]  =     {0xE6250230U, 0x5557FFFFU}, /* ECMERRTGTR12 */
+    [13]  =     {0xE6250234U, 0x00000055U}, /* ECMERRTGTR13 */
+        /* Skip ECMERRTGTR14 setting */
+        /* Skip ECMERRTGTR15 setting */
+    [14]  =     {0xE6250240U, 0x3FFFFFFFU}, /* ECMERRTGTR16 */
+    [15]  =     {0xE6250244U, 0x2FFF8CE0U}, /* ECMERRTGTR17 */
+    [16]  =     {0xE6250248U, 0x0EC03FFFU}, /* ECMERRTGTR18 */
+    [17]  =     {0xE625024CU, 0xFFFFFFF9U}, /* ECMERRTGTR19 */
+    [18]  =     {0xE6250250U, 0xFE66667EU}, /* ECMERRTGTR20 */
+    [19]  =     {0xE6250254U, 0xBFE3BE0FU}, /* ECMERRTGTR21 */
+    [20]  =     {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
+    [21]  =     {0xE625025CU, 0x7EF3C008U}, /* ECMERRTGTR23 */
+    [22]  =     {0xE6250260U, 0x7FFE8ADBU}, /* ECMERRTGTR24 */
+    [23]  =     {0xE6250264U, 0xCF807FFFU}, /* ECMERRTGTR25 */
+    [24]  =     {0xE6250268U, 0x7EF3C008U}, /* ECMERRTGTR26 */
+    [25]  =     {0xE625026CU, 0x7FFE8ADBU}, /* ECMERRTGTR27 */
+    [26]  =     {0xE6250270U, 0xCF807FFFU}, /* ECMERRTGTR28 */
+    [27]  =     {0xE6250274U, 0x0073C008U}, /* ECMERRTGTR29 */
+    [28]  =     {0xE6250278U, 0x7FE68A9BU}, /* ECMERRTGTR30 */
+    [29]  =     {0xE625027CU, 0x8C007E00U}, /* ECMERRTGTR31 */
+    [30]  =     {0xE6250280U, 0xCFFFFFFFU}, /* ECMERRTGTR32 */
+    [31]  =     {0xE6250284U, 0x0FFFFFFFU}, /* ECMERRTGTR33 */
+    [32]  =     {0xE6250288U, 0x000003FFU}, /* ECMERRTGTR34 */
+    [33]  =     {0xE625028CU, 0xFFFFFFC0U}, /* ECMERRTGTR35 */
+    [34]  =     {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
+        /* Skip ECMERRTGTR37 setting */
+    [35]  =     {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
+    [36]  =     {0xE625029CU, 0x1FFF0000U}, /* ECMERRTGTR39 */
+    [37]  =     {0xE62502A0U, 0x1FFC7FFFU}, /* ECMERRTGTR40 */
+    [38]  =     {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
+    [39]  =     {0xE62502A8U, 0x3FBFFDFFU}, /* ECMERRTGTR42 */
+    };
+#elif (ECMERRTGTR_INTC == 0)
+    const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
+    [1]   =     {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
+    [2]   =     {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
+    [3]   =     {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
+    [4]   =     {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
+    [5]   =     {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
+    [6]   =     {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
+    [7]   =     {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
+    [8]   =     {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
+    [9]   =     {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
+    [10]  =     {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
+    [11]  =     {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
+    [12]  =     {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
+    [13]  =     {0xE6250234U, 0x00000000U}, /* ECMERRTGTR13 */
+        /* Skip ECMERRTGTR14 setting */
+        /* Skip ECMERRTGTR15 setting */
+    [14]  =     {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
+    [15]  =     {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
+    [16]  =     {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
+    [17]  =     {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
+    [18]  =     {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
+    [19]  =     {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
+    [20]  =     {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
+    [21]  =     {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
+    [22]  =     {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
+    [23]  =     {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
+    [24]  =     {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
+    [25]  =     {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
+    [26]  =     {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
+    [27]  =     {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
+    [28]  =     {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
+    [29]  =     {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
+    [30]  =     {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
+    [31]  =     {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
+    [32]  =     {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
+    [33]  =     {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
+    [34]  =     {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
+        /* Skip ECMERRTGTR37 setting */
+    [35]  =     {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
+    [36]  =     {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
+    [37]  =     {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
+    [38]  =     {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
+    [39]  =     {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
+    };
+#endif /* ECMERRTGTR_INTC == 1 */
+
+    /* Unlock the write protect of ECM registers */
+    ecm_unlock();
+
+    NOTICE("ECMERRCTLR register setting.\n");
+    for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
+    {
+        /* Set ECMERRCTLR registers. */
+        reg  = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
+        reg |= ecmerrctlr_tbl[loop].value;
+        ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
+
+        INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
+            loop,
+            ecmerrctlr_tbl[loop].phys_addr,
+            mem_read32(ecmerrctlr_tbl[loop].phys_addr),
+            ecmerrctlr_tbl[loop].value);
+    }
+
+    NOTICE("ECMERRTGTR register setting.\n");
+    for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
+    {
+        /* Set ECMERRTGTR registers. */
+        reg  = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
+        reg |= ecmerrtgtr_tbl[loop].value;
+        ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
+
+        INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
+            loop,
+            ecmerrtgtr_tbl[loop].phys_addr,
+            mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
+            ecmerrtgtr_tbl[loop].value);
+    }
+
+    /* Lock the ECM registers */
+    ecm_lock();
+}
+/* End of function ecm_error_enable(void) */
+#endif /* ECM_ERROR_ENABLE == 1 */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h

@@ -0,0 +1,42 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECM driver header
+ ******************************************************************************/
+
+#ifndef ECM_ENABLE
+#define ECM_ENABLE
+
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+void ecm_unlock(void);
+void ecm_write(uint32_t adr, uint32_t val);
+void ecm_lock(void);
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+void ecm_error_enable(void);
+#endif /* ECM_ERROR_ENABLE == 1 */
+
+#endif/* ECM_ENABLE */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c

@@ -0,0 +1,240 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+#include <stdint.h>
+#if defined(__RH850G3K__)
+#include "mem_io.h"
+#include "log.h"
+#else
+#include "mem_io.h"
+#include "log.h"
+#endif
+#include "boot_init_dram_regdef.h"
+#include "boot_init_dram_config.h"
+
+/*******************************************************************************
+ *    PLEASE SET board number or board judge function
+ ******************************************************************************/
+#define BOARD_JUDGE_AUTO
+#ifdef BOARD_JUDGE_AUTO
+static uint32_t r_board_judge(void);
+uint32_t r_boardcnf_get_brd_type(void)
+{
+    return r_board_judge();
+}
+#else /* BOARD_JUDGE_AUTO */
+uint32_t r_boardcnf_get_brd_type(void)
+{
+    return (0);
+}
+#endif /* BOARD_JUDGE_AUTO */
+
+/*******************************************************************************
+ *    EXTAL CLOCK DEFINITION
+ *    PLEASE DEFINE HOW TO JUDGE BORAD CLK
+ ******************************************************************************/
+/*
+ * RENESAS GRAY HAWK BOARD EXAMPLE
+ * judge by md14/md13
+ *
+ * 16.66MHz CLK,DIV= 50,3  (md14,md13==0,0)
+ * 20.00MHz CLK,DIV= 60,3  (md14,md13==0,1)
+ * 33.33MHz CLK,DIV=100,3  (md14,md13==1,1)
+*/
+void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
+{
+    uint32_t md;
+
+    md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
+    switch (md)
+    {
+        case 0x0U : *clk = 50U; *clk_div = 3U; break;               /*  50 / 3 = 16.66MHz */
+        case 0x1U : *clk = 60U; *clk_div = 3U; break;               /*  60 / 3 = 20.00MHz */
+        case 0x2U   : NOTICE("MD14/MD13 is invalid!!\n"); panic;    /*  Not supported     */
+        case 0x3U : *clk =100U; *clk_div = 3U; break;               /* 100 / 3 = 33.33MHz */
+        default   : /* Nothing */              break;
+    }
+    (void)brd;
+}
+
+/*******************************************************************************
+ *    DDR MBPS TARGET
+ *    PLEASE DEFINE HOW TO JUDGE DDR BPS
+ ******************************************************************************/
+/*
+  DDRxxxx (judge by md19,17) : Mbps
+  SSCG enable / disable for PLL1 (judge by md18/md37/md36)
+*/
+void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en)
+{
+    uint32_t md;
+    uint32_t product;
+
+    md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
+    md = (md | (md >> 1)) & 0x03U;
+    *sscg = ((mmio_read_32(RST_MODEMR0) >> 16) & 0x04U) | ((mmio_read_32(RST_MODEMR1) >> 4) & 0x03U);
+    product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
+
+    if (product == 0x01U)
+    {
+        /* V4M-5 */
+        switch (md)
+        {
+            case 0x0U : *mbps =   5000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5000Mbps */
+            case 0x1U : *mbps =   5000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5000Mbps */
+            case 0x2U : *mbps =   5000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5000Mbps */
+            case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            default   : /* Nothing */                                       break;
+        }
+    }
+    else if (product == 0x02U)
+    {
+        /* V4M-3 */
+        switch (md)
+        {
+            case 0x0U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x1U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x2U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            default   : /* Nothing */                                       break;
+        }
+    }
+    else if (product == 0x04U)
+    {
+        /* V4M-2 */
+        switch (md)
+        {
+            case 0x0U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x1U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x2U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+            default   : /* Nothing */                                       break;
+        }
+    }
+    else
+    {
+        /* V4M-7 */
+        switch (*sscg)
+        {
+            case 0x0U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x1U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =  19000U; *mbps_div = 3U; *med_freq_en = 1U; break;    /* 6333Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x2U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x3U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =  19000U; *mbps_div = 3U; *med_freq_en = 1U; break;    /* 6333Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x4U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x5U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x6U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            case 0x7U :
+                switch (md)
+                {
+                    case 0x0U : *mbps =   6400U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6400Mbps */
+                    case 0x1U : *mbps =   6000U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 6000Mbps */
+                    case 0x2U : *mbps =   5500U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 5500Mbps */
+                    case 0x3U : *mbps =   4800U; *mbps_div = 1U; *med_freq_en = 1U; break;    /* 4800Mbps */
+                    default   : /* Nothing */                                       break;
+                }
+                break;
+            default :
+                /* Nothing */
+                break;
+        }/* Setting of SSCG */
+    } /* (product == 0x01U) */
+
+    (void)brd;
+}
+
+#ifdef BOARD_JUDGE_AUTO
+/*******************************************************************************
+ *    SAMPLE board detect function
+ ******************************************************************************/
+static uint32_t r_board_judge(void)
+{
+    uint32_t brd;
+
+    brd = 0U;    /* gray hawk (64Gbit 2rank) */
+
+    return brd;
+}
+#endif

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h

@@ -0,0 +1,156 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+#ifndef BOOT_INIT_DRAM_CONFIG_H_
+#define BOOT_INIT_DRAM_CONFIG_H_
+
+/*******************************************************************************
+ * DRAM Param setting
+ ******************************************************************************/
+#define JS2_DERATE                    0U
+#define DBSC_REFINT                   1920U     /* Average periodic refresh interval/Average Refresh Interval [ns] */
+#ifndef DBSC_REFINTS
+#define DBSC_REFINTS                  0U        /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
+#endif
+#define PERIODIC_TRAINING_INTERVAL    20000U    /* Periodic-WriteDQ/ReadDQ Training Interval [us] */
+
+/*******************************************************************************
+ *    NUMBER OF BOARD CONFIGURATION
+ *    PLEASE DEFINE
+ ******************************************************************************/
+#define BOARDNUM    2U    /* Add User platform BOARD */
+
+/*******************************************************************************
+ *    Prototypes
+ ******************************************************************************/
+uint32_t r_boardcnf_get_brd_type(void);
+void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
+void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en);
+
+/*******************************************************************************
+ *    BOARD CONFIGURATION
+ *    PLEASE DEFINE boardcnfs[]
+ ******************************************************************************/
+typedef struct
+{
+    /*
+     0x00...0000B:  4Gb dual channel die /  2Gb single channel die
+     0x01...0001B:  6Gb dual channel die /  3Gb single channel die
+     0x02...0010B:  8Gb dual channel die /  4Gb single channel die
+     0x03...0011B: 12Gb dual channel die /  6Gb single channel die
+     0x04...0100B: 16Gb dual channel die /  8Gb single channel die
+     0x05...0101B: 24Gb dual channel die / 12Gb single channel die
+     0x06...0110B: 32Gb dual channel die / 16Gb single channel die
+     0x07...0111B: 24Gb single channel die
+     0x08...1000B: 32Gb single channel die
+     0xFF...NO_MEMORY
+    */
+    uint8_t bdcfg_ddr_density[CS_CNT];
+    /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+    uint32_t bdcfg_ca_swap;
+    /* SoC dqsX([1][0]) -> MEM dqsY: */
+    uint8_t bdcfg_dqs_swap;
+    /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
+    uint32_t bdcfg_dq_swap[SLICE_CNT];
+    /* SoC dm -> MEM dqY/dm:  (8 means DM) */
+    uint8_t bdcfg_dm_swap[SLICE_CNT];
+    /* SoC ckeX([1][0]) -> MEM csY */
+    uint8_t bdcfg_cs_swap;
+} st_boardcnf_ch_t;
+
+typedef struct
+{
+    /* ch in use */
+    uint8_t bdcfg_phyvalid;
+    /* Read vref (SoC) training range         : [23:16]step  / [15:8]stop  / [7:0]start,  0x00000000 = default val */
+    uint32_t bdcfg_vref_r;
+    /* Write vref (MR14, MR15) training range : [15:8]stop   / [7:0]start,  0x0000 = default val */
+    uint16_t bdcfg_vref_w;
+    /* CA vref (MR12) training range          : [15:8]stop   / [7:0]start,  0x0000 = default val */
+    uint16_t bdcfg_vref_ca;
+    /* RFM required check                     : 0x01 = check enable, 0x00 = check disable */
+    uint8_t bdcfg_rfm_chk;
+
+    st_boardcnf_ch_t ch[2];
+} st_boardcnf_t;
+
+static const st_boardcnf_t boardcnfs[BOARDNUM] = {
+/*
+ * boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank)
+ */
+{
+    0x03U,          /* bdcfg_phyvalid */
+    0x00000000U,    /* bdcfg_vref_r */
+    0x0000U,        /* bdcfg_vref_w */
+    0x0000U,        /* bdcfg_vref_ca */
+    0x01U,          /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
+/* bdcfg_ca_swap */            0x06235104U,
+/* bdcfg_dqs_swap */           0x01U,
+/* bdcfg_dq_swap[] */        { 0x43061257U, 0x30721685U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x04U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
+/* bdcfg_ca_swap */            0x04012653U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x58147026U, 0x70132685U },
+/* bdcfg_dm_swap[] */        { 0x03U, 0x04U },
+/* bdcfg_cs_swap */            0x10U
+        }
+    }
+},
+/*
+ * boardcnf[1] RENESAS V4M (2ch)
+ */
+{
+    0x03U,          /* bdcfg_phyvalid */
+    0x00000000U,    /* bdcfg_vref_r */
+    0x0000U,        /* bdcfg_vref_w */
+    0x0000U,        /* bdcfg_vref_ca */
+    0x01U,          /* bdcfg_rfm_chk */
+    {
+/* ch[0] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        },
+/* ch[1] */    {
+/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
+/* bdcfg_ca_swap */            0x06543210U,
+/* bdcfg_dqs_swap */           0x10U,
+/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
+/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
+/* bdcfg_cs_swap */            0x10U
+        }
+    }
+}
+};
+
+#endif /* BOOT_INIT_DRAM_CONFIG_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h

@@ -0,0 +1,165 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+#ifndef BOOT_INIT_DRAM_REGDEF_H_
+#define BOOT_INIT_DRAM_REGDEF_H_
+
+#if defined(__RH850G3K__)
+#include "remap_register.h"
+#endif
+
+#define RCAR_DDR_VERSION             "rev.1.00"
+#define DRAM_CH_CNT                  0x02U
+#define SLICE_CNT                    0x02U
+#define CS_CNT                       0x02U
+
+/* for pll setting */
+#define CLK_DIV(a, diva, b, divb)    (((a) * (divb)) / ((b) * (diva)))
+
+/* for ddr density setting */
+#define DBMEMCONF_REG(d3, row, BG, bank, col, dw)    (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
+#define DBMEMCONF_REGD(density)      (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U))    /* 16bit */
+
+/* system registers : CPG */
+#define CPG_FRQCRD_KICK_BIT          (1U << 31)
+#define CPG_PLL3CR0_KICK_BIT         (1U << 31)
+#define CPG_PLLECR_PLL3ST_BIT        (1U << 11)
+
+#if defined(__RH850G3K__)
+#define CPG_BASE                     (BASE_CPG_ADDR)
+#else
+#define CPG_BASE                     (0xE6150000U)
+#endif
+#define CPG_CPGWPR                   (CPG_BASE + 0x0000U)
+#define CPG_FRQCRD0                  (CPG_BASE + 0x080CU)
+#define CPG_PLLECR                   (CPG_BASE + 0x0820U)
+#define CPG_PLL3CR0                  (CPG_BASE + 0x083CU)
+#define CPG_PLL3CR1                  (CPG_BASE + 0x08C0U)
+#define CPG_FSRCHKCLRR4              (CPG_BASE + 0x0590U)
+#define CPG_FSRCHKSETR4              (CPG_BASE + 0x0510U)
+#define CPG_FSRCHKRA4                (CPG_BASE + 0x0410U)
+#define CPG_SRCR4                    (CPG_BASE + 0x2C10U)
+#define CPG_SRSTCLR4                 (CPG_BASE + 0x2C90U)
+
+#if defined(__RH850G3K__)
+#define RST_BASE                     (BASE_RESET_ADDR)
+#else
+#define RST_BASE                     (0xE6160000U)
+#endif
+#define RST_MODEMR0                  (RST_BASE + 0x0000U)
+#define RST_MODEMR1                  (RST_BASE + 0x0004U)
+
+#if defined(__RH850G3K__)
+#define OTP_MEM_1_BASE               (BASE_OTP_MEM_ADDR)
+#else
+#define OTP_MEM_1_BASE               (0xE61BF000U)
+#endif
+#define OTP_MEM_OTPMONITOR17         (OTP_MEM_1_BASE + 0x0144U)
+#define OTP_MEM_PRODUCT_MASK         (0x000000FFU)
+
+/* Product Register */
+#define PRR                          (0xFFF00044U)
+#define PRR_PRODUCT_MASK             (0x00007F00U)
+#define PRR_CUT_MASK                 (0x000000FFU)
+
+#define PRR_PRODUCT_V4M              (0x00005D00U)    /* R-Car V4M */
+
+#define PRR_PRODUCT_10               (0x00000000U)    /* ver 1.0 */
+#define PRR_PRODUCT_20               (0x00000010U)    /* ver 2.0 */
+
+/* DBSC registers */
+#if defined(__RH850G3K__)
+#define DBSC_D_BASE                  (BASE_DBSC_ADDR + 0x14000U)    /* forV4M DBSC0 clk_dbsc region */
+#define DBSC_A_BASE                  (BASE_DBSC_ADDR)               /* forV4M DBSC0 clk_axim region */
+#else
+#define DBSC_D_BASE                  (0xE67A4000U)    /* forV4M DBSC0 clk_dbsc region */
+#define DBSC_A_BASE                  (0xE6790000U)    /* forV4M DBSC0 clk_axim region */
+#endif
+
+#define DBSC_DBSYSCONF0              (DBSC_A_BASE    +    0x0000U)
+#define DBSC_DBSYSCONF1              (DBSC_D_BASE    +    0x0000U)
+#define DBSC_DBSYSCONF1A             (DBSC_A_BASE    +    0x0004U)
+#define DBSC_DBSYSCONF2              (DBSC_D_BASE    +    0x0004U)
+#define DBSC_DBPHYCONF0              (DBSC_D_BASE    +    0x0008U)
+#define DBSC_DBSYSCONF2A             (DBSC_A_BASE    +    0x0008U)
+#define DBSC_DBMEMKIND               (DBSC_D_BASE    +    0x0020U)
+#define DBSC_DBMEMKINDA              (DBSC_A_BASE    +    0x0020U)
+
+#define DBSC_DBMEMCONF(ch,cs)        (DBSC_D_BASE    +    0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
+
+#define DBSC_DBMEMCONFA(ch,cs)       (DBSC_A_BASE    +    0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
+
+#define DBSC_DBSYSCNT0               (DBSC_D_BASE    +    0x0100U)
+#define DBSC_DBSYSCNT0A              (DBSC_A_BASE    +    0x0100U)
+
+#define DBSC_DBACEN                  (DBSC_A_BASE    +    0x0200U)
+#define DBSC_DBRFEN                  (DBSC_D_BASE    +    0x0204U)
+#define DBSC_DBCMD                   (DBSC_D_BASE    +    0x0208U)
+#define DBSC_DBWAIT                  (DBSC_D_BASE    +    0x0210U)
+
+#define DBSC_DBTR(x)                 (DBSC_D_BASE    +    0x0300U + (0x04U * (x)))
+
+#define DBSC_DBBL                    (DBSC_D_BASE    +    0x0400U)
+#define DBSC_DBBLA                   (DBSC_A_BASE    +    0x0400U)
+
+#define DBSC_DBRFCNF1                (DBSC_D_BASE    +    0x0414U)
+#define DBSC_DBRFCNF2                (DBSC_D_BASE    +    0x0418U)
+
+#define DBSC_DBCALCNF                (DBSC_D_BASE    +    0x0424U)
+
+#define DBSC_DBRNK(x)                (DBSC_D_BASE    +    0x0430U + (0x04U * (x)))
+
+#define DBSC_DBDBICNT                (DBSC_D_BASE    +    0x0518U)
+#define DBSC_DBDFIPMSTRCNF           (DBSC_D_BASE    +    0x0520U)
+#define DBSC_DBDFICUPDCNF            (DBSC_D_BASE    +    0x0540U)
+
+#define DBSC_DBDFISTAT(ch)           (DBSC_D_BASE    +    0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBDFICNT(ch)            (DBSC_D_BASE    +    0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDCNT2(ch)            (DBSC_D_BASE    +    0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDLK(ch)              (DBSC_D_BASE    +    0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDRGA(ch)             (DBSC_D_BASE    +    0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDRGD(ch)             (DBSC_D_BASE    +    0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDRGM(ch)             (DBSC_D_BASE    +    0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDSTAT0(ch)           (DBSC_D_BASE    +    0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBPDSTAT1(ch)           (DBSC_D_BASE    +    0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
+
+#define DBSC_DBBUS0CNF1              (DBSC_A_BASE    +    0x0804U)
+
+#define DBSC_DBBCAMDIS               (DBSC_A_BASE    +    0x09FCU)
+
+#define DBSC_DBSCHRW1                (DBSC_A_BASE    +    0x1024U)
+
+#define DBSC_DBSCHTR0                (DBSC_A_BASE    +    0x1030U)
+
+#define DBSC_DBSCHFCTST0             (DBSC_A_BASE    +    0x1040U)
+#define DBSC_DBSCHFCTST1             (DBSC_A_BASE    +    0x1044U)
+
+#endif /* BOOT_INIT_DRAM_REGDEF_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h

@@ -0,0 +1,390 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+#ifndef DDR_REGDEF_H_
+#define DDR_REGDEF_H_
+
+#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL                  0x10031000U
+#define PHY_PER_CS_TRAINING_MULTICAST_EN              0x18011006U
+#define PHY_PER_CS_TRAINING_INDEX                     0x00011007U
+#define PHY_VREF_INITIAL_STEPSIZE                     0x1808100EU
+#define PHY_RDLVL_BEST_THRSHLD                        0x0004100FU
+#define PHY_RDLVL_VREF_OUTLIER                        0x1003100FU
+#define SC_PHY_WCK_CALC                               0x1801101BU
+#define PHY_WRLVL_PER_START                           0x00071020U
+#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x08051022U
+#define PHY_CALVL_VREF_DRIVING_SLICE                  0x08011026U
+#define PHY_WRLVL_HARD0_DELAY_OBS                     0x000A102DU
+#define PHY_WRLVL_HARD1_DELAY_OBS                     0x100A102DU
+#define PHY_WRLVL_STATUS_OBS                          0x001C102EU
+#define PHY_WRLVL_ERROR_OBS                           0x00021030U
+#define PHY_GTLVL_STATUS_OBS                          0x00121032U
+#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x10091033U
+#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x00091034U
+#define PHY_WDQLVL_STATUS_OBS                         0x00201038U
+#define PHY_DATA_DC_CAL_START                         0x08011041U
+#define PHY_SLV_DLY_CTRL_GATE_DISABLE                 0x00011042U
+#define PHY_REGULATOR_EN_CNT                          0x00061044U
+#define PHY_VREF_INITIAL_START_POINT                  0x00091048U
+#define PHY_VREF_INITIAL_STOP_POINT                   0x10091048U
+#define PHY_VREF_TRAINING_CTRL                        0x00021049U
+#define PHY_RDDQ0_SLAVE_DELAY                         0x00091050U
+#define PHY_RDDQ1_SLAVE_DELAY                         0x10091050U
+#define PHY_RDDQ2_SLAVE_DELAY                         0x00091051U
+#define PHY_RDDQ3_SLAVE_DELAY                         0x10091051U
+#define PHY_RDDQ4_SLAVE_DELAY                         0x00091052U
+#define PHY_RDDQ5_SLAVE_DELAY                         0x10091052U
+#define PHY_RDDQ6_SLAVE_DELAY                         0x00091053U
+#define PHY_RDDQ7_SLAVE_DELAY                         0x10091053U
+#define PHY_RDDM_SLAVE_DELAY                          0x00091054U
+#define PHY_RX_CAL_ALL_DLY                            0x18061054U
+#define PHY_RX_PCLK_CLK_SEL                           0x00031055U
+#define PHY_DATA_DC_CAL_CLK_SEL                       0x08031055U
+#define PHY_PAD_VREF_CTRL_DQ                          0x100E1058U
+#define PHY_PER_CS_TRAINING_EN                        0x10011059U
+#define PHY_RDDATA_EN_TSEL_DLY                        0x0805105BU
+#define PHY_RDDATA_EN_OE_DLY                          0x1005105BU
+#define PHY_RPTR_UPDATE                               0x0804105EU
+#define PHY_WRLVL_RESP_WAIT_CNT                       0x0006105FU
+#define PHY_RDLVL_DLY_STEP                            0x08041062U
+#define PHY_RDLVL_MAX_EDGE                            0x00091063U
+#define PHY_DATA_DC_WDQLVL_ENABLE                     0x08021068U
+#define PHY_RDDATA_EN_DLY                             0x10051069U
+#define PHY_DQ_DM_SWIZZLE0                            0x0020106AU
+#define PHY_DQ_DM_SWIZZLE1                            0x0004106BU
+#define PHY_CLK_WRDQS_SLAVE_DELAY                     0x00091071U
+#define PHY_WRITE_PATH_LAT_DEC                        0x10011071U
+#define PHY_RDDQS_LATENCY_ADJUST                      0x1005107BU
+#define PHY_WRITE_PATH_LAT_ADD                        0x1803107BU
+#define PHY_WRITE_PATH_LAT_FRAC                       0x0008107CU
+#define PHY_GTLVL_LAT_ADJ_START                       0x0005107DU
+#define PHY_DATA_DC_DQS_CLK_ADJUST                    0x0008107FU
+#define PHY_ADR_CALVL_SWIZZLE0                        0x00201202U
+#define PHY_ADR_MEAS_DLY_STEP_ENABLE                  0x10011203U
+#define PHY_ADR_CALVL_RANK_CTRL                       0x18021205U
+#define PHY_ADR_CALVL_OBS1                            0x0020120AU
+#define PHY_ADR_CALVL_OBS2                            0x0020120BU
+#define PHY_ADR_CALVL_DLY_STEP                        0x00041210U
+#define PHY_CS_ACS_ALLOCATION_BIT2_2                  0x08021215U
+#define PHY_CS_ACS_ALLOCATION_BIT3_2                  0x10021215U
+#define PHY_CSLVL_OBS1                                0x00201221U
+#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE          0x1008122DU
+#define PHY_CLK_DC_CAL_CLK_SEL                        0x0803123AU
+#define PHY_FREQ_SEL_MULTICAST_EN                     0x08011301U
+#define PHY_FREQ_SEL_INDEX                            0x10021301U
+#define SC_PHY_MANUAL_UPDATE                          0x18011304U
+#define PHY_SET_DFI_INPUT_RST_PAD                     0x18011311U
+#define PHY_TCKSRE_WAIT                               0x1004131FU
+#define PHY_CAL_MODE_0                                0x000D132CU
+#define PHY_CAL_INTERVAL_COUNT_0                      0x0020132DU
+#define PHY_DATA_BYTE_ORDER_SEL                       0x0020133FU
+#define PHY_PAD_ACS_RX_PCLK_CLK_SEL                   0x1003134AU
+#define PHY_PLL_CTRL                                  0x000E134DU
+#define PHY_PLL_CTRL_8X                               0x100E134DU
+#define PHY_CAL_CLK_SELECT_0                          0x00031361U
+
+#define PI_START                                      0x00010800U
+#define PI_TRAIN_ALL_FREQ_REQ                         0x18010804U
+#define PI_FREQ_MAP                                   0x0020080DU
+#define PI_INIT_WORK_FREQ                             0x0005080EU
+#define PI_CS_MAP                                     0x08020815U
+#define PI_WRLVL_REQ                                  0x0801081FU
+#define PI_WRLVL_CS_SW                                0x1002081FU
+#define PI_RDLVL_REQ                                  0x10010827U
+#define PI_RDLVL_GATE_REQ                             0x18010827U
+#define PI_RDLVL_CS_SW                                0x00020828U
+#define PI_RDLVL_PERIODIC                             0x08010831U
+#define PI_RDLVL_INTERVAL                             0x08100838U
+#define PI_DRAMDCA_FLIP_MASK                          0x0802083EU
+#define PI_DRAMDCA_LVL_REQ                            0x10010840U
+#define PI_DCMLVL_CS_SW                               0x18020840U
+#define PI_WRDCM_LVL_EN_F1                            0x00020842U
+#define PI_DRAMDCA_LVL_EN_F1                          0x08020842U
+#define PI_WRDCM_LVL_EN_F2                            0x18020842U
+#define PI_DRAMDCA_LVL_EN_F2                          0x00020843U
+#define PI_TCKCKEL_F2                                 0x18040851U
+#define PI_WDQLVL_VREF_EN                             0x08040852U
+#define PI_WDQLVL_PERIODIC                            0x00010854U
+#define PI_WDQLVL_INTERVAL                            0x00100858U
+#define PI_INT_STATUS                                 0x002008B7U
+#define PI_INT_ACK_0                                  0x002008B9U
+#define PI_INT_ACK_1                                  0x000108BAU
+#define PI_LONG_COUNT_MASK                            0x100508BCU
+#define PI_ADDRESS_MUX_0                              0x000308BDU
+#define PI_ADDRESS_MUX_1                              0x080308BDU
+#define PI_ADDRESS_MUX_2                              0x100308BDU
+#define PI_ADDRESS_MUX_3                              0x180308BDU
+#define PI_ADDRESS_MUX_4                              0x000308BEU
+#define PI_ADDRESS_MUX_5                              0x080308BEU
+#define PI_ADDRESS_MUX_6                              0x100308BEU
+#define PI_DATA_BYTE_SWAP_EN                          0x180108BEU
+#define PI_DATA_BYTE_SWAP_SLICE0                      0x000108BFU
+#define PI_DATA_BYTE_SWAP_SLICE1                      0x080108BFU
+#define PI_PWRUP_SREFRESH_EXIT                        0x100108C2U
+#define PI_DLL_RST                                    0x000108C6U
+#define PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x000808E8U
+#define PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x000808E9U
+#define PI_WRLAT_F1                                   0x100708EDU
+#define PI_TWCKENL_RD_ADJ_F1                          0x000608EEU
+#define PI_TWCKPRE_STATIC_F1                          0x080608EEU
+#define PI_TWCKPRE_TOGGLE_RD_F1                       0x180608EEU
+#define PI_WCK_ACTIVE_WR_F1                           0x000708EFU
+#define PI_WCK_ACTIVE_RD_F1                           0x080708EFU
+#define PI_CASLAT_F1                                  0x180708EFU
+#define PI_WRLAT_F2                                   0x000708F0U
+#define PI_TWCKENL_WR_ADJ_F2                          0x080608F0U
+#define PI_TWCKENL_RD_ADJ_F2                          0x100608F0U
+#define PI_TWCKPRE_STATIC_F2                          0x180608F0U
+#define PI_TWCKPRE_TOGGLE_RD_F2                       0x080608F1U
+#define PI_WCK_ACTIVE_WR_F2                           0x100708F1U
+#define PI_WCK_ACTIVE_RD_F2                           0x180708F1U
+#define PI_TWCKENL_FS_ADJ_F2                          0x000608F2U
+#define PI_CASLAT_F2                                  0x080708F2U
+#define PI_TRFC_F1                                    0x000A08F4U
+#define PI_TREF_F1                                    0x001408F5U
+#define PI_TRFC_F2                                    0x000A08F6U
+#define PI_TREF_F2                                    0x001408F7U
+#define PI_WRLVL_EN_F1                                0x000208FAU
+#define PI_TDFI_WRLVL_WW_F1                           0x080A08FAU
+#define PI_WRLVL_EN_F2                                0x000208FBU
+#define PI_TDFI_WRLVL_WW_F2                           0x080A08FBU
+#define PI_WRLVL_WCKOFF_F2                            0x180808FBU
+#define PI_RDLVL_EN_F1                                0x100208FFU
+#define PI_RDLVL_GATE_EN_F1                           0x180208FFU
+#define PI_RDLVL_EN_F2                                0x00020900U
+#define PI_RDLVL_GATE_EN_F2                           0x08020900U
+#define PI_RDLVL_VREF_EN_F0                           0x18040900U
+#define PI_RDLVL_RDDQ_EN_F1                           0x00040902U
+#define PI_RDLVL_VREF_EN_F1                           0x08040902U
+#define PI_RDLVL_VREF_EN_F2                           0x18040903U
+#define PI_RDLAT_ADJ_F1                               0x10090905U
+#define PI_RDLAT_ADJ_F2                               0x00090906U
+#define PI_WRLAT_ADJ_F1                               0x18070906U
+#define PI_WRLAT_ADJ_F2                               0x00070907U
+#define PI_TDFI_CALVL_CC_F1                           0x000A0909U
+#define PI_TDFI_CALVL_CAPTURE_F1                      0x100A0909U
+#define PI_TDFI_CALVL_CC_F2                           0x000A090AU
+#define PI_TDFI_CALVL_CAPTURE_F2                      0x100A090AU
+#define PI_CALVL_EN_F1                                0x0802090BU
+#define PI_CALVL_EN_F2                                0x1002090BU
+#define PI_TCAENT_F1                                  0x000E090DU
+#define PI_TCAENT_F2                                  0x000E090EU
+#define PI_TVREF_LONG_F1                              0x000A0912U
+#define PI_TVRCG_ENABLE_F1                            0x100A0912U
+#define PI_TVRCG_DISABLE_F1                           0x000A0913U
+#define PI_TVREF_LONG_F2                              0x100A0914U
+#define PI_TVRCG_ENABLE_F2                            0x000A0915U
+#define PI_TVRCG_DISABLE_F2                           0x100A0915U
+#define PI_CALVL_VREF_INITIAL_START_POINT_F2          0x10070917U
+#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x18070917U
+#define PI_TDFI_CALVL_STROBE_F2                       0x0804091AU
+#define PI_TXP_F2                                     0x1005091AU
+#define PI_TMRWCKEL_F2                                0x1808091AU
+#define PI_TCKEHDQS_F1                                0x10060921U
+#define PI_TFC_F1                                     0x000A0922U
+#define PI_TCKEHDQS_F2                                0x10060922U
+#define PI_TFC_F2                                     0x000A0923U
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x10070925U
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x18070925U
+#define PI_TDFI_WDQLVL_WR_F1                          0x080A0928U
+#define PI_TDFI_WDQLVL_RW_F1                          0x000A0929U
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x10070929U
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x18070929U
+#define PI_WDQLVL_EN_F1                               0x0802092AU
+#define PI_WDQLVL_RDLAT_ADJ_F1                        0x0009092BU
+#define PI_WDQLVL_WRLAT_ADJ_F1                        0x1009092BU
+#define PI_WDQLVL_TWCKENL_RD_ADJ_F1                   0x0006092CU
+#define PI_TDFI_WDQLVL_WR_F2                          0x080A092CU
+#define PI_TDFI_WDQLVL_RW_F2                          0x000A092DU
+#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x1007092DU
+#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x1807092DU
+#define PI_WDQLVL_EN_F2                               0x0802092EU
+#define PI_WDQLVL_RDLAT_ADJ_F2                        0x0009092FU
+#define PI_WDQLVL_WRLAT_ADJ_F2                        0x1009092FU
+#define PI_WDQLVL_TWCKENL_RD_ADJ_F2                   0x00060930U
+#define PI_TRTP_F1                                    0x18080936U
+#define PI_TRP_F1                                     0x00080937U
+#define PI_TRCD_F1                                    0x08080937U
+#define PI_TWTR_S_F1                                  0x18060937U
+#define PI_TWTR_L_F1                                  0x00060938U
+#define PI_TWTR_F1                                    0x10060938U
+#define PI_TWR_F1                                     0x18080938U
+#define PI_TRAS_MAX_F1                                0x00100939U
+#define PI_TRAS_MIN_F1                                0x10090939U
+#define PI_TSR_F1                                     0x1008093AU
+#define PI_TRTP_F2                                    0x0808093BU
+#define PI_TRP_F2                                     0x1008093BU
+#define PI_TRCD_F2                                    0x1808093BU
+#define PI_TWTR_S_F2                                  0x0806093CU
+#define PI_TWTR_L_F2                                  0x1006093CU
+#define PI_TWTR_F2                                    0x0006093DU
+#define PI_TWR_F2                                     0x0808093DU
+#define PI_TRAS_MAX_F2                                0x1010093DU
+#define PI_TRAS_MIN_F2                                0x0009093EU
+#define PI_TDQSCK_MAX_F2                              0x1004093EU
+#define PI_TSR_F2                                     0x0008093FU
+#define PI_TMRD_F2                                    0x0808093FU
+#define PI_TDFI_CTRLUPD_MAX_F1                        0x00150942U
+#define PI_TDFI_CTRLUPD_INTERVAL_F1                   0x00200943U
+#define PI_TDFI_CTRLUPD_MAX_F2                        0x00150944U
+#define PI_TDFI_CTRLUPD_INTERVAL_F2                   0x00200945U
+#define PI_TXSR_F1                                    0x10100946U
+#define PI_TXSR_F2                                    0x00100947U
+#define PI_TINIT_F1                                   0x0018094EU
+#define PI_TINIT1_F1                                  0x0018094FU
+#define PI_TINIT3_F1                                  0x00180950U
+#define PI_TINIT4_F1                                  0x00180951U
+#define PI_TINIT5_F1                                  0x00180952U
+#define PI_TXSNR_F1                                   0x00100953U
+#define PI_TINIT_F2                                   0x00180954U
+#define PI_TINIT1_F2                                  0x00180955U
+#define PI_TINIT3_F2                                  0x00180956U
+#define PI_TINIT4_F2                                  0x00180957U
+#define PI_TINIT5_F2                                  0x00180958U
+#define PI_TXSNR_F2                                   0x00100959U
+#define PI_TZQCAL_F1                                  0x100C095CU
+#define PI_TZQLAT_F1                                  0x0007095DU
+#define PI_TZQCAL_F2                                  0x100C095EU
+#define PI_TZQLAT_F2                                  0x0007095FU
+#define PI_ZQRESET_F1                                 0x000C0960U
+#define PI_ZQRESET_F2                                 0x100C0960U
+#define PI_TDQ72DQ_F1                                 0x000A0964U
+#define PI_TCBTRTW_F1                                 0x10060964U
+#define PI_TDQ72DQ_F2                                 0x100A0965U
+#define PI_TCBTRTW_F2                                 0x00060966U
+#define PI_MC_TRFC_F1                                 0x100A0968U
+#define PI_MC_TRFC_F2                                 0x000A0969U
+#define PI_TDFI_WCK_STOP_F1                           0x0808096EU
+#define PI_TDFI_WCK_STOP_F2                           0x1808096EU
+#define PI_CKE_MUX_0                                  0x1802096FU
+#define PI_CKE_MUX_1                                  0x00020970U
+#define PI_SEQ_DEC_SW_CS                              0x0002097BU
+#define PI_SW_SEQ_START                               0x1001097BU
+#define PI_SEQ_ARRAY_29                               0x001D09C9U
+#define PI_SEQ_ARRAY_64                               0x001D09ECU
+#define PI_SEQ_ARRAY_65                               0x001D09EDU
+#define PI_SEQ_ARRAY_66                               0x001D09EEU
+#define PI_SEQ_ARRAY_67                               0x001D09EFU
+#define PI_SEQ_ARRAY_68                               0x001D09F0U
+#define PI_SEQ_ARRAY_69                               0x001D09F1U
+#define PI_SEQ_ARRAY_70                               0x001D09F2U
+#define PI_SEQ_ARRAY_71                               0x001D09F3U
+#define PI_SEQ_ARRAY_72                               0x001D09F4U
+#define PI_SEQ_ARRAY_81                               0x001D09FDU
+#define PI_SEQ_ARRAY_82                               0x001D09FEU
+#define PI_SEQ_ARRAY_333                              0x001B0AF9U
+#define PI_SEQ_ARRAY_334                              0x001B0AFAU
+#define PI_SEQ_ARRAY_335                              0x001B0AFBU
+#define PI_SEQ_ARRAY_349                              0x001B0B09U
+#define PI_SEQ_ARRAY_350                              0x001B0B0AU
+#define PI_RDLVL_TRAIN_SEQ_1                          0x001B0B9EU
+#define PI_RDLVL_TRAIN_SEQ_2                          0x001B0B9FU
+#define PI_RDLVL_TRAIN_SEQ_3                          0x001B0BA0U
+#define PI_RDLVL_TRAIN_SEQ_4                          0x001B0BA1U
+#define PI_RDLVL_TRAIN_SEQ_5                          0x001B0BA2U
+#define PI_SEQ_WAIT_16_F1                             0x00180BD2U
+#define PI_SEQ_WAIT_16_F2                             0x00180BD3U
+#define PI_SEQ_WAIT_17_F1                             0x00180BD5U
+#define PI_SEQ_WAIT_17_F2                             0x00180BD6U
+#define PI_SEQ_WAIT_18_F2                             0x00180BD9U
+#define PI_SEQ_WAIT_19_F1                             0x00180BDBU
+#define PI_SEQ_WAIT_19_F2                             0x00180BDCU
+#define PI_SEQ_WAIT_20_F1                             0x00180BDEU
+#define PI_SEQ_WAIT_20_F2                             0x00180BDFU
+#define PI_SEQ_WAIT_21_F1                             0x00180BE1U
+#define PI_SEQ_WAIT_21_F2                             0x00180BE2U
+#define PI_SEQ_WAIT_22_F1                             0x00180BE4U
+#define PI_SEQ_WAIT_22_F2                             0x00180BE5U
+#define PI_SEQ_WAIT_23_F1                             0x00180BE7U
+#define PI_SEQ_WAIT_23_F2                             0x00180BE8U
+#define PI_SEQ_WAIT_24_F1                             0x00180BEAU
+#define PI_SEQ_WAIT_24_F2                             0x00180BEBU
+#define PI_SEQ_WAIT_25_F1                             0x00180BEDU
+#define PI_SEQ_WAIT_25_F2                             0x00180BEEU
+#define PI_SEQ_WAIT_26_F1                             0x00180BF0U
+#define PI_SEQ_WAIT_26_F2                             0x00180BF1U
+#define PI_SEQ_WAIT_27_F2                             0x00180BF4U
+#define PI_SEQ_WAIT_31_F1                             0x00180BFFU
+#define PI_SEQ_WAIT_31_F2                             0x00180C00U
+#define PI_WP_GAP_0_F1                                0x100F0C0DU
+#define PI_WP_GAP_0_F2                                0x000F0C0EU
+#define PI_RP_GAP_0_F1                                0x000F0C0FU
+#define PI_RP_GAP_0_F2                                0x100F0C0FU
+#define PI_WR_GAP_S_0_F1                              0x100F0C10U
+#define PI_WR_GAP_S_0_F2                              0x000F0C11U
+#define PI_WR_GAP_L_0_F1                              0x000F0C12U
+#define PI_WR_GAP_L_0_F2                              0x100F0C12U
+#define PI_RW_GAP_0_F1                                0x100F0C13U
+#define PI_RW_GAP_0_F2                                0x000F0C14U
+#define PI_WP_GAP_1_F1                                0x000F0C1BU
+#define PI_WP_GAP_1_F2                                0x100F0C1BU
+#define PI_RP_GAP_1_F1                                0x100F0C1CU
+#define PI_RP_GAP_1_F2                                0x000F0C1DU
+#define PI_WR_GAP_S_1_F1                              0x000F0C1EU
+#define PI_WR_GAP_S_1_F2                              0x100F0C1EU
+#define PI_WR_GAP_L_1_F1                              0x100F0C1FU
+#define PI_WR_GAP_L_1_F2                              0x000F0C20U
+#define PI_RW_GAP_1_F1                                0x000F0C21U
+#define PI_RW_GAP_1_F2                                0x100F0C21U
+#define PI_WP_GAP_2_F1                                0x100F0C28U
+#define PI_WP_GAP_2_F2                                0x000F0C29U
+#define PI_RP_GAP_2_F1                                0x000F0C2AU
+#define PI_RP_GAP_2_F2                                0x100F0C2AU
+#define PI_WR_GAP_S_2_F1                              0x100F0C2BU
+#define PI_WR_GAP_S_2_F2                              0x000F0C2CU
+#define PI_WR_GAP_L_2_F1                              0x000F0C2DU
+#define PI_WR_GAP_L_2_F2                              0x100F0C2DU
+#define PI_RW_GAP_2_F1                                0x100F0C2EU
+#define PI_RW_GAP_2_F2                                0x000F0C2FU
+#define PI_WP_GAP_3_F1                                0x000F0C36U
+#define PI_WP_GAP_3_F2                                0x100F0C36U
+#define PI_RP_GAP_3_F1                                0x100F0C37U
+#define PI_RP_GAP_3_F2                                0x000F0C38U
+#define PI_WR_GAP_S_3_F1                              0x000F0C39U
+#define PI_WR_GAP_S_3_F2                              0x100F0C39U
+#define PI_WR_GAP_L_3_F1                              0x100F0C3AU
+#define PI_WR_GAP_L_3_F2                              0x000F0C3BU
+#define PI_RW_GAP_3_F1                                0x000F0C3CU
+#define PI_RW_GAP_3_F2                                0x100F0C3CU
+#define PI_DARRAY3_0_CS0_F0                           0x00080C9DU
+#define PI_DARRAY3_1_CS0_F0                           0x08080C9DU
+#define PI_DARRAY3_0_CS0_F1                           0x00080CA7U
+#define PI_DARRAY3_1_CS0_F1                           0x08080CA7U
+#define PI_DARRAY3_0_CS0_F2                           0x00080CB1U
+#define PI_DARRAY3_1_CS0_F2                           0x08080CB1U
+#define PI_DARRAY3_2_CS0_F2                           0x10080CB1U
+#define PI_DARRAY3_20_CS0_F2                          0x00080CB6U
+#define PI_DARRAY3_0_CS1_F0                           0x00080CBBU
+#define PI_DARRAY3_1_CS1_F0                           0x08080CBBU
+#define PI_DARRAY3_0_CS1_F1                           0x00080CC5U
+#define PI_DARRAY3_1_CS1_F1                           0x08080CC5U
+#define PI_DARRAY3_0_CS1_F2                           0x00080CCFU
+#define PI_DARRAY3_1_CS1_F2                           0x08080CCFU
+#define PI_DARRAY3_2_CS1_F2                           0x10080CCFU
+#define PI_DARRAY3_20_CS1_F2                          0x00080CD4U
+
+#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
+#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
+#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)
+
+#endif /* DDR_REGDEF_H_ */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c

@@ -0,0 +1,171 @@
+/*******************************************************************************
+ * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
+ *
+ *     RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ *
+ * This software is provided as reference/sample code under the license
+ * agreement between Renesas Electronics Corporation and licensee (the
+ * "License Agreement") and shall be treated as specified in the License
+ * Agreement.
+ * These instructions, statements, and software are the confidential
+ * information of Renesas Electronics Corporation. They must be used and
+ * modified solely for the purpose for which it was furnished by Renesas
+ * Electronics Corporation. All or part of these instructions, statements and
+ * software must not be reproduced nor disclosed to any third party in any
+ * form, unless permitted by the License Agreement.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+ * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
+ * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECC initialize function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ecc_enable_v4m.c
+ * - Version      : 0.05
+ * @brief         Enable setting process of ECC for DRAM.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 21.08.2023 0.01     First Release
+ *         : 21.08.2023 0.02     Update the ecc setting according to HW SAN rev0.82.
+ *         : 08.04.2024 0.03     Update the ecc register setting.
+ *         : 13.06.2024 0.04     Fix register setting for EDC_CFG, and revise
+ *         :                     the ecm_lock()/ecm_unlock() process.
+ *         : 27.01.2025 0.05     Add ECM setting process.
+ *                               Remove unused functions.
+ *****************************************************************************/
+
+#include <stdint.h>
+
+#if (ECC_ENABLE == 1)
+#include "ecc_enable_v4m.h"
+#include "ecm_enable_v4m.h"
+#include "mem_io.h"
+#include "v4m/lpddr5/boot_init_dram_regdef.h"
+
+/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
+void ecc_sdram_enable(void)
+{
+    NOTICE("ECC for DRAM is enable.\n");
+
+    uint32_t ecm_tmp;
+
+    /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
+    After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
+    mem_write32(DB0SYSCNT0, 0x00001234U);
+    mem_write32(DB0SYSCNT0A, 0x00001234U);
+
+    /* (A) Setting ECM */
+    /* Unlock the write protect of ECM registers */
+    ecm_unlock();
+    /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
+                to inform the external device of the error via the ERROROUT# pin. */
+    /* Set bit 1 of ECMERRTGTR0 to 0 and bit 1 of ECMERRCTLR0 to 1.  */
+    ecm_tmp = mem_read32(ECMERRTGTR0);
+    ecm_tmp &= ~(0x2U);
+    ecm_write(ECMERRTGTR0, ecm_tmp);
+
+    ecm_tmp = mem_read32(ECMERRCTLR0);
+    ecm_tmp |= (0x2U);
+    ecm_write(ECMERRCTLR0, ecm_tmp);
+
+    /* (B) Setting ECC protection area */
+    /* Set the bottom row address of the ECC protection area */
+    mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
+    mem_write32(DB0FSDRAMECCAREA01, ECC_PROT_SIZE01);
+
+    /* (C) Initialization for DRAM */
+    mem_write32(DBSC_DB0ACEN, 0x00000000U);
+
+    /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
+    /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
+    mem_write32(DB0FSCONF00A, 0x0U);
+
+    /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
+    mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
+
+    /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
+    mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
+
+    /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
+    mem_write32(DB0FSCTRL01A, 0x01U);
+
+    /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
+    NOTICE("DRAM rank 0 of DBSC0 is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB0FSSTAT01A);
+    } while ((ecm_tmp & 0x01U) != 0x01U);
+
+    /*** If DRAM is connected to RANK1, Initialize RANK1 by the following procedure ***/
+    /* [Step1] Specify RANK1 as the initialization target. Set 0x1 to DB0FSCONF00A[1:0]. */
+    mem_write32(DB0FSCONF00A, 0x1U);
+
+    /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
+    mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA01);
+
+    /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
+    mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA01);
+
+    /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
+    mem_write32(DB0FSCTRL01A, 0x01U);
+
+    /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
+    NOTICE("DRAM rank 1 of DBSC0 is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB0FSSTAT01A);
+    } while ((ecm_tmp & 0x01U) != 0x01U);
+
+    /* (D) Setting ECC protection enable */
+    ecm_tmp = mem_read32(DB0FSCONFAXI0);
+    ecm_tmp |= (0x3U << 8U);
+    mem_write32(DB0FSCONFAXI0, ecm_tmp);
+
+    /* (E) System RAM initialization */
+    /* Read DB0FSSTAT00A and wait until its value changes to 0x1. */
+    /* When DB0FSSTAT00A changes to 0x1, the System RAM area initialization is complete of dbs0 */
+    NOTICE("System RAM is initializing.......\n");
+    do
+    {
+        ecm_tmp = 0x01U;
+        ecm_tmp &= mem_read32(DB0FSSTAT00A);
+    } while (ecm_tmp != 0x1U);
+
+    /* (F) Setting for ECC error interrupt */
+    /* (1) Set the ECC error interrupt for read data */
+    mem_write32(DB0FSINTENB02A, 0xFF00U);
+
+    /* (2) Set the ECC error interrupt during RMW operation for System RAM. */
+    ecm_tmp = mem_read32(DB0FSINTENB02A);
+    ecm_tmp |= 0xFF000000U;
+    mem_write32(DB0FSINTENB02A, ecm_tmp);
+
+    /* (3) Set the ECC error interrupt during RMW operation for DRAM. */
+    mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
+
+    /* Lock the ECM registers */
+    ecm_lock();
+
+    /* Enable the write protect of ECM registers */
+    mem_write32(DBSC_DB0ACEN, 0x00000001U);
+
+    /* Enable the access protect for DBSC registers */
+    mem_write32(DB0SYSCNT0, 0x00000000U);
+    mem_write32(DB0SYSCNT0A, 0x00000000U);
+}
+#endif /* ECC_ENABLE == 1 */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h

@@ -0,0 +1,116 @@
+/*******************************************************************************
+ * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
+ *
+ *     RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ *
+ * This software is provided as reference/sample code under the license
+ * agreement between Renesas Electronics Corporation and licensee (the
+ * "License Agreement") and shall be treated as specified in the License
+ * Agreement.
+ * These instructions, statements, and software are the confidential
+ * information of Renesas Electronics Corporation. They must be used and
+ * modified solely for the purpose for which it was furnished by Renesas
+ * Electronics Corporation. All or part of these instructions, statements and
+ * software must not be reproduced nor disclosed to any third party in any
+ * form, unless permitted by the License Agreement.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+ * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
+ * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECC driver header
+ ******************************************************************************/
+
+#ifndef ECC_PROTECT
+#define ECC_PROTECT
+/* DBSC registers */
+#if defined(__RH850G3K__)
+#include "remap_register.h"
+#include "mem_io.h"
+#include "log.h"
+#define DBSC_D_BASE			  (BASE_DBSC_ADDR + 0x14000U)	/* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE			  (BASE_DBSC_ADDR)	            /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
+#define ECM_BASE              (BASE_ECC_ADDR)
+#else
+#if (ECC_ENABLE == 1)
+#include "mem_io.h"
+#include "log.h"
+#define DBSC_D_BASE			  (0xE67A4000U)	                /* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
+#define DBSC_A_BASE			  (0xE6790000U)	                /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
+#endif /* ECC_ENABLE == 1 */
+#define ECM_BASE              (0xE6250000U)
+#endif/* defined(__RH850G3K__) */
+
+#if (ECC_ENABLE == 1)
+void ecc_sdram_enable(void);
+
+#define DB0SYSCNT0            (DBSC_D_BASE + 0x0100U)
+#define DB0SYSCNT0A           (DBSC_A_BASE + 0x0100U)
+#define DB1SYSCNT0            (DB0SYSCNT0 +  0x4000U)
+#define DB1SYSCNT0A           (DB0SYSCNT0A + 0x8000U)
+
+#define	DBSC_DB0ACEN		  (DBSC_A_BASE + 0x0200U)
+#define	DBSC_DB1ACEN		  (DBSC_DB0ACEN + 0x8000U)
+#endif /* ECC_ENABLE == 1 */
+
+#define ECMWACNTR             (ECM_BASE + 0x0A04U)
+#define ECMWPCNTR             (ECM_BASE + 0x0A00U)
+#if (ECC_ENABLE == 1)
+#define ECMERRTGTR0           (ECM_BASE + 0x0200U)
+#define ECMERRCTLR0           (ECM_BASE + 0x0000U)
+#define DB0FSCONF00A          (DBSC_A_BASE    + 0x7640U)
+#define DB1FSCONF00A          (DB0FSCONF00A   + 0x8000U)
+#define DB0FSCONF01A          (DBSC_A_BASE    + 0x7644U)
+#define DB1FSCONF01A          (DB0FSCONF01A   + 0x8000U)
+#define DB0FSCONF02A          (DBSC_A_BASE    + 0x7648U)
+#define DB1FSCONF02A          (DB0FSCONF02A   + 0x8000U)
+#define DB0FSCTRL01A          (DBSC_A_BASE    + 0x7604U)
+#define DB1FSCTRL01A          (DB0FSCTRL01A   + 0x8000U)
+#define DB0FSSTAT01A          (DBSC_A_BASE    + 0x7684U)
+#define DB1FSSTAT01A          (DB0FSSTAT01A   + 0x8000U)
+#define DB0FSSTAT00A          (DBSC_A_BASE    + 0x7680U)
+#define DB1FSSTAT00A          (DB0FSSTAT00A   + 0x8000U)
+#define DB0FSINTENB02A        (DBSC_A_BASE    + 0x7088U)
+#define DB1FSINTENB02A        (DB0FSINTENB02A + 0x8000U)
+#define DB0FSINTENB04A        (DBSC_A_BASE    + 0x7090U)
+#define DB1FSINTENB04A        (DB0FSINTENB04A + 0x8000U)
+
+#define DB0FSDRAMECCAREA00     (DBSC_A_BASE + 0x7450U)
+#define DB0FSDRAMECCAREA01     (DBSC_A_BASE + 0x7454U)
+#define DB1FSDRAMECCAREA00     (DB0FSDRAMECCAREA00 + 0x8000U)
+#define DB1FSDRAMECCAREA01     (DB0FSDRAMECCAREA01 + 0x8000U)
+
+#define DB0FSCONFAXI0        (DBSC_A_BASE   + 0x7400U)
+#define DB1FSCONFAXI0        (DB0FSCONFAXI0 + 0x8000U)
+
+/********************* Set by the user *********************/
+/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
+#define ECC_PROT_SIZE00        (0xCCCCU)
+#define ECC_PROT_SIZE01        (0xCCCCU)
+#define ECC_PROT_SIZE10        (0xCCCCU)
+#define ECC_PROT_SIZE11        (0xCCCCU)
+
+/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
+#define START_ECC_INIT_AREA00   (0x00000000U)
+#define START_ECC_INIT_AREA10   (0x00000000U)
+#define END_ECC_INIT_AREA00     (0x0000CCCBU)
+#define END_ECC_INIT_AREA10     (0x0000CCCBU)
+
+/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
+#define START_ECC_INIT_AREA01   (0x00000000U)
+#define START_ECC_INIT_AREA11   (0x00000000U)
+#define END_ECC_INIT_AREA01     (0x0000CCCBU)
+#define END_ECC_INIT_AREA11     (0x0000CCCBU)
+/***********  Other settings cannot be changed ***************/
+#endif /* ECC_ENABLE == 1 */
+
+#endif/* ECC_PROTECT */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c

@@ -0,0 +1,265 @@
+/*******************************************************************************
+ * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
+ *
+ *     RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ *
+ * This software is provided as reference/sample code under the license
+ * agreement between Renesas Electronics Corporation and licensee (the
+ * "License Agreement") and shall be treated as specified in the License
+ * Agreement.
+ * These instructions, statements, and software are the confidential
+ * information of Renesas Electronics Corporation. They must be used and
+ * modified solely for the purpose for which it was furnished by Renesas
+ * Electronics Corporation. All or part of these instructions, statements and
+ * software must not be reproduced nor disclosed to any third party in any
+ * form, unless permitted by the License Agreement.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+ * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
+ * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECM initialize function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ecm_enable_v4m.c
+ * - Version      : 0.01
+ * @brief         ECM setting.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 29.01.2025 0.01     First Release
+ *****************************************************************************/
+
+#include <stdint.h>
+#include "ecm_enable_v4m.h"
+
+#if (ECM_ERROR_ENABLE == 1)
+#include "log.h"
+#endif /* ECM_ERROR_ENABLE == 1 */
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+#include "ecc_enable_v4m.h"
+#include "mem_io.h"
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+#define ECM_ERR_REG_MAX     (39U)
+
+typedef struct{
+    uint32_t phys_addr; /* Physical address of ECM registers. */
+    uint32_t value;     /* Setting value of ECM registers. */
+} ECM_ERROR_TABLE;
+#endif /* ECM_ERROR_ENABLE == 1 */
+
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+void ecm_unlock(void)
+{
+    mem_write32(ECMWPCNTR, 0xACCE0001U);
+}
+
+void ecm_write(uint32_t adr, uint32_t val)
+{
+    mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
+    mem_write32(adr, val);
+}
+
+void ecm_lock(void)
+{
+    mem_write32(ECMWPCNTR, 0xACCE0000U);
+}
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+void ecm_error_enable(void)
+{
+    uint32_t reg;
+    uint32_t loop;
+
+    const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250000U, 0xFFFFF003U}, /* ECMERRCTLR0 */
+    [1]   =     {0xE6250004U, 0xA7F8C000U}, /* ECMERRCTLR1 */
+    [2]   =     {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
+    [3]   =     {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
+    [4]   =     {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
+    [5]   =     {0xE6250014U, 0x8FFFFFFFU}, /* ECMERRCTLR5 */
+    [6]   =     {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
+    [7]   =     {0xE625001CU, 0x68980FFFU}, /* ECMERRCTLR7 */
+    [8]   =     {0xE6250020U, 0x60A00000U}, /* ECMERRCTLR8 */
+    [9]   =     {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
+    [10]  =     {0xE6250028U, 0x557D554CU}, /* ECMERRCTLR10 */
+    [11]  =     {0xE625002CU, 0xFF3C1555U}, /* ECMERRCTLR11 */
+    [12]  =     {0xE6250030U, 0x0003FFFFU}, /* ECMERRCTLR12 */
+        /* Skip ECMERRCTLR13 setting */
+        /* Skip ECMERRCTLR14 setting */
+        /* Skip ECMERRCTLR15 setting */
+    [13]  =     {0xE6250040U, 0x33F03FFFU}, /* ECMERRCTLR16 */
+    [14]  =     {0xE6250044U, 0x2DFF9CE0U}, /* ECMERRCTLR17 */
+    [15]  =     {0xE6250048U, 0x0CC037FFU}, /* ECMERRCTLR18 */
+    [16]  =     {0xE625004CU, 0xFFFFFF31U}, /* ECMERRCTLR19 */
+    [17]  =     {0xE6250050U, 0xFE60067EU}, /* ECMERRCTLR20 */
+    [18]  =     {0xE6250054U, 0xBF61820FU}, /* ECMERRCTLR21 */
+    [19]  =     {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
+    [20]  =     {0xE625005CU, 0x7E90C008U}, /* ECMERRCTLR23 */
+    [21]  =     {0xE6250060U, 0x7E788AD9U}, /* ECMERRCTLR24 */
+    [22]  =     {0xE6250064U, 0xC7807AB7U}, /* ECMERRCTLR25 */
+    [23]  =     {0xE6250068U, 0x7E90C008U}, /* ECMERRCTLR26 */
+    [24]  =     {0xE625006CU, 0x7E788AD9U}, /* ECMERRCTLR27 */
+    [25]  =     {0xE6250070U, 0xC7807AB7U}, /* ECMERRCTLR28 */
+    [26]  =     {0xE6250074U, 0x0010C008U}, /* ECMERRCTLR29 */
+    [27]  =     {0xE6250078U, 0x7E608A99U}, /* ECMERRCTLR30 */
+    [28]  =     {0xE625007CU, 0x84007A00U}, /* ECMERRCTLR31 */
+    [29]  =     {0xE6250080U, 0xDFFFFFFFU}, /* ECMERRCTLR32 */
+    [30]  =     {0xE6250084U, 0x1FFFFFFFU}, /* ECMERRCTLR33 */
+    [31]  =     {0xE6250088U, 0x0000001FU}, /* ECMERRCTLR34 */
+    [32]  =     {0xE625008CU, 0xA3BEEA80U}, /* ECMERRCTLR35 */
+    [33]  =     {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
+        /* Skip ECMERRCTLR37 setting */
+    [34]  =     {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
+    [35]  =     {0xE625009CU, 0x19FF0000U}, /* ECMERRCTLR39 */
+    [36]  =     {0xE62500A0U, 0x0000601EU}, /* ECMERRCTLR40 */
+    [37]  =     {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
+    [38]  =     {0xE62500A8U, 0x0000000FU}, /* ECMERRCTLR42 */
+    };
+
+#if (ECMERRTGTR_INTC == 1)
+    const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250200U, 0xFFFFF003U}, /* ECMERRTGTR0 */
+    [1]   =     {0xE6250204U, 0xA7F8C000U}, /* ECMERRTGTR1 */
+    [2]   =     {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
+    [3]   =     {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
+    [4]   =     {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
+    [5]   =     {0xE6250214U, 0x8FFFFFFFU}, /* ECMERRTGTR5 */
+    [6]   =     {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
+    [7]   =     {0xE625021CU, 0x68980FFFU}, /* ECMERRTGTR7 */
+    [8]   =     {0xE6250220U, 0x60A00000U}, /* ECMERRTGTR8 */
+    [9]   =     {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
+    [10]  =     {0xE6250228U, 0x557D554CU}, /* ECMERRTGTR10 */
+    [11]  =     {0xE625022CU, 0xFF3C1555U}, /* ECMERRTGTR11 */
+    [12]  =     {0xE6250230U, 0x0003FFFFU}, /* ECMERRTGTR12 */
+        /* Skip ECMERRTGTR13 setting */
+        /* Skip ECMERRTGTR14 setting */
+        /* Skip ECMERRTGTR15 setting */
+    [13]  =     {0xE6250240U, 0x33F03FFFU}, /* ECMERRTGTR16 */
+    [14]  =     {0xE6250244U, 0x2DFF9CE0U}, /* ECMERRTGTR17 */
+    [15]  =     {0xE6250248U, 0x0CC037FFU}, /* ECMERRTGTR18 */
+    [16]  =     {0xE625024CU, 0xFFFFFF31U}, /* ECMERRTGTR19 */
+    [17]  =     {0xE6250250U, 0xFE60067EU}, /* ECMERRTGTR20 */
+    [18]  =     {0xE6250254U, 0xBF61820FU}, /* ECMERRTGTR21 */
+    [19]  =     {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
+    [20]  =     {0xE625025CU, 0x7E90C008U}, /* ECMERRTGTR23 */
+    [21]  =     {0xE6250260U, 0x7E788AD9U}, /* ECMERRTGTR24 */
+    [22]  =     {0xE6250264U, 0xC7807AB7U}, /* ECMERRTGTR25 */
+    [23]  =     {0xE6250268U, 0x7E90C008U}, /* ECMERRTGTR26 */
+    [24]  =     {0xE625026CU, 0x7E788AD9U}, /* ECMERRTGTR27 */
+    [25]  =     {0xE6250270U, 0xC7807AB7U}, /* ECMERRTGTR28 */
+    [26]  =     {0xE6250274U, 0x0010C008U}, /* ECMERRTGTR29 */
+    [27]  =     {0xE6250278U, 0x7E608A99U}, /* ECMERRTGTR30 */
+    [28]  =     {0xE625027CU, 0x84007A00U}, /* ECMERRTGTR31 */
+    [29]  =     {0xE6250280U, 0xDFFFFFFFU}, /* ECMERRTGTR32 */
+    [30]  =     {0xE6250284U, 0x1FFFFFFFU}, /* ECMERRTGTR33 */
+    [31]  =     {0xE6250288U, 0x0000001FU}, /* ECMERRTGTR34 */
+    [32]  =     {0xE625028CU, 0xA3BEEA80U}, /* ECMERRTGTR35 */
+    [33]  =     {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
+        /* Skip ECMERRTGTR37 setting */
+    [34]  =     {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
+    [35]  =     {0xE625029CU, 0x19FF0000U}, /* ECMERRTGTR39 */
+    [36]  =     {0xE62502A0U, 0x0000601EU}, /* ECMERRTGTR40 */
+    [37]  =     {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
+    [38]  =     {0xE62502A8U, 0x0000000FU}, /* ECMERRTGTR42 */
+    };
+#elif (ECMERRTGTR_INTC == 0)
+    const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
+    [0]   =     {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
+    [1]   =     {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
+    [2]   =     {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
+    [3]   =     {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
+    [4]   =     {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
+    [5]   =     {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
+    [6]   =     {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
+    [7]   =     {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
+    [8]   =     {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
+    [9]   =     {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
+    [10]  =     {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
+    [11]  =     {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
+    [12]  =     {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
+        /* Skip ECMERRTGTR13 setting */
+        /* Skip ECMERRTGTR14 setting */
+        /* Skip ECMERRTGTR15 setting */
+    [13]  =     {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
+    [14]  =     {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
+    [15]  =     {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
+    [16]  =     {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
+    [17]  =     {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
+    [18]  =     {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
+    [19]  =     {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
+    [20]  =     {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
+    [21]  =     {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
+    [22]  =     {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
+    [23]  =     {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
+    [24]  =     {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
+    [25]  =     {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
+    [26]  =     {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
+    [27]  =     {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
+    [28]  =     {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
+    [29]  =     {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
+    [30]  =     {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
+    [31]  =     {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
+    [32]  =     {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
+    [33]  =     {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
+        /* Skip ECMERRTGTR37 setting */
+    [34]  =     {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
+    [35]  =     {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
+    [36]  =     {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
+    [37]  =     {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
+    [38]  =     {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
+    };
+#endif /* ECMERRTGTR_INTC == 1 */
+
+    /* Unlock the write protect of ECM registers */
+    ecm_unlock();
+
+    NOTICE("ECMERRCTLR register setting.\n");
+    for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
+    {
+        /* Set ECMERRCTLR registers. */
+        reg  = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
+        reg |= ecmerrctlr_tbl[loop].value;
+        ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
+
+        INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
+            loop,
+            ecmerrctlr_tbl[loop].phys_addr,
+            mem_read32(ecmerrctlr_tbl[loop].phys_addr),
+            ecmerrctlr_tbl[loop].value);
+    }
+
+    NOTICE("ECMERRTGTR register setting.\n");
+    for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
+    {
+        /* Set ECMERRTGTR registers. */
+        reg  = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
+        reg |= ecmerrtgtr_tbl[loop].value;
+        ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
+
+        INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
+            loop,
+            ecmerrtgtr_tbl[loop].phys_addr,
+            mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
+            ecmerrtgtr_tbl[loop].value);
+    }
+
+    /* Lock the ECM registers */
+    ecm_lock();
+}
+/* End of function ecm_error_enable(void) */
+#endif /* ECM_ERROR_ENABLE == 1 */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h

@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
+ *
+ *     RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ *
+ * This software is provided as reference/sample code under the license
+ * agreement between Renesas Electronics Corporation and licensee (the
+ * "License Agreement") and shall be treated as specified in the License
+ * Agreement.
+ * These instructions, statements, and software are the confidential
+ * information of Renesas Electronics Corporation. They must be used and
+ * modified solely for the purpose for which it was furnished by Renesas
+ * Electronics Corporation. All or part of these instructions, statements and
+ * software must not be reproduced nor disclosed to any third party in any
+ * form, unless permitted by the License Agreement.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+ * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
+ * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : ECM driver header
+ ******************************************************************************/
+
+#ifndef ECM_ENABLE
+#define ECM_ENABLE
+
+#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
+void ecm_unlock(void);
+void ecm_write(uint32_t adr, uint32_t val);
+void ecm_lock(void);
+#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
+
+#if (ECM_ERROR_ENABLE == 1)
+void ecm_error_enable(void);
+#endif /* ECM_ERROR_ENABLE == 1 */
+
+#endif/* ECM_ENABLE */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c

@@ -0,0 +1,95 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc boot
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_boot.c
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 18.03.2022 0.02     Removed unnecessary functions
+ *                               Removed unnecessary header file inclusions
+ *         : 16.06.2022 0.03     Change log output
+ *         : 31.10.2022 0.04     License notation change.
+ *****************************************************************************/
+
+#include "emmc_boot.h"
+#include "log.h"
+#include "emmc_std.h"
+#include "emmc_def.h"
+
+
+/************************************************************************************************/
+/*	Definitions																					*/
+/************************************************************************************************/
+
+
+/************************************************************************************************/
+/*	Unions																						*/
+/************************************************************************************************/
+
+
+/************************************************************************************************/
+/*	Structs																						*/
+/************************************************************************************************/
+
+
+/************************************************************************************************/
+/*	Globals																						*/
+/************************************************************************************************/
+
+/************************************************************************************************/
+/*	Macros																						*/
+/************************************************************************************************/
+
+/************************************************************************************************/
+/*	Prototypes																					*/
+/************************************************************************************************/
+
+void emmc_initialize( void )
+{
+	EMMC_ERROR_CODE result;
+
+	/* eMMC driver initialize */
+	(void)emmc_init(); /* Normal clock mode */
+
+	/* Card power on */
+	(void)emmc_memcard_power(TRUE);
+
+	/* Card mount */
+	result = emmc_mount();
+
+	if (result != EMMC_SUCCESS)
+	{
+		NOTICE("eMMC initialize error!!\n");
+		panic;
+	}
+}

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c

@@ -0,0 +1,622 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc command
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_cmd.c
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 16.06.2022 0.02     Change log output
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 07.06.2024 0.04     Modify the transfer end bit of DMAC channel.
+ *****************************************************************************/
+
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "timer.h"
+#include "log.h"
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+static void emmc_read_response(uint32_t *response);
+static void emmc_little_to_big(uint8_t *p, uint32_t value);
+static void emmc_data_transfer_dma(void);
+static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask);
+static void emmc_softreset(void);
+static void emmc_WaitCmd2Cmd_8Cycle(void);
+
+/* ********************************* CODE ********************************** */
+
+/* execute MMC command.
+ *
+ * - Pre-conditions:<BR>
+ *  * Clock to memory card IF is enabled.
+ * - Post-conditions:<BR>
+ * Requested command is executed successfully
+ *
+ * param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS)
+ * param[in,out] *response Response from the card  (virtual address)
+ * return eMMC error code.
+ */
+EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
+{
+    EMMC_ERROR_CODE rtn_code = EMMC_ERR;
+    HAL_MEMCARD_RESPONSE_TYPE response_type;
+    HAL_MEMCARD_COMMAND_TYPE cmd_type;
+    EMMC_INT_STATE state;
+
+    /* parameter check */
+    if (response == NULL)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
+        return EMMC_ERR_PARAM;
+    }
+
+    /* state check */
+    if (mmc_drv_obj.clock_enable != TRUE)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE);
+        return EMMC_ERR_STATE;
+    }
+
+    if (mmc_drv_obj.state_machine_blocking == TRUE)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR);
+        return EMMC_ERR;
+    }
+
+    state = ESTATE_BEGIN;
+    response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK);
+    cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK);
+
+    /* state machine */
+    while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END))
+    {
+        /* The interrupt factor flag is observed. */
+        (void)emmc_interrupt();
+
+        /* wait interrupt */
+        if (mmc_drv_obj.state_machine_blocking == TRUE)
+        {
+            continue;
+        }
+
+        switch (state)
+        {
+            case ESTATE_BEGIN:
+                /* Busy check */
+                if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U)
+                {
+                    ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY);
+                    return EMMC_ERR_CARD_BUSY;
+                }
+
+                /* clear register */
+                mem_write32(SD_INFO1, 0x00000000U);
+                mem_write32(SD_INFO2, SD_INFO2_CLEAR);
+                mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0);
+                mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+
+                /* fallthrough */
+
+            case ESTATE_ISSUE_CMD:
+                /* ARG */
+                mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg);
+                /* issue cmd */
+                mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw);
+                /* Set driver flag */
+                mmc_drv_obj.state_machine_blocking = TRUE;
+
+                if (response_type == HAL_MEMCARD_RESPONSE_NONE)
+                {
+                    state = ESTATE_NON_RESP_CMD;
+                } else {
+                    state = ESTATE_RCV_RESP;
+                }
+
+                break;
+
+            case ESTATE_NON_RESP_CMD:
+                /* interrupt disable */
+                mem_write32(SD_INFO1_MASK, 0x00000000U);
+                mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+
+                /* check interrupt */
+                if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
+                {
+                    /* error interrupt */
+                    rtn_code = EMMC_ERR_INFO2;
+                    state = ESTATE_ERROR;
+                } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) {
+                    /* not receive expected interrupt */
+                    rtn_code = EMMC_ERR_RESPONSE;
+                    state = ESTATE_ERROR;
+                } else {
+                    emmc_WaitCmd2Cmd_8Cycle();
+                    state = ESTATE_END;
+                }
+                break;
+
+            case ESTATE_RCV_RESP:
+                /* interrupt disable */
+                mem_write32(SD_INFO1_MASK, 0x00000000U);
+                mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+
+                /* check interrupt */
+                if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
+                {
+                    /* error interrupt */
+                    rtn_code = EMMC_ERR_INFO2;
+                    state = ESTATE_ERROR;
+                    break;
+                } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) {
+                    /* not receive expected interrupt */
+                    rtn_code = EMMC_ERR_RESPONSE;
+                    state = ESTATE_ERROR;
+                    break;
+                } else {
+                    /* nop */
+                }
+
+                /* read response */
+                emmc_read_response(response);
+
+                /* check response */
+                rtn_code = emmc_response_check(response, error_mask);
+                if (rtn_code != EMMC_SUCCESS)
+                {
+                    state = ESTATE_ERROR;
+                    break;
+                }
+
+                if (response_type == HAL_MEMCARD_RESPONSE_R1b)
+                {
+                    /* R1b */
+                    mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+                    state = ESTATE_RCV_RESPONSE_BUSY;
+                } else {
+                    state = ESTATE_CHECK_RESPONSE_COMPLETE;
+                }
+                break;
+
+            case ESTATE_RCV_RESPONSE_BUSY:
+                /* check interrupt */
+                if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
+                {
+                    /* error interrupt */
+                    rtn_code = EMMC_ERR_INFO2;
+                    state = ESTATE_ERROR;
+                    break;
+                }
+                /* DAT0 not Busy */
+                if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U)
+                {
+                    state = ESTATE_CHECK_RESPONSE_COMPLETE;
+                    break;
+                }
+                break;
+
+            case ESTATE_CHECK_RESPONSE_COMPLETE:
+                if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE)
+                {
+                    state = ESTATE_DATA_TRANSFER;
+                } else {
+                    emmc_WaitCmd2Cmd_8Cycle();
+                    state = ESTATE_END;
+                }
+                break;
+
+            case ESTATE_DATA_TRANSFER:
+                /* ADTC command  */
+                mmc_drv_obj.during_transfer = TRUE;
+                mmc_drv_obj.state_machine_blocking = TRUE;
+
+                if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA)
+                {
+                    /* DMA */
+                    emmc_data_transfer_dma();
+                } else {
+                    /* PIO */
+                    /* interrupt enable (FIFO read/write enable) */
+                    if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
+                    {
+                        mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+                    } else {
+                        mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+                    }
+                }
+                state = ESTATE_DATA_TRANSFER_COMPLETE;
+                break;
+
+            case ESTATE_DATA_TRANSFER_COMPLETE:
+                /* check interrupt */
+                if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
+                {
+                    /* error interrupt */
+                    rtn_code = EMMC_ERR_INFO2;
+                    state = ESTATE_TRANSFER_ERROR;
+                    break;
+                } else {
+                    /* success. nothing to do. */
+                }
+
+                /* DMAC error ? */
+                if (mmc_drv_obj.dma_error_flag == TRUE)
+                {
+                    /* Error occurred in DMAC driver. */
+                    rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER;
+                    state = ESTATE_TRANSFER_ERROR;
+                } else if (mmc_drv_obj.during_dma_transfer == TRUE) {
+                    /* DMAC not finished. unknown error */
+                    rtn_code = EMMC_ERR;
+                    state = ESTATE_TRANSFER_ERROR;
+                } else {
+                    mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2);
+                    mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+
+                    mmc_drv_obj.state_machine_blocking = TRUE;
+
+                    state = ESTATE_ACCESS_END;
+                }
+                break;
+
+            case ESTATE_ACCESS_END:
+
+                /* clear flag */
+                if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode)
+                {
+                    mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+                    mem_write32(SD_STOP, 0x00000000U);
+                    mmc_drv_obj.during_dma_transfer = FALSE;
+                }
+
+                mem_write32(SD_INFO1_MASK, 0x00000000U);
+                mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+                mem_write32(SD_INFO1, 0x00000000U);
+                mem_write32(SD_INFO2, SD_INFO2_CLEAR);
+
+                if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U)
+                {
+                    emmc_WaitCmd2Cmd_8Cycle();
+                    state = ESTATE_END;
+                } else {
+                    state = ESTATE_ERROR;
+                }
+                break;
+
+            case ESTATE_TRANSFER_ERROR:
+                /* The error occurred in the Data transfer.  */
+                if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode)
+                {
+                    mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+                    mem_write32(SD_STOP, 0x00000000U);
+                    mmc_drv_obj.during_dma_transfer = FALSE;
+                }
+                /* fallthrough */
+
+            case ESTATE_ERROR:
+                emmc_softreset();
+                ERROR("%s:0x%x\n",__func__,rtn_code);
+                return rtn_code;
+
+            default:
+                state = ESTATE_END;
+                break;
+        } /* switch (state) */
+    } /*  while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
+
+    /* force terminate */
+    if (mmc_drv_obj.force_terminate == TRUE)
+    {
+        /* timeout timer is expired. Or, PIO data transfer error. */
+        /* Timeout occurred in the DMA transfer. */
+        if (mmc_drv_obj.during_dma_transfer == TRUE)
+        {
+            mmc_drv_obj.during_dma_transfer = FALSE;
+        }
+        emmc_softreset();
+
+        return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
+    }
+
+    /* success */
+    mmc_drv_obj.during_transfer = FALSE;
+
+    return EMMC_SUCCESS;
+}
+
+/** host controller softrest.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param None.
+ * return None.
+ */
+static void emmc_softreset(void)
+{
+    int32_t loop = 10000;
+    int32_t retry = 1000;
+
+    /* flag clear */
+    mmc_drv_obj.during_transfer = FALSE;
+    mmc_drv_obj.during_dma_transfer = FALSE;
+    mmc_drv_obj.state_machine_blocking = FALSE;
+    mmc_drv_obj.force_terminate = FALSE;
+    mmc_drv_obj.dma_error_flag = FALSE;
+
+    /* during operation ? */
+    if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)
+    {
+        /* wait CMDSEQ = 0 */
+        while (loop > 0)
+        {
+            if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U)
+            {
+                break; /* ready */
+            }
+
+            loop--;
+            if ((loop == 0) && (retry > 0))
+            {
+                micro_wait(1000U); /* wait 1ms */
+                loop = 10000;
+                retry--;
+            }
+        }
+    }
+
+    /* reset */
+    mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */
+    mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */
+
+    /* initialize */
+    mem_write32(SD_INFO1, 0x00000000U);
+    mem_write32(SD_INFO2, SD_INFO2_CLEAR);
+    mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
+    mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
+
+}
+
+/** read response
+ *
+ * - Pre-conditions:<BR>
+ * Called from emmc_exec_cmd().
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] *response Response from the card
+ * return None.
+ */
+static void emmc_read_response(uint32_t *response)
+{
+
+    uint8_t *p = NULL;
+
+    if (response == NULL)
+    {
+        return;
+    }
+
+    /* read response */
+    if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH)
+    {
+        /* CSD or CID */
+        p = (uint8_t *)(response);
+        emmc_little_to_big(p,       ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U)));    /* [127:96] */
+        emmc_little_to_big(p + 4U,  ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U)));    /* [95:64]  */
+        emmc_little_to_big(p + 8U,  ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U)));    /* [63:32]  */
+        emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U));                                      /* [31:0]   */
+    } else {
+        *response = mem_read32(SD_RSP10); /* [39:8] */
+    }
+}
+
+/** response check
+ *
+ * - Pre-conditions:<BR>
+ * Called from emmc_exec_cmd().
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in] *response Response from the card
+ * param[in] error_mask  Errors to be checked (for R1/R1b response)
+ * return error code.
+ */
+static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask)
+{
+
+    HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd)
+            & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK);
+
+    if (response == NULL)
+    {
+        return EMMC_ERR_PARAM;
+    }
+
+    if (response_type == HAL_MEMCARD_RESPONSE_NONE)
+    {
+        return EMMC_SUCCESS;
+    }
+
+    /* response check */
+    if (response_type <= HAL_MEMCARD_RESPONSE_R1b)
+    {
+        /* R1 or R1b */
+        mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT);
+        if ((*response & error_mask) != 0U)
+        {
+            return EMMC_ERR_CARD_STATUS_BIT;
+        }
+    } else if (response_type == HAL_MEMCARD_RESPONSE_R4) {
+        /* R4 */
+        if ((*response & EMMC_R4_STATUS) != 0U)
+        {
+            return EMMC_ERR_CARD_STATUS_BIT;
+        }
+    } else {
+        ; /* nothing to do. other type does not have status bit */
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/** brief converts endian from little to big
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] p destination buffer address.
+ * param[in] value convert data.(little)
+ * return None.
+ */
+static void emmc_little_to_big(uint8_t *p, uint32_t value)
+{
+    if (p == NULL)
+    {
+        return;
+    }
+
+    p[0] = (uint8_t)(value >> 24U);
+    p[1] = (uint8_t)(value >> 16U);
+    p[2] = (uint8_t)(value >> 8U);
+    p[3] = (uint8_t)value;
+}
+
+/** data transfer with DMA.
+ *
+ * - Pre-conditions:<BR>
+ * Called from emmc_exec_cmd().
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return error code.
+ */
+static void emmc_data_transfer_dma(void)
+{
+    mmc_drv_obj.during_dma_transfer = TRUE;
+    mmc_drv_obj.dma_error_flag = FALSE;
+
+    mem_write32(SD_INFO1_MASK, 0x00000000U);
+    mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
+
+    /* DMAC setting */
+    if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
+    {
+        /* transfer complete interrupt enable when write to eMMC */
+        mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE ));
+        /* When writing to eMMC, set only bit 17 to "0". */
+        mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH0_ENABLE ));
+        /* BUFF --> FIFO */
+        mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */
+    } else {
+        /* transfer complete interrupt enable when read from eMMC */
+        mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE ));
+        /* When reading from eMMC, set only bit 16 to "0". */
+        mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH1_ENABLE ));
+        /* FIFO --> BUFF */
+        mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH1(upstream), 64-bit width */
+    }
+    mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */
+
+    mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */
+}
+
+/** wait cmd-cmd 8cycle
+ *
+ * - Pre-conditions:<BR>
+ *
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return None.
+ */
+static void emmc_WaitCmd2Cmd_8Cycle(void)
+{
+    uint32_t dataL, wait = 0U;
+
+    dataL = mem_read32(SD_CLK_CTRL);
+    dataL &= 0x000000FFU;
+
+    switch (dataL)
+    {
+        case 0xFFU: /* 1/1    10 us wait  (  1/200MHz)*8=  0.04 us(min) */
+            wait = 10U;
+            break;
+        case 0x00U: /* 1/2    10 us wait  (  2/200MHz)*8=  0.08 us(min) */
+            wait = 10U;
+            break;
+        case 0x01U: /* 1/4    10 us wait  (  4/200MHz)*8=  0.16 us(min) */
+            wait = 10U;
+            break;
+        case 0x02U: /* 1/8    10 us wait  (  8/200MHz)*8=  0.32 us(min) */
+            wait = 10U;
+            break;
+        case 0x04U: /* 1/16   10 us wait  ( 16/200MHz)*8=  0.64 us(min) */
+            wait = 10U;
+            break;
+        case 0x08U: /* 1/32   10 us wait  ( 32/200MHz)*8=  1.28 us(min) */
+            wait = 10U;
+            break;
+        case 0x10U: /* 1/64   10 us wait  ( 64/200MHz)*8=  2.56 us(min) */
+            wait = 10U;
+            break;
+        case 0x20U: /* 1/128  10 us wait  (128/200MHz)*8=  5.12 us(min) */
+            wait = 10U;
+            break;
+        case 0x40U: /* 1/256  20 us wait  (256/200MHz)*8= 10.24 us(min) */
+            wait = 20U;
+            break;
+        case 0x80U: /* 1/512  30 us wait  (512/200MHz)*8= 20.48 us(min) */
+            wait = 30U;
+            break;
+        default:
+            /* nop */
+            break;
+    }
+    micro_wait(wait);
+
+}
+
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c

@@ -0,0 +1,399 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc initialize
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_init.c
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 22.03.2022 0.02     Removed CPG setting
+ *                               Added Function End comment
+ *                               Added header file inclusion
+ *         : 24.10.2022 0.03     Add CPG setting to support HS200/400
+ *         : 31.10.2022 0.04     License notation change.
+ *****************************************************************************/
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "mem_io.h"
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+#undef DUMP_EMMC_REGISTERS
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+st_mmc_base mmc_drv_obj;
+#define CX_IPL_EMMC_DATA    (0x41DFF000UL)
+#define CX_IPL_CSD_DATA     (CX_IPL_EMMC_DATA)
+#define CX_IPL_CID_DATA     (CX_IPL_CSD_DATA + EMMC_MAX_CSD_LENGTH)
+#define CX_IPL_EXT_CSD_DATA (CX_IPL_CID_DATA + EMMC_MAX_CID_LENGTH)
+volatile uint8_t *default_csd_data = (volatile uint8_t *)CX_IPL_CSD_DATA;
+volatile uint8_t *default_cid_data = (volatile uint8_t *)CX_IPL_CID_DATA;
+volatile uint8_t *default_ext_csd_data = (volatile uint8_t *)CX_IPL_EXT_CSD_DATA;
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+static void emmc_drv_init(void);
+static EMMC_ERROR_CODE emmc_dev_init(void);
+static EMMC_ERROR_CODE emmc_dev_finalize(void);
+static void emmc_memset(void *buff, uint8_t data, uint32_t cnt);
+static EMMC_ERROR_CODE emmc_reset_controller(void);
+static void emmc_driver_config(void);
+static void emmc_set_data_timeout(uint32_t data_timeout);
+
+/* ********************************* CODE ********************************** */
+
+#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE)
+static void dump_buf(const uint8_t *buf, int size)
+{
+    int i;
+    for (i = 0; i < size; i++)
+    {
+        if ((i % 16) == 0)
+        {
+            log_printf("\n%x: ", i);
+        }
+        log_printf("%b ", (uint8_t)buf[i]);
+    }
+    log_printf("\n");
+}
+#endif
+
+void dump_mmc_drv_obj(void)
+{
+#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE)
+    NOTICE("[%s:%d] size of mmc_drv_obj %d\n", __func__, __LINE__, sizeof(mmc_drv_obj));
+    NOTICE("CSD data:");
+    dump_buf(mmc_drv_obj.csd_data, sizeof(mmc_drv_obj.csd_data));
+    NOTICE("CID data:");
+    dump_buf(mmc_drv_obj.cid_data, sizeof(mmc_drv_obj.cid_data));
+    NOTICE("ext CSD data:");
+    dump_buf(mmc_drv_obj.ext_csd_data, sizeof(mmc_drv_obj.ext_csd_data));
+#endif
+}
+
+void import_mmc_drv_obj(void)
+{
+    /* Fill mmc_drv_obj with default values */
+    emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base));
+
+    for(int i=0; i < EMMC_MAX_CID_LENGTH; i++)
+    {
+        mmc_drv_obj.cid_data[i] = default_cid_data[i];
+    }
+    for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++)
+    {
+        mmc_drv_obj.csd_data[i] = default_csd_data[i];
+    }
+    for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++)
+    {
+        mmc_drv_obj.ext_csd_data[i] = default_ext_csd_data[i];
+    }
+    dump_mmc_drv_obj();
+
+    mmc_drv_obj.card_power_enable = TRUE;
+    mmc_drv_obj.clock_enable = TRUE;
+    mmc_drv_obj.initialize = TRUE;
+    mmc_drv_obj.mount = TRUE;
+    mmc_drv_obj.selected = TRUE;
+}
+
+void export_mmc_drv_obj(void)
+{
+    for(int i=0; i < EMMC_MAX_CID_LENGTH; i++)
+    {
+        *((volatile uint8_t *)&default_cid_data[i]) = mmc_drv_obj.cid_data[i];
+    }
+    for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++)
+    {
+        *((volatile uint8_t *)&default_csd_data[i]) = mmc_drv_obj.csd_data[i];
+    }
+    for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++)
+    {
+        *((volatile uint8_t *)&default_ext_csd_data[i]) = mmc_drv_obj.ext_csd_data[i];
+    }
+
+    dump_mmc_drv_obj();
+}
+
+/** brief eMMC initialize.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * retval EMMC_SUCCESS successful.
+ * retval EMMC_ERR error from interrupt API.
+ */
+EMMC_ERROR_CODE emmc_init(void)
+{
+    /* initialize H/W */
+    (void)emmc_reset_controller();
+
+    /* Configuration */
+    emmc_driver_config();
+
+    return EMMC_SUCCESS;
+}
+
+/** terminate emmc driver
+ *
+ * EMMC H/W and S/W resource is released.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return None.
+ */
+EMMC_ERROR_CODE emmc_terminate(void)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* H/W finalize */
+    result = emmc_dev_finalize();
+
+    /* driver finalize */
+    emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base));  /* clear global variable */
+
+    return result;
+}
+
+/** Function executes full reset to MMC host controller without taking power out from the memory card.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * Reset MMC host controller without taking power out from the memory card.
+ * Memory card preserves its state.
+ *
+ * return None
+ */
+static EMMC_ERROR_CODE emmc_reset_controller(void)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* initialize mmc driver */
+    emmc_drv_init();
+
+    mmc_drv_obj.base_address = MMC0_SD_BASE;
+
+    /* initialize H/W */
+    result = emmc_dev_init();
+
+    mmc_drv_obj.initialize = TRUE;
+
+    return result;
+
+}
+
+/** Configuration eMMC driver
+ *
+ * - Pre-conditions:<BR>
+ * initialized eMMC driver.
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return None
+ */
+static void emmc_driver_config(void)
+{
+    /* Read/Write data timeout */
+    emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT);
+}
+
+/** Sets data timeout
+ *
+ * Sets the data timeout value for read and write operations.
+ *
+ * - Pre-conditions:<BR>
+ * initialized eMMC driver.
+ *
+ * - Post-conditions:<BR>
+ * After this function is called, the timeout value is set according to argument.
+ *
+ * param[in] time_out The desired timeout value in milliseconds.
+ * return None
+ */
+static void emmc_set_data_timeout(uint32_t data_timeout)
+{
+    mmc_drv_obj.data_timeout = data_timeout;
+}
+
+/** eMMC driver initialize. (software)
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return None.
+ */
+static void emmc_drv_init(void)
+{
+    /* initialize */
+    emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base));
+
+    mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT;
+
+    mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
+}
+
+/** eMMC driver initialize. (H/W)
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * return None.
+ */
+static EMMC_ERROR_CODE emmc_dev_init(void)
+{
+    /* InitSdCkcr */
+    mem_write32(CPG_CPGWPR, ~(0x00000001U));
+    mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */
+
+    /* MMCIF initialize */
+    mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */
+    mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */
+    mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
+    mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
+
+    mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */
+    mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */
+    mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */
+
+    return EMMC_SUCCESS;
+}
+
+/** EMMC H/W finalize
+ *
+ * EMMC Host and Card hardware resource is released.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ *
+ * - Post-conditions:<BR>
+ * .
+ * return None.
+ */
+static EMMC_ERROR_CODE emmc_dev_finalize(void)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* MMC power off
+        * the power supply of eMMC device is always turning on.
+        * RST_n : Hi --> Low level.
+        */
+    result = emmc_memcard_power(FALSE);
+
+    mem_write32(SD_INFO1, 0x00000000U);
+    mem_write32(SD_INFO2, 0x00000800U);
+    mem_write32(DM_CM_INFO1, 0x00000000U);
+    mem_write32(DM_CM_INFO2, 0x00000000U);
+
+    mem_write32(SD_CLK_CTRL, 0x00000020U);
+    mem_write32(CC_EXT_MODE, 0x00000000U);
+    mem_write32(SD_STOP, 0x00000000U);
+    mem_write32(SD_SECCNT, 0x00000000U);
+    mem_write32(DM_CM_DTRAN_MODE, 0x00000000U);
+    mem_write32(DM_DTRAN_ADDR, 0x00000000U);
+    mem_write32(SD_OPTION, 0x00000000U);
+    mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U);
+
+    return result;
+}
+
+/** Set power to memory card IF.
+ * This function control Vcc and Vccq and RST_n.
+ *
+ * attention
+ * CPU cannot control Vcc&Vccq.
+ * The power supply of eMMC device is always turning on.
+ *
+ * param[in] mode TRUE = power on, FALSE = power off
+ *
+ * retval EMMC_SUCCESS powering succeeded
+ * retval EMMC_ERR_CARD_POWER powering failed
+ */
+EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode)
+{
+    if (mode == TRUE)
+    {
+        /* power on (Vcc&Vccq is always power on) */
+        mmc_drv_obj.card_power_enable = TRUE;
+    } else {
+        /* power off (Vcc&Vccq is always power on) */
+        mmc_drv_obj.card_power_enable = FALSE;
+        mmc_drv_obj.mount = FALSE;
+        mmc_drv_obj.selected = FALSE;
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/** memset(). no use C standard library.
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] buff pointer to buffer (virtual)
+ * param[in] data fill data.
+ * param[in] cnt fill size (number of bytes)
+ * return None.
+ */
+static void emmc_memset(void *buff, uint8_t data, uint32_t cnt)
+{
+    uint8_t *tmp = NULL;
+    tmp = (uint8_t *)buff;
+
+    if (buff == NULL)
+    {
+        return;
+    }
+
+    while (cnt > 0U)
+    {
+        *tmp = data;
+        tmp++;
+        cnt--;
+    }
+}
+
+/* ******************************** END ************************************ */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c

@@ -0,0 +1,239 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc interrupt
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_interrupt.c
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 16.06.2022 0.02     Change log output
+ *         : 31.10.2022 0.03     License notation change.
+ *         : 07.06.2024 0.04     Modify the transfer end bit of DMAC channel.
+ *****************************************************************************/
+
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "log.h"
+#include "mem_io.h"
+#include <stdint.h>
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual);
+
+
+/* ********************************* CODE ********************************** */
+
+
+
+/** emmc driver interrupt service routine.
+ *
+ * - Pre-conditions:<BR>
+ * Must be block emmc driver state machine.
+ * - Post-conditions:<BR>
+ * unblocking emmc driver state machine.
+ *
+ * retval INT_SUCCESS
+ */
+uint32_t emmc_interrupt(void)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* SD_INFO */
+    mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1);
+    mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2);
+
+    /* SD_INFO EVENT */
+    mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK);
+    mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK);
+
+    /* ERR_STS */
+    mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1);
+    mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2);
+
+    /* DM_CM_INFO */
+    mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1);
+    mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2);
+
+    /* DM_CM_INFO EVENT */
+    mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK);
+    mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK);
+
+    /* ERR SD_INFO2 */
+    if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U)
+    {
+        mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */
+        mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */
+        mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */
+        mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */
+        mmc_drv_obj.state_machine_blocking = FALSE;
+    }
+
+    /* PIO Transfer */
+    /* BWE/BRE */
+    else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) {
+        /* BWE */
+        if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U)
+        {
+            mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */
+        }
+        /* BRE */
+        else {
+            mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */
+        }
+
+        result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */
+        mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH;
+        mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH;
+
+        if (result != EMMC_SUCCESS)
+        {
+            /* data transfer error */
+            ERROR("%s:0x%x\n",__func__, result);
+
+            /* Panic */
+            mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */
+            mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */
+            mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */
+            mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */
+            mmc_drv_obj.force_terminate = TRUE;
+        } else {
+            mmc_drv_obj.during_transfer = FALSE;
+        }
+        mmc_drv_obj.state_machine_blocking = FALSE;
+    }
+
+    /* DMA_TRANSFER */
+    /* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */
+    else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) {
+        mem_write32(DM_CM_INFO1, 0x00000000U);
+        mem_write32(DM_CM_INFO2, 0x00000000U);
+        mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */
+        /* DM_CM_INFO2:  DMA-ch0 error occured */
+        if (( DM_CM_INFO2_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U)
+        {
+            mmc_drv_obj.dma_error_flag = TRUE;
+        } else {
+            mmc_drv_obj.during_dma_transfer = FALSE;
+            mmc_drv_obj.during_transfer = FALSE;
+        }
+        mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */
+    }
+    /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+    else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) {
+        mem_write32(DM_CM_INFO1, 0x00000000U);
+        mem_write32(DM_CM_INFO2, 0x00000000U);
+        mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */
+        /* DM_CM_INFO2: DMA-ch1 error occured */
+        if (( DM_CM_INFO2_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U)
+        {
+            mmc_drv_obj.dma_error_flag = TRUE;
+        } else {
+            mmc_drv_obj.during_dma_transfer = FALSE;
+            mmc_drv_obj.during_transfer = FALSE;
+        }
+        mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */
+    }
+
+    /* Response end  */
+    else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) {
+        mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */
+        mmc_drv_obj.state_machine_blocking = FALSE;
+    }
+    /* Access end  */
+    else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) {
+        mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */
+        mmc_drv_obj.state_machine_blocking = FALSE;
+    } else {
+        /* nothing to do. */
+    }
+
+    return 0U;
+}
+
+/** Data transfer function with PIO (Single sector).
+ *
+ * - Pre-conditions:<BR>
+ * Called from interrupt service.
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] buff_address_virtual Dest/Src buffer address(virtual).
+ * retval EMMC_SUCCESS successful.
+ * retval EMMC_ERR_PARAM parameter error.
+ * retval EMMC_ERR_STATE state error.
+ */
+static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual)
+{
+    uint32_t length, i;
+    uint64_t *bufPtrLL;
+
+    if (buff_address_virtual == NULL)
+    {
+        return EMMC_ERR_PARAM;
+    }
+
+    if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U))
+    {
+        return EMMC_ERR_STATE;
+    }
+
+    bufPtrLL = (uint64_t*)buff_address_virtual;
+    length = mmc_drv_obj.remain_size;
+
+    /* data transefer */
+    for (i = 0U; i < (length >> 3U); i++)
+    {
+        /* Write */
+        if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
+        {
+            mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */
+        }
+        /* Read */
+        else {
+            *bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */
+        }
+        bufPtrLL++;
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c

@@ -0,0 +1,94 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc multi boot
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc multiboot.c
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_def.h"
+#include "emmc_multiboot.h"
+#include "types.h"
+
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+uint32_t emmc_check_result(uint32_t result);
+
+/* ********************************* CODE ********************************** */
+
+
+uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize)
+{
+    EMMC_ERROR_CODE result;
+    uint32_t rtn_val = EMMC_DEV_ERR;
+
+    /* Partition select */
+    result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition);
+
+    if (result == EMMC_SUCCESS)
+    {
+        result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE);
+    }
+
+    /* EMMC_ERROR_CODE -> ROM_XX */
+    rtn_val = emmc_check_result((uint32_t)result);
+
+    return rtn_val;
+}
+uint32_t emmc_check_result(uint32_t result)
+{
+    uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION;
+
+    if (result == EMMC_SUCCESS)
+    {
+        ret = EMMC_DEV_OK;
+    } else if (result == EMMC_ERR) {
+        ret = EMMC_DEV_ERR;
+    } else { /* other */
+        ret = EMMC_DEV_ERR_HW;
+    }
+
+    return ret;
+}
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c

@@ -0,0 +1,216 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc read
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_read.c
+ * - Version      : 0.04
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 23.03.2022 0.02     Added header file inclusion
+ *         : 16.06.2022 0.03     Change log output
+ *         : 31.10.2022 0.04     License notation change.
+ *****************************************************************************/
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "log.h"
+#include "mem_io.h"
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+#define EMMC_RW_SECTOR_COUNT_MAX        0x0000ffffUL
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
+
+static inline uint32_t get_min_value(uint32_t a, uint32_t b)
+{
+    uint32_t ret = a;
+
+    if(b < a)
+    {
+        ret = b;
+    }
+
+    return ret;
+}
+
+/* ********************************* CODE ********************************** */
+
+/** function of read sector
+ *
+ * This function always use block read.
+ * Single block read is not used.
+ *
+ * - Pre-conditions:<BR>
+ * MMC card is mounted.
+ *
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] buff_address_virtual  virtual address of read data buffer.
+ * param[in] sector_number data address for MMC device (sector number).
+ * param[in] count number of sector.
+ * param[in] transfermode Mode of data transfer, DMA or not DMA.
+ */
+EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count,
+        uint32_t feature_flags)
+{
+    uint32_t trans_count;
+    uint32_t remain;
+    EMMC_ERROR_CODE result = EMMC_ERR;
+    HAL_MEMCARD_DATA_TRANSFER_MODE transfermode;
+
+    /* parameter check */
+    if (count == 0U)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
+        return EMMC_ERR_PARAM;
+    }
+
+    /* state check */
+    if (mmc_drv_obj.mount != TRUE)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE);
+        return EMMC_ERR_STATE;
+    }
+
+    /* DMA? */
+    if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U)
+    {
+        transfermode = HAL_MEMCARD_DMA;
+    } else {
+        transfermode = HAL_MEMCARD_NOT_DMA;
+    }
+
+    remain = count;
+    while (remain != 0U)
+    {
+        trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX);
+        result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode);
+        if (result != EMMC_SUCCESS)
+        {
+            return result;
+        }
+
+        buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count);
+        sector_number += trans_count;
+        remain -= trans_count;
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/** multiple block read
+ *
+ * Multiple block read with pre-defined block count.
+ *
+ * - Pre-conditions:<BR>
+ * MMC card is mounted.
+ *
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in,out] buff_address_virtual  virtual address of read data buffer.
+ * param[in] sector_number data address for MMC device (sector number).
+ * param[in] count number of sector. (0x1 - 0xffff)
+ * param[in] transfer_mode Mode of data transfer, DMA or not DMA.
+ */
+static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count,
+        HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* parameter check */
+    if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U)
+            || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA)))
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
+        return EMMC_ERR_PARAM;
+    }
+
+    /* CMD23 */
+    emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count);
+    result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+    if (result != EMMC_SUCCESS)
+    {
+        return result;
+    }
+    mem_write32(SD_SECCNT, count);
+    mem_write32(SD_STOP, 0x00000100U);
+    mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */
+
+    /* CMD18 */
+    emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT,
+            HAL_MEMCARD_READ, transfer_mode);
+    result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+    if (result != EMMC_SUCCESS)
+    {
+        return result; /* CMD18 error code */
+    }
+
+    /* CMD13 */
+    emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U);
+    result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+    if (result != EMMC_SUCCESS)
+    {
+        return result;
+    }
+
+    /* ready status check */
+    if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY);
+        return EMMC_ERR_CARD_BUSY;
+    }
+
+    /* state check */
+    if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN)
+    {
+        ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_STATE);
+        return EMMC_ERR_CARD_STATE;
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c

@@ -0,0 +1,305 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : emmc utility
+ ******************************************************************************/
+/******************************************************************************
+ * @file          emmc_utility
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+#define BUSY_SIGNAL (1U << 10U)
+
+static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] = 
+{
+        0x00000000U, /* CMD0 */
+        0x00000701U, /* CMD1 */
+        0x00000002U, /* CMD2 */
+        0x00000003U, /* CMD3 */
+        0x00000004U, /* CMD4 */
+        0x00000505U, /* CMD5 */
+        0x00000406U, /* CMD6 */
+        0x00000007U, /* CMD7 */
+        0x00001C08U, /* CMD8 */
+        0x00000009U, /* CMD9 */
+        0x0000000AU, /* CMD10 */
+        0x00000000U, /* reserved */
+        0x0000000CU, /* CMD12 */
+        0x0000000DU, /* CMD13 */
+        0x00001C0EU, /* CMD14 */
+        0x0000000FU, /* CMD15 */
+        0x00000010U, /* CMD16 */
+        0x00000011U, /* CMD17 */
+        0x00007C12U, /* CMD18 */
+        0x00000C13U, /* CMD19 */
+        0x00000000U,
+        0x00001C15U, /* CMD21 */
+        0x00000000U,
+        0x00000017U, /* CMD23 */
+        0x00000018U, /* CMD24 */
+        0x00006C19U, /* CMD25 */
+        0x00000C1AU, /* CMD26 */
+        0x0000001BU, /* CMD27 */
+        0x0000001CU, /* CMD28 */
+        0x0000001DU, /* CMD29 */
+        0x0000001EU, /* CMD30 */
+        0x00001C1FU, /* CMD31 */
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000423U, /* CMD35 */
+        0x00000424U, /* CMD36 */
+        0x00000000U,
+        0x00000026U, /* CMD38 */
+        0x00000427U, /* CMD39 */
+        0x00000428U, /* CMD40 : send cmd */
+        0x00000000U,
+        0x0000002AU, /* CMD42 */
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000C31U,
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00007C35U,
+        0x00006C36U,
+        0x00000037U, /* CMD55 */
+        0x00000038U, /* CMD56 : Read */
+        0x00000000U,
+        0x00000000U,
+        0x00000000U,
+        0x00000000U
+};
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+/** make non-transfer command data
+ *
+ * Response data buffer is automatically selected.
+ *
+ * - Pre-conditions:<BR>
+ * Clock to memory card IF is enabled.
+ *
+ * - Post-conditions:<BR>
+ * After this function is called, command can be executed.
+ *
+ * param[in] cmd command information.
+ * param[in] arg command argument
+ * return None.
+ */
+void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg)
+{
+    /* command information */
+    mmc_drv_obj.cmd_info.cmd = cmd;
+    mmc_drv_obj.cmd_info.arg = arg;
+    mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ;
+    mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK];
+
+    /* clear data transfer information */
+    mmc_drv_obj.trans_size = 0U;
+    mmc_drv_obj.remain_size = 0U;
+    mmc_drv_obj.buff_address_virtual = NULL;
+    mmc_drv_obj.buff_address_physical = NULL;
+
+    /* response information */
+    mmc_drv_obj.response_length = 6U;
+
+    switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK))
+    {
+        case HAL_MEMCARD_RESPONSE_NONE:
+            mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
+            mmc_drv_obj.response_length = 0U;
+            break;
+        case HAL_MEMCARD_RESPONSE_R1:
+            mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
+            break;
+        case HAL_MEMCARD_RESPONSE_R1b:
+            mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */
+            mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
+            break;
+        case HAL_MEMCARD_RESPONSE_R2:
+            mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
+            mmc_drv_obj.response_length = 17U;
+            break;
+        case HAL_MEMCARD_RESPONSE_R3:
+            mmc_drv_obj.response = &mmc_drv_obj.r3_ocr;
+            break;
+        case HAL_MEMCARD_RESPONSE_R4:
+            mmc_drv_obj.response = &mmc_drv_obj.r4_resp;
+            break;
+        case HAL_MEMCARD_RESPONSE_R5:
+            mmc_drv_obj.response = &mmc_drv_obj.r5_resp;
+            break;
+        default:
+            mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
+            break;
+    }
+}
+
+/** Making command information for data transfer command.
+ *
+ * - Pre-conditions:<BR>
+ * None.
+ *
+ * - Post-conditions:<BR>
+ * After this function is called, command can be executed.
+ *
+ * param[in] cmd command
+ * param[in] arg command argument
+ * param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address)
+ *            Client is responsible of allocation and deallocation of the buffer.
+ * param[in] len transfer length in bytes
+ * param[in] dir direction
+ * param[in] transfer_mode Mode of data transfer, DMA or not DMA.
+ * return None.
+ */
+void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */
+uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
+{
+    emmc_make_nontrans_cmd(cmd, arg); /* update common information */
+
+    /* for data transfer command */
+    mmc_drv_obj.cmd_info.dir = dir;
+    mmc_drv_obj.buff_address_virtual = buff_address_virtual;
+    mmc_drv_obj.buff_address_physical = buff_address_virtual;
+    mmc_drv_obj.trans_size = len;
+    mmc_drv_obj.remain_size = len;
+    mmc_drv_obj.transfer_mode = transfer_mode;
+}
+
+/** Send idle command.
+ * Function execute CMD0.
+ *
+ * - Pre-conditions:<BR>
+ * Clock to MMC I/F enabled.
+ *
+ * - Post-conditions:<BR>
+ * Card reset to idle or pre-idle state.
+ *
+ * param[in] arg CMD0 argument.
+ * return error code
+ */
+EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg)
+{
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    /* initialize state */
+    mmc_drv_obj.mount = FALSE;
+    mmc_drv_obj.selected = FALSE;
+    mmc_drv_obj.during_transfer = FALSE;
+    mmc_drv_obj.during_dma_transfer = FALSE;
+    mmc_drv_obj.dma_error_flag = FALSE;
+    mmc_drv_obj.force_terminate = FALSE;
+    mmc_drv_obj.state_machine_blocking = FALSE;
+
+    mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
+    mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */
+    mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE;
+
+    /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */
+    emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */
+    result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+    if (result != EMMC_SUCCESS)
+    {
+        return result;
+    }
+
+    /* change MMC clock(400KHz) */
+    mmc_drv_obj.set_freq = MMC_400KHZ;
+    result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq);
+    if (result != EMMC_SUCCESS)
+    {
+        return result;
+    }
+
+    return EMMC_SUCCESS;
+}
+
+/** get bit field data for 16bytes data(CSD register).
+ *
+ * - Pre-conditions:<BR>
+ * .
+ * - Post-conditions:<BR>
+ * .
+ *
+ * param[in] data  16bytes data.
+ * param[in] top bit number(top). 128>top
+ * param[in] bottom bit number(bottom). (0<=bottom<=top)
+ * return bit field.
+ */
+uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom)
+{
+    uint32_t value;
+
+    uint32_t index_top = (uint32_t)(15U - (top >> 3U));
+    uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U));
+
+    if (index_top == index_bottom)
+    {
+        value = data[index_top];
+    } else if ((index_top + 1U) == index_bottom) {
+        value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]);
+    } else if ((index_top + 2U) == index_bottom) {
+        value = (uint32_t)(
+                ((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]);
+    } else {
+        value = (uint32_t)(
+                ((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U)
+                        | ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]);
+    }
+
+    value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U));
+
+    return value;
+}
+
+/* ******************************** END ************************************ */
+

IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c

@@ -0,0 +1,102 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : INTC handler function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          interrupt.c
+ * - Version      : 0.05
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.08.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *         : 15.12.2022 0.03     V4H interrupt support.
+ *         : 27.12.2022 0.04     Change argument of pabort_error.
+ *         : 21.08.2023 0.05     Add support for V4M.
+ *****************************************************************************/
+#include "ip_control.h"
+#include "log.h"
+#include "gic.h"
+#include "swdt.h"
+#include "interrupt.h"
+
+#if (RCAR_LSI == RCAR_S4)
+void handler_fiq(void)
+{
+    uint32_t intid = GIC_AcknowledgePending();
+    if (intid == INTC_SPI_SWDT)
+    {
+        swdt_exec();
+    }
+    else
+    {
+        ERROR("Invalid interrupt occurred.(%d)\n",intid);
+        panic;
+    }
+}
+/* End of function handler_fiq(void) */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar)
+{
+
+    ERROR("Data abort.\n");
+    ERROR("     Data abort occurrred address : 0x%x\n", occ_add);
+    ERROR("     DFSR:0x%x DFAR:0x%x\n", dfsr, dfar);
+    panic;
+
+}
+/* End of function dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfare) */
+
+void pabort_error(uint32_t ifsr, uint32_t ifar)
+{
+
+    ERROR("Prefetch abort.\n");
+    ERROR("     IFSR:0x%x IFAR:0x%x\n", ifsr, ifar);
+    panic;
+}
+/* End of function pabort_error(uint32_t ifsr, uint32_t ifar) */
+
+void Undefined_error(uint32_t occ_add)
+{
+
+    ERROR("Undefined Instruction.\n");
+    ERROR("     Undefined Instruction occurrred address : 0x%x\n", occ_add);
+    panic;
+}
+/* End of function Undefined_error(uint32_t occ_add) */
+#endif /* RCAR_LSI == RCAR_S4 */
+
+void handler_error(uint32_t ex_type)
+{
+
+    ERROR("Unhandled exception occurred.\n");
+    ERROR("     Exception type = 0x%x.\n", ex_type);
+    panic;
+}
+/* End of function handler_error(uint32_t ex_type) */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c

@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : IP's control function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          ip_control.c
+ * - Version      : 0.08
+ * @brief         Initial setting controller.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 30.11.2021 0.01     First Release
+ *         : 18.01.2022 0.02     Changed log output
+ *                               Supported Generic Timer
+ *         : 22.03.2022 0.03     Removed unnecessary header file inclusions
+ *                               Removed unnecessary functions
+ *         : 10.05.2022 0.04     Added function return value judgment
+ *         : 16.06.2022 0.05     Change log output
+ *         : 02.08.2022 0.06     Added SWDT and GIC
+ *         : 31.10.2022 0.07     License notation change.
+ *         : 04.09.2023 0.08     Add C4 power domain setting.
+ *         : 13.10.2023 0.09     Moved C4 power domain setting to ICUMX IPL.
+ *****************************************************************************/
+#include <scif.h>
+#include <ip_control.h>
+#include <emmc_boot.h>
+#include <emmc_def.h>
+#include <timer.h>
+#include <log.h>
+#include "gic.h"
+#include "swdt.h"
+#if (1 == (MEASURE_TIME))
+	#include <scmt.h>
+	#include <scmt_checkpoint.h>
+#else
+  #define scmt_wait_ticks(x)
+  #define store_time_checkpoint(x,y)
+#endif
+
+void ip_init(void)
+{
+    scif_init();
+    generic_timer_init();
+
+#if (RCAR_LSI == RCAR_S4)
+    Interrupt_Config();
+    Interrupt_Enable(INTC_SPI_SWDT);
+    swdt_init();
+#endif /* RCAR_LSI == RCAR_S4 */
+#ifndef MOBIS_PRK3
+    emmc_initialize();
+    store_time_checkpoint("emmc_initialize", 0);
+#endif
+}
+/* End of function ip_init(void) */
+
+void ip_release(void)
+{
+#if (BL2_LOAD_ENABLE == BL2_DISABLE)
+    EMMC_ERROR_CODE result = EMMC_ERR;
+
+    result = emmc_terminate();
+    if(EMMC_SUCCESS != result)
+    {
+        ERROR("ip_release error (emmc_terminate).\n");
+        panic;
+    }
+#endif
+
+#if (RCAR_LSI == RCAR_S4)
+    swdt_release();
+    Interrupt_Disable(INTC_SPI_SWDT);
+#endif /* RCAR_LSI == RCAR_S4 */
+}
+/* End of function ip_release(void) */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c

@@ -0,0 +1,553 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : QoS initialize function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          qos.c
+ * - Version      : 0.14
+ * @brief         Initial setting process of QoS.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 28.07.2021 0.01     First Release
+ *         : 23.05.2022 0.02     Integration of S4 and V4H
+ *                               Update QoS setting rev.0.02 (for S4)
+ *                               Update QoS setting rev.0.03 (for V4H)
+ *         : 20.01.2023 0.03     Add DBSC W/A 1,2,3 (OTLINT-5579)
+ *         : 19.04.2023 0.04     Update the setting version from v6.1 to v7.0(for V4H).
+ *         : 22.05.2023 0.05     Update the setting version from v7.0 to v7.1.1(for V4H).
+ *         : 22.05.2023 0.06     Update the setting version from v7.1.1 to v8.0.0(for V4H).
+ *         : 08.06.2023 0.07     Update the setting version from v8.0.0 to v8.0.1(for V4H).
+ *         : 15.06.2023 0.08     Update the setting version from v8.0.1 to v8.0.2(for V4H).
+ *         : 21.08.2023 0.09     Add support for V4M.
+ *         : 20.09.2023 0.10     Update the setting version from v9.0.1 to v10.0.0(for V4M).
+ *         : 20.09.2023 0.11     Update the setting version from v10.0.0 to v10.1.0(for V4H).
+ *         : 11.10.2023 0.12     Update the setting version from v10.1.0 to v10.2.1(for V4H/V4M).
+ *         : 17.01.2024 0.13     Update the setting version from v10.1.0 to v11.0.0(for V4H/V4M).
+ *         : 05.04.2024 0.14     Update the setting version from v11.0.0 to v12.0.0(for V4H/V4M).
+ *****************************************************************************/
+
+#include <stdint.h>
+#if defined(__RH850G3K__)
+#include <log.h>
+#include <remap_register.h>
+#include <remap.h>
+#else
+#include <log.h>
+#include <rcar_register.h>
+#endif
+#include <qos.h>
+#include <mem_io.h>
+#include <cnf_tbl.h>
+#include <rcar_def.h>
+
+#if (RCAR_LSI == RCAR_S4)
+#define RCAR_QOS_VERSION    "base_v6.1"
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define RCAR_QOS_VERSION    "v12.0.0"
+#endif /* RCAR_LSI == RCAR_S4 */
+
+#define RCAR_DRAM_SPLIT_DISABLE     (0U)
+#define RCAR_DRAM_SPLIT_ENABLE      (1U)
+#define RCAR_REWT_TRAINING_DISABLE  (0U)
+#define RCAR_REWT_TRAINING_ENABLE   (1U)
+
+#if defined(__RH850G3K__)
+#define AXMM_BASE           (BASE_AXMM_ADDR)
+#else
+#define AXMM_BASE           (0xE6780000U)
+#endif
+#define AXMM_MMCR           (AXMM_BASE + 0x4300U)
+#define AXMM_ADSPLCR0       (AXMM_BASE + 0x4008U)
+#define AXMM_ADSPLCR1       (AXMM_BASE + 0x400CU)
+#define AXMM_ADSPLCR2       (AXMM_BASE + 0x4010U)
+#define AXMM_ADSPLCR3       (AXMM_BASE + 0x4014U)
+#define AXMM_TR3CR          (AXMM_BASE + 0x5100CU)
+
+#if (RCAR_LSI == RCAR_S4)
+#if defined(__RH850G3K__)
+#define DBSC_BASE           (BASE_DBSC_ADDR)
+#else
+#define DBSC_BASE           (0xE6790000U)
+#endif
+
+#define DBSC_CH_NUM           (1U)    /* Number of DBSCx */
+#define DBSC_A_CH_OFFSET      (0U)    /* 1ch only (for S4)*/
+#define DBSC_D_CH_OFFSET      (0U)    /* 1ch only (for S4)*/
+
+#define DBSC_SYSCNT0        (DBSC_BASE + 0x0100U)
+#define DBSC_SYSCNT0A       (DBSC_BASE + 0x0108U)
+#define DBSC_DBBUS0CNF2     (DBSC_BASE + 0x0808U)
+#define DBSC_DBCAM0CNF1     (DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2     (DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3     (DBSC_BASE + 0x090CU)
+#define DBSC_DBCAMDIS       (DBSC_BASE + 0x09FCU)
+#define DBSC_DBSCHCNT0      (DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHSZ0       (DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0       (DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHQOS_0_0   (DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS_0_1   (DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS_0_2   (DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS_0_3   (DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS_4_0   (DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS_4_1   (DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS_4_2   (DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS_4_3   (DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS_9_0   (DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS_9_1   (DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS_9_2   (DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS_9_3   (DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS_12_0  (DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS_12_1  (DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS_12_2  (DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS_12_3  (DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS_13_0  (DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_13_1  (DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_13_2  (DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_13_3  (DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_14_0  (DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS_14_1  (DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS_14_2  (DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS_14_3  (DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS_15_0  (DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS_15_1  (DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS_15_2  (DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS_15_3  (DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST2       (DBSC_BASE + 0x170CU)
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#if defined(__RH850G3K__)
+#define DBSC_D_BASE         (BASE_DBSC_ADDR + 0x14000U)
+#define DBSC_A_BASE         (BASE_DBSC_ADDR)
+#else
+#define DBSC_D_BASE         (0xE67A4000U)
+#define DBSC_A_BASE         (0xE6790000U)
+#endif
+
+#if (RCAR_LSI == RCAR_V4H)
+#define DBSC_CH_NUM         (2U)    /* ch number of DBSCx */
+#elif (RCAR_LSI == RCAR_V4M)
+#define DBSC_CH_NUM         (1U)    /* ch number of DBSCx */
+#endif
+
+#define DBSC_A_CH_OFFSET    (0x8000U)
+#define DBSC_D_CH_OFFSET    (0x4000U)
+
+#define DBSC_SYSCNT0        (DBSC_D_BASE + 0x0100U)
+#define DBSC_SYSCNT1        (DBSC_A_BASE + 0x0104U)
+#define DBSC_SYSCNT0A       (DBSC_A_BASE + 0x0100U)
+#define DBSC_DBBUS0CNF2     (DBSC_A_BASE + 0x0808U)
+#define DBSC_DBCAM0CNF1     (DBSC_A_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2     (DBSC_A_BASE + 0x0908U)
+#define DBSC_DBCAMDIS       (DBSC_A_BASE + 0x09FCU)
+#define DBSC_DBCAM0CNF3     (DBSC_A_BASE + 0x090CU)
+#define DBSC_DBSCHCNT0      (DBSC_A_BASE + 0x1000U)
+#define DBSC_DBSCHSZ0       (DBSC_A_BASE + 0x1010U)
+#define DBSC_DBSCHRW0       (DBSC_A_BASE + 0x1020U)
+#define DBSC_DBSCHQOS_0_0   (DBSC_A_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_0_1   (DBSC_A_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_0_2   (DBSC_A_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_0_3   (DBSC_A_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_4_0   (DBSC_A_BASE + 0x1140U)
+#define DBSC_DBSCHQOS_4_1   (DBSC_A_BASE + 0x1144U)
+#define DBSC_DBSCHQOS_4_2   (DBSC_A_BASE + 0x1148U)
+#define DBSC_DBSCHQOS_4_3   (DBSC_A_BASE + 0x114CU)
+#define DBSC_DBSCHQOS_9_0   (DBSC_A_BASE + 0x1190U)
+#define DBSC_DBSCHQOS_9_1   (DBSC_A_BASE + 0x1194U)
+#define DBSC_DBSCHQOS_9_2   (DBSC_A_BASE + 0x1198U)
+#define DBSC_DBSCHQOS_9_3   (DBSC_A_BASE + 0x119CU)
+#define DBSC_DBSCHQOS_12_0  (DBSC_A_BASE + 0x11C0U)
+#define DBSC_DBSCHQOS_12_1  (DBSC_A_BASE + 0x11C4U)
+#define DBSC_DBSCHQOS_12_2  (DBSC_A_BASE + 0x11C8U)
+#define DBSC_DBSCHQOS_12_3  (DBSC_A_BASE + 0x11CCU)
+#define DBSC_DBSCHQOS_13_0  (DBSC_A_BASE + 0x11D0U)
+#define DBSC_DBSCHQOS_13_1  (DBSC_A_BASE + 0x11D4U)
+#define DBSC_DBSCHQOS_13_2  (DBSC_A_BASE + 0x11D8U)
+#define DBSC_DBSCHQOS_13_3  (DBSC_A_BASE + 0x11DCU)
+#define DBSC_DBSCHQOS_14_0  (DBSC_A_BASE + 0x11E0U)
+#define DBSC_DBSCHQOS_14_1  (DBSC_A_BASE + 0x11E4U)
+#define DBSC_DBSCHQOS_14_2  (DBSC_A_BASE + 0x11E8U)
+#define DBSC_DBSCHQOS_14_3  (DBSC_A_BASE + 0x11ECU)
+#define DBSC_DBSCHQOS_15_0  (DBSC_A_BASE + 0x11F0U)
+#define DBSC_DBSCHQOS_15_1  (DBSC_A_BASE + 0x11F4U)
+#define DBSC_DBSCHQOS_15_2  (DBSC_A_BASE + 0x11F8U)
+#define DBSC_DBSCHQOS_15_3  (DBSC_A_BASE + 0x11FCU)
+#define DBSC_SCFCTST2       (DBSC_A_BASE + 0x1048U)
+
+#define AXMM_TR0CR0         (AXMM_BASE + 0x51000U)
+#define AXMM_TR1CR0         (AXMM_BASE + 0x51004U)
+#define AXMM_TR2CR0         (AXMM_BASE + 0x51008U)
+#define AXMM_TR3CR0         (AXMM_BASE + 0x5100CU)
+#define AXMM_TR0CR1         (AXMM_BASE + 0x51100U)
+#define AXMM_TR1CR1         (AXMM_BASE + 0x51104U)
+#define AXMM_TR2CR1         (AXMM_BASE + 0x51108U)
+#define AXMM_TR3CR1         (AXMM_BASE + 0x5110CU)
+#define AXMM_TR0CR2         (AXMM_BASE + 0x51200U)
+#define AXMM_TR1CR2         (AXMM_BASE + 0x51204U)
+#define AXMM_TR2CR2         (AXMM_BASE + 0x51208U)
+#define AXMM_TR3CR2         (AXMM_BASE + 0x5120CU)
+#define DBSC_FCPRSCTRL      (DBSC_A_BASE + 0x0110U)
+#define ACTEXT_RT0_R        (0xFFC50800U)
+#define ACTEXT_RT0_W        (0xFFC51800U)
+#define ACTEXT_IR0_R        (0xFF890800U)
+#define ACTEXT_IR0_W        (0xFF891800U)
+#define ACTEXT_IR1_R        (0xFF892800U)
+#define ACTEXT_IR1_W        (0xFF893800U)
+#define SI0_RW_MAX          (0xF1201110U)
+#define SI1_RW_MAX          (0xF1202110U)
+#endif /* RCAR_LSI == RCAR_S4 */
+
+#if defined(__RH850G3K__)
+#define QOS_BASE            (BASE_QOS_ADDR)
+#else
+#define QOS_BASE            (0xE67E0000U)
+#endif
+#define QOS_FIX_QOS_BANK0   (QOS_BASE + 0x00000000U)
+#define QOS_FIX_QOS_BANK1   (QOS_BASE + 0x00001000U)
+#define QOS_BE_QOS_BANK0    (QOS_BASE + 0x00002000U)
+#define QOS_BE_QOS_BANK1    (QOS_BASE + 0x00003000U)
+#define QOS_SL_INIT         (QOS_BASE + 0x00008000U)
+#define QOS_REF_ARS         (QOS_BASE + 0x00008004U)
+#define QOS_STATQC          (QOS_BASE + 0x00008008U)
+#define QOS_REF_ENBL        (QOS_BASE + 0x00008044U)
+#define QOS_BWG             (QOS_BASE + 0x0000804CU)
+#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
+#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U)
+#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U)
+#define QOSWT_BE_QOS_BANK0  (QOS_BASE + 0x00002800U)
+#define QOSWT_BE_QOS_BANK1  (QOS_BASE + 0x00003800U)
+#define QOSWT_WTEN          (QOS_BASE + 0x00008030U)
+#define QOSWT_WTREF         (QOS_BASE + 0x00008034U)
+#define QOSWT_WTSET0        (QOS_BASE + 0x00008038U)
+#define QOSWT_WTSET1        (QOS_BASE + 0x0000803CU)
+#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#define QOS_RAS             (QOS_BASE + 0x00010000U)
+#define QOS_RAEN            (QOS_BASE + 0x00010018U)
+#define QOS_DANN_LOW        (QOS_BASE + 0x00010030U)
+#define QOS_DANN_HIGH       (QOS_BASE + 0x00010034U)
+#define QOS_DANT            (QOS_BASE + 0x00010038U)
+#define QOS_EMS_LOW         (QOS_BASE + 0x00010040U)
+#define QOS_EMS_HIGH        (QOS_BASE + 0x00010044U)
+#define QOS_FSS             (QOS_BASE + 0x00010048U)
+#define QOS_INSFC           (QOS_BASE + 0x00010050U)
+#define QOS_EARLYR          (QOS_BASE + 0x00010060U)
+#define QOS_RACNT0          (QOS_BASE + 0x00010080U)
+#define QOS_STATGEN0        (QOS_BASE + 0x00010088U)
+
+#define CCI_BASE            (BASE_CCI_ADDR)
+#define CCIQOS00            (CCI_BASE + 0xC020U)
+#define CCIQOS01            (CCI_BASE + 0xC024U)
+#define CCIQOS10            (CCI_BASE + 0xD000U)
+#define CCIQOS11            (CCI_BASE + 0xD004U)
+#if (RCAR_LSI == RCAR_S4)
+#define CCIQOS12            (CCI_BASE + 0xD008U)
+#define CCIQOS13            (CCI_BASE + 0xD00CU)
+#endif
+
+static void dbsc_setting(void)
+{
+    for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++)
+    {
+        /* DBSC CAM, Scheduling Setting */
+        mem_write32((DBSC_SYSCNT0       + (DBSC_D_CH_OFFSET * loop)), 0x00001234U);
+        mem_write32((DBSC_SYSCNT0A      + (DBSC_A_CH_OFFSET * loop)), 0x00001234U);
+        mem_write32((DBSC_DBCAM0CNF1    + (DBSC_A_CH_OFFSET * loop)), 0x00048218U);   /* dbcam0cnf1 */
+#if ((ECC_ENABLE == 1) && (RCAR_LSI == RCAR_V4H))
+    /* For WA for DBSC5 Hang5 issue. */
+    if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
+    {
+        mem_write32((DBSC_DBCAM0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x000002C4U);   /* dbcam0cnf2 */
+    }
+    else
+    {
+        mem_write32((DBSC_DBCAM0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U);   /* dbcam0cnf2 */
+    }
+#elif (RCAR_LSI == RCAR_V4M)
+    mem_write32((DBSC_DBCAM0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U);   /* dbcam0cnf2 */
+#else
+        mem_write32((DBSC_DBCAM0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U);   /* dbcam0cnf2 */
+#endif
+        mem_write32((DBSC_DBCAM0CNF3    + (DBSC_A_CH_OFFSET * loop)), 0x00000003U);   /* dbcam0cnf3 */
+
+#if (RCAR_LSI == RCAR_S4)
+    #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1))
+        mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000002U);   /* OTLINT-5579: V4H DBSC W/A-1,2 */
+    #else
+        mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000000U);
+    #endif
+#elif (RCAR_LSI == RCAR_V4H)
+    #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1))
+        if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
+        {
+            mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000013U);   /* OTLINT-5579: V4H DBSC W/A-1,2,3 */
+        }
+        else if((mem_read32(PRR) & PRR_CUT_MASK) == PRR_PRODUCT_22)
+        {
+            mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000012U);
+        }
+        else
+        {
+            mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
+        }
+    #elif ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 0))
+        if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
+        {
+            mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000011U);   /* OTLINT-5579: V4H DBSC W/A-3 */
+        }
+        else
+        {
+            mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
+        }
+    #else
+        mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
+    #endif
+#elif (RCAR_LSI == RCAR_V4M)
+    # if (ECC_ENABLE == 1)
+        mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000012U);
+    #else
+        mem_write32((DBSC_DBCAMDIS      + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
+    # endif
+#endif
+
+        mem_write32((DBSC_DBSCHCNT0     + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U);   /* dbschcnt0 */
+        mem_write32((DBSC_DBSCHSZ0      + (DBSC_A_CH_OFFSET * loop)), 0x00000001U);   /* dbschsz0 */
+        mem_write32((DBSC_DBSCHRW0      + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U);   /* dbschrw0 */
+        mem_write32((DBSC_SCFCTST2      + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU);
+
+#if (((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) || (RCAR_LSI == RCAR_V4M))
+        mem_write32((DBSC_DBBUS0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x00000007U);   /* OTLINT-5579: V4H DBSC WA3 */
+#else
+        mem_write32((DBSC_DBBUS0CNF2    + (DBSC_A_CH_OFFSET * loop)), 0x00000003U);   /* S4, V4H w/o DBSC WA3 */
+#endif
+
+        /* DBSC QoS Setting */
+        mem_write32((DBSC_DBSCHQOS_0_0  + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU);
+        mem_write32((DBSC_DBSCHQOS_0_1  + (DBSC_A_CH_OFFSET * loop)), 0x00000480U);
+        mem_write32((DBSC_DBSCHQOS_0_2  + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
+        mem_write32((DBSC_DBSCHQOS_0_3  + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
+        mem_write32((DBSC_DBSCHQOS_4_0  + (DBSC_A_CH_OFFSET * loop)), 0x00000400U);
+        mem_write32((DBSC_DBSCHQOS_4_1  + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
+        mem_write32((DBSC_DBSCHQOS_4_2  + (DBSC_A_CH_OFFSET * loop)), 0x00000200U);
+        mem_write32((DBSC_DBSCHQOS_4_3  + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
+        mem_write32((DBSC_DBSCHQOS_9_0  + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
+        mem_write32((DBSC_DBSCHQOS_9_1  + (DBSC_A_CH_OFFSET * loop)), 0x00000240U);
+        mem_write32((DBSC_DBSCHQOS_9_2  + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
+        mem_write32((DBSC_DBSCHQOS_9_3  + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
+        mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U);
+        mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U);
+        mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U);
+        mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
+        mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
+        mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U);
+        mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
+        mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
+        mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U);
+        mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
+        mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
+        mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U);
+        mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
+        mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
+        mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U);
+        mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U);
+        if (loop == 0) /* Target register is only DBSC0 side. */
+        {
+            mem_write32(DBSC_FCPRSCTRL, 0x00000001U);
+        }
+        mem_write32((DBSC_SYSCNT1       + (DBSC_A_CH_OFFSET * loop)), 0x00000001U);
+        mem_write32((DBSC_SYSCNT0       + (DBSC_D_CH_OFFSET * loop)), 0x00000000U);
+        mem_write32((DBSC_SYSCNT0A      + (DBSC_A_CH_OFFSET * loop)), 0x00000000U);
+    }
+}
+/* End of function dbsc_setting(void) */
+
+void qos_init(void)
+{
+    uint32_t i;
+
+    /* Setting the register of DBSC4 for QoS initialize */
+    dbsc_setting();
+
+    NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION);
+    NOTICE("DRAM refresh interval 1.91 usec\n");
+
+#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
+    NOTICE("Periodic Write DQ Training\n");
+#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#if (RCAR_LSI == RCAR_S4)
+    /* Resource Alloc setting */
+    mem_write32(QOS_RAS,        0x00000028U);
+    mem_write32(QOS_DANN_LOW,   0x02020201U);
+    mem_write32(QOS_DANN_HIGH,  0x04040200U);
+    mem_write32(QOS_DANT,       0x00181004U);
+    mem_write32(QOS_EMS_LOW,    0x00000000U);
+    mem_write32(QOS_EMS_HIGH,   0x00000000U);
+    mem_write32(QOS_FSS,        0x0000000AU);
+    mem_write32(QOS_INSFC,      0x030F0001U);
+    mem_write32(QOS_EARLYR,     0x00000000U);
+    mem_write32(QOS_RACNT0,     0x00050003U);
+    mem_write32(QOS_STATGEN0,   0x00000000U);
+
+    /* QoS MSTAT setting */
+    mem_write32(QOS_SL_INIT,    0x00050100U);
+    mem_write32(QOS_REF_ARS,    0x00FB0000U);
+    mem_write32(QOS_REF_ENBL,   0x00000012U);
+    mem_write32(QOS_BWG,        0x00000002U);
+    mem_write32(AXMM_MMCR,      0x00010000U);
+
+    mem_write32(CCIQOS00,       0x08000000);
+    mem_write32(CCIQOS01,       0x08000000);
+    mem_write32(CCIQOS10,       0x00000001);
+    mem_write32(CCIQOS11,       0x00000001);
+    mem_write32(CCIQOS12,       0x00000001);
+    mem_write32(CCIQOS13,       0x00000001);
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+  #if (RCAR_LSI == RCAR_V4H)
+    #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE)
+    /* Address Split 2ch */
+    mem_write32(AXMM_ADSPLCR0,  0x00000000U);
+    mem_write32(AXMM_ADSPLCR1,  0x00FF1B0CU);
+    mem_write32(AXMM_ADSPLCR2,  0x00000000U);
+    mem_write32(AXMM_ADSPLCR3,  0x00000000U);
+    #endif
+#endif
+
+#if (RCAR_LSI == RCAR_V4H)
+    mem_write32(CCIQOS00,       0x08000000);
+    mem_write32(CCIQOS01,       0x08000000);
+    if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20)
+    {
+        mem_write32(CCIQOS10,       0x00000001U);
+        mem_write32(CCIQOS11,       0x00000001U);
+    }
+    else
+    {
+        mem_write32(CCIQOS10,       0x00000000U);
+        mem_write32(CCIQOS11,       0x00000000U);
+    }
+ #endif
+    /* Resource Alloc setting */
+#if (RCAR_LSI == RCAR_V4H)
+    mem_write32(QOS_RAS,        0x00000048U);
+#elif (RCAR_LSI == RCAR_V4M)
+    mem_write32(QOS_RAS,        0x00000030U);
+#endif
+    mem_write32(QOS_DANN_LOW,   0x02020201U);
+    mem_write32(QOS_DANN_HIGH,  0x04040200U);
+    mem_write32(QOS_DANT,       0x00181008U);
+    mem_write32(QOS_EMS_LOW,    0x00000000U);
+    mem_write32(QOS_EMS_HIGH,   0x00000000U);
+    mem_write32(QOS_FSS,        0x0000000AU);
+    mem_write32(QOS_INSFC,      0x030F0001U);
+    mem_write32(QOS_EARLYR,     0x00000000U);
+    mem_write32(QOS_RACNT0,     0x00050003U);
+    mem_write32(QOS_STATGEN0,   0x00000000U);
+
+    /* QoS MSTAT setting */
+    mem_write32(QOS_SL_INIT,    0x00070120U);
+    mem_write32(QOS_REF_ARS,    0x011B0000U);
+    mem_write32(QOS_REF_ENBL,   0x00000012U);
+    mem_write32(QOS_BWG,        0x00000004U);
+  #if ((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1))
+  if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
+  {
+    mem_write32(AXMM_MMCR,      0x00000000U);    /* OTLINT-5579: V4H DBSC WA3 */
+  }
+  else
+  {
+    mem_write32(AXMM_MMCR,      0x00010000U);    /* OTLINT-5579: V4H DBSC WA3 */
+  }
+  #elif (RCAR_LSI == RCAR_V4M)
+    mem_write32(AXMM_MMCR,      0x00010000U);
+  #else
+    mem_write32(AXMM_MMCR,      0x00010000U);
+  #endif
+    mem_write32(ACTEXT_RT0_R,   0x00000003U);
+    mem_write32(ACTEXT_RT0_W,   0x00000003U);
+    mem_write32(ACTEXT_IR0_R,   0x00000003U);
+    mem_write32(ACTEXT_IR0_W,   0x00000003U);
+    mem_write32(ACTEXT_IR1_R,   0x00000003U);
+    mem_write32(ACTEXT_IR1_W,   0x00000003U);
+#if (RCAR_LSI == RCAR_V4H)
+  mem_write32(AXMM_TR3CR,      0x00010000U);
+#endif
+
+#if (RCAR_LSI == RCAR_V4M)
+    mem_write32(AXMM_TR0CR0,      0x00000000U);
+    mem_write32(AXMM_TR1CR0,      0x00000000U);
+    mem_write32(AXMM_TR2CR0,      0x00000000U);
+    mem_write32(AXMM_TR3CR0,      0x00000000U);
+    mem_write32(AXMM_TR0CR1,      0x70707070U);
+    mem_write32(AXMM_TR1CR1,      0x70707070U);
+    mem_write32(AXMM_TR2CR1,      0x70707070U);
+    mem_write32(AXMM_TR3CR1,      0x70707070U);
+    mem_write32(AXMM_TR0CR2,      0x70707070U);
+    mem_write32(AXMM_TR1CR2,      0x70707070U);
+    mem_write32(AXMM_TR2CR2,      0x70707070U);
+    mem_write32(AXMM_TR3CR2,      0x70707070U);
+#endif
+
+
+#if (RCAR_LSI == RCAR_V4H)
+    if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20)
+    {
+        /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */
+        mem_write32(SI0_RW_MAX, 0x00000038U);
+        mem_write32(SI1_RW_MAX, 0x00000038U);
+    }
+#endif
+
+#endif /* RCAR_LSI == RCAR_S4 */
+
+    for (i = 0U; i < QOS_TBL_MAX; i++)
+    {
+        mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix);
+        mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix);
+        mem_write64((QOS_BE_QOS_BANK0  + (i * 8U)), g_qosbw_tbl[i].be);
+        mem_write64((QOS_BE_QOS_BANK1  + (i * 8U)), g_qosbw_tbl[i].be);
+    }
+
+#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
+    for (i = 0U; i < QOS_TBL_MAX; i++)
+    {
+        mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix);
+        mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix);
+        mem_write64((QOSWT_BE_QOS_BANK0  + (i * 8U)), g_qoswt_tbl[i].be);
+        mem_write64((QOSWT_BE_QOS_BANK1  + (i * 8U)), g_qoswt_tbl[i].be);
+    }
+#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+    /* QoS SRAM setting */
+    mem_write32(QOS_RAEN,       0x00000001U);
+#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
+    mem_write32(QOSWT_WTREF,    0x02080208U);
+    mem_write32(QOSWT_WTSET0,   0x0D90050FU);
+    mem_write32(QOSWT_WTSET1,   0x0D90050FU);
+    mem_write32(QOSWT_WTEN,     0x00000001U);
+#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+    mem_write32(QOS_STATQC,     0x00000101U);
+}
+/* End of function qos_init(void) */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c

@@ -0,0 +1,81 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : RT-VRAM driver
+ ******************************************************************************/
+/******************************************************************************
+ * @file          RTVRAM.c
+ * - Version      : 0.03
+ * @brief         RT-VRAM driver.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 17.11.2021 0.01     First Release
+ *         : 03.12.2021 0.02     remove Cache flush.
+ *         : 06.01.2022 0.03     Static analysis support
+ *****************************************************************************/
+
+#if defined(__RH850G3K__)
+#include <ram_def.h>
+#else
+#include <rcar_register.h>
+#endif
+#include <rtvram.h>
+#include <mem_io.h>
+#include <log.h>
+#include <inline_asm.h>
+
+#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY    (1U << 8U)
+#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M      (6U << 0U)
+
+#define RTVRAM_EXT_MODE_EXT     (1U << 0U)
+
+#define RTVRAM_VBUF_NUM    (7U)
+
+#define RTVRAM_EXTEND_ENABLE    (1U)
+
+void rtvram_extendmode(void)
+{
+#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE)
+    uint32_t reg;
+    uint32_t loop;
+
+    /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
+    for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++)
+    {
+        mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U));
+    }
+
+    reg = mem_read32(RTVRAM_VBUF_CFG);
+    reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M);  /* Cache Mode: 8-way, VBF size: 28M */
+    mem_write32(RTVRAM_VBUF_CFG, reg);
+
+    /* Set at the end */
+    mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */
+
+    syncm();
+#endif
+}
+/* End of function rtvram_extendmode(void) */

IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c

@@ -0,0 +1,123 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Watchdog Timer function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          swdt.c
+ * - Version      : 0.02
+ * @brief
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 12.08.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+*****************************************************************************/
+#include "mem_io.h"
+#include "rcar_def.h"
+#include "rcar_register.h"
+#include "swdt.h"
+#include "gic.h"
+#include "log.h"
+#include "ip_control.h"
+
+void swdt_init(void)
+{
+    uint32_t sr;
+    uint32_t reg;
+    uint32_t val;
+    uint32_t chk_data;
+
+    /* 1. Clear the TME bit in SWTCSRA to 0 to temporarily stop counting. */
+    reg = mem_read32(SWDT_WTCSRA) & WTCSRA_TME;
+    if (WTCSRA_TME == reg)
+    {
+        mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
+    }
+
+    /* 2.Write the set value in SWTCNT */
+    /* OSCCLK check */
+    reg = mem_read32(RST_MODEMR0);
+    chk_data = reg & CHECK_MD13_MD14;
+
+    val = WTCNT_UPPER_BYTE;
+
+	if (MD14_MD13_TYPE_0 == chk_data)
+    {
+        val |= SWDTCNT_133330HZ;
+    }
+    else if(MD14_MD13_TYPE_1 == chk_data)
+    {
+        val |= SWDTCNT_131570HZ;
+    }
+    else if(MD14_MD13_TYPE_3 == chk_data)
+    {
+        val |= SWDTCNT_131570HZ;
+    }
+    else
+    {
+        ERROR("MODEMR ERROR value = 0x%x\n", chk_data);
+        panic;
+    }
+
+    mem_write32(SWDT_WTCNT, val);
+
+    /* 3. Clear the bit4(WOVF) in SWTCSRA to 0. */
+    mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | WTCSRA_WOVFE | WTCSRA_CKS0_OSCCLK);
+
+    /* 5.Confirm that SWTCSRA.WRFLG becomes 0.*/
+    while (true)
+    {
+        if ((mem_read32(SWDT_WTCSRA) & WTCSRA_WRFLG) == 0U)
+        {
+            break;
+        }
+    }
+
+    /* 6. Start the counting by setting the TME bit in SWTCSRA to 1. */
+    sr = mem_read32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
+
+    mem_write32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | WTCSRA_TME));
+
+}
+/* End of function swdt_init(void) */
+
+void swdt_release(void)
+{
+
+    mem_write32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
+    mem_write32(SWDT_WTCNT, WTCNT_INIT_DATA);
+}
+/* End of function swdt_release(void) */
+
+void swdt_exec(void)
+{
+    ERROR("System Watchdog Timer overflow.\n");
+    panic;
+}
+/* End of function swdt_exec(void) */
+

IPL/Customer/Mobis/V4H_Cx_Loader/loader/asm_macros.S

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : macro
+ ******************************************************************************/
+/******************************************************************************
+ * @file          asm_macros.S
+ * - Version      : 0.03
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 07.02.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *         : 17.02.2023 0.03     Modified instruction to lower case.
+ *****************************************************************************/
+#ifndef ASM_MACROS_S 
+#define ASM_MACROS_S 
+
+	.macro mov_imm _reg, _val
+		.if (\_val) > 65535
+			mov 	\_reg, (\_val >> 0)  & 0xffff
+			movk	\_reg, (\_val >> 16) & 0xffff, lsl #16
+			movk	\_reg, (\_val >> 32) & 0xffff, lsl #32
+			movk	\_reg, (\_val >> 48) & 0xffff, lsl #48
+		.else
+			mov     \_reg, (\_val)
+		.endif
+	.endm 
+
+#endif /* ASM_MACROS_S */ 

IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_exceptions.S

@@ -0,0 +1,207 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Image load function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          loader_exceptions.S
+ * - Version      : 0.02
+ * @brief         
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 02.08.2022 0.01     First Release
+ *         : 31.10.2022 0.02     License notation change.
+ *****************************************************************************/
+#define SYNC_SP_EL0         (0x0U)
+#define IRQ_SP_EL0          (0x1U)
+#define FIQ_SP_EL0          (0x2U)
+#define SERROR_SP_EL0       (0x3U)
+#define SYNC_SP_ELX         (0x4U)
+#define IRQ_SP_ELX          (0x5U)
+#define FIQ_SP_ELX          (0x6U)
+#define SERROR_SP_ELX       (0x7U)
+#define SYNC_AARCH64        (0x8U)
+#define IRQ_AARCH64         (0x9U)
+#define FIQ_AARCH64         (0xAU)
+#define SERROR_AARCH64      (0xBU)
+#define SYNC_AARCH32        (0xCU)
+#define IRQ_AARCH32         (0xDU)
+#define FIQ_AARCH32         (0xEU)
+#define SERROR_AARCH32      (0xFU)
+
+	.global	loader_exceptions
+	.global	SyncSP0
+	.global	IrqSP0
+	.global	FiqSP0
+	.global	SErrorSP0
+	.global	SyncSPx
+	.global	IrqSPx
+	.global	FiqSPx
+	.global	SErrorSPx
+	.global	SyncA64
+	.global	IrqA64
+	.global	FiqA64
+	.global	SErrorA64
+	.global	SyncA32
+	.global	IrqA32
+	.global	FiqA32
+	.global	SErrorA32
+
+	/* Pre macro for a vector */
+	.macro bigin_vector  label, section_name=.vectors
+	.cfi_sections .debug_frame
+	.section \section_name, "ax"
+	.align 7, 0
+	.type \label, %function
+	.cfi_startproc
+	\label:
+	.endm
+
+	/* Post macro for a vector */
+	.macro end_vector label
+	.cfi_endproc
+	.fill	\label + (32 * 4) - .
+	.endm
+
+
+/*****************************************************************************/
+/* Exception Vector Table                                                    */
+/*****************************************************************************/
+	.section .vectors, "ax"
+	.align 11, 0
+
+loader_exceptions:
+
+	/***********************/
+	/* Current EL with SP0 */
+	/***********************/
+bigin_vector SyncSP0
+	mov	x0, #SYNC_SP_EL0
+	msr spsel, #0
+	bl	handler_error
+end_vector SyncSP0
+
+bigin_vector IrqSP0
+	mov	x0, #IRQ_SP_EL0
+	msr spsel, #0
+	bl	handler_error
+end_vector IrqSP0
+
+bigin_vector FiqSP0
+	mov	x0, #FIQ_SP_EL0
+	msr spsel, #0
+	b	handler_fiq
+end_vector FiqSP0
+
+bigin_vector SErrorSP0
+	mov	x0, #SERROR_SP_EL0
+	msr spsel, #0
+	bl	handler_error
+end_vector SErrorSP0
+
+	/***********************/
+	/* Current EL with SPx */
+	/***********************/
+bigin_vector SyncSPx
+	mov	x0, #SYNC_SP_ELX
+	msr spsel, #0
+	bl	handler_error
+end_vector SyncSPx
+
+bigin_vector IrqSPx
+	mov	x0, #IRQ_SP_ELX
+	msr spsel, #0
+	bl	handler_error
+end_vector IrqSPx
+
+bigin_vector FiqSPx
+	mov	x0, #FIQ_SP_ELX
+	msr spsel, #0
+	bl	handler_error
+end_vector FiqSPx
+
+bigin_vector SErrorSPx
+	mov	x0, #SERROR_SP_ELX
+	msr spsel, #0
+	bl	handler_error
+end_vector SErrorSPx
+
+	/**************************/
+	/* Lower EL using AArch64 */
+	/**************************/
+bigin_vector SyncA64
+	mov	x0, #SYNC_AARCH64
+	msr spsel, #0
+	bl	handler_error
+end_vector SyncA64
+
+bigin_vector IrqA64
+	mov	x0, #IRQ_AARCH64
+	msr spsel, #0
+	bl	handler_error
+end_vector IrqA64
+
+bigin_vector FiqA64
+	mov	x0, #FIQ_AARCH64
+	msr spsel, #0
+	bl	handler_error
+end_vector FiqA64
+
+bigin_vector SErrorA64
+	mov	x0, #SERROR_AARCH64
+	msr spsel, #0
+	bl	handler_error
+end_vector SErrorA64
+
+	/**************************/
+	/* Lower EL using AArch32 */
+	/**************************/
+bigin_vector SyncA32
+	mov	x0, #SYNC_AARCH32
+	msr spsel, #0
+	bl	handler_error
+end_vector SyncA32
+
+bigin_vector IrqA32
+	mov	x0, #IRQ_AARCH32
+	msr spsel, #0
+	bl	handler_error
+end_vector IrqA32
+
+bigin_vector FiqA32
+	mov	x0, #FIQ_AARCH32
+	msr spsel, #0
+	bl	handler_error
+end_vector FiqA32
+
+bigin_vector SErrorA32
+	mov	x0, #SERROR_AARCH32
+	msr spsel, #0
+	bl	handler_error
+end_vector SErrorA32
+

IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main.c

@@ -0,0 +1,575 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+ * DESCRIPTION   : Loader main function
+ ******************************************************************************/
+/******************************************************************************
+ * @file          loader_main.c
+ * - Version      : 0.17
+ * @brief         1. IP initialization.
+ *                2. Transfer image.
+ *                3. Release of used resources.
+ * .
+ *****************************************************************************/
+/******************************************************************************
+ * History : DD.MM.YYYY Version  Description
+ *         : 30.11.2021 0.01     First Release
+ *         : 14.02.2022 0.02     Changed log output
+ *                               Added device version log output
+ *                               Removed Include in micro_wait.h
+ *                               Removed the parameter setting process to BL31
+ *                               Removed LCS judgement
+ *                               Memory map change
+ *         : 17.02.2022 0.03     Support AArch32
+ *         : 22.03.2022 0.04     Support for GSCE[5.4a, 5.4b],[10.3b]
+ *                               Support for coverity
+ *                               cid:3430806, 3307617, 3430797
+ *                               Changed comment
+ *         : 10.05.2022 0.05     Integrated processing
+ *                               Changed to processing for each device
+ *                               Change log output
+ *                               Add argument of load_init()
+ *         : 16.06.2022 0.06     Change log output
+ *                               Support secure boot for S4
+ *         : 31.10.2022 0.07     License notation change.
+ *         : 07.11.2022 0.08     Added the parameter setting process to BL31
+ *                               Added DDR initialization/QOS initialization
+ *         : 07.12.2022 0.09     Warning support when log output is disabled
+ *         : 15.12.2022 0.10     Support RegionID check
+ *         : 04.04.2023 0.11     Removed stdio.h.
+ *         : 21.08.2023 0.12     Add support for V4M.
+ *         : 23.01.2024 0.13     Add calling of ram_protection_check function.
+ *                               Move calling of final_hash_cmp function.
+ *         : 10.09.2024 0.14     Updated Region ID and RAM protection setting
+ *                               for QNX.
+ *         : 11.10.2024 0.15     Updated Region ID and RAM protection setting
+ *                               for QNX for V4M.
+ *         : 19.12.2024 0.16     Add loading RTOS#1 and RTOS#2 process.
+ *                               Add calling ecm_error_enable() function.
+ *         : 26.05.2025 0.17     Add argument of OP-TEE boot address to
+ *                               smoni_set_param function.
+*****************************************************************************/
+
+#include <stdint.h>
+#include <loader_main.h>
+#include <rst_register.h>
+#include <image_load.h>
+#include <ip_control.h>
+#include <rcar_def.h>
+#include <mem_io.h>
+#include <log.h>
+#include <string.h>
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#include "cpu_on.h"
+#include "qos.h"
+#include "rtvram.h"
+#include "loader_main_common.h"
+#include "../ip/ddr/boot_init_dram.h"
+#include "access_protection.h"
+#if (ECC_ENABLE == 1)
+#if (RCAR_LSI == RCAR_V4H)
+#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h"
+#elif (RCAR_LSI == RCAR_V4M)
+#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h"
+#endif /* RCAR_LSI == RCAR_V4H */
+#endif /* ECC_ENABLE == 1 */
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+#if (BOOT_MODE == SECURE)
+#include "secure_boot.h"
+#endif /* BOOT_MODE == SECURE */
+/* Time analysis */
+#if (1 == (MEASURE_TIME))
+	#include <scmt.h>
+	#include <scmt_checkpoint.h>
+#else
+  #define scmt_wait_ticks(x)
+  #define store_time_checkpoint(x,y)
+  #define print_time_checkpoints(x)
+#endif
+#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+#include "axmm_register.h"
+#include "ram_protection.h"
+#endif
+#if (ECM_ERROR_ENABLE == 1)
+#if (RCAR_LSI == RCAR_V4H)
+#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h"
+#elif (RCAR_LSI == RCAR_V4M)
+#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h"
+#endif /* RCAR_LSI == RCAR_V4H */
+#endif /* ECM_ERROR_ENABLE == 1 */
+#include <android_ab.h>
+#include <emmc_def.h>
+#include <emmc_boot.h>
+
+#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+#define AXMM_DPTSECCR_NUM   (SDRAM_PROTECT_AREA)    /* set 0 to 15 */
+#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
+#define AXMM_DPTSECCR_NUM2  (SDRAM_PROTECT_AREA2)   /* set 0 to 15 */
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
+
+#define AXMM_DPTSECCR_SECGRP_MASK   (0x00000F00U)
+#define AXMM_DPTSECCR_SECGRP_SEC    (0x00000400U)
+#define AXMM_DPTSECCR_SECGWP_MASK   (0x0000000FU)
+#define AXMM_DPTSECCR_SECGWP_SEC    (0x00000004U)
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+#define DPTRGNCR_PROTECT_AREA       (3U)
+#define DPTRGNCR_LINUX_AREA         (6U)
+#else
+#define DPTRGNCR_PROTECT_AREA       (4U)
+#define DPTRGNCR_LINUX_AREA         (9U)
+#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+#define SECCTRWD_AREA0              (0U)
+#define SECCTRWD_AREA2              (2U)
+
+#define AXMM_DPTRGNCR_RGN0RP_MASK   (0x00010000U)
+#define AXMM_DPTRGNCR_RGN0RP        (0x00010000U)
+#define AXMM_DPTRGNCR_RGN0WP_MASK   (0x00000001U)
+#define AXMM_DPTRGNCR_RGN0WP        (0x00000001U)
+#define SECCTRWD_SAFG15WP_MASK      (0x00000005U)
+#define SECCTRWD_SAFG15WP           (0x00000005U)
+
+static void remove_rgid0_previlege(void);
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+
+static void sdram_protection(uint32_t num);
+#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
+
+uint32_t loader_main(void)
+{
+    uint32_t ca_load_num; /* number of load for CA program */
+    uint32_t loop;
+    uint32_t reg;       /* store register value */
+#ifdef MOBIS_PRK3
+    int slot = 0;
+#endif
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+    int32_t  result;     /* store result of ddr_init() */
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+
+    __attribute__((unused))const char *str;
+#if (RCAR_LSI == RCAR_S4)
+    const char *product_s4      = "S4";
+#elif (RCAR_LSI == RCAR_V4H)
+    const char *product_v4h     = "V4H";
+#elif (RCAR_LSI == RCAR_V4M)
+    const char *product_v4m     = "V4M";
+#endif /* RCAR_LSI == RCAR_S4 */
+    const char *unknown         = "unknown";
+#if (BOOT_MODE == SECURE)
+    uint32_t bootmode;       /* store boot mode */
+#endif /* BOOT_MODE == SECURE */
+
+    LOAD_INFO li[MAX_PLACED];
+
+#if (1 == (MEASURE_TIME))
+    scmt_module_start();
+    store_time_checkpoint("loader_main", 0);
+#endif
+/*****************************************************************************
+ *  Initialize Hardware
+ *****************************************************************************/
+    /* IP initialize */
+    ip_init();
+
+/*****************************************************************************
+ *  Output boot message
+ *****************************************************************************/
+#if (RCAR_LSI == RCAR_S4)
+    NOTICE("CA55 Loader Program Rev.%s\n", IPL_VERSION);
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+    NOTICE("CR52 Loader Program Rev.%s\n", IPL_VERSION);
+#endif /* RCAR_LSI == RCAR_S4 */
+
+    NOTICE("%s\n", build_message);
+
+    /* Get PRR */
+    reg = mem_read32(PRR);
+    switch (reg & PRR_PRODUCT_MASK)
+    {
+        #if (RCAR_LSI == RCAR_S4)
+        case PRR_PRODUCT_S4:
+        {
+            str = product_s4;
+            break;
+        }
+        #elif (RCAR_LSI == RCAR_V4H)
+        case PRR_PRODUCT_V4H:
+        {
+            str = product_v4h;
+            break;
+        }
+        #elif (RCAR_LSI == RCAR_V4M)
+        case PRR_PRODUCT_V4M:
+        {
+            str = product_v4m;
+            break;
+        }
+        #endif /* RCAR_LSI == RCAR_S4 */
+        default:
+        {
+            str = unknown;
+            break;
+        }
+    }
+    NOTICE("PRR is R-Car %s Ver.%d.%d\n", str,
+        ((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT)
+        + PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK));
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+    #if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+    /* Notice the ecc enable */
+    NOTICE("Access Protection Enable\n");
+    #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+    store_time_checkpoint("init_done", 0);
+
+/*****************************************************************************
+ *  DDR Initialization
+ *****************************************************************************/
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+
+    /* DDR initialize */
+    result = R_DRAM_Init();
+    if (INITDRAM_OK != result)
+    {
+        ERROR("Failed to DRAM initialize (%d).\n", (int)result);
+        panic;
+    }
+
+#if (ECM_ERROR_ENABLE == 1)
+    ecm_error_enable();
+#endif /* ECM_ERROR_ENABLE == 1 */
+
+#if (ECC_ENABLE == 1)
+    /* ECC Protection */
+    ecc_sdram_enable();
+#endif /* ECC_ENABLE == 1 */
+
+    /* QoS configuration */
+    qos_init();
+
+    /* RT-VRAM Extend mode */
+    rtvram_extendmode();
+
+    /* memory copy */
+    memcpy((void *)DISK_BUFFER_ADDR, (void *)DISK_BUFFER__IPL, 4096);
+    memset((void *)DISK_BUFFER__IPL, 0xFF, 4096);
+    memcpy((void *)AB_INFO_FLAG_ADDR, (void *)AB_INFO_FLAG__IPL, 4);
+    memset((void *)AB_INFO_FLAG__IPL, 0xFF, 4);
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+    store_time_checkpoint("DDR_and_Bus_init_done", 0);
+
+/*****************************************************************************
+ *  Load Certficate
+ *****************************************************************************/
+
+    /* Load content certificate */
+    ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR);
+
+    /* Get load information */
+    load_init(li, ca_load_num);
+
+#if (BOOT_MODE == SECURE)
+/*****************************************************************************
+ *  Check SecureBoot
+ *****************************************************************************/
+    secureboot_init();
+
+    /* LCS judgement for secure boot */
+    bootmode = judge_bootmode();
+
+    if (NORMAL_BOOT != bootmode)
+    {
+        /* Content cert certification */
+#if (BL2_LOAD_ENABLE == BL2_DISABLE)
+        secureboot_verify(li, CA_OPTIONAL_ID, CA_OPTIONAL_ID + ca_load_num);
+#else
+        secureboot_verify(li, CA_BL2_ID, CA_BL2_ID + 1);
+#endif
+        store_time_checkpoint("verify_cert_done", 0);
+    }
+#endif /* BOOT_MODE == SECURE */
+
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+/*****************************************************************************
+ *  Load RTOS#2
+ *****************************************************************************/
+    /* Start loading RTOS#2 image */
+    load_image(&li[RTOS2_ID]);
+    store_time_checkpoint("load_RTOS#2_done", li[RTOS2_ID].image_size);
+
+    #if (BOOT_MODE == SECURE)
+        /* Decryption image and Image cerfification */
+        if (NORMAL_BOOT != bootmode)
+        {
+            secureboot_image(&li[RTOS2_ID], 1);
+            store_time_checkpoint("verify_RTOS#2_done", 0);
+        }
+    #endif /* BOOT_MODE == SECURE */
+
+    /* boot CR core2 */
+    arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS2_ID].boot_addr, 2);
+    store_time_checkpoint("started_RTOS#2", 0);
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+/*****************************************************************************
+ *  Load RTOS#0
+ *****************************************************************************/
+#define _IPL_END     (0xEB22FFF4)
+#ifdef MOBIS_PRK3
+    emmc_initialize();
+    store_time_checkpoint("emmc_initialize", 0);
+#if (BL2_LOAD_ENABLE == BL2_ENABLE)	/* do not clear eMMC */
+    export_mmc_drv_obj();
+#endif
+
+    reg = mem_read32(AB_INFO_FLAG_ADDR);
+    if (reg & AB_INFO_SELECT_2nd)
+        slot = 1;
+    // slot = ab_select_slot();
+    load_update_part_num(li, ca_load_num, slot);
+    NOTICE("slot: %d\n", slot);
+
+    mem_write32(_IPL_END, 0x0);
+#endif
+
+    /* Start loading RTOS#0 image */
+    load_image(&li[RTOS_ID]);
+    store_time_checkpoint("load_RTOS#0_done", li[RTOS_ID].image_size);
+
+    #if (BOOT_MODE == SECURE)
+        /* Decryption image and Image cerfification */
+        if (NORMAL_BOOT != bootmode)
+        {
+            /* WARNING! WARNING! WARNING! WARNING! */
+            /* TODO: set 1 to panic! later */
+            secureboot_image(&li[RTOS_ID], 0);
+            store_time_checkpoint("verify_RTOS#0_done", 0);
+        }
+    #endif /* BOOT_MODE == SECURE */
+
+    /* boot CR core0 */
+    arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, -1);
+
+#ifdef MOBIS_PRK3
+    /* enable CR-52 Core 2 */
+    arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, 2);
+    store_time_checkpoint("started_RTOS#0", 0);
+#endif
+#if (BOOT_TIME_CHECK != 0)
+    gpio_N1305(2);
+#endif
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+
+/*****************************************************************************
+ *  Load CA Program#2--#8
+ *****************************************************************************/
+#if (BL2_LOAD_ENABLE == BL2_DISABLE)
+    /* Start loading CA Program#n image */
+    for (loop = 0U; loop < ca_load_num; loop++)
+#else
+    /* load bl2 */
+    loop = (CA_BL2_ID - CA_OPTIONAL_ID);
+#endif
+    {
+        /* Loading start */
+        NOTICE("Loading %s...\n", li[CA_OPTIONAL_ID + loop].name);
+        load_image(&li[CA_OPTIONAL_ID + loop]);
+        store_time_checkpoint("load_CA_#_done", li[CA_OPTIONAL_ID + loop].image_size);
+
+#if (BOOT_MODE == SECURE)
+        /* Decryption image and Image certification  */
+        if (NORMAL_BOOT != bootmode)
+        {
+            secureboot_image(&li[CA_OPTIONAL_ID + loop], 1);
+            store_time_checkpoint("verify_CA_#_done", 0);
+        }
+#endif /* BOOT_MODE == SECURE */
+    }
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+    /* Set Secure Monitor parameter */
+    #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
+    smoni_set_param(li[CA_OPTIONAL_ID].boot_addr,        /* BL31 */
+                    li[CA_OPTIONAL_ID + 1U].boot_addr);  /* U-Boot */
+    #else
+     #if (BL2_LOAD_ENABLE == BL2_DISABLE)	/* BL2 will load these */
+    smoni_set_param(li[CA_OPTIONAL_ID].boot_addr,        /* BL31 */
+                    li[CA_OPTIONAL_ID + 1U].boot_addr,   /* U-Boot */
+                    li[CA_OPTIONAL_ID + 2U].boot_addr);  /* OP-TEE */
+     #endif
+    #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
+
+    /* Before Boot CPU, Set the division ratio for CPU operating frequency */
+    adj_ca_variant_freq();
+
+/* boot CA */
+#if (BL2_LOAD_ENABLE == BL2_DISABLE)
+    arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_OPTIONAL_ID].boot_addr, -1);
+#else	/* run BL2, not BL31 */
+    arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_BL2_ID].boot_addr, -1);
+#endif
+    store_time_checkpoint("started_CA_core", 0);
+
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+/*****************************************************************************
+ *  Load RTOS#1
+ *****************************************************************************/
+    /* Start loading RTOS#1 image */
+    load_image(&li[RTOS1_ID]);
+    store_time_checkpoint("load_RTOS#1_done", li[RTOS1_ID].image_size);
+
+    #if (BOOT_MODE == SECURE)
+        /* Decryption image and Image cerfification */
+        if (NORMAL_BOOT != bootmode)
+        {
+            secureboot_image(&li[RTOS1_ID], 1);
+            store_time_checkpoint("verify_RTOS#1_done", 0);
+        }
+    #endif /* BOOT_MODE == SECURE */
+
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+
+    #if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+    sdram_protection(AXMM_DPTSECCR_NUM);
+    #if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
+    sdram_protection(AXMM_DPTSECCR_NUM2);
+    #endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
+    remove_rgid0_previlege();
+    /*
+     * SAN(Safety Application Note) 6.23.5 Operation
+     * Checker processor :
+     * Check RegionID/LifeC & memory area protection settings (including order & content of intermediate updates)
+     * done by ICUMX.
+     */
+    rgid_protection_check();
+    ram_protection_check();
+    #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
+
+    #if (BOOT_MODE == SECURE)
+    if (NORMAL_BOOT != bootmode)
+    {
+        /* Compare Hash verified at ICUMX IPL (V4H only). (Target images are Secure FW and Cx 2nd IPL.) */
+        /*
+         * SAN(Safety Application Note) 6.23.5 Operation
+         * Checker processor :
+         * Re-do comparison of hash in Flash vs hash generated by ICUMX to confirm proper comparison.
+         */
+        final_hash_cmp();
+        store_time_checkpoint("final_verify_done", 0);
+    }
+    #endif /* BOOT_MODE == SECURE */
+
+    NOTICE("Load finish.(CR52 Loader)\n");
+
+#elif (RCAR_LSI == RCAR_S4)
+    #if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+    sdram_protection(AXMM_DPTSECCR_NUM);
+    #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
+    NOTICE("Load finish.(CA55 Loader)\n");
+#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
+    // ip_release();
+
+    store_time_checkpoint("Cx_done_starting_RTOS#1", 0);
+    // scmt_wait_ticks(SCMT_MS2TICKS(1000));
+    print_time_checkpoints();
+#if (BOOT_TIME_CHECK != 0)
+    gpio_N1305(2);
+#endif
+
+#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
+ #ifdef MOBIS_PRK3
+    return li[RTOS_ID].boot_addr;
+ #else
+    return li[CA_OPTIONAL_ID].boot_addr;
+ #endif
+#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
+    return li[RTOS1_ID].boot_addr;
+#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
+}
+/* End of function loader_main(void) */
+
+
+#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
+static void sdram_protection(uint32_t num)
+{
+    uint32_t val;
+    uint32_t addr;
+
+    /* Calculation of the address of the DPTSECCR register. */
+    addr = (AXMM_DPTSECCR + (num * 4U));
+
+    val = mem_read32(addr);
+    val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK);
+    val |= (AXMM_DPTSECCR_SECGRP_SEC | AXMM_DPTSECCR_SECGWP_SEC);
+    mem_write32(addr, val);
+}/* End of function void sdram_protection(void) */
+
+#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+static void remove_rgid0_previlege(void)
+{
+    uint32_t val;
+    uint32_t addr;
+
+    /* Calculation of the address of the DPTRGNCR register. */
+    addr = get_dptrgncr_addr(DPTRGNCR_PROTECT_AREA);
+
+    val  = mem_read32(addr);
+    val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
+    val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP);    /* Remove RGID0 read/write previlege on SDRAM Area. */
+    mem_write32(addr, val);
+
+    /* Calculation of the address of the DPTRGNCR register. */
+    addr = get_dptrgncr_addr(DPTRGNCR_LINUX_AREA);
+
+    val  = mem_read32(addr);
+    val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
+    val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP);    /* Remove RGID0 read/write previlege on SDRAM Area. */
+    mem_write32(addr, val);
+
+    /* Calculation of the address of the SECCTRW0D_1 register. */
+    addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA0);
+
+    val  = mem_read32(addr);
+    val &= ~(SECCTRWD_SAFG15WP_MASK);
+    val |= SECCTRWD_SAFG15WP;   /* Remove RGID0/2 write previlege on RT-VRAM1 Area0. */
+    mem_write32(addr, val);
+
+    /* Calculation of the address of the SECCTRW2D_1 register. */
+    addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA2);
+
+    val  = mem_read32(addr);
+    val &= ~(SECCTRWD_SAFG15WP_MASK);
+    val |= SECCTRWD_SAFG15WP;   /* Remove RGID0/2 write previlege on RT-VRAM1 Area2. */
+    mem_write32(addr, val);
+}
+/* End of function void remove_rgid0_previlege(void) */
+#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
+
+#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */