273 lines
11 KiB
C
273 lines
11 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Image load function
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******************************************************************************/
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/******************************************************************************
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* @file image_load.h
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* - Version : 0.09
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* @brief Access protection setting driver.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 02.02.2022 0.01 First Release
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* : 10.02.2022 0.02 Change the number of CA programs
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* : 17.02.2022 0.03 Support AArch32
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* : 18.05.2022 0.04 Integrated LOAD_INFO
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* Defined value integration
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* Remove unused define values
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* Changed to processing for each device
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* Change structure member name
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* Remove LOGICAL_CONTENT_CERT_ADDR
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* Add get_logic_cont_cert_addr
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* Change the argument type of get_src_addr_offset_in_cert
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* Added argument check
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* Remove unnecessary macros
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* Add argument of load_init()
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* Change for memory map update
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* : 16.06.2022 0.05 Change log output
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* Support secure boot for S4
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* : 31.10.2022 0.06 License notation change.
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* : 21.08.2023 0.07 Add support for V4M.
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* : 19.12.2024 0.08 Add definitions for RTOS#1 and RTOS#2.
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* : 26.05.2025 0.09 Change address and size of CA program2.
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*****************************************************************************/
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#ifndef LOAD_IMAGE_H_
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#define LOAD_IMAGE_H_
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#include "log.h"
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/* define */
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/* For Build Option RTOS_LOAD_NUM */
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#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */
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#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
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/* For Build Option OPTEE_LOAD_ENABLE */
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#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */
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#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */
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/* For Build Option BL2_LOAD_ENABLE */
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#define BL2_DISABLE (0U) /* Load BL2 image disable. */
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#define BL2_ENABLE (1U) /* Load BL2 image enable. */
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/* For Build Option QNX_OS_LOAD_ENABLE */
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#define QNX_OS_DISABLE (0U) /* Load QNX_OS image disable. */
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#define QNX_OS_ENABLE (1U) /* Load QNX_OS image enable. */
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/* DRAM address */
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#define DRAM_BASE (0x40000000U)
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#define DRAM_SIZE (0x80000000U)
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#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
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/* RT-SRAM */
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/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */
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#define RTSRAM_BASE (0xEB200000U)
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#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */
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#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
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/* RT-VRAM */
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/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */
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#define RTVRAM_BASE (0xE2000000U)
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#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */
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#define RTVRAM_VBUF_28M (28U) /* 28MB */
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#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */
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#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */
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#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U)
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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#define RTVRAM_8WAY_28M_SRAM_SIZE (0x00010000U) /* 64KiB */
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#define RTVRAM_SRAM_TOP (RTVRAM_BASE)
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#define RTVRAM_SRAM_END (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U) /* 0xE2000000 - 0xE200FFFF */
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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/* System RAM */
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#define SYSRAM_BASE (0xE6300000U)
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#if (RCAR_LSI == RCAR_S4)
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#define SYSRAM_SIZE (384U * 1024U) /* 384KB */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */
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#endif /* RCAR_LSI == RCAR_S4 */
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#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U)
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/* Cx Loader */
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#define IPL_TOP (0xE6300000U)
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#define IPL_SIZE (0x00030000U) /* 192KiB */
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#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U)
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/* Certificate size */
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#define CONTENT_CERT_OFFSET (0x00006000U) /* certificate top offset */
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#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header area size(4KiB) */
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#define CONTENT_CERT_DST_SIZE (0x00000800U) /* content cert dst size */
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#define KEY_CERT_SIZE (0x00002000U) /* Key cert area size(8KiB) */
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/* Load ID */
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#define RTOS_ID (1U)
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#define CA_PROGRAM_ID (2U)
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#define CA_OPTIONAL_ID (6U)
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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#define RTOS1_ID (16U) /* 16:RTOS#1 */
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#define RTOS2_ID (17U) /* 17:RTOS#2 */
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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/* Number of Max loading image */
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#define CA_MAX_IMAGE (8U) /* CA Load program MAX image num */
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
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#define MAX_PLACED (16U) /* Load program MAX image num */
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#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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#define MAX_PLACED (18U) /* Load program MAX image num */
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */
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#define TARGET_MEM_DRAM (0U)
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#define TARGET_MEM_RTSRAM (1U)
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#define TARGET_MEM_RTVRAM (2U)
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#define TARGET_MEM_SYSRAM (3U)
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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#define TARGET_MEM_SRAM_IN_RTVRAM (4U)
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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/* get info from cert address offset */
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#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
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#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
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#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
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#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
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#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */
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#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */
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/* Certificate logical address */
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#define CONTENT_CERT_DEST_ADDR (0xEB230000U)
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#define CONTENT_CERT_DEST_SIZE (0x00008000U) /* 32KB */
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/* BL31/BL32(S4), BL31/tee-OS/u-boot(V4H) check */
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/* check image num */
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#ifdef MOBIS_PRK3
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#error "OPTEE_LOAD_ENABLE==1 should be for PRK3"
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#endif
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#if (BL2_LOAD_ENABLE == BL2_DISABLE)
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#error "BL2_LOAD_ENABLE==1 should be for PRK3"
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#endif
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#if (QNX_OS_LOAD_ENABLE == QNX_OS_DISABLE)
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#error "QNX_OS_LOAD_ENABLE==1 should be for PRK3"
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#endif
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#define CA_IMAGESIZECHK_DEF (5U)
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#else
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#define CA_IMAGESIZECHK_DEF (2U)
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#endif
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/* load_id */
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#define CA_PROGRAM1_ID (6U) /* bl31 */
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#define CA_PROGRAM2_ID (7U) /* u-boot */
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#define CA_PROGRAM3_ID (8U) /* tee-os */
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#define CA_PROGRAM4_ID (9U) /* ca76-loader */
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#define CA_PROGRAM5_ID (10U) /* qnx OS */
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#define CA_BL2_ID CA_PROGRAM4_ID
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#define CA_QNX_OS_ID CA_PROGRAM5_ID
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#define CA_PROGRAM1_ADR (0x46400000U)
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#define CA_PROGRAM1_SIZE (0x00022000U)
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#if (RCAR_LSI == RCAR_S4)
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#define CA_PROGRAM2_ADR (0x44100000U)
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#define CA_PROGRAM2_SIZE (0x00100000U)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define CA_PROGRAM2_ADR (0x00000000U)
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#define CA_PROGRAM2_SIZE (0x00000000U)
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#endif /* RCAR_LSI == RCAR_S4 */
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#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
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#define CA_PROGRAM3_ADR (0x44100000U)
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#define CA_PROGRAM3_SIZE (0x00100000U)
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
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#if (BL2_LOAD_ENABLE == BL2_ENABLE)
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#define CA_PROGRAM4_ADR (0x41D00000U)
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#define CA_PROGRAM4_SIZE (0x00020000U) /* 128KB */
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#endif /* BL2_LOAD_ENABLE == BL2_ENABLE */
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#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE)
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#define CA_PROGRAM5_ADR (0x50100000U)
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#define CA_PROGRAM5_SIZE (0x00800000U) /* 8MB */
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#endif /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */
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/* key cert address */
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#define TFMV_KEY_CERT_ADDR (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */
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#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xEB233000 */
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/* struct */
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/* load image range */
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typedef struct {
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uint32_t load_id;
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uint32_t image_adr;
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uint32_t image_size;
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} IMAGE_RANGE;
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/* load address range */
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typedef struct {
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uint32_t cx_topadd;
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uint32_t cx_endadd;
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} ADDRESS_RANGE;
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/* load info */
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typedef struct{
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const char *name; /* store load image name */
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uint32_t image_size; /* store image size */
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uint32_t boot_addr; /* store boot address of image */
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uint32_t key_cert_addr; /* store key cert address */
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uint32_t cnt_cert_addr; /* store content cert address */
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uint32_t src_addr; /* store source address */
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uint32_t part_num; /* store eMMC partition number */
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uint32_t load_id; /* store Load ID */
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uint32_t cmac[4U]; /* store cmac */
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} LOAD_INFO;
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static inline uint32_t get_src_addr_offset_in_cert(uint32_t id)
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{
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/* INT30-C Pre confirmation */
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if (id > UINT32_MAX / 0x10U)
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{
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ERROR("get_src_addr_offset_in_cert id error.\n");
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panic;
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}
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return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U));
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}
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static inline uint32_t get_logic_cont_cert_addr(uint32_t num)
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{
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/* INT30-C Pre confirmation */
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if (num > UINT32_MAX / 0x10U)
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{
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ERROR("get_logic_cont_cert_addr num error.\n");
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panic;
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}
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return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE));
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}
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/* Prototype */
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void load_image(LOAD_INFO* li);
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void load_init(LOAD_INFO* li, uint32_t num);
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void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot);
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void load_start(LOAD_INFO* li);
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#endif /* LOAD_IMAGE_H_ */
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