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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
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37
IPL/Customer/Mobis/V4H_Cx_Loader/include/access_protection.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Region ID function header
******************************************************************************/
#ifndef REGION_ID_H__
#define REGION_ID_H__
#define PROTECTION_DISABLE (0U)
#define PROTECTION_ENABLE (1U)
void rgid_protection_check(void);
void ram_protection_check(void);
#endif /* REGION_ID_H__ */

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IPL/Customer/Mobis/V4H_Cx_Loader/include/android_ab.h Normal file
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2017 The Android Open Source Project
*/
#ifndef __ANDROID_AB_H
#define __ANDROID_AB_H
// struct blk_desc;
// struct disk_partition;
/* Android standard boot slot names are 'a', 'b', 'c', ... */
#define BOOT_SLOT_NAME(slot_num) ('a' + (slot_num))
/* Number of slots */
#define NUM_SLOTS 2
/* CX_EMMC_AB_CONTROL from icumx_IPL */
#define DISK_BUFFER__IPL (0xEB22E000U)
#define DISK_BUFFER_ADDR (0x41DFE000U)
/* pass ab info from Cx_IPL to BL2 */
#define AB_INFO_FLAG__IPL (0xEB22FFFCU)
#define AB_INFO_FLAG_ADDR (0x41DFFFFCU)
#define AB_INFO_FLAG_INIT (0xDEADBEEFU)
#define AB_INFO_SELECT_1st (0x00000000U)
#define AB_INFO_SELECT_2nd (0x10000000U)
#define AB_INFO_FLAG_STORE (0x0BADF00DU)
#define AB_INFO_FLAG_OK (0x00FACADEU)
/**
* Select the slot where to boot from.
*
* On Android devices with more than one boot slot (multiple copies of the
* kernel and system images) selects which slot should be used to boot from and
* registers the boot attempt. This is used in by the new A/B update model where
* one slot is updated in the background while running from the other slot. If
* the selected slot did not successfully boot in the past, a boot attempt is
* registered before returning from this function so it isn't selected
* indefinitely.
*
* @param[in] dev_desc Place to store the device description pointer
* @param[in] part_info Place to store the partition information
* @return The slot number (>= 0) on success, or a negative on error
*/
int ab_select_slot(
// struct blk_desc *dev_desc, struct disk_partition *part_info
void
);
#endif /* __ANDROID_AB_H */

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/*
* This is from the Android Project,
* Repository: https://android.googlesource.com/platform/bootable/recovery
* File: bootloader_message/include/bootloader_message/bootloader_message.h
* Commit: See U-Boot commit description
*
* Copyright (C) 2008 The Android Open Source Project
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ANDROID_BOOTLOADER_MESSAGE_H
#define __ANDROID_BOOTLOADER_MESSAGE_H
#ifndef __UBOOT__
#include <assert.h>
#include <stddef.h>
#include <stdint.h>
#else
/* compiler.h defines the types that otherwise are included from stdint.h and
* stddef.h
*/
#include <compiler.h>
#endif
// Spaces used by misc partition are as below:
// 0 - 2K For bootloader_message
// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used
// as bootloader_message_ab struct)
// 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices
// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
// are not configurable without changing all of them.
static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
/* Bootloader Message (2-KiB)
*
* This structure describes the content of a block in flash
* that is used for recovery and the bootloader to talk to
* each other.
*
* The command field is updated by linux when it wants to
* reboot into recovery or to update radio or bootloader firmware.
* It is also updated by the bootloader when firmware update
* is complete (to boot into recovery for any final cleanup)
*
* The status field was used by the bootloader after the completion
* of an "update-radio" or "update-hboot" command, which has been
* deprecated since Froyo.
*
* The recovery field is only written by linux and used
* for the system to send a message to recovery or the
* other way around.
*
* The stage field is written by packages which restart themselves
* multiple times, so that the UI can reflect which invocation of the
* package it is. If the value is of the format "#/#" (eg, "1/3"),
* the UI will add a simple indicator of that status.
*
* We used to have slot_suffix field for A/B boot control metadata in
* this struct, which gets unintentionally cleared by recovery or
* uncrypt. Move it into struct bootloader_message_ab to avoid the
* issue.
*/
struct bootloader_message {
char command[32];
char status[32];
char recovery[768];
// The 'recovery' field used to be 1024 bytes. It has only ever
// been used to store the recovery command line, so 768 bytes
// should be plenty. We carve off the last 256 bytes to store the
// stage string (for multistage packages) and possible future
// expansion.
char stage[32];
// The 'reserved' field used to be 224 bytes when it was initially
// carved off from the 1024-byte recovery field. Bump it up to
// 1184-byte so that the entire bootloader_message struct rounds up
// to 2048-byte.
char reserved[1184];
};
/**
* We must be cautious when changing the bootloader_message struct size,
* because A/B-specific fields may end up with different offsets.
*/
#ifndef __UBOOT__
#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
static_assert(sizeof(struct bootloader_message) == 2048,
"struct bootloader_message size changes, which may break A/B devices");
#endif
#endif /* __UBOOT__ */
/**
* The A/B-specific bootloader message structure (4-KiB).
*
* We separate A/B boot control metadata from the regular bootloader
* message struct and keep it here. Everything that's A/B-specific
* stays after struct bootloader_message, which should be managed by
* the A/B-bootloader or boot control HAL.
*
* The slot_suffix field is used for A/B implementations where the
* bootloader does not set the androidboot.ro.boot.slot_suffix kernel
* commandline parameter. This is used by fs_mgr to mount /system and
* other partitions with the slotselect flag set in fstab. A/B
* implementations are free to use all 32 bytes and may store private
* data past the first NUL-byte in this field. It is encouraged, but
* not mandatory, to use 'struct bootloader_control' described below.
*
* The update_channel field is used to store the Omaha update channel
* if update_engine is compiled with Omaha support.
*/
struct bootloader_message_ab {
struct bootloader_message message;
char slot_suffix[32];
char update_channel[128];
// Round up the entire struct to 4096-byte.
char reserved[1888];
};
/**
* Be cautious about the struct size change, in case we put anything post
* bootloader_message_ab struct (b/29159185).
*/
#ifndef __UBOOT__
#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
static_assert(sizeof(struct bootloader_message_ab) == 4096,
"struct bootloader_message_ab size changes");
#endif
#endif /* __UBOOT__ */
#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */
#define BOOT_CTRL_VERSION 1
struct slot_metadata {
// Slot priority with 15 meaning highest priority, 1 lowest
// priority and 0 the slot is unbootable.
uint8_t priority : 4;
// Number of times left attempting to boot this slot.
uint8_t tries_remaining : 3;
// 1 if this slot has booted successfully, 0 otherwise.
uint8_t successful_boot : 1;
// 1 if this slot is corrupted from a dm-verity corruption, 0
// otherwise.
uint8_t verity_corrupted : 1;
// Reserved for further use.
uint8_t reserved : 7;
} __attribute__((packed));
/* Bootloader Control AB
*
* This struct can be used to manage A/B metadata. It is designed to
* be put in the 'slot_suffix' field of the 'bootloader_message'
* structure described above. It is encouraged to use the
* 'bootloader_control' structure to store the A/B metadata, but not
* mandatory.
*/
struct bootloader_control {
// NUL terminated active slot suffix.
char slot_suffix[4];
// Bootloader Control AB magic number (see BOOT_CTRL_MAGIC).
uint32_t magic;
// Version of struct being used (see BOOT_CTRL_VERSION).
uint8_t version;
// Number of slots being managed.
uint8_t nb_slot : 3;
// Number of times left attempting to boot recovery.
uint8_t recovery_tries_remaining : 3;
// Ensure 4-bytes alignment for slot_info field.
uint8_t reserved0[2];
// Per-slot information. Up to 4 slots.
struct slot_metadata slot_info[4];
// Reserved for further use.
uint8_t reserved1[8];
// CRC32 of all 28 bytes preceding this field (little endian
// format).
uint32_t crc32_le;
} __attribute__((packed));
#ifndef __UBOOT__
#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
static_assert(sizeof(struct bootloader_control) ==
sizeof(((struct bootloader_message_ab *)0)->slot_suffix),
"struct bootloader_control has wrong size");
#endif
#endif /* __UBOOT__ */
#ifndef __UBOOT__
#ifdef __cplusplus
#include <string>
#include <vector>
// Return the block device name for the bootloader message partition and waits
// for the device for up to 10 seconds. In case of error returns the empty
// string.
std::string get_bootloader_message_blk_device(std::string* err);
// Read bootloader message into boot. Error message will be set in err.
bool read_bootloader_message(bootloader_message* boot, std::string* err);
// Read bootloader message from the specified misc device into boot.
bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device,
std::string* err);
// Write bootloader message to BCB.
bool write_bootloader_message(const bootloader_message& boot, std::string* err);
// Write bootloader message to the specified BCB device.
bool write_bootloader_message_to(const bootloader_message& boot,
const std::string& misc_blk_device, std::string* err);
// Write bootloader message (boots into recovery with the options) to BCB. Will
// set the command and recovery fields, and reset the rest.
bool write_bootloader_message(const std::vector<std::string>& options, std::string* err);
// Write bootloader message (boots into recovery with the options) to the specific BCB device. Will
// set the command and recovery fields, and reset the rest.
bool write_bootloader_message_to(const std::vector<std::string>& options,
const std::string& misc_blk_device, std::string* err);
// Update bootloader message (boots into recovery with the options) to BCB. Will
// only update the command and recovery fields.
bool update_bootloader_message(const std::vector<std::string>& options, std::string* err);
// Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update
// the command and recovery fields.
bool update_bootloader_message_in_struct(bootloader_message* boot,
const std::vector<std::string>& options);
// Clear BCB.
bool clear_bootloader_message(std::string* err);
// Writes the reboot-bootloader reboot reason to the bootloader_message.
bool write_reboot_bootloader(std::string* err);
// Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC).
bool read_wipe_package(std::string* package_data, size_t size, std::string* err);
// Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC).
bool write_wipe_package(const std::string& package_data, std::string* err);
#else
#include <stdbool.h>
// C Interface.
bool write_bootloader_message(const char* options);
bool write_reboot_bootloader(void);
#endif // ifdef __cplusplus
#endif /* __UBOOT__ */
#endif /* __ANDROID_BOOTLOADER_MESSAGE_H */

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IPL/Customer/Mobis/V4H_Cx_Loader/include/axmm_register.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AXMM register header
******************************************************************************/
#ifndef AXMM_REGISTER_H__
#define AXMM_REGISTER_H__
#include <stdint.h>
/* System RAM / SDRAM register base address */
#define AXMM_BASE (0xE6780000U)
#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U)
#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U)
#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U)
#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U)
#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U)
#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U)
static inline uint32_t get_dptdivcr_addr(uint32_t num)
{
return ((AXMM_DPTDIVCR + (num * 4U)));
}
static inline uint32_t get_dptrgncr_addr(uint32_t num)
{
return ((AXMM_DPTRGNCR + (num * 4U)));
}
static inline uint32_t get_dptseccr_addr(uint32_t num)
{
return ((AXMM_DPTSECCR + (num * 4U)));
}
static inline uint32_t get_sptdivcr_addr(uint32_t num)
{
return ((AXMM_SPTDIVCR + (num * 4U)));
}
static inline uint32_t get_sptrgncr_addr(uint32_t num)
{
return ((AXMM_SPTRGNCR + (num * 4U)));
}
static inline uint32_t get_sptseccr_addr(uint32_t num)
{
return ((AXMM_SPTSECCR + (num * 4U)));
}
#endif /* AXMM_REGISTER_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Configuration table header
******************************************************************************/
#ifndef CNF_TBL_H_
#define CNF_TBL_H_
#include <stdint.h>
typedef struct{
uint64_t fix;
uint64_t be;
} QOS_SETTING_TABLE;
typedef struct{
uint32_t phys_addr; /* Physical address of Region ID registers. */
uint32_t value; /* setting value of Region ID registers. */
} REGION_ID_SETTING_TABLE;
/* For RAM protection table */
typedef struct {
uint32_t rw_val;
uint32_t sec_val;
}RAM_PROTECTION_VALUE_FORMAT;
typedef struct {
uint32_t read_val;
uint32_t write_val;
}RTRAM_PROTECTION_VALUE_FORMAT;
typedef struct {
uint32_t addr;
RTRAM_PROTECTION_VALUE_FORMAT setting_value;
}RTRAM_PROTECTION_STRUCTUR;
typedef struct {
uint32_t addr;
RAM_PROTECTION_VALUE_FORMAT setting_value;
}SYSTEM_RAM_PROTECTION_STRUCTUR;
typedef struct {
uint64_t addr;
RAM_PROTECTION_VALUE_FORMAT setting_value;
}DRAM_PROTECTION_STRUCTUR;
#if (RCAR_LSI == RCAR_S4)
#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */
#endif /* RCAR_LSI == RCAR_S4 */
#if (RCAR_LSI == RCAR_V4H)
#define RGID_MASTER_MAX (77U) /* Max number of Region registers. (Master) */
#define RGID_READ_MAX (908U) /* Max number of Region registers. (Read) */
#define RGID_WRITE_MAX (907U) /* Max number of Region registers. (Write) */
#define RGID_SEC_MAX (957U) /* Max number of Region registers. (Secure) */
#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */
#elif (RCAR_LSI == RCAR_V4M)
#define RGID_MASTER_MAX (85U) /* Max number of Region registers. (Master) */
#define RGID_READ_MAX (805U) /* Max number of Region registers. (Read) */
#define RGID_WRITE_MAX (804U) /* Max number of Region registers. (Write) */
#define RGID_SEC_MAX (819U) /* Max number of Region registers. (Secure) */
#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */
#endif /* RCAR_LSI == RCAR_V4H */
#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */
#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */
#if (RCAR_LSI == RCAR_V4H)
#define IMP_MASTER_MAX (19U)
#define IMP_SLAVE_MAX (38U)
#endif /* (RCAR_LSI == RCAR_V4H) */
#if (RCAR_LSI == RCAR_V4H)
#define IPMMU_RGID_MAX (11U)
#elif (RCAR_LSI == RCAR_V4M)
#define IPMMU_RGID_MAX (10U)
#endif /* (RCAR_LSI == RCAR_V4H) */
extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX];
extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_master_tbl[RGID_MASTER_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_read_tbl[RGID_READ_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_write_tbl[RGID_WRITE_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX];
#if (RCAR_LSI == RCAR_V4H)
extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX];
extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX];
#endif /* (RCAR_LSI == RCAR_V4H) */
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX];
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX];
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX];
/* For RAM protection */
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX];
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX];
extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX];
extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX];
#endif /* CNF_TBL_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : cpu on function header
******************************************************************************/
/******************************************************************************
* @file cpu_on.h
* - Version : 0.04
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 17.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
* : 09.12.2024 0.03 Remove OTP_MEM_OTPMONITOR60 register.
* : 19.12.2024 0.04 Add definition for booting CR52 core 2.
*****************************************************************************/
#ifndef CPU_ON_H__
#define CPU_ON_H__
#define RCAR_PWR_TARGET_CR (0U)
#define RCAR_PWR_TARGET_CA (1U)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id);
void adj_ca_variant_freq(void);
#define OTP_MEM_1_BASE (0xE61BF000U)
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
#if (RCAR_LSI == RCAR_V4H)
#define VARIANT_V4H_7 (0x00U)
#define VARIANT_V4H_5 (0x01U)
#define VARIANT_V4H_3 (0x02U)
#elif (RCAR_LSI == RCAR_V4M)
#define VARIANT_V4M_7 (0x00U)
#define VARIANT_V4M_5 (0x01U)
#define VARIANT_V4M_3 (0x02U)
#define VARIANT_V4M_2 (0x04U)
#endif /* RCAR_LSI == RCAR_V4H */
#endif /* CPU_ON_H__ */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*/
#ifndef _UBOOT_CRC_H
#define _UBOOT_CRC_H
// #include <compiler.h> /* 'uint*' definitions */
typedef unsigned int uint;
/**
* crc32 - Calculate the CRC32 for a block of data
*
* @crc: Input crc to chain from a previous calculution (use 0 to start a new
* calculation)
* @buf: Bytes to checksum
* @len: Number of bytes to checksum
* @return checksum value
*/
uint32_t crc32(uint32_t crc, const unsigned char *buf, uint len);
/**
* crc32_no_comp - Calculate the CRC32 for a block of data (no one's compliment)
*
* This version uses a different algorithm which doesn't use one's compliment.
* JFFS2 (and other things?) use this.
*
* @crc: Input crc to chain from a previous calculution (use 0 to start a new
* calculation)
* @buf: Bytes to checksum
* @len: Number of bytes to checksum
* @return checksum value
*/
uint32_t crc32_no_comp(uint32_t crc, const unsigned char *buf, uint len);
#endif /* _UBOOT_CRC_H */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc boot header
******************************************************************************/
/******************************************************************************
* @file emmc_boot.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef EMMC_BOOT_
#define EMMC_BOOT_
void emmc_initialize( void );
#endif /* EMMC_BOOT_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc config header
******************************************************************************/
/******************************************************************************
* @file emmc_config.h
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 18.03.2022 0.02 Delete unnecessary define
* Delete unnecessary include file
* : 31.10.2022 0.03 License notation change.
*****************************************************************************/
#ifndef EMMC_CONFIG_H__
#define EMMC_CONFIG_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC driver config */
#define EMMC_RCA (1U) /* RCA */
#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
#define EMMC_CMD_MAX (60U) /* Don't change. */
/* etc */
#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* #ifndef EMMC_CONFIG_H__ */
/* ******************************** END ************************************ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc def header
******************************************************************************/
/******************************************************************************
* @file emmc_def.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef EMMC_DEF_H__
#define EMMC_DEF_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "emmc_std.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
extern st_mmc_base mmc_drv_obj;
/* ************************** FUNCTION PROTOTYPES ************************** */
/* eMMC driver API */
EMMC_ERROR_CODE emmc_init(void);
void import_mmc_drv_obj(void);
void export_mmc_drv_obj(void);
EMMC_ERROR_CODE emmc_terminate(void);
EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode);
EMMC_ERROR_CODE emmc_mount(void);
EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq);
EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg);
EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id);
EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags);
uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom);
/* interrupt service */
uint32_t emmc_interrupt(void);
/* send command API */
EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response);
void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg);
void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual,
uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg);
/* ********************************* CODE ********************************** */
#endif /* #define EMMC_DEF_H__ */
/* ******************************** END ************************************ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc HW Layer header
******************************************************************************/
/******************************************************************************
* @file emmc_hal.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef EMMC_HAL_H__
#define EMMC_HAL_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include <types.h>
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* Memory card response types */
#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* memory access operation */
typedef enum
{
HAL_MEMCARD_READ = 0U, /**< read */
HAL_MEMCARD_WRITE = 1U /**< write */
} HAL_MEMCARD_OPERATION;
/* Type of data width on memorycard bus */
typedef enum
{
HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
/* mode of data transfer */
typedef enum
{
HAL_MEMCARD_DMA = 0U,
HAL_MEMCARD_NOT_DMA = 1U
} HAL_MEMCARD_DATA_TRANSFER_MODE;
/* Memory card response types. */
typedef enum hal_memcard_response_type
{
HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
} HAL_MEMCARD_RESPONSE_TYPE;
/* Memory card command types. */
typedef enum hal_memcard_command_type
{
HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
} HAL_MEMCARD_COMMAND_TYPE;
/* Type of memory card */
typedef enum hal_memcard_command_card_type
{
HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
} HAL_MEMCARD_COMMAND_CARD_TYPE;
/* Memory card application command. */
typedef enum hal_memcard_command_app_norm
{
HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
HAL_MEMCARD_COMMAND_APP = 0x20000U,
HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
} HAL_MEMCARD_COMMAND_APP_NORM;
/* Memory card command codes. */
typedef enum
{
/* class 0 and class 1 */
CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */
CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
/* class 2 */
CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
/* class 3 */
CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
CMD21 = 21, /* CMD21 */
CMD22 = 22, /* CMD22 */
ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
/* class 4 */
CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */
} HAL_MEMCARD_COMMAND;
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* EMMC_HAL_H__ */
/* ******************************** END ************************************ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc multi boot header
******************************************************************************/
/******************************************************************************
* @file emmc_multiboot.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef EMMC_MULTIBOOT_H_
#define EMMC_MULTIBOOT_H_
/* ************************ HEADER (INCLUDE) SECTION *********************** */
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* EMMC */
#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */
#define EMMC_DEV_ERR (0xFFFFFFFFU)
#define EMMC_DEV_ERR_HW (0x00000004U)
#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U)
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize);
/* ******************************** END ************************************ */
#endif /* #ifndef EMMC_MULTIBOOT_H_*/

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc register header
******************************************************************************/
/******************************************************************************
* @file emmc_register.h
* - Version : 0.04
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 24.10.2022 0.02 SDIF_MODE register to support HS200/400
* : 31.10.2022 0.03 License notation change.
* : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel.
*****************************************************************************/
#ifndef EMMC_REGISTERS_H__
#define EMMC_REGISTERS_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include <rcar_register.h>
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC0 channel */
#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */
#define SD_CMD (MMC0_SD_BASE + 0x0000U)
#define SD_ARG (MMC0_SD_BASE + 0x0010U)
#define SD_STOP (MMC0_SD_BASE + 0x0020U)
#define SD_SECCNT (MMC0_SD_BASE + 0x0028U)
#define SD_RSP10 (MMC0_SD_BASE + 0x0030U)
#define SD_RSP32 (MMC0_SD_BASE + 0x0040U)
#define SD_RSP54 (MMC0_SD_BASE + 0x0050U)
#define SD_RSP76 (MMC0_SD_BASE + 0x0060U)
#define SD_INFO1 (MMC0_SD_BASE + 0x0070U)
#define SD_INFO2 (MMC0_SD_BASE + 0x0078U)
#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U)
#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U)
#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U)
#define SD_SIZE (MMC0_SD_BASE + 0x0098U)
#define SD_OPTION (MMC0_SD_BASE + 0x00A0U)
#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U)
#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U)
#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U)
#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U)
#define SOFT_RST (MMC0_SD_BASE + 0x0380U)
#define HOST_MODE (MMC0_SD_BASE + 0x0390U)
#define SDIF_MODE (MMC0_SD_BASE + 0x0398U)
#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U)
#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U)
#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U)
#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U)
#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U)
#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U)
#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U)
#define SCC_DTCNTL (MMC0_SD_BASE + 0x1000U)
#define SCC_TAPSET (MMC0_SD_BASE + 0x1008U)
#define SCC_DT2FF (MMC0_SD_BASE + 0x1010U)
#define SCC_CKSEL (MMC0_SD_BASE + 0x1018U)
#define SCC_SMPCMP (MMC0_SD_BASE + 0x1030U)
#define SCC_TMPPORT2 (MMC0_SD_BASE + 0x1038U)
/* SD_INFO1 Registers */
#define SD_INFO1_INFO2 (0x00000004U) /* Access end*/
#define SD_INFO1_INFO0 (0x00000001U) /* Response end*/
/* SD_INFO2 Registers */
#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy*/
#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable*/
#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable*/
#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0*/
#define SD_INFO2_ALL_ERR (0x0000807FU)
#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */
/* DM_INFO1 Registers */
#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */
#define DM_CM_INFO_DTRANEND1 (0x00100000U) /* DMAC Channel 1 Transfer End */
/* DM_INFO2 Registers */
#define DM_CM_INFO2_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Error */
#define DM_CM_INFO2_DTRANEND1 (0x00020000U) /* DMAC Channel 1 Error */
/* SOFT_RST */
#define SOFT_RST_SDRST (0x00000001U)
/* SD_CLK_CTRL */
#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU)
#define SD_CLK_WRITE_MASK (0x000003FFU)
/* SD_OPTION */
#define SD_OPTION_WIDTH (0x00008000U)
#define SD_OPTION_WIDTH8 (0x00002000U)
#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U)
/* MMC Clock Frequency
* 200MHz * 1/x = output clock
*/
#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */
#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode*/
#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz*/
#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz*/
#define MMC_200MHZ (1U) /* 200MHz * 1/1 = 200 MHz HS200/HS400 mode 200Mhz*/
#define MMC_FREQ_52MHZ (52000000U)
#define MMC_FREQ_26MHZ (26000000U)
#define MMC_FREQ_20MHZ (20000000U)
/* MMC Clock DIV */
#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */
#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
/* DM_CM_DTRAN_MODE */
#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream*/
#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream*/
#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U)
/* CC_EXT_MODE */
#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */
#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */
/* DM_CM_INFO_MASK */
#define DM_CM_INFO_MASK_CLEAR (0xFFEEFEFEU)
#define DM_CM_INFO_CH0_ENABLE (0x00010001U)
#define DM_CM_INFO_CH1_ENABLE (0x00100001U)
/* DM_CM_INFO2_MASK */
#define DM_CM_INFO2_MASK_CLEAR (0xFFFCFFFEU)
#define DM_CM_INFO2_CH0_ENABLE (0x00010001U)
#define DM_CM_INFO2_CH1_ENABLE (0x00020001U)
/* DM_DTRAN_ADDR */
#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U)
/*DM_CM_DTRAN_CTRL */
#define DM_CM_DTRAN_CTRL_START (0x00000001U)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* EMMC_REGISTERS_H__ */
/* ******************************** END ************************************ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : emmc std header
******************************************************************************/
/******************************************************************************
* @file emmc_std.h
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 24.10.2022 0.02 Add supports for HS200/400
* : 31.10.2022 0.03 License notation change.
*****************************************************************************/
#ifndef EMMC_STD_H__
#define EMMC_STD_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "emmc_hal.h"
#include "emmc_registers.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/*CSD register Macros */
#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122))
#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96))
/* for sector access */
#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U)
#define EMMC_SECTOR_SIZE (512U)
#define EMMC_BLOCK_LENGTH (512U)
#define EMMC_BLOCK_LENGTH_DW (128U)
/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
typedef enum
{
EMMC_ERR = 0U, /**< unknown error */
EMMC_SUCCESS , /**< OK */
EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */
EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */
EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */
EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */
EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */
EMMC_ERR_CMD_CRC , /**< command CRC error */
EMMC_ERR_DATA_CRC , /**< data CRC error */
EMMC_ERR_PARAM , /**< parameter error */
EMMC_ERR_RESPONSE , /**< response error */
EMMC_ERR_RESPONSE_BUSY , /**< response busy error */
EMMC_ERR_TRANSFER , /**< data transfer error */
EMMC_ERR_READ_SECTOR , /**< read sector error */
EMMC_ERR_WRITE_SECTOR , /**< write sector error */
EMMC_ERR_STATE , /**< state error */
EMMC_ERR_TIMEOUT , /**< timeout error */
EMMC_ERR_ILLEGAL_CARD , /**< illegal card */
EMMC_ERR_CARD_BUSY , /**< Busy state */
EMMC_ERR_CARD_STATE , /**< card state error */
EMMC_ERR_SET_TRACE , /**< trace information error */
EMMC_ERR_FROM_TIMER , /**< Timer error */
EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */
EMMC_ERR_CARD_POWER , /**< card power fail */
EMMC_ERR_ERASE_SECTOR , /**< erase sector error */
EMMC_ERR_INFO2 , /**< exec cmd error info2 */
RCAR_ERR /**< Error judged by R-Car register */
} EMMC_ERROR_CODE;
/* Error code judged by R-car register or eMMC return*/
#define EMMC_TUNING_FAIL (0U) /* Fail judged by eMMC return*/
#define TUNING_SUCCESS (1U) /* Tuning success */
#define RCAR_TUNING_FAIL (2U) /* Fail judged by R-car register*/
/* Response */
/** R1 */
#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */
#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */
#define EMMC_R1_READY (0x00000100U) /* bit8 */
#define EMMC_R1_STATE_SHIFT (9U)
/** R4 */
#define EMMC_R4_STATUS (0x00008000U)
/** CSD */
#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */
#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */
#define EMMC_TRANSPEED_MULT_SHIFT (3U)
/** OCR */
#define EMMC_HOST_OCR_VALUE (0x40FF8080U)
#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */
#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */
#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U)
/** EXT_CSD */
#define EMMC_EXT_CSD_CARD_TYPE (196U)
#define EMMC_EXT_CSD_PARTITION_CONFIG (179U)
#define EMMC_EXT_CSD_PWR_CL_DDR_200_360 (253U) /* Power class for 200MHz, DDR at VCC= 3.6V */
#define EMMC_EXT_CSD_PWR_CL_200_195 (237U) /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */
#define EMMC_EXT_CSD_PWR_CL_26_195 (201U) /* Power class for 26MHz at 1.95V 1 R */
#define EMMC_EXT_CSD_PWR_CL_52_195 (200U) /* Power class for 52MHz at 1.95V 1 R */
#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U)
#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U)
#define EMMC_EXT_CSD_CARD_TYPE_200MHZ (0x10U)
#define EMMC_EXT_CSD_CARD_TYPE_400MHZ (0x40U)
/** SWITCH (CMD6) argument */
#define EXTCSD_ACCESS_BYTE (0x03000000U) /* H'03000000 */
#define BUS_WIDTH_ADD (183U<<16U) /* H'00b70000 */
#define HS_TIMING_ADD (185U<<16U) /* H'00b90000 */
#define POW_CLASS_ADD (187U<<16U) /* H'00bb0000 */
#define BUS_WIDTH_1 (0U<<8U) /* H'00000000 */
#define BUS_WIDTH_8 (2U<<8U) /* H'00000200 */
#define BUS_WIDTH_8_DDR (6U<<8U) /* H'00000400 */
#define HS_TIMING_1 (1U<<8U) /* H'00000100 */
#define HS_TIMING_HS200 (2U<<8U) /* H'00000200 */
#define HS_TIMING_HS400 (3U<<8U) /* H'00000300 */
#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
#define EMMC_SWITCH_HS200 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200) /**< H'03b90200 */
#define EMMC_SWITCH_HS400 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400) /**< H'03b90300 */
#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
#define EMMC_SWITCH_BUS_WIDTH_8_DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR) /**< H'03b70600 */
#define EMMC_SWITCH_PARTITION_CONFIG (0x03B30000UL) /**< Partition config = 0x00 */
/** for st_mmc_base */
#define EMMC_MAX_RESPONSE_LENGTH (17U)
#define EMMC_MAX_CID_LENGTH (16U)
#define EMMC_MAX_CSD_LENGTH (16U)
#define EMMC_MAX_EXT_CSD_LENGTH (512U)
/* speed mode */
#define TIMING_HIGH_SPEED_OFF (0U)
#define TIMING_HIGH_SPEED (1U)
#define TIMING_HS200 (2U)
#define TIMING_HS400 (3U)
/* MMC Clock Frequency */
/* 200MHz * 1/x = output clock */
#define HS400_50MHZ (8U) /* 400MHz * 1/8 = 50MHz */
#define HS400_200MHZ (2U) /* 400MHz * 1/2 = 200MHz */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* Partition id */
typedef enum
{
PARTITION_ID_USER = 0x0, /**< User Area */
PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
PARTITION_ID_MASK = 0x7 /**< [2:0] */
} EMMC_PARTITION_ID;
/* card state in R1 response [12:9] */
typedef enum
{
EMMC_R1_STATE_IDLE = 0,
EMMC_R1_STATE_READY,
EMMC_R1_STATE_IDENT,
EMMC_R1_STATE_STBY,
EMMC_R1_STATE_TRAN,
EMMC_R1_STATE_DATA,
EMMC_R1_STATE_RCV,
EMMC_R1_STATE_PRG,
EMMC_R1_STATE_DIS,
EMMC_R1_STATE_BTST,
EMMC_R1_STATE_SLEP
} EMMC_R1_STATE;
typedef enum{
ESTATE_BEGIN = 0,
ESTATE_ISSUE_CMD,
ESTATE_NON_RESP_CMD,
ESTATE_RCV_RESP,
ESTATE_RCV_RESPONSE_BUSY,
ESTATE_CHECK_RESPONSE_COMPLETE,
ESTATE_DATA_TRANSFER,
ESTATE_DATA_TRANSFER_COMPLETE,
ESTATE_ACCESS_END,
ESTATE_TRANSFER_ERROR,
ESTATE_ERROR,
ESTATE_END
}EMMC_INT_STATE;
/* eMMC boot driver error information */
typedef struct
{
volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */
volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */
volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */
volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */
} st_error_info;
/* Command information */
typedef struct
{
HAL_MEMCARD_COMMAND cmd; /**< Command information */
uint32_t arg; /**< argument */
HAL_MEMCARD_OPERATION dir; /**< direction */
uint32_t hw; /**< H/W dependence. SD_CMD register value. */
} st_command_info;
/* MMC driver base */
typedef struct
{
st_error_info error_info; /**< error information */
st_command_info cmd_info; /**< command information */
/* for data transfer */
uint32_t *buff_address_virtual; /**< Dest or Src buff */
uint32_t *buff_address_physical; /**< Dest or Src buff */
HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */
uint32_t trans_size; /**< transfer size for this command */
uint32_t remain_size; /**< remain size for this command */
uint32_t response_length; /**< response length for this command */
/* clock */
uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
uint32_t set_freq; /**< Frequency to be set. */
/* state flag */
uint32_t card_power_enable; /**< True : Power ON */
uint32_t clock_enable; /**< True : Clock ON */
uint32_t initialize; /**< True : initialize complete. */
uint32_t mount; /**< True : mount complete. */
uint32_t selected; /**< True : selected card. */
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */
EMMC_R1_STATE current_state; /**< card state */
volatile uint32_t during_transfer; /**< True : during transfer */
volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
volatile uint32_t force_terminate; /**< force terminate flag */
volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
/* timeout */
uint32_t data_timeout; /**< read and write data timeout.*/
/* interrupt */
volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
/* response */
uint32_t *response; /**< pointer to buffer for executing command. */
uint32_t r1_card_status; /**< R1 response data */
uint32_t r3_ocr; /**< R3 response data */
uint32_t r4_resp; /**< R4 response data */
uint32_t r5_resp; /**< R5 response data */
/* Card registers (4byte align) */
uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */
uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */
uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */
uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */
/* SDHI base address */
uintptr_t base_address;
} st_mmc_base;
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
/* ******************************** END ************************************ */
#endif /* EMMC_STD_H__ */
/* EMMC_STD_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : GIC Control Function
******************************************************************************/
/******************************************************************************
* @file gic.h
* - Version : 0.04
* @brief Controls GIC-600 registers and interrupts.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.08.2022 0.01 First Release
* : 20.09.2022 0.02 Set ChildrenAsleep of GICR_WAKER to 1 and end processing
* : 31.10.2022 0.03 License notation change.
* : 04.04.2023 0.04 Removed stdio.h.
*****************************************************************************/
#ifndef GIC_H
#define GIC_H
/*******************************************************************************
** Include Section **
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
** Version Information **
*******************************************************************************/
/*******************************************************************************
** Global Symbols **
*******************************************************************************/
/* GIC base */
#define GICD_BASE (0xF1000000UL)
#define GICR_BASE (GICD_BASE + 0x60000U)
/* Generic Interrupt Controller Distributor (GICD) */
#define GICD_CTLR *((volatile uint32_t *)(GICD_BASE + 0x000U))
#define GICD_IGROUPR(n) *((volatile uint32_t *)(GICD_BASE + 0x080U + 4U*(n)))
#define GICD_ISENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x100U + 4U*(n)))
#define GICD_ICENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x180U + 4U*(n)))
#define GICD_ISPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x200U + 4U*(n)))
#define GICD_ICPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x280U + 4U*(n)))
#define GICD_IPRIORITYR(n) *((volatile uint32_t *)(GICD_BASE + 0x400U + 4U*(n)))
#define GICD_ICFGR(n) *((volatile uint32_t *)(GICD_BASE + 0xC00U + 4U*(n)))
#define GICD_IGRPMODR(n) *((volatile uint32_t *)(GICD_BASE + 0xD00U + 4U*(n)))
#define GICD_IROUTER(n) *((volatile uint64_t *)(GICD_BASE + 0x6000U + 8U*(n)))
/* Generic Interrupt Controller Redistributor (GICR) */
#define GICR_CTLR *((volatile uint32_t *)(GICR_BASE + 0x0000U))
#define GICR_WAKER *((volatile uint32_t *)(GICR_BASE + 0x0014U))
#define GICR_PWRR *((volatile uint32_t *)(GICR_BASE + 0x0024U))
#define CHILDREN_ASLEEP (1U << 2U)
#define PROCESSOR_SLEEP (1U << 1U)
#define RDPOWER_DOWN (1U << 0U)
/*******************************************************************************
** Global Data Types **
*******************************************************************************/
/*******************************************************************************
** Function Prototypes **
*******************************************************************************/
/*******************************************************************************
** Macro **
*******************************************************************************/
/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
/* ICC_SRE_EL3 */
#define ICC_SRE_EN_BIT (8U)
#define ICC_SRE_DIB_BIT (4U)
#define ICC_SRE_DFB_BIT (2U)
#define ICC_SRE_SRE_BIT (1U)
/* SCR_EL3 */
#define SCR_NS_BIT (1U)
/* Affinity Leve mask value */
#define AFFINITY0_MASK (0xFFU)
#define AFFINITY1_MASK (0xFF00U)
#define AFFINITY2_MASK (0xFF0000U)
#define AFFINITY3_MASK (0xFF00000000U)
#define IRM_OFF (0x80000000U)
/* Get ICC_IAR0 */
static inline uint64_t get_ICC_IAR0(void)
{
uint64_t value = 0U;
__asm__ volatile("mrs %0, S3_0_c12_c8_0" : "=r" (value));
return value;
}
/* Set ICC_PMR */
static inline void set_ICC_PMR(uint64_t value)
{
__asm__ volatile ("msr S3_0_C4_C6_0, %0" :: "r" (value));
}
/* Set ICC_IGRPEN0 */
static inline void set_ICC_IGRPEN0(uint64_t value)
{
__asm__ volatile ("msr S3_0_c12_c12_6, %0" :: "r" (value));
}
/* Set ICC_SRE_EL1 */
static inline void set_ICC_SRE_EL1(uint64_t value)
{
__asm__ volatile ("msr S3_0_C12_C12_5, %0" :: "r" (value));
}
/* Get ICC_SRE_EL3 */
static inline uint64_t get_ICC_SRE_EL3(void)
{
uint64_t value = 0U;
__asm__ volatile("mrs %0, S3_6_C12_C12_5" : "=r" (value));
return value;
}
/* Set ICC_SRE_EL3 */
static inline void set_ICC_SRE_EL3(uint64_t value)
{
__asm__ volatile ("msr S3_6_C12_C12_5, %0" :: "r" (value));
}
/* Get MPIDR_EL1 */
static inline uint64_t get_MPIDR_EL1(void)
{
uint64_t value = 0U;
__asm__ volatile("mrs %0, mpidr_el1" : "=r" (value));
return value;
}
/* ISB */
static inline void GIC_isb(void)
{
__asm__ volatile ("isb");
}
/* Enable the interrupt distributor using the GIC's CTLR register */
static inline void GIC_EnableDistributor(void)
{
GICD_CTLR |= 0x31U;
}
/* Disable the interrupt distributor using the GIC's CTLR register */
static inline void GIC_DisableDistributor(void)
{
GICD_CTLR &= 0xFFFFFFFEU;
}
/* Set the interrupt enable from the GIC's ISENABLER register */
static inline void GIC_SetEnable(uint32_t intid, uint32_t value)
{
uint32_t reg = GICD_ISENABLER(intid / 32U);
uint32_t shift = (intid % 32U);
reg &= (~(1U << shift));
reg |= ( (value & 1U) << shift);
GICD_ISENABLER(intid / 32U) = reg;
}
/* Set the interrupt disable from the GIC's ICENABLER register */
static inline void GIC_SetClearEnable(uint32_t intid, uint32_t value)
{
uint32_t reg = GICD_ICENABLER(intid / 32U);
uint32_t shift = (intid % 32U);
reg &= (~(1U << shift));
reg |= ( (value & 1U) << shift);
GICD_ICENABLER(intid / 32U) = reg;
}
/* Sets the interrupt configuration using GIC's ICFGR register */
static inline void GIC_SetConfiguration(uint32_t intid, uint32_t int_config)
{
uint32_t icfgr = GICD_ICFGR(intid / 16U);
uint32_t shift = (intid % 16U) << 1U;
icfgr &= (~(3U << shift));
icfgr |= ( int_config << shift);
GICD_ICFGR(intid / 16U) = icfgr;
}
/* Set the priority for the given interrupt in the GIC's IPRIORITYR register */
static inline void GIC_SetPriority(uint32_t intid, uint32_t priority)
{
uint32_t mask = GICD_IPRIORITYR(intid / 4U);
uint32_t shift = ((intid % 4U) * 8U);
mask &= (~(0xFFU << shift));
mask |= ( (priority & 0xFFU) << shift);
GICD_IPRIORITYR(intid / 4U) = mask;
}
/* Set the interrupt group from the GIC's IGROUPR register */
static inline void GIC_SetGroup(uint32_t intid, uint32_t group)
{
uint32_t igroupr = GICD_IGROUPR(intid / 32U);
uint32_t shift = (intid % 32U);
igroupr &= (~(1U << shift));
igroupr |= ( (group & 1U) << shift);
GICD_IGROUPR(intid / 32U) = igroupr;
}
/* Set the interrupt group from the GIC's IGRPMODR register */
static inline void GIC_SetGrpMode(uint32_t intid, uint32_t mode)
{
uint32_t imode = GICD_IGRPMODR(intid / 32U);
uint32_t shift = (intid % 32U);
imode &= (~(1U << shift));
imode |= ( (mode & 1U) << shift);
GICD_IGRPMODR(intid / 32U) = imode;
}
/* Set the interrupt routing from the GIC's IROUTER register */
static inline void GIC_SetRouter(uint32_t intid)
{
uint64_t affinity = 0U;
/* Get Affinity level */
affinity = get_MPIDR_EL1();
affinity &= (AFFINITY0_MASK | AFFINITY1_MASK | AFFINITY2_MASK | AFFINITY3_MASK);
/* Interrupt routing mode bit OFF */
affinity &= (~(IRM_OFF));
GICD_IROUTER(intid) = affinity;
}
/* Get power register value from the GIC's GICR_PWRR register */
static inline uint32_t GIC_Getpwwr(void)
{
return (GICR_PWRR);
}
/* Set power register value from the GIC's GICR_PWRR register */
static inline void GIC_Setpwwr(uint32_t set_value)
{
GICR_PWRR = set_value;
}
/* Get power management cotrol register from the GIC's GICR_WAKER register */
static inline uint32_t GIC_Getwaker(void)
{
return (GICR_WAKER);
}
/* Set power management cotrol register from the GIC's GICR_WAKER register */
static inline void GIC_Setwaker(uint32_t set_value)
{
GICR_WAKER = set_value;
}
/* Enables the given interrupt using GIC's ISENABLER register */
static inline void GIC_EnableFIQ(uint32_t intid)
{
/* Disable interrupt forwarding */
GIC_DisableDistributor();
/* Set level-sensitive */
GIC_SetConfiguration(intid, 0U);
/* Set priority */
GIC_SetPriority(intid, 0U);
/* Set group 0 (secure) */
GIC_SetGroup(intid, 0U);
/* Set group 0 (secure) */
GIC_SetGrpMode(intid, 0U);
/* Enable distributor */
GIC_EnableDistributor();
/* Enable the SPI interrupt */
GIC_SetEnable(intid, 1U);
/* Set the interrupt routing */
GIC_SetRouter(intid);
}
/* Enable the interrupt redistributor wakeup */
static inline void GIC_WakeupRedistributor(void)
{
uint32_t get_value = 0U;
uint32_t set_value = 0U;
get_value = GIC_Getpwwr();
set_value = get_value & ~(RDPOWER_DOWN);
GIC_Setpwwr(set_value);
get_value = GIC_Getwaker();
set_value = get_value & ~(PROCESSOR_SLEEP);
GIC_Setwaker(set_value);
do
{
get_value = GIC_Getwaker();
}while((get_value & CHILDREN_ASLEEP) == CHILDREN_ASLEEP);
}
/* Enable the CPU's interrupt interface */
static inline void GIC_EnableInterface(void)
{
uint64_t reg = 0U;
uint64_t icc_sre_el3 = 0U;
/* Disable the legacy interrupt bypass */
icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
reg = get_ICC_SRE_EL3();
set_ICC_SRE_EL3(reg | icc_sre_el3);
set_ICC_SRE_EL1(ICC_SRE_SRE_BIT);
GIC_isb();
set_ICC_IGRPEN0(1U); /* enable interface grp0 */
GIC_isb();
}
/* Disable the CPU's interrupt interface */
static inline void GIC_DisableInterface(uint32_t intid)
{
uint32_t get_value = 0U;
uint32_t set_value = 0U;
/* Clear Enable the SPI interrupt */
GIC_SetClearEnable(intid, 1U);
/* Set ChildrenAsleep of GICR_WAKER to 1 and end processing */
get_value = GIC_Getwaker();
set_value = get_value | PROCESSOR_SLEEP;
GIC_Setwaker(set_value);
do
{
get_value = GIC_Getwaker();
}while((get_value & CHILDREN_ASLEEP) != CHILDREN_ASLEEP);
}
/* Read the CPU's IAR register */
static inline uint32_t GIC_AcknowledgePending(void)
{
return (uint32_t)(get_ICC_IAR0());
}
/* Set the interrupt priority mask using CPU's PMR register */
static inline void GIC_SetInterfacePriorityMask(uint64_t priority)
{
/* Specify F8. 32 priority levels are bit0-2 invalid */
set_ICC_PMR(priority << 3U);
}
/* Initialize and enable the GIC */
static inline void GIC_Enable(void)
{
GIC_WakeupRedistributor();
/* Enable interface */
GIC_EnableInterface();
/* Set priority mask */
GIC_SetInterfacePriorityMask(0xFFUL);
}
/*******************************************************************************
** Function **
*******************************************************************************/
/* Interrupt configuration */
#define Interrupt_Config(void) GIC_Enable(void)
/* Enable */
#define Interrupt_Enable(intid) GIC_EnableFIQ((uint32_t)intid)
/* Disable */
#define Interrupt_Disable(intid) GIC_DisableInterface((uint32_t)intid)
#endif /* GIC_H */
/*******************************************************************************
** End of File **
*******************************************************************************/

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : HSCIF register header
******************************************************************************/
/******************************************************************************
* @file hscif_register.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef HSCIF_REGISTER_H_
#define HSCIF_REGISTER_H_
#include <rcar_register.h>
/* HSCIF0 base address */
/* 0xE6540000U */
#define HSCIF0_BASE (BASE_HSCIF_ADDR)
#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */
#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */
#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */
#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */
#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */
#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */
#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */
#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */
#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */
#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */
#endif /* HSCIF_REGISTER_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file image_load.h
* - Version : 0.09
* @brief Access protection setting driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 10.02.2022 0.02 Change the number of CA programs
* : 17.02.2022 0.03 Support AArch32
* : 18.05.2022 0.04 Integrated LOAD_INFO
* Defined value integration
* Remove unused define values
* Changed to processing for each device
* Change structure member name
* Remove LOGICAL_CONTENT_CERT_ADDR
* Add get_logic_cont_cert_addr
* Change the argument type of get_src_addr_offset_in_cert
* Added argument check
* Remove unnecessary macros
* Add argument of load_init()
* Change for memory map update
* : 16.06.2022 0.05 Change log output
* Support secure boot for S4
* : 31.10.2022 0.06 License notation change.
* : 21.08.2023 0.07 Add support for V4M.
* : 19.12.2024 0.08 Add definitions for RTOS#1 and RTOS#2.
* : 26.05.2025 0.09 Change address and size of CA program2.
*****************************************************************************/
#ifndef LOAD_IMAGE_H_
#define LOAD_IMAGE_H_
#include "log.h"
/* define */
/* For Build Option RTOS_LOAD_NUM */
#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */
#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
/* For Build Option OPTEE_LOAD_ENABLE */
#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */
#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */
/* For Build Option BL2_LOAD_ENABLE */
#define BL2_DISABLE (0U) /* Load BL2 image disable. */
#define BL2_ENABLE (1U) /* Load BL2 image enable. */
/* For Build Option QNX_OS_LOAD_ENABLE */
#define QNX_OS_DISABLE (0U) /* Load QNX_OS image disable. */
#define QNX_OS_ENABLE (1U) /* Load QNX_OS image enable. */
/* DRAM address */
#define DRAM_BASE (0x40000000U)
#define DRAM_SIZE (0x80000000U)
#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
/* RT-SRAM */
/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */
#define RTSRAM_BASE (0xEB200000U)
#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */
#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
/* RT-VRAM */
/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */
#define RTVRAM_BASE (0xE2000000U)
#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */
#define RTVRAM_VBUF_28M (28U) /* 28MB */
#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */
#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */
#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U)
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define RTVRAM_8WAY_28M_SRAM_SIZE (0x00010000U) /* 64KiB */
#define RTVRAM_SRAM_TOP (RTVRAM_BASE)
#define RTVRAM_SRAM_END (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U) /* 0xE2000000 - 0xE200FFFF */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* System RAM */
#define SYSRAM_BASE (0xE6300000U)
#if (RCAR_LSI == RCAR_S4)
#define SYSRAM_SIZE (384U * 1024U) /* 384KB */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */
#endif /* RCAR_LSI == RCAR_S4 */
#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U)
/* Cx Loader */
#define IPL_TOP (0xE6300000U)
#define IPL_SIZE (0x00030000U) /* 192KiB */
#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U)
/* Certificate size */
#define CONTENT_CERT_OFFSET (0x00006000U) /* certificate top offset */
#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header area size(4KiB) */
#define CONTENT_CERT_DST_SIZE (0x00000800U) /* content cert dst size */
#define KEY_CERT_SIZE (0x00002000U) /* Key cert area size(8KiB) */
/* Load ID */
#define RTOS_ID (1U)
#define CA_PROGRAM_ID (2U)
#define CA_OPTIONAL_ID (6U)
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define RTOS1_ID (16U) /* 16:RTOS#1 */
#define RTOS2_ID (17U) /* 17:RTOS#2 */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* Number of Max loading image */
#define CA_MAX_IMAGE (8U) /* CA Load program MAX image num */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
#define MAX_PLACED (16U) /* Load program MAX image num */
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define MAX_PLACED (18U) /* Load program MAX image num */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */
#define TARGET_MEM_DRAM (0U)
#define TARGET_MEM_RTSRAM (1U)
#define TARGET_MEM_RTVRAM (2U)
#define TARGET_MEM_SYSRAM (3U)
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define TARGET_MEM_SRAM_IN_RTVRAM (4U)
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* get info from cert address offset */
#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */
/* Certificate logical address */
#define CONTENT_CERT_DEST_ADDR (0xEB230000U)
#define CONTENT_CERT_DEST_SIZE (0x00008000U) /* 32KB */
/* BL31/BL32(S4), BL31/tee-OS/u-boot(V4H) check */
/* check image num */
#ifdef MOBIS_PRK3
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#error "OPTEE_LOAD_ENABLE==1 should be for PRK3"
#endif
#if (BL2_LOAD_ENABLE == BL2_DISABLE)
#error "BL2_LOAD_ENABLE==1 should be for PRK3"
#endif
#if (QNX_OS_LOAD_ENABLE == QNX_OS_DISABLE)
#error "QNX_OS_LOAD_ENABLE==1 should be for PRK3"
#endif
#define CA_IMAGESIZECHK_DEF (5U)
#else
#define CA_IMAGESIZECHK_DEF (2U)
#endif
/* load_id */
#define CA_PROGRAM1_ID (6U) /* bl31 */
#define CA_PROGRAM2_ID (7U) /* u-boot */
#define CA_PROGRAM3_ID (8U) /* tee-os */
#define CA_PROGRAM4_ID (9U) /* ca76-loader */
#define CA_PROGRAM5_ID (10U) /* qnx OS */
#define CA_BL2_ID CA_PROGRAM4_ID
#define CA_QNX_OS_ID CA_PROGRAM5_ID
#define CA_PROGRAM1_ADR (0x46400000U)
#define CA_PROGRAM1_SIZE (0x00022000U)
#if (RCAR_LSI == RCAR_S4)
#define CA_PROGRAM2_ADR (0x44100000U)
#define CA_PROGRAM2_SIZE (0x00100000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define CA_PROGRAM2_ADR (0x00000000U)
#define CA_PROGRAM2_SIZE (0x00000000U)
#endif /* RCAR_LSI == RCAR_S4 */
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
#define CA_PROGRAM3_ADR (0x44100000U)
#define CA_PROGRAM3_SIZE (0x00100000U)
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
#if (BL2_LOAD_ENABLE == BL2_ENABLE)
#define CA_PROGRAM4_ADR (0x41D00000U)
#define CA_PROGRAM4_SIZE (0x00020000U) /* 128KB */
#endif /* BL2_LOAD_ENABLE == BL2_ENABLE */
#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE)
#define CA_PROGRAM5_ADR (0x50100000U)
#define CA_PROGRAM5_SIZE (0x00800000U) /* 8MB */
#endif /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */
/* key cert address */
#define TFMV_KEY_CERT_ADDR (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */
#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xEB233000 */
/* struct */
/* load image range */
typedef struct {
uint32_t load_id;
uint32_t image_adr;
uint32_t image_size;
} IMAGE_RANGE;
/* load address range */
typedef struct {
uint32_t cx_topadd;
uint32_t cx_endadd;
} ADDRESS_RANGE;
/* load info */
typedef struct{
const char *name; /* store load image name */
uint32_t image_size; /* store image size */
uint32_t boot_addr; /* store boot address of image */
uint32_t key_cert_addr; /* store key cert address */
uint32_t cnt_cert_addr; /* store content cert address */
uint32_t src_addr; /* store source address */
uint32_t part_num; /* store eMMC partition number */
uint32_t load_id; /* store Load ID */
uint32_t cmac[4U]; /* store cmac */
} LOAD_INFO;
static inline uint32_t get_src_addr_offset_in_cert(uint32_t id)
{
/* INT30-C Pre confirmation */
if (id > UINT32_MAX / 0x10U)
{
ERROR("get_src_addr_offset_in_cert id error.\n");
panic;
}
return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U));
}
static inline uint32_t get_logic_cont_cert_addr(uint32_t num)
{
/* INT30-C Pre confirmation */
if (num > UINT32_MAX / 0x10U)
{
ERROR("get_logic_cont_cert_addr num error.\n");
panic;
}
return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE));
}
/* Prototype */
void load_image(LOAD_INFO* li);
void load_init(LOAD_INFO* li, uint32_t num);
void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot);
void load_start(LOAD_INFO* li);
#endif /* LOAD_IMAGE_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function for eMMC header
******************************************************************************/
/******************************************************************************
* @file image_load_emmc.h
* - Version : 0.05
* @brief Access protection setting driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 17.02.2022 0.02 Support AArch32
* : 10.05.2022 0.03 Defined value integration
* Change the argument type of get_part_num_in_cert
* Added argument check
* Changed define name
* Change log output
* Change the direct value reference
* Remove Prototype
* : 08.07.2022 0.04 Change log output
* Adds the defined used in the emmc_trans_data argument
* : 31.10.2022 0.05 License notation change.
*****************************************************************************/
#ifndef LOAD_IMAGE_EMMC_H_
#define LOAD_IMAGE_EMMC_H_
#include <image_load.h>
#include <log.h>
/* define */
/* eMMC */
#define CX_EMMC_TOP (0x00000000U)
#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */
#define CX_EMMC_END ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U)
#define SRC_TOP (CX_EMMC_TOP)
/* For eMMC */
#define CX_EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
#define CX_EMMC_SECTOR_SIZE (512U)
#define CX_EMMC_CONTENT_CERT_ADDR (0x00240000U)
#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT)
/* A side certificate setting */
/* RT-SRAM Offset */
#define SEC_BOOT_KEY_CERT_OFFSET (0x00001000U)
#define SEC_DEBUG_SEC_CERT_OFFSET (0x00006000U)
/* A side RT-SRAM physical address */
/* RT-SRAM(0xEB200000) + CERT_OFFSET */
#define SEC_BOOT_KEY_CERT_ADDR (ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET)
/* A/B side certificate setting */
/* Boot side Offset */
#define CERT_OFFSET_2ND (0x8000U)
/* A/B side RT-SRAM physical address */
/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/
#define GET_SEC_BOOT_KEY_CERT_ADDR(a) ((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a)))
#define SEC_DEBUG_CERT_SIZE (6396U)
static inline void load_image_info_print_for_emmc(LOAD_INFO* li)
{
NOTICE("======== %s image load info ========\n", li->name);
NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n"
"source address \t= (p:%u)0x%x\n",
(unsigned int)li->boot_addr, (unsigned int)(li->image_size),
(unsigned int)li->part_num, (unsigned int)li->src_addr );
}
static inline uint32_t get_part_num_in_cert(uint32_t id)
{
/* INT30-C Pre confirmation */
if (UINT32_MAX - id < 1U)
{
ERROR("get_part_num_in_cert id error.\n");
panic;
}
return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U));
}
#endif /* LOAD_IMAGE_EMMC_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : inline asm func header
******************************************************************************/
#ifndef INLINE_ASM_H__
#define INLINE_ASM_H__
#if defined(__RH850G3K__)
static inline void syncm(void)
{
__asm__ __volatile__ ("SYNCM");
}
static inline void synci(void)
{
__asm__ __volatile__ ("SYNCI");
}
#else
static inline void syncm(void)
{
__asm__ volatile ("dsb");
}
static inline void synci(void)
{
__asm__ volatile ("dsb");
__asm__ volatile ("isb");
}
#endif
#endif /* INLINE_ASM_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : INTC header
******************************************************************************/
/******************************************************************************
* @file interrupt.h
* - Version : 0.05
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
* : 15.12.2022 0.03 V4H interrupt support.
* : 27.12.2022 0.04 Change argument of pabort_error.
* : 21.08.2023 0.05 Add support for V4M.
*****************************************************************************/
#ifndef INTERRUPT_H_
#define INTERRUPT_H_
/* Prototype */
#if (RCAR_LSI == RCAR_S4)
extern void handler_fiq(void);
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar);
void pabort_error(uint32_t ifsr, uint32_t ifar);
void Undefined_error(uint32_t occ_add);
#endif /* RCAR_LSI == RCAR_S4 */
extern void handler_error(uint32_t ex_type);
#endif /* INTERRUPT_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : IP's control header
******************************************************************************/
/******************************************************************************
* @file ip_control.h
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 02.08.2022 0.02 Added define value
* : 31.10.2022 0.03 License notation change.
*****************************************************************************/
#ifndef IP_CONTROL_H_
#define IP_CONTROL_H_
#define INTC_SPI_SWDT (548U)
/* Prototype */
void ip_init(void);
void ip_release(void);
#endif /* IP_CONTROL_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main header
******************************************************************************/
/******************************************************************************
* @file loader_main.h
* - Version : 0.34
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 18.02.2022 0.02 Updated IPL_VERSION 0.7.0
* : 22.03.2022 0.03 Updated IPL_VERSION 0.8.0
* : 20.05.2022 0.04 Updated IPL_VERSION 0.9.0
* : 12.07.2022 0.05 Updated IPL_VERSION 0.11.0
* : 22.08.2022 0.06 Updated IPL_VERSION 0.12.0
* : 03.10.2022 0.07 Updated IPL_VERSION 0.13.0
* : 27.10.2022 0.08 Updated IPL_VERSION 0.14.0
* : 31.10.2022 0.09 License notation change.
* : 07.11.2022 0.10 Removed unnecessary define values.
* : 14.12.2022 0.11 Updated IPL_VERSION 0.15.0
* : 08.02.2023 0.12 Updated IPL_VERSION 0.17.0
* : 17.02.2023 0.13 Updated IPL_VERSION 0.17.1
* : 24.04.2023 0.14 Updated IPL_VERSION 0.18.0
* : 22.05.2023 0.15 Updated IPL_VERSION 0.19.0
* : 19.06.2023 0.16 Updated IPL_VERSION 0.21.0
* : 22.08.2023 0.17 Updated IPL_VERSION 1.25.0
* : 19.09.2023 0.18 Updated IPL_VERSION 1.30.0
* : 23.10.2023 0.19 Updated IPL_VERSION 1.31.0
* : 17.11.2023 0.20 Updated IPL_VERSION 1.41.0
* : 26.01.2024 0.21 Updated IPL_VERSION 1.42.0
* : 07.02.2024 0.22 Updated IPL_VERSION 1.44.0
* : 05.04.2024 0.23 Updated IPL_VERSION 1.45.0
* : 11.06.2024 0.24 Updated IPL_VERSION 1.48.0
* : 19.08.2024 0.25 Updated IPL_VERSION 1.50.0
* : 19.09.2024 0.26 Updated IPL_VERSION 1.51.2
* : 22.10.2024 0.27 Updated IPL_VERSION 1.52.0
* : 23.10.2024 0.28 Updated IPL_VERSION 1.53.0
* : 28.10.2024 0.29 Updated IPL_VERSION 1.53.1
* : 28.10.2024 0.30 Updated IPL_VERSION 1.54.0
* : 05.12.2024 0.31 Updated IPL_VERSION 1.55.0
* : 08.01.2025 0.32 Updated IPL_VERSION 1.56.0
* : 09.04.2025 0.33 Updated IPL_VERSION 1.57.0
* : 26.05.2025 0.34 Updated IPL_VERSION 1.58.0
*****************************************************************************/
#ifndef LOADER_MAIN_H_
#define LOADER_MAIN_H_
/* define */
#define IPL_VERSION "1.58.0"
/* Global */
extern const char build_message[];
/* prototype */
uint32_t loader_main(void);
#endif /* LOAD_MAIN_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main common header
******************************************************************************/
#ifndef LOADER_MAIN_COMMON_H_
#define LOADER_MAIN_COMMON_H_
#include <image_load.h>
/* prototype */
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
void smoni_set_param(uintptr_t smoni_entry_point,
uintptr_t uboot_entry_point);
#else
void smoni_set_param(uintptr_t smoni_entry_point,
uintptr_t uboot_entry_point,
uintptr_t tee_entry_point);
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#endif /* LOADER_MAIN_COMMON_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Definitions used by the MMU.
******************************************************************************/
/******************************************************************************
* @file loader_mmu_table.h
* - Version : 0.01
* @brief MMU define.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 14.12.2022 0.01 First Release
*****************************************************************************/
#ifndef MMU_TABLE_H_
#define MMU_TABLE_H_
#include <stdint.h> /* for uint32_t */
/* b[1:0] Block and Table descriptors */
#define MMU_TBL_TYPE_TABLE (3UL << 0)
#define MMU_TBL_TYPE_BLOCK (1UL << 0)
#define MMU_TBL_TYPE_PAGE (3UL << 0)
/* Lower attributes:SH[1:0] unused */
#define MMU_TBL_BLOCK_OUTER_SHARE (2ULL << 8)
#define MMU_TBL_BLOCK_INNER_SHARE (3ULL << 8)
/* Lower attributes:AF[10] */
#define MMU_TBL_BLOCK_AF (1UL << 10)
/* Lower attributes:AP[2:1] access permissions model */
#define MMU_TBL_AP_APP_RW (1UL << 6)
#define MMU_TBL_AP_APP_R (3UL << 6)
/* Lower attributes:AttrIndx[2:0] */
#define MMU_TBL_ATTRINDX0 (0UL << 2) /* Device-nGnRnE memory */
#define MMU_TBL_ATTRINDX1 (1UL << 2) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
#define MMU_TBL_ATTRINDX2 (2UL << 2) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
/* Upper attributes:Block descriptors */
#define MMU_TBL_BLOCK_XN (1UL << 54)
#define MMU_TBL_BLOCK_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
#define MMU_TBL_BLOCK_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
#define MMU_TBL_BLOCK_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
/* Level 3 */
#define MMU_TBL_PAGE_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
#define MMU_TBL_PAGE_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
#define MMU_TBL_PAGE_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
extern const uint64_t g_loader_level1_table[];
extern const uint64_t g_loader_level2_table[];
extern const uint64_t g_loader_level3_table[];
#endif /* MMU_TABLE_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : log header file
******************************************************************************/
/******************************************************************************
* @file log.h
* - Version : 0.06
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 12.05.2022 0.02 Changed __LOG_H__ to LOG_H_
* Changed panic (Static analysis)
* : 16.06.2022 0.03 Change log output
* : 31.10.2022 0.04 License notation change.
* : 07.11.2022 0.05 Change log macro.
* : 04.04.2023 0.06 Removed stdio.h.
*****************************************************************************/
#ifndef LOG_H_
#define LOG_H_
#include <stdbool.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) log_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) log_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) log_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) log_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) log_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#define panic \
do { \
log_printf("P:%s\n", __func__); \
while(true){} \
} while (false)
void log_printf(const char *fmt, ...);
void gpio_N1307(int set);
void gpio_N1305(int set);
#endif /* LOG_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory access driver header
******************************************************************************/
/******************************************************************************
* @file mem_io.h
* - Version : 0.05
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 17.02.2022 0.02 Change the return type of mem_read64
* : 31.10.2022 0.03 License notation change.
* : 07.11.2022 0.04 Added to convert mmio.
* : 21.08.2023 0.05 Add support for V4M.
*****************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
static inline void mem_write8(uintptr_t addr, uint8_t data)
{
*(volatile uint8_t*)addr = data;
}
static inline uint8_t mem_read8(uintptr_t addr)
{
return (*(volatile uint8_t*)addr);
}
static inline void mem_write16(uintptr_t addr, uint16_t data)
{
*(volatile uint16_t*)addr = data;
}
static inline uint16_t mem_read16(uintptr_t addr)
{
return (*(volatile uint16_t*)addr);
}
static inline void mem_write32(uintptr_t addr, uint32_t data)
{
*(volatile uint32_t*)addr = data;
}
static inline uint32_t mem_read32(uintptr_t addr)
{
return (*(volatile uint32_t*)addr);
}
static inline void mem_write64(uintptr_t addr, uint64_t data)
{
*(volatile uint64_t*)addr = data;
}
static inline uint64_t mem_read64(uintptr_t addr)
{
return (*(volatile uint64_t*)addr);
}
static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
}
static inline void mem_bitset32(uintptr_t addr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) | set) );
}
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
#endif /* MEM_IO_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS driver header
******************************************************************************/
#ifndef QOS_INIT_H_
#define QOS_INIT_H_
extern void qos_init(void);
#endif /* QOS_INIT_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2024-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RAM protection driver header
******************************************************************************/
#ifndef RAM_PROTECTION_H_
#define RAM_PROTECTION_H_
#include <stdint.h>
#include <image_load.h>
#define RTVRAM0_AREA1_TOP (0xE0040000U)
#define RTVRAM0_ADDR_END (0xE0100000U)
#define RTVRAM1_AREA1_TOP (0xE2010000U)
#define RTVRAM1_AREA2_TOP (0xE2100000U)
#define RTVRAM1_ADDR_END (0xE3C00000U)
#define SYSTEM_RAM_AREA1_TOP (0xE635E000U)
#define SYSTEM_RAM_AREA2_TOP (0xE6360000U)
#define SYSTEM_RAM_ADDR_END (0xE6400000U)
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
#define DRAM_ADDR_AREA2 (0x0401D00000ULL)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define DRAM_ADDR_AREA3 (0x0406400000ULL)
#define DRAM_ADDR_AREA4 (0x0406440000ULL)
#define DRAM_ADDR_AREA5 (0x0407FC0000ULL)
#define DRAM_ADDR_AREA6 (0x0408000000ULL)
#define DRAM_ADDR_AREA7 (0x041DC00000ULL)
#define DRAM_ADDR_AREA8 (0x0420000000ULL)
#define DRAM_ADDR_AREA9 (0x0440000000ULL)
#define DRAM_ADDR_AREA10 (0x0460000000ULL)
#define DRAM_ADDR_AREA11 (0x0480000000ULL)
#define DRAM_ADDR_AREA12 (0x0500000000ULL)
#define DRAM_ADDR_AREA13 (0x0600000000ULL)
#else
#define DRAM_ADDR_AREA3 (0x0404100000ULL)
#define DRAM_ADDR_AREA4 (0x0406400000ULL)
#define DRAM_ADDR_AREA5 (0x0406440000ULL)
#define DRAM_ADDR_AREA6 (0x0407E00000ULL)
#define DRAM_ADDR_AREA7 (0x0407F00000ULL)
#define DRAM_ADDR_AREA8 (0x0407FC0000ULL)
#define DRAM_ADDR_AREA9 (0x0408000000ULL)
#define DRAM_ADDR_AREA10 (0x041DC00000ULL)
#define DRAM_ADDR_AREA11 (0x0420000000ULL)
#define DRAM_ADDR_AREA12 (0x0440000000ULL)
#define DRAM_ADDR_AREA13 (0x0460000000ULL)
#define DRAM_ADDR_AREA14 (0x0480000000ULL)
#define DRAM_ADDR_AREA15 (0x0500000000ULL)
#define DRAM_ADDR_AREA16 (0x0600000000ULL)
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#else
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
#define DRAM_ADDR_AREA2 (0x0406400000ULL)
#define DRAM_ADDR_AREA3 (0x0406440000ULL)
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#define DRAM_ADDR_END (0x0700000000ULL)
#define NOT_USED_VALUE (0x00000000U)
/* RAM DIVISION AREA ID */
/* RT-SRAM */
#define RTVRAM0_ICUMX_IPL_AREA (0U) /* 0xEB200000 -- 0xEB23FFFF */
#define RTVRAM0_ICUMX_FW_AREA (1U) /* 0xEB240000 -- 0xEB2FFFFF */
/* RT-VRAM */
#define RTVRAM1_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */
#define RTVRAM1_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */
#define RTVRAM1_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */
/* System RAM */
#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */
#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */
/* SDRAM */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */
#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF
* OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */
#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF
* OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */
#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
#else
#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */
#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */
#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */
#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */
#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#if (RCAR_LSI == RCAR_V4H)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#else
#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#elif (RCAR_LSI == RCAR_V4M)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#else
#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#endif /* RCAR_LSI == RCAR_V4H */
#else
#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */
#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */
#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#endif /* RAM_PROTECTION_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : R-Car common header
******************************************************************************/
/******************************************************************************
* @file rcar_def.h
* - Version : 0.05
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 17.02.2022 0.02 Support V4H
* : 31.10.2022 0.03 License notation change.
* : 23.05.2023 0.04 Add the define "PRR_PRODUCT_21" for V4H v2.1.
* : 21.08.2023 0.05 Add support for V4M.
*****************************************************************************/
#ifndef RCAR_DEF_H_
#define RCAR_DEF_H_
/* Product Register */
#define PRR (0xFFF00044U) /* PRR register */
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
#define PRR_MAJOR_OFFSET (1U)
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
#define PRR_PRODUCT_21 (0x00000011U) /* ver 2.1 */
#define PRR_PRODUCT_22 (0x00000012U) /* ver 2.2 */
#endif /* RCAR_DEF_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : rcar register header
******************************************************************************/
/******************************************************************************
* @file rcar_register.h
* - Version : 0.07
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 17.02.2022 0.02 Add APMU
* Support AArch32
* : 09.05.2022 0.03 Changed to processing for each device
* : 24.10.2022 0.04 Add supports for HS200/400
* : 31.10.2022 0.05 License notation change.
* : 07.11.2022 0.06 Added QOS and RTVRAM related registers.
* : 21.08.2023 0.07 Add support for V4M.
*****************************************************************************/
#ifndef RCAR_REGISTER_H_
#define RCAR_REGISTER_H_
#include <stdint.h>
#define BASE_ADDR_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET */
#define BASE_ADDR_RPC (0xEE200000U) /* RPC */
#if (RCAR_LSI == RCAR_S4)
#define BASE_ADDR_SCIF (0xE6C00000U) /* SCIF */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ADDR_SCIF (0xE6E00000U) /* SCIF */
#endif /* RCAR_LSI == RCAR_S4 */
#define BASE_ADDR_MMC (0xEE000000U) /* MMC */
#define BASE_ADDR_HSCIF (0xE6400000U) /* HSCIF */
#define BASE_AP_CORE_ADDR (0xE6280000U) /* ECM */
/* Base address offset of each register */
/* CPGA */
#define OFFSET_CPGA (0x00150000U)
/* RESET */
#define OFFSET_RESET (0x00160000U)
/* APMU */
#define OFFSET_APMU (0x00170000U)
/*RPC*/
#define OFFSET_RPC (0x00000000U)
/*SCIF*/
#if (RCAR_LSI == RCAR_S4)
#define OFFSET_SCIF3 (0x00050000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define OFFSET_SCIF0 (0x00060000U)
#endif /* RCAR_LSI == RCAR_S4 */
/* SDHI2/MMC0 */
#define OFFSET_SDHI (0x00140000U)
/* HSCIF */
#define OFFSET_HSCIF0 (0x00140000U)
/* PFC0 */
#define OFFSET_PFC0 (0x00050000U)
/* PFC1 */
#if (RCAR_LSI == RCAR_S4)
#define OFFSET_PFC1 (0x00051000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define OFFSET_PFC1 (0x00058000U)
#endif /* RCAR_LSI == RCAR_S4 */
/* Port Group */
#define OFFSET_PORTGR (0x00000800U)
/* CPGWPR */
#define OFFSET_CPG_CPGWPR (0x00000000U)
/* SD0CKCR */
#define OFFSET_CPG_SD0CKCR (0x00000870U)
/* PLL2CR0 */
#define OFFSET_CPG_PLL2CR0 (0x00000834U)
/* PLLECR */
#define OFFSET_CPG_PLLECR (0x00000820U)
/* QOS */
#define ICU_CC (0xE6600000U) /* CC63S,I2C,AXMM,QoS */
#define ICU_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */
#define BASE_CCI_ADDR (ICU_CC + ICU_OFFSET_CCI)
/* RTVRAM */
#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL)
#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */
#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
#define BASE_RESET_ADDR (BASE_ADDR_PFC + OFFSET_RESET)
#define BASE_APMU_ADDR (BASE_ADDR_PFC + OFFSET_APMU)
#define BASE_RPC_ADDR (BASE_ADDR_RPC + OFFSET_RPC)
#if (RCAR_LSI == RCAR_S4)
#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF3)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF0)
#endif /* RCAR_LSI == RCAR_S4 */
#define BASE_MMC0_ADDR (BASE_ADDR_MMC + OFFSET_SDHI)
#define BASE_HSCIF_ADDR (BASE_ADDR_HSCIF + OFFSET_HSCIF0)
#define BASE_PFC0_ADDR (BASE_ADDR_PFC + OFFSET_PFC0)
#define BASE_PFC1_ADDR (BASE_ADDR_PFC + OFFSET_PFC1)
#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
#define PFC_GP1_BASE (BASE_PFC0_ADDR + OFFSET_PORTGR)
#define PFC_GP3_BASE (BASE_PFC1_ADDR + OFFSET_PORTGR)
#define CPG_CPGWPR (BASE_CPG_ADDR + OFFSET_CPG_CPGWPR)
#define CPG_PLL2CR0 (BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0)
#define CPG_PLLECR (BASE_CPG_ADDR + OFFSET_CPG_PLLECR)
#define CPG_SD0CKCR (BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR)
#define CPG_FRQCRC0 (BASE_CPG_ADDR + OFFSET_CPG_FRQCRC0 0x0808U)
#define OFFSET_PFC_DRV0CTRL (0x00000080U)
#define OFFSET_PFC_DRV1CTRL (0x00000084U)
#define OFFSET_PFC_DRV2CTRL (0x00000088U)
#if (RCAR_LSI == RCAR_S4)
#define PFC_DRVCTRL1_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register0 PortGroup 3
#define PFC_DRVCTRL2_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL) // R/W 32 POC control register1 PortGroup 3
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define PFC_DRVCTRL0_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL) // R/W 32 POC control register0 PortGroup 3
#define PFC_DRVCTRL1_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register1 PortGroup 3
#endif /* RCAR_LSI == RCAR_S4 */
#define PFC_PMMR(addr) ((addr) & (uintptr_t)0xFFFFF800U) // R/W 32 LSI Multiplexed Pin Setting Mask Register
#endif /* RCAR_REGISTER_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RST register header
******************************************************************************/
/******************************************************************************
* @file rst_register.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_
#include <rcar_register.h>
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */
#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */
#define RST_MODEMR0_MD31 (1U << 31U)
#define RST_MODEMR1_MD32 (1U << 0U)
#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU)
/* SCIF / HSCIF clock speed */
#define MODEMR_SCIF_DLMODE (0x00000000U)
#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U)
#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
#endif /* RST_REGISTER_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-VRAM driver header
******************************************************************************/
#ifndef RTVRAM_H_
#define RTVRAM_H_
#include <rtvram_register.h>
void rtvram_extendmode(void);
#endif /* RTVRAM_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-VRAM register header
******************************************************************************/
#ifndef RTVRAM_REGISTER_H__
#define RTVRAM_REGISTER_H__
#include <stdint.h>
/* RT-VRAM register base address */
#define RTVRAM_REG_BASE (0xFFEC0000U)
#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U)
#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U)
#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U)
#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U)
#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U)
#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U)
#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U)
/* RT-VRAM0 register base address */
#define RTVRAM0_REG_BASE (0xFFE90000U)
/* RT-VRAM1 register base address */
#define RTVRAM1_REG_BASE (0xFFEC0000U)
#define RTVRAM0_SECDIVD (RTVRAM0_REG_BASE + 0x0000U)
#define RTVRAM0_SECCTRRD (RTVRAM0_REG_BASE + 0x0040U)
#define RTVRAM0_SECCTRWD (RTVRAM0_REG_BASE + 0x0340U)
#define RTVRAM1_SECDIVD (RTVRAM1_REG_BASE + 0x0000U)
#define RTVRAM1_SECCTRRD (RTVRAM1_REG_BASE + 0x0040U)
#define RTVRAM1_SECCTRWD (RTVRAM1_REG_BASE + 0x0340U)
static inline uint32_t get_rtvram0_secdivd_addr(uint32_t num)
{
return ((RTVRAM0_SECDIVD + (num * 4U)));
}
static inline uint32_t get_rtvram0_secctrrd_addr(uint32_t num)
{
return ((RTVRAM0_SECCTRRD + (num * 4U)));
}
static inline uint32_t get_rtvram0_secctrwd_addr(uint32_t num)
{
return ((RTVRAM0_SECCTRWD + (num * 4U)));
}
static inline uint32_t get_rtvram1_secdivd_addr(uint32_t num)
{
return ((RTVRAM1_SECDIVD + (num * 4U)));
}
static inline uint32_t get_rtvram1_secctrrd_addr(uint32_t num)
{
return ((RTVRAM1_SECCTRRD + (num * 4U)));
}
static inline uint32_t get_rtvram1_secctrwd_addr(uint32_t num)
{
return ((RTVRAM1_SECCTRWD + (num * 4U)));
}
static inline uint32_t get_vbuf_baddr_addr(uint32_t num)
{
return ((RTVRAM_VBUF_BADDR + (num * 4U)));
}
#endif /* RTVRAM_REGISTER_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver header
******************************************************************************/
/******************************************************************************
* @file scif.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef SCIF_H_
#define SCIF_H_
#include <scif_register.h>
#include <hscif_register.h>
/* Prototype */
void scif_init(void);
void console_putc(uint8_t outchar);
#endif /* SCIF_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF register header
******************************************************************************/
/******************************************************************************
* @file scif_register.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_
#include <rcar_register.h>
/* SCIF3 base address */
/* 0xE6C50000 */
#define SCIF_BASE (BASE_SCIF_ADDR)
#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */
#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */
#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */
#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */
#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */
#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */
#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */
#endif /* SCIF_REGISTER_H_ */

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#ifndef SCMT_CONFIG_H_
#define SCMT_CONFIG_H_
/* Activate measurement functions. Provide dummy functions otherwise */
#ifndef MEASURE_TIME
#define MEASURE_TIME (0)
#endif
/* Replace printing by dummy function. This will keep timer init, but removes impact of printing on system performance */
#ifndef MEASURE_TIME_NOPRINT
#define MEASURE_TIME_NOPRINT (0)
#endif
/* Only first IPL should init the timer.
In case of bus access issues, you can check addresses and register values with SCMT_DEBUG.
(Dont forget to add a call to scmt_module_start then and set debug level to NOTICE(2). ) */
#define SCMT_INIT (0)
#define SCMT_DEBUG (0)
/* SCMT base address */
/* V4H:0xE6040000 */
/* V4H-ICUMX: 0xFC000000 + (13*0x00200000) + 0x00040000 = 0xFDA40000 */
#define SCMT_BASE (0xE6040000)
/* For boot time measurement, you can signal the start of SCMT by GPIO pin toggle */
/* See code for adaption of toggled pin */
#define SCMT_TOGGLE_GPIO (0)
/* SCMT is counting with OSCCLK = 131.57 kHz */
/* Tick = 7.6 µs*/
/* Full 32-bit wrap around therefore: 32643 seconds == 9.07 hours */
/* NOTE: WRAPAROUND HANDLING NOT IMPLEMENTED! */
#define SCMT_MS2TICKS(ms) ((ms)*131.579)
/* If the startup time until start of SCMT is known, we can set it as start value of the timer to see absolute time right away */
//#define SCMT_START_VALUE (0) /* No offset, add offset using your spreadsheet program */
//#define SCMT_START_VALUE (2750) /* 20.9ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 160MHz, Unsecure Boot */
//#define SCMT_START_VALUE (2842) /* 21.6ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 80MHz, Unsecure Boot */
//#define SCMT_START_VALUE (2974) /* 22.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 133MHz QuadIO, Unsecure Boot */
//#define SCMT_START_VALUE (3237) /* 24.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 80MHz QuadIO, Unsecure Boot */
#define SCMT_START_VALUE (7184) /* 54.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 40MHz, Unsecure Boot */
/* Start a little self-test routine to check Timer-Frequency against baudrate */
/* #define TIMER_TEST_VS_BAUD (921600) */
#define TIMER_TEST_VS_BAUD (0)
/* SCMT frequency slightly depends on MD-Pin settings!! See V4H UM Table 8.1.4e Note 5 */
#define TIMER_FREQ (131578.9)
/* Module name show in log output */
#define MODULE "Cx:"
/* Arry size for time checkpoints */
#define TIME_CHECKPOINTS_MAX (20)
/* Print additional infos about compiler or MODEMR register */
#define PRINT_INFO (0)
/* Calculates milliseconds from timer ticks. May be disabled if compiler is currently not prepared to handle floats */
#define PRINT_FLOAT (1)
/* PRINTING
You need to configure a way to hook into the systems print functionality
*/
/* Uses the ERROR macro defined by log.h - Works for ICUMX and CR Core */
#include <log.h> /* Access to ERROR() print function */
#define PRINTFN(args...) ERROR(args)
/* Uses facilities provided by Dummy_CA76 application */
// #define USE_LOG_PRINTF (1)
// void log_printf(const char *fmt, ...); /* Provided by scmt_checkpoint_log.c */
// int32_t PutChar(char outChar); /* Provided by devdrv.c */
// #define PRINTFN(args...) {log_printf(args);}
// #define PUTFN(outChar) PutChar(outChar)
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ICUMIF control function header
******************************************************************************/
/******************************************************************************
* @file secure_boot.h
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 17.06.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
* : 16.02.2023 0.03 Added prototype declaration of final_hash_cmp.
*****************************************************************************/
#ifndef SECURE_BOOT_H_
#define SECURE_BOOT_H_
#define SECURE_BOOT (0x0U)
#define NORMAL_BOOT (0x211883DFU)
#define ROMAPI_OK (0x00000000U)
#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void secureboot_init(void);
uint32_t judge_bootmode(void);
void secureboot_verify(LOAD_INFO* li, uint32_t start, uint32_t end);
int secureboot_image(LOAD_INFO* li, int do_panic);
void final_hash_cmp(void);
#endif /* SECURE_BOOT_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : string function header
******************************************************************************/
/******************************************************************************
* @file string.h
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 06.04.2023 0.01 First Release
*****************************************************************************/
#ifndef STRING_H__
#define STRING_H__
#include <stddef.h>
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void *memcpy(void *dst, const void *src, size_t len);
void *memset(void *dst, int val, size_t len);
int memcmp(const void * cs, const void * ct, size_t count);
#endif /* STRING_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : swdt header
******************************************************************************/
/******************************************************************************
* @file swdt.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 12.08.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef SWDT_H_
#define SWDT_H_
#include <stdint.h>
#include "mem_io.h"
#include "rst_register.h"
#define SWDT_BASE (0xE6030000U)
#define SWDT_WTCNT (SWDT_BASE + 0x0000U)
#define SWDT_WTCSRA (SWDT_BASE + 0x0004U)
#define SWDT_WTCSRB (SWDT_BASE + 0x0008U)
#define WTCNT_UPPER_BYTE (0x5A5A0000U)
#define WTCSRA_UPPER_BYTE (0xA5A5A500U)
#define WTCSRB_UPPER_BYTE (0xA5A5A500U)
#define WTCNT_RESET_VALUE (0xF488U)
#define WTCSRA_BIT_CKS (0x0007U)
#define WTCSRB_BIT_CKS (0x003FU)
#define SWDT_RSTMSK (0U << 1U)
#define WTCSRA_WOVFE (1U << 3U)
#define WTCSRA_WRFLG (1U << 5U)
#define WTCSRA_TME (1U << 7U)
#define WDTRSTCR_MASK_ALL (0x0000FFFFU)
#define WTCSRA_MASK_ALL (0x000000FFU)
#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU)
#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U)
/* CKS0 setting */
#define OSCCLK_32 (32U) /* 011:OSCCLK/32 */
#define WTCSRA_CKS0_OSCCLK (0x00000003U)
/* WDT Timeout Setting */
/* OSCCLK */
#define OSCCLK_133330HZ (133330U) /* MD13=0 MD14=0*/
#define OSCCLK_131570HZ (131570U) /* MD13=H MD14=L*/
/* clock */
/* (micro sec / (Hz / RPhi) */
#define CLK_133330HZ ((uint32_t)((1U * 1000U * 1000U) \
/ (OSCCLK_133330HZ / OSCCLK_32)))
#define CLK_131570HZ ((uint32_t)((1U * 1000U * 1000U) \
/ (OSCCLK_131570HZ / OSCCLK_32)))
#define SWDT_COUNT_SEC (10U) /* set param(1--10sec) */
/* SWDT over flow sec need count*/
#define SWDT_COUNT_133330HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \
/ CLK_133330HZ))
#define SWDT_COUNT_131570HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \
/ CLK_131570HZ))
#define SWDTCNT_133330HZ (0x10000U - SWDT_COUNT_133330HZ)
#define SWDTCNT_131570HZ (0x10000U - SWDT_COUNT_131570HZ)
#define MD14_MD13_TYPE_0 (0x00000000U) /* MD14=0 MD13=0 */
#define MD14_MD13_TYPE_1 (0x00002000U) /* MD14=0 MD13=1 */
#define MD14_MD13_TYPE_3 (0x00006000U) /* MD14=1 MD13=1 */
#define CHECK_MD13_MD14 (0x00006000U)
/* Prototype */
void swdt_init(void);
void swdt_exec(void);
void swdt_release(void);
#endif /* SWDT_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : timer header
******************************************************************************/
/******************************************************************************
* @file timer.h
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 09.05.2022 0.02 Moved the definition of the define value
* : 31.10.2022 0.03 License notation change.
*****************************************************************************/
#ifndef TIMER_H_
#define TIMER_H_
#include <stdint.h>
#include <mem_io.h>
/* Prototype */
void generic_timer_init(void);
void micro_wait(uint64_t micro_sec);
#endif /* TIMER_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Type header
******************************************************************************/
/******************************************************************************
* @file types.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#ifndef TYPES_H
#define TYPES_H
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* File Name: types.h
* Contents : Types Define
****************************************************************************/
#include <stdint.h>
#include <stddef.h>
#ifndef FALSE
#define FALSE (0U)
#endif
#ifndef TRUE
#define TRUE (1U)
#endif
#ifdef __cplusplus
}
#endif
#endif