woody/Tool
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add IPL

Browse Source
This commit is contained in:
woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;##### Stack Pointer (Memory Image) #####################
;## #
;## H'E632F600 System_stack (MiniMon) #
;## H'E632F800 UND_stack #
;## H'E632FA00 SVC(SWI)_stack #
;## H'E632FC00 ABT_stack #
;## H'E632FE00 FIQ_stack #
;## H'E6323000 IRQ_stack #
;## #
;########################################################
;#System RAM
.EQU STACK_IRQ_ADR, __STACKS_END__ ;# IRQ mode (unused)
.EQU STACK_FIQ_ADR, __STACKS_END__ ;# FIQ mode (unused)
.EQU STACK_ABT_ADR, __STACKS_END__ ;# ABT mode (unused)
.EQU STACK_SVC_ADR, __STACKS_END__ ;# SVC(SWI) mode (unused)
.EQU STACK_UND_ADR, __STACKS_END__ ;# UND mode(unused)
.EQU STACK_SYS_ADR, __STACKS_END__ ;# SYS mode
;#################### CPSR bit ##########################
.EQU PSR_MODE_USER, 0x10 ;#USR mode
.EQU PSR_MODE_FIQ, 0x11 ;#FIQ mode
.EQU PSR_MODE_IRQ, 0x12 ;#IRQ mode
.EQU PSR_MODE_SVC, 0x13 ;#SVC mode
.EQU PSR_MODE_ABT, 0x17 ;#ABT mode
.EQU PSR_MODE_UND, 0x1B ;#UND mode
.EQU PSR_MODE_SYS, 0x1F ;#SYS mode
;# PRR
.EQU PRR , 0xFFF00044 ;#Product Register
;#RWDT
;#R-CarH3 77. RCLK Watchdog Timer
.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter
.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A
.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B
;#SystemWDT
;#R-CarH3 78. System Watchdog Timer
.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter
.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A
.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B

217
IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.s Normal file
View File

@@ -0,0 +1,217 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.INCLUDE "boot_mon.h"
.ALIGN 4
;#---CACHE_SET--------------------------------------------------------------------------------------
.equ CACHE_MODE,ENABLE ;# ENABLE
;#.equ CACHE_MODE,DISABLE ;# DISABLE
;#--------------------------------------------------------------------------------------------------
;####################################################################################################
;# Vector table
;####################################################################################################
Vector_Table:
LDR PC,=Reset_Handler
LDR PC,=Undefined_Handler
LDR PC,=SVC_Handler
LDR PC,=Prefetch_Handler
LDR PC,=Abort_Handler
NOP
LDR PC,=IRQ_Handler
LDR PC,=FIQ_Handler
;####################################################################################################
;# Exception handler
;####################################################################################################
Undefined_Handler:
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
SVC_Handler:
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
Prefetch_Handler:
SUB R14, R14 , #4
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
Abort_Handler:
SUB R14,R14,#8
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
IRQ_Handler:
SUB R14, R14 , #4
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
FIQ_Handler:
SUB R14,R14,#4
STMFD SP!, {R0-R7,LR}
LDMFD SP!, {R0-R7,PC}^
;####################################################################################################
;####################################################################################################
;######
;###### reset handler
;######
;####################################################################################################
;####################################################################################################
Reset_Handler:
Register_init:
LDR R0, =0
LDR R1, =0
LDR R2, =0
LDR R3, =0
LDR R4, =0
LDR R5, =0
LDR R6, =0
LDR R7, =0
LDR R8, =0
LDR R9, =0
LDR R10, =0
LDR R11, =0
LDR R12, =0
LDR R13, =0
LDR R14, =0
;# LDR R15, =0
Set_EnableRAM:
LDR R0, =0xE67F0018
LDR R1, =0x00000001 ;#Resource Alloc On
STR R1, [R0]
Stack_init:
;#--------------------------------------------------------------------------------------------------
Stack_init_irq:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_IRQ
MSR CPSR_c, R1
LDR R0, =STACK_IRQ_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_frq:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_FIQ
MSR CPSR_c, R1
LDR R0, =STACK_FIQ_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_abt:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_ABT
MSR CPSR_c, R1
LDR R0, =STACK_ABT_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_svc:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_SVC
MSR CPSR_c, R1
LDR R0, =STACK_SVC_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_und:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_UND
MSR CPSR_c, R1
LDR R0, =STACK_UND_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_sys:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_SYS
MSR CPSR_c, R1
LDR R0, =STACK_SYS_ADR
MOV SP, R0
;####################################################################################################
;#
;# board initialize
;#
;####################################################################################################
;####################################################################################################
;#### RWDT,SystemWDT setting (Timer Disable setting)
;####################################################################################################
.ifdef Area0Boot
Init_set_WDT:
LDR R0, =RWDT_RWTCSRA
LDR R1, =0xA5A5A500 ;#Timer disabled
STR R1, [R0]
Init_set_SYSWDT:
LDR R0, =SYSWDT_WTCSRA
LDR R1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
STR R1, [R0]
.endif
.IF CACHE_MODE == ENABLE
;####################################################################################################
;##### enable I cache
;####################################################################################################
CACHE_ENABLE:
MRC p15, 0, R1, c1, c0, 0 ;# Read System Control Register configuration data
ORR R1, R1, #0x1 <<12 ;# instruction cache enable
MCR p15, 0, r0, c7, c5, 0 ;# Invalidate entire instruction cache
MCR p15, 0, R1, c1, c0, 0 ;# enabled instruction cache
ISB
B CACHE_ENABLE_END
.ENDIF
CACHE_ENABLE_END:
/* clear bss section */
mov r0, #0x0
ldr r1, =__BSS_START__
ldr r2, =__BSS_SIZE__
bss_loop:
subs r2, r2, #4
bcc bss_end
str r0, [r1, +r2]
b bss_loop
bss_end:
.ifdef Area0Boot
/* copy data section */
ldr r0, =__DATA_COPY_START__
ldr r1, =__DATA_START__
ldr r2, =__DATA_SIZE__
data_loop:
subs r2, r2, #4
bcc data_end
ldr r3, [r0, +r2]
str r3, [r1, +r2]
b data_loop
data_end:
.endif
BL InitScif
;####################################################################################################
;#### go to main
;####################################################################################################
Jmp_MAIN_C:
BL Main
.END

11
IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/stack.s Normal file
View File

@@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.section writer_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end

39
IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved.
*/
;#RWDT
;#R-CarH3 77. RCLK Watchdog Timer
.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter
#if ACC_PROT_ENABLE == 0
.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A
#else
.EQU RWDT_RWTCSRA , 0x20E6020004 ;#RCLK watchdog timer control/status register A
;#Change to RGID2 when ACC_PROT_ENABLE == 1
#endif
.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B
;#SystemWDT
;#R-CarH3 78. System Watchdog Timer
.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter
#if ACC_PROT_ENABLE == 0
.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A
#else
.EQU SYSWDT_WTCSRA , 0x20E6030004 ;#watchdog timer control/status register A
;#Change to RGID2 when ACC_PROT_ENABLE == 1
#endif
.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B
.EQU PRR , 0xFFF00044 ;#Product Register
.macro STARTFUNC name
.global \name
.func \name
\name:
.endm
.macro ENDFUNC name
.type \name, %function
.endfunc
.endm

181
IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.s Normal file
View File

@@ -0,0 +1,181 @@
/*
* Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved.
*/
;# W0-W30 : 32bit Register (W30=Link Register)
;# X0-X30 : 64bit Register (X30=Link Register)
;# WZR : 32bit Zero Register
;# XZR : 64bit Zero Register
;# WSP : 32bit Stack Pointer
;# SP : 64bit Stack Pointer
.INCLUDE "boot_mon.h"
.ALIGN 4
;# Initialize registers
Register_init:
LDR X0, =0
LDR X1, =0
LDR X2, =0
LDR X3, =0
LDR X4, =0
LDR X5, =0
LDR X6, =0
LDR X7, =0
LDR X8, =0
LDR X9, =0
LDR X10, =0
LDR X11, =0
LDR X12, =0
LDR X13, =0
LDR X14, =0
LDR X15, =0
LDR X16, =0
LDR X17, =0
LDR X18, =0
LDR X19, =0
LDR X20, =0
LDR X21, =0
LDR X22, =0
LDR X23, =0
LDR X24, =0
LDR X25, =0
LDR X26, =0
LDR X27, =0
LDR X28, =0
LDR X29, =0
LDR X30, =0
Set_EnableRAM:
;# LDR X0, =0xE67F0018
;# LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM
;# STR W1, [X0]
MRS X0, CurrentEL
CMP X0, #0x0000000C
BEQ current_EL3
current_EL1:
;# Loader
LDR x0, =__STACKS_END__
;# MSR SP_EL0,x0
;# MSR SP_EL1,x0
;# MSR SP_EL2,x0
MOV sp,x0
MOV x0, #0x50000000
.if ACC_PROT_ENABLE == 1
MOVK x0, #0x0020, LSL #32 ;#mov address #0x2050000000
.endif
MSR ELR_EL1,x0
;# MSR ELR_EL2,x0
;# MSR ELR_EL3,x0
MOV x0, #0x03C5
MSR SPSR_EL1,x0
;# MSR SPSR_EL2,x0
;# MSR SPSR_EL3,x0
;# Enable cache
;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1
orr x0, x0, #(0x1 << 12)
orr x0, x0, #(0x1 << 1)
orr x0, x0, #(0x1 << 3)
msr sctlr_el1, x0
isb
b bss_clr
current_EL3:
;# Loader
LDR x0, =__STACKS_END__
;# MSR SP_EL0,x0
;# MSR SP_EL1,x0
;# MSR SP_EL2,x0
MOV sp,x0
.if OPTEE_LOAD_ENABLE == 0
MOV x0, #0xE38
MSR SCR_EL3, x0
MOV x0, #0x50000000
.if ACC_PROT_ENABLE == 1
MOVK x0, #0x0020, LSL #32 ;#mov address #0x2050000000
.endif
;# MSR ELR_EL1,x0
;# MSR ELR_EL2,x0
MSR ELR_EL3,x0
MOV x0, #0x03C5
;# MSR SPSR_EL1,x0
;# MSR SPSR_EL2,x0
MSR SPSR_EL3,x0
.else
MOV x0, #0xE38
MSR SCR_EL3, x0
MOV x0, #0x44100000
.if ACC_PROT_ENABLE == 1
MOVK x0, #0x0020, LSL #32 ;#mov address #0x2044100000
.endif
MSR ELR_EL3,x0
MOV x0, #0x03C5
MSR SPSR_EL3,x0
.endif
;# Board Initialize
.ifdef Area0Boot
Init_set_WDT:
LDR W0, =RWDT_RWTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled
STR W1, [X0]
Init_set_SYSWDT:
LDR W0, =SYSWDT_WTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
STR W1, [X0]
.endif
;# Enable cache
;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el3
orr x0, x0, #(0x1 << 12)
orr x0, x0, #(0x1 << 1)
orr x0, x0, #(0x1 << 3)
msr sctlr_el3, x0
isb
/* clear bss section */
bss_clr:
mov X0, #0x0
ldr X1, =__BSS_START__
ldr X2, =__BSS_SIZE__
bss_loop:
subs X2, X2, #4
bcc bss_end
str W0, [X1, X2]
b bss_loop
bss_end:
.ifdef Area0Boot
/* copy data section */
ldr X0, =__DATA_COPY_START__
ldr X1, =__DATA_START__
ldr X2, =__DATA_SIZE__
data_loop:
subs X2, X2, #4
bcc data_end
ldr W3, [X0, X2]
str W3, [X1, X2]
b data_loop
.endif
data_end:
;# BL InitScif
BL Main
eret
.END

14
IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.h Normal file
View File

@@ -0,0 +1,14 @@
/*
* Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef D_ARMASM_H
#define D_ARMASM_H
void DCacheEnable();
void WriteTCR_EL3(uint64_t data);
void WriteMAIR_EL3(uint64_t data);
void WriteTTBR0_EL3(uint64_t data);
#endif /* D_ARMASM_H */

288
IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.s Normal file
View File

@@ -0,0 +1,288 @@
/**********************************************************/
/* Sample program : Debug ARM Assembly Program */
/* File Name : d_armasm.s */
/* Copyright (C) Renesas Electronics Corp. 2015. */
/**********************************************************/
.INCLUDE "boot_mon.h"
.ALIGN 4
;# uint32_t MonCp15Mpidr(void);
STARTFUNC MonCp15Mpidr
MRS X0, VMPIDR_EL2 ;# read Multiprocessor ID register
RET
ENDFUNC MonCp15Mpidr
;# uint32_t MonCp15Midr(void);
STARTFUNC MonCp15Midr
MRS X0, VPIDR_EL2 ;# read Processor ID Register
RET
ENDFUNC MonCp15Midr
;# void WriteTCR_EL3( uint64_t data );
;# data[63:39]=RES0
;# data[38][37][36][35][34:32]=TBI1,TBI0,AS,RES0,IPS
;# data[31:30][29:28][27:26][25:24][23][22][21:16]=TG1,SH1,ORGN1,IRGN1,EPD1,A1 ,T1SZ
;# data[15:14][13:12][11:10][09:08][07][06][05:00]=TG0,SH0,ORGN0,IRGN0,EPD0,RES0,T0SZ
STARTFUNC WriteTCR_EL3
MSR TCR_EL3, X0
RET
ENDFUNC WriteTCR_EL3
;# void WriteMAIR_EL3( uint64_t data );
;# data[63:56][55:48][47:40][39:32]=Attr7,Attr6,Attr5,Attr4
;# data[31:24][23:16][15: 8][ 7: 0]=Attr3,Attr2,Attr1,Attr0
STARTFUNC WriteMAIR_EL3
MSR MAIR_EL3, X0
RET
ENDFUNC WriteMAIR_EL3
;# void WriteTTBR0_EL3( uint64_t data );
;# data[63:48]=ASID
;# data[47: 0]=BADDR
STARTFUNC WriteTTBR0_EL3
MSR TTBR0_EL3, X0
RET
ENDFUNC WriteTTBR0_EL3
;# void CleaningAndInvalidateICache(void);
STARTFUNC CleaningAndInvalidateICache
IC IALLUIS
ISB SY
RET
ENDFUNC CleaningAndInvalidateICache
;# Refer: DEN0024A_v8_architecture_PG.pdf
;# void CleaningDCache(void);
STARTFUNC CleaningDCache
MRS X0, CLIDR_EL1
AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
LSR W3, W3, #23
CBZ W3, DC_Finished
MOV W10, #0 // W10 = 2 x cache level
MOV W8, #1 // W8 = constant 0b1
DC_Loop1:
ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
LSR W1, W0, W2 // extract 3-bit cache type for this level
AND W1, W1, #0x7
CMP W1, #2
B.LT DC_Skip // No data or unified cache at this level
MSR CSSELR_EL1, X10 // Select this cache level
ISB // Synchronize change of CSSELR
MRS X1, CCSIDR_EL1 // Read CCSIDR
AND W2, W1, #7 // W2 = log2(linelen)-4
ADD W2, W2, #4 // W2 = log2(linelen)
UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
DC_Loop2:
UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
DC_Loop3:
ORR W11, W10, W9 // W11 = combine way number and cache number...
ORR W11, W11, W7 // ... and set number for DC operand
DC CSW, X11 // Do data cache clean by set and way
SUBS W7, W7, W17 // Decrement set number
B.GE DC_Loop3
SUBS X9, X9, X16 // Decrement way number
B.GE DC_Loop2
DC_Skip:
ADD W10, W10, #2 // Increment 2 x cache level
CMP W3, W10
DSB SY // Ensure completion of previous cache maintenance operation
B.GT DC_Loop1
DC_Finished:
DSB SY ;# Add DSB
ISB ;# Add ISB
RET
ENDFUNC CleaningDCache
;# Refer: DEN0024A_v8_architecture_PG.pdf
;# uint32_t CleaningAndInvalidateDCache(void);
STARTFUNC CleaningAndInvalidateDCache
MRS X0, CLIDR_EL1
AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
LSR W3, W3, #23
CBZ W3, DCI_Finished
MOV W10, #0 // W10 = 2 x cache level
MOV W8, #1 // W8 = constant 0b1
DCI_Loop1:
ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
LSR W1, W0, W2 // extract 3-bit cache type for this level
AND W1, W1, #0x7
CMP W1, #2
B.LT DCI_Skip // No data or unified cache at this level
MSR CSSELR_EL1, X10 // Select this cache level
ISB // Synchronize change of CSSELR
MRS X1, CCSIDR_EL1 // Read CCSIDR
AND W2, W1, #7 // W2 = log2(linelen)-4
ADD W2, W2, #4 // W2 = log2(linelen)
UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
DCI_Loop2:
UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
DCI_Loop3:
ORR W11, W10, W9 // W11 = combine way number and cache number...
ORR W11, W11, W7 // ... and set number for DC operand
DC CISW, X11 // Do data cache clean and invalidate by set and way
SUBS W7, W7, W17 // Decrement set number
B.GE DCI_Loop3
SUBS X9, X9, X16 // Decrement way number
B.GE DCI_Loop2
DCI_Skip:
ADD W10, W10, #2 // Increment 2 x cache level
CMP W3, W10
DSB SY // Ensure completion of previous cache maintenance operation
B.GT DCI_Loop1
DCI_Finished:
DSB SY ;# Add DSB
ISB ;# Add ISB
RET
ENDFUNC CleaningAndInvalidateDCache
;# void DCacheEnable(void);
STARTFUNC DCacheEnable
MOV X20, X30 ;# Save LR data to X20
BL SetVmsaTable ;# MMU Table setting
ISB ;# The ISB forces these changes to be seen before the MMU is enabled.
MRS X0, SCTLR_EL3 ;# Read System Control Register configuration data
ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
DSB SY
MSR SCTLR_EL3, X0 ;# Write System Control Register configuration data
ISB ;# The ISB forces these changes to be seen by the next instruction
MOV X30, X20 ;# Load LR data from X20
RET
ENDFUNC DCacheEnable
;# void DCacheDisable(void);
STARTFUNC DCacheDisable
MOV X20, X30 ;# Save LR data to X20
DSB SY
ISB ;#
MRS X0, SCTLR_EL3 ;#
;# ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
;# ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
bic X0, X0, #1 ;# Set [M] bit and disable the MMU.
bic X0, X0, #4 ;# Set [C] bit and disable the Data Cache.
DSB SY
MSR SCTLR_EL3, X0 ;#
DSB SY
ISB ;#
BL CleaningDCache
BL CleaningAndInvalidateDCache
DSB SY
ISB ;#
MOV X30, X20 ;# Load LR data from X20
RET
ENDFUNC DCacheDisable
STARTFUNC InterruptDisableDAIF
MRS X0, DAIF ;# Read DAIF
LDR W2, =0xC0 ;# bit[7]:IRQ mask bit, bit[6]:FIQ mask bit
ORR X0,X0,X2 ;# => 0:Exception not masked, 1: Exception masked
MSR DAIF, X0 ;# Write DAIF
RET
ENDFUNC InterruptDisableDAIF
STARTFUNC ReadSCR_EL3
MRS X0, SCR_EL3 ;# Read SCR_EL3
RET
ENDFUNC ReadSCR_EL3
STARTFUNC InterruptDisableSCR_EL3
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x6 ;# bit[2]:Physical FIQ Routing, bit[1]:Physical IRQ Routing
BIC X0,X0,X2 ;# => 0:Interrupt not taken, 1: Interrupt are taken
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC InterruptDisableSCR_EL3
STARTFUNC DropToEl1
MRS X0, HCR_EL2 ;# Read HCR_EL2
LDR W2, =0x80000000 ;# bit[31]:EL1 is AArch64
ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL1 is AArch64
MSR HCR_EL2, X0 ;# Write HCR_EL2
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x400 ;# bit[10]:EL1 is AArch64
ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL2/1 are AArch64
MSR SCR_EL3, X0 ;# Write SCR_EL3
LDR W0, =0x3C5 ;# bit[3:0]:EL1h
MSR SPSR_EL3, X0 ;# Write SPSR_EL3
MOV X0, SP
MSR SP_EL1,X0
MOV X0, X30
MSR ELR_EL3,X0
ERET
ENDFUNC DropToEl1
STARTFUNC UpToEl3
LDR W0, =0x3CD ;# bit[3:0]:EL3h
MSR SPSR_EL3, X0 ;# Write SPSR_EL3
MRS X0, SP_EL1 ;# Read SP_EL1
MOV SP, X0
;# MOV X0, X30
;# MRS X0, ELR_EL1 ;# Read ELR_EL1
;# MSR ELR_EL3,X0
RET
ENDFUNC UpToEl3
STARTFUNC ChangeNonSecure
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x1 ;# bit[0]:Non-secure bit
;# LDR W2, =0x481 ;# bit[0]:Non-secure bit
ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC ChangeNonSecure
STARTFUNC ChangeSecure
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x0 ;# bit[0]:Non-secure bit
ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC ChangeSecure
;# void SoftDelayAsm(uint32_t count); <20>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>ON<4F>̏ꍇ<CC8F>A2clock<63><6B>1<EFBFBD><31><EFBFBD>”\ (AArch64)
STARTFUNC SoftDelayAsm ;# <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂܂܌<DC82><DC8C>Z<EFBFBD>Ɏg<C98E>p<EFBFBD><70><EFBFBD><EFBFBD>
SUBS W0, W0, #1 ;# <20>t<EFBFBD><74><EFBFBD>O<EFBFBD><4F><EFBFBD>X<EFBFBD>V<EFBFBD><56><EFBFBD>‚Œ<C282><C28C>Z 1step
BNE SoftDelayAsm ;# R0==0<>ɂȂ<C982><C882>܂Ń<DC82><C583>[<5B>v 1step
RET ;# <20>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>ɖ߂<C996>
ENDFUNC SoftDelayAsm
.END

11
IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/stack.s Normal file
View File

@@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.section writer_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end

1
IPL/SDK/v4h/src/Dummy_CA76/LICENSE.md Normal file
View File

@@ -0,0 +1 @@
Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.

16
IPL/SDK/v4h/src/Dummy_CA76/cert_param.c Normal file
View File

@@ -0,0 +1,16 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
/* 0xE6300400 */
const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000;
/* 0xE630048C */
const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000;
/* 0xE63005D4 */
const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000;
/* 0xE63006E4 */
const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000;
/* 0xE6301154 */
const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000;
/* 0xE6301264 */
const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000;

265
IPL/SDK/v4h/src/Dummy_CA76/common.c Normal file
View File

@@ -0,0 +1,265 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "types.h"
#include "common.h"
#include "devdrv.h"
__attribute__((aligned(32))) uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE];
/************************************************************************/
/*NAME : PutMes */
/************************************************************************/
int32_t PutMess(const char *const mess[])
{
int32_t i=0;
while(mess[i]){
PutStr(mess[i],ENB_RTN);
i++;
}
return(0);
}
/************************************************************************/
/*NAME : PutStr */
/************************************************************************/
int32_t PutStr(const char *str,char rtn)
{
while(*str){
PutChar(*str);
str++;
}
if(rtn == 1){
PutChar(CR_CODE);
PutChar(LF_CODE);
}
return(0);
}
/************************************************************************/
/*NAME : Hex2Ascii */
/************************************************************************/
uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt)
{
long i;
char ch;
for( i = 7; i >= 0; i-- ) {
ch = (char)(hexdata & 0x0F);
if( ch > 9 )
ch += 7;
ch += 0x30;
hexdata >>= 4;
*(str + i) = ch;
}
*(str + 8) = '\0';
*chcnt = 8;
return 0U;
}
uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt)
{
char Count;
char countstart;
uint32_t Compdata;
unsigned char dataB;
uint32_t dataL;
uint32_t i;
Count = 0;
countstart = 0x0;
dataB = 0;
dataL = 10;
while( dataL > 0 ){
Compdata = 1;
i = 1;
while( i < dataL ){
Compdata *= 10;
i++;
}
while( hexdata >= Compdata ){
hexdata -= Compdata;
dataB++;
countstart = 1;
}
if( countstart == 1 ){
*(str++) = dataB + '0';
Count++;
}
dataB = 0;
dataL--;
}
if(Count==0){
*str = '0';
str++;
Count++;
}
*str = '\0';
*chcnt = Count;
return(0);
}
/************************************************************************/
void ChgLtl2Lrg(char *str)
{
while(*str!=0){
if(('a' <= *str)&&(*str<='z'))
*str -= 0x20;
str++;
}
}
char HexAscii2Data(unsigned char *buf,uint32_t *data)
{
char chCnt;
uint32_t tmpData;
*data = 0;
chCnt = 0;
ChgLtl2Lrg(buf);
if(*buf=='@') return(3);
while(*buf){
if(('0'<= *buf)&&(*buf<='9')){
tmpData = (uint32_t)(*buf - '0');
*data <<= 4;
*data |= tmpData;
}else if(('A'<= *buf)&&(*buf<='F')){
tmpData = (uint32_t)(*buf - 55);
*data <<= 4;
*data |= tmpData;
}else{
return(1);
}
buf++;
chCnt++;
if(chCnt>(SIZE_32BIT*2)) return(1);
}
return(0);
}
char HexAscii2Data_64(unsigned char *buf,uintptr_t *data)
{
char chCnt;
uintptr_t tmpData;
*data = 0;
chCnt = 0;
ChgLtl2Lrg(buf);
if(*buf=='@') return(3);
while(*buf){
if(('0'<= *buf)&&(*buf<='9')){
tmpData = (uintptr_t)(*buf - '0');
*data <<= 4;
*data |= tmpData;
}else if(('A'<= *buf)&&(*buf<='F')){
tmpData = (uintptr_t)(*buf - 55);
*data <<= 4;
*data |= tmpData;
}else{
return(1);
}
buf++;
chCnt++;
if(chCnt>(CPU_BYTE_SIZE*2)) return(1);
}
return(0);
}
char Data2HexAscii(uint32_t data,char *buf,char size)
{
char loopCnt,i;
uint32_t tmpData;
switch(size){
case SIZE_8BIT:
data <<= (SIZE_32BIT*8-8);
loopCnt=2;
break;
case SIZE_16BIT:
data <<= (SIZE_32BIT*8-16);
loopCnt=4;
break;
case SIZE_32BIT:
data <<= (SIZE_32BIT*8-32);
loopCnt=8;
break;
}
for(i=0;i<loopCnt;i++,buf++){
tmpData = (data >> (SIZE_32BIT*8-4));
if(tmpData < 0x0a){ /* case 1 to 9 */
*buf = (char)(tmpData + '0');
}else{ /* case A to F */
*buf = (char)(tmpData + 55);
}
data <<= 4;
}
*buf = 0;
return(0);
}
char Data2HexAscii_64(uintptr_t data,char *buf,char size)
{
char loopCnt,i;
uintptr_t tmpData;
switch(size){
case SIZE_8BIT:
data <<= (CPU_BYTE_SIZE*8-8);
loopCnt=2;
break;
case SIZE_16BIT:
data <<= (CPU_BYTE_SIZE*8-16);
loopCnt=4;
break;
case SIZE_32BIT:
data <<= (CPU_BYTE_SIZE*8-32);
loopCnt=8;
break;
#ifdef AArch64
case SIZE_64BIT:
data <<= (CPU_BYTE_SIZE*8-64);
loopCnt=16;
break;
#endif
}
for(i=0;i<loopCnt;i++,buf++){
tmpData = (data >> (CPU_BYTE_SIZE*8-4));
if(tmpData < 0x0a){ /* case 1 to 9 */
*buf = (char)(tmpData + '0');
}else{ /* case A to F */
*buf = (char)(tmpData + 55);
}
data <<= 4;
}
*buf = 0;
return(0);
}
void SoftDelay(uint32_t loop)
{
uint32_t i;
for(i=0;i<loop;i++);
}
void *memset(void *dst, int val, unsigned long count)
{
char *ptr = dst;
while (count--)
*ptr++ = val;
return dst;
}

105
IPL/SDK/v4h/src/Dummy_CA76/devdrv.c Normal file
View File

@@ -0,0 +1,105 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "devdrv.h"
#include "scifdrv0.h"
#include "scifdrv3.h"
#include "hscifdrv0.h"
#include "reg_rcargen3.h"
/************************
PutChar *
*************************/
int32_t PutChar(char outChar)
{
uint32_t product;
uint32_t modemr0;
uint32_t modemr1;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_S4:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
PutCharSCIF3(outChar);
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
PutCharHSCIF0(outChar);
break;
default:
break;
}
case PRR_PRODUCT_V4H:
case PRR_PRODUCT_V4M:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
PutCharSCIF0(outChar);
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
PutCharHSCIF0(outChar);
break;
default:
break;
}
default:
break;
}
return(0);
}
int32_t WaitPutCharSendEnd(void)
{
uint32_t product;
uint32_t modemr0;
uint32_t modemr1;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_S4:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
WaitPutScif3SendEnd();
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
WaitPutHscif0SendEnd();
break;
default:
break;
}
case PRR_PRODUCT_V4H:
case PRR_PRODUCT_V4M:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
WaitPutScif0SendEnd();
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
WaitPutHscif0SendEnd();
break;
default:
break;
}
break;
default:
break;
}
}

109
IPL/SDK/v4h/src/Dummy_CA76/generic_timer.c Normal file
View File

@@ -0,0 +1,109 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : generic timer
******************************************************************************/
/******************************************************************************
* @file generic_timer.c
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 19.09.2023 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <mem_io.h>
#include <timer.h>
#include "common.h"
#include "devdrv.h"
#define RCAR_CNTC_EXTAL (16666600U) /* V4H/V4M : 16.666600MHz */
#define RCAR_CONV_MICROSEC (1000000U)
static inline uint64_t get_cntfrq(void)
{
uint64_t freq;
__asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq));
return(freq);
}
static inline void set_cntfrq(uint64_t reg_cntfid)
{
__asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid));
}
static inline uint64_t get_cntpct(void)
{
uint64_t base_count;
__asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count));
return(base_count);
}
void generic_timer_init(void)
{
/* Update memory mapped and register based freqency */
/* AArch64:cntfrq_el0 */
set_cntfrq(RCAR_CNTC_EXTAL);
}
/* End of function generic_timer_init(void) */
void micro_wait(uint64_t micro_sec)
{
uint64_t base_count = 0U;
uint64_t get_count = 0U;
uint64_t wait_time = 0U;
uint64_t freq = 0U;
/* cntfrq_el0 */
freq = get_cntfrq();
/* cntpct_el0 */
base_count = get_cntpct();
micro_sec *= freq;
while (micro_sec > wait_time)
{
/* cntpct */
get_count = get_cntpct();
/* INT30-C Pre confirmation */
if (get_count < base_count)
{
PutStr("micro_wait(Timer value error!!).", 1U);
while(1U); /* panic */
}
else
{
wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC);
}
}
}
/* End of function micro_wait(uint64_t micro_sec) */

215
IPL/SDK/v4h/src/Dummy_CA76/hscifdrv0.c Normal file
View File

@@ -0,0 +1,215 @@
/*
* Copyright (c) 2020, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "common.h"
#include "hscifdrv0.h"
#include "bit.h"
#include "reg_rcargen3.h"
/********************************************************************************/
/* */
/* Debug Seirial(HSCIF0) */
/* */
/********************************************************************************/
int32_t PutCharHSCIF0(char outChar)
{
while(!(0x60U & *((volatile uint16_t*)HSCIF0_HSFSR) ));
*((volatile uint8_t*)HSCIF0_HSFTDR) = outChar;
*((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x60U; /* TEND,TDFE clear */
return(0);
}
int32_t GetCharHSCIF0(char *inChar)
{
do{
if(0x91 & *((volatile uint16_t *)HSCIF0_HSFSR))
*((volatile uint16_t *)HSCIF0_HSFSR) &= ~0x91;
if(0x01 & *((volatile uint16_t *)HSCIF0_HSLSR))
{
PutStr("ORER",1);
*((volatile uint16_t *)HSCIF0_HSLSR) &= ~0x01;
}
}while( !(0x02 & *((volatile uint16_t *)HSCIF0_HSFSR)) );
*inChar = *((volatile unsigned char*)HSCIF0_HSFRDR);
*((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x02;
return(0);
}
void PowerOnHscif0(void)
{
uint32_t dataL;
#ifdef RCAR_GEN3_CONDOR
dataL = *((volatile uint32_t*)CPG_MSTPSR5);
if(dataL & BIT20){ /* case HSCIF0 */
dataL &= ~BIT20;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR5) = dataL;
while( BIT20 & *((volatile uint32_t*)CPG_MSTPSR5) ); /* wait bit=0 */
}
#endif /* RCAR_GEN3_CONDOR */
#ifdef RCAR_GEN3_FALCON
dataL = *((volatile uint32_t*)CPG_MSTPSR5);
if(dataL & BIT14){ /* case HSCIF0 */
dataL &= ~BIT14;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_MSTPCR5) = dataL;
while( BIT14 & *((volatile uint32_t*)CPG_MSTPSR5) ); /* wait bit=0 */
}
#endif /* RCAR_GEN3_FALCON */
}
void WaitPutHscif0SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1U;
while(loop){
dataW = *((volatile uint16_t*)HSCIF0_HSFSR);
if(dataW & BIT6) {
loop = 0U;
}
}
}
void InitHscif0PinFunction(void)
{
uint32_t dataL;
#ifdef RCAR_GEN3_CONDOR
/* HSCIF0 */
dataL = *((volatile uint32_t*)PFC_IPSR7);
dataL &= ~(0x0FF00000U);
dataL |= 0x05500000U; /* IPSR7[27:24]=4'b0101, IPSR7[23:20]=4'b0101 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR7) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x00000030U; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
#endif /* RCAR_GEN3_CONDOR */
#ifdef RCAR_GEN3_FALCON
/* HSCIF0 */
dataL = *((volatile uint32_t*)PFC_IP0SR1);
dataL &= ~(0x00F000F0U);
dataL |= 0x00000000U; /* IP0SR1[23:20]=4'b0000(HTX0), IP0SR1[4:7]=4'b0000(HRX0) */
dataL &= 0x0; /* bit0:SCIF_CLK=0 */
*((volatile uint32_t*)PFC_PMMR1) = ~dataL;
*((volatile uint32_t*)PFC_IP0SR1) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR1); /* SDA2/SCL2 is not found in V3U TS */
dataL |= 0x00000022U; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_PMMR1) = ~dataL;
*((volatile uint32_t*)PFC_GPSR1) = dataL;
#endif /* RCAR_GEN3_FALCON */
}
void InitHscif0_SCIFCLK(void)
{
uint16_t dataW;
#if RCAR_GEN3_FALCON
uint32_t modemr0;
uint32_t modemr1;
#endif /* RCAR_GEN3_FALCON */
PowerOnHscif0();
InitHscif0PinFunction();
dataW = *((volatile uint16_t*)HSCIF0_HSLSR); /* dummy read */
*((volatile uint16_t*)HSCIF0_HSLSR) = 0x0000U; /* clear ORER bit */
*((volatile uint16_t*)HSCIF0_HSFSR) = 0x0000U; /* clear all error bit */
*((volatile uint16_t*)HSCIF0_HSSCR) = 0x0000U; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)HSCIF0_HSFCR) = 0x0006U; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)HSCIF0_HSFSR) = 0x0000U; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)HSCIF0_HSSCR) = 0x0000U; /* internal clock, SCK pin is not used */
*((volatile uint16_t*)HSCIF0_HSSMR) = 0x0000U; /* 8bit data, no-parity, 1 stop, Po/1 */
#if defined(RCAR_GEN3_CONDOR)
*((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */
SoftDelay(100U);
*((volatile uint8_t*)HSCIF0_HSBRR) = 0x11U; /* 921600bps@266.6MHz */
#elif defined(RCAR_GEN3_FALCON)
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */
switch(modemr0 | modemr1){
case MODEMR_SCIF_921600_V3U:
*((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */
SoftDelay(100U);
*((volatile uint8_t*)HSCIF0_HSBRR) = 0x11U; /* 921600bps@266.6MHz */
break;
case MODEMR_SCIF_1843200_V3U:
*((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */
SoftDelay(100U);
*((volatile uint8_t*)HSCIF0_HSBRR) = 0x08U; /* 1843200bps@266.6MHz */
break;
case MODEMR_SCIF_3000000_V3U:
*((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007; /* 3000000bps with SCIF_CLK */
*((volatile uint16_t*)HSCIF0_HSSCR) = 0x0002; /* external clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)HSCIF0_DL) = 0x0001; /* Frequency Division is 1 */
*((volatile uint16_t*)HSCIF0_CKS) = 0x0000; /* select scif_clk */
break;
default:
break;
}
#endif /* defined(RCAR_GEN3_CONDOR) */
SoftDelay(100U);
*((volatile uint16_t*)HSCIF0_HSFCR) = 0x0000U; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)HSCIF0_HSSCR) = 0x0030U; /* enable TE, RE; SCK pin is not used */
SoftDelay(100U);
}
uint32_t HSCIF0_TerminalInputCheck(char* str)
{
char result = 0;
if(0x91 & *((volatile uint16_t *)HSCIF0_HSFSR))
*((volatile uint16_t *)HSCIF0_HSFSR) &= ~0x91;
if(0x01 & *((volatile uint16_t *)HSCIF0_HSLSR))
{
PutStr("ORER",1);
*((volatile uint16_t *)HSCIF0_HSLSR) &= ~0x01;
}
if(0x02 & *((volatile uint16_t *)HSCIF0_HSFSR))
{
*str = *((volatile unsigned char*)HSCIF0_HSFRDR);
*((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x02;
result = 1;
}
return result;
}

41
IPL/SDK/v4h/src/Dummy_CA76/include/bit.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef BIT_H
#define BIT_H
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif /* BIT_H */

58
IPL/SDK/v4h/src/Dummy_CA76/include/common.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef COMMON_H
#define COMMON_H
#include <stdint.h>
#ifdef AArch64
//typedef uint64_t uintptr_t;
#define CPU_BYTE_SIZE SIZE_64BIT
#endif
#ifdef AArch32
//typedef uint32_t uintptr_t;
#define CPU_BYTE_SIZE SIZE_32BIT
#endif
#define DIS_RTN 0 /* Disable Return */
#define ENB_RTN 1 /* Enable Return */
#define OK 0x1
#ifndef NULL
#define NULL 0x0
#endif
#define INT_CODE 0x25 /* "%" */
#define BS_CODE 0x08 /* "BS" */
#define CR_CODE 0x0d /* "CR" */
#define SP_CODE 0x20 /* "LF" */
#define LF_CODE 0x0a /* "LF" */
#define SIZE_8BIT 1 // Old name : BYTE_SIZE
#define SIZE_16BIT 2 // Old name : WORD_SIZE
#define SIZE_32BIT 4 // Old name : LONG_SIZE
#define SIZE_64BIT 8 // New
#define COMMAND_BUFFER_SIZE 1024
/****************************
Module Proto Type *
****************************/
int32_t PutMess(const char *const mess[]);
int32_t PutStr(const char *str,char rtn);
uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt);
uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt);
void ChgLtl2Lrg(char *str);
char HexAscii2Data(unsigned char *buf,uint32_t *data);
char HexAscii2Data_64(unsigned char *buf,uintptr_t *data);
char Data2HexAscii(uint32_t data,char *buf,char size);
char Data2HexAscii_64(uintptr_t data,char *buf,char size);
void SoftDelay(uint32_t roop);
#endif

11
IPL/SDK/v4h/src/Dummy_CA76/include/devdrv.h Normal file
View File

@@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef DEVDRV_H
#define DEVDRV_H
int32_t PutChar(char outChar);
int32_t WaitPutCharSendEnd(void);
#endif /* DEVDRV_H */

42
IPL/SDK/v4h/src/Dummy_CA76/include/hscifdrv0.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (c) 2020, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef HSCIFDRV0_H
#define HSCIFDRV0_H
int32_t PutCharHSCIF0(char outChar);
int32_t GetCharHSCIF0(char *inChar);
void PowerOnHscif0(void);
void WaitPutHscif0SendEnd(void);
void InitHscif0_SCIFCLK(void);
uint32_t HSCIF0_TerminalInputCheck(char* str);
#endif /* HSCIFDRV0_H */

10
IPL/SDK/v4h/src/Dummy_CA76/include/init_scif.h Normal file
View File

@@ -0,0 +1,10 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef INITSCIF_H
#define INITSCIF_H
void InitScif(void);
#endif /* INITSCIF_H */

10
IPL/SDK/v4h/src/Dummy_CA76/include/main.h Normal file
View File

@@ -0,0 +1,10 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef MAIN_H
#define MAIN_H
void Main(void);
#endif /* MAIN_H */

54
IPL/SDK/v4h/src/Dummy_CA76/include/mem_io.h Normal file
View File

@@ -0,0 +1,54 @@
/*******************************************************************************
* Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/

608
IPL/SDK/v4h/src/Dummy_CA76/include/reg_rcargen3.h Normal file
View File

@@ -0,0 +1,608 @@
/*
* Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef REG_RCARGEN3_H
#define REG_RCARGEN3_H
#define RCAR_CNTC_BASE (0xE6080000) /* The base addess of generic timer control register */
#define CNTFID_OFF 0x020
#define CNTCR_OFF 0x000
//CPG for S4
#define CPG_BASE (0xE6150000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U) // R/W 32 CPG Write Protect Control Register
#define CPG_CPGWPR (CPG_BASE + 0x0000U) // R/W 32 CPG Write Protect Register
#define CPG_SD0CKCR (CPG_BASE + 0x0870U) // R/W 32 SD-IF0 clock frequency control register
#define CPG_RPCCKCR (CPG_BASE + 0x0874U) // R/W 32 RPC clock frequency control register
//MSTPRST
#define CPG_SRCR0 (CPG_BASE + 0x2C00U) // R/W 32 Software reset register 0
#define CPG_SRCR1 (CPG_BASE + 0x2C04U) // R/W 32 Software reset register 1
#define CPG_SRCR2 (CPG_BASE + 0x2C08U) // R/W 32 Software reset register 2
#define CPG_SRCR3 (CPG_BASE + 0x2C0CU) // R/W 32 Software reset register 3
#define CPG_SRCR4 (CPG_BASE + 0x2C10U) // R/W 32 Software reset register 4
#define CPG_SRCR5 (CPG_BASE + 0x2C14U) // R/W 32 Software reset register 5
#define CPG_SRCR6 (CPG_BASE + 0x2C18U) // R/W 32 Software reset register 6
#define CPG_SRCR7 (CPG_BASE + 0x2C1CU) // R/W 32 Software reset register 7
#define CPG_SRCR8 (CPG_BASE + 0x2C20U) // R/W 32 Software reset register 8
#define CPG_SRCR9 (CPG_BASE + 0x2C24U) // R/W 32 Software reset register 9
#define CPG_SRCR10 (CPG_BASE + 0x2C28U) // R/W 32 Software reset register 10
#define CPG_SRCR11 (CPG_BASE + 0x2C2CU) // R/W 32 Software reset register 11
#define CPG_SRCR12 (CPG_BASE + 0x2C30U) // R/W 32 Software reset register 12
#define CPG_SRCR13 (CPG_BASE + 0x2C34U) // R/W 32 Software reset register 13
#define CPG_SRCR14 (CPG_BASE + 0x2C38U) // R/W 32 Software reset register 14
#define CPG_SRCR15 (CPG_BASE + 0x2C3CU) // R/W 32 Software reset register 15
#define CPG_SRCR16 (CPG_BASE + 0x2C40U) // R/W 32 Software reset register 16
#define CPG_SRCR17 (CPG_BASE + 0x2C44U) // R/W 32 Software reset register 17
#define CPG_SRCR18 (CPG_BASE + 0x2C48U) // R/W 32 Software reset register 18
#define CPG_SRCR19 (CPG_BASE + 0x2C4CU) // R/W 32 Software reset register 19
#define CPG_SRCR20 (CPG_BASE + 0x2C50U) // R/W 32 Software reset register 20
#define CPG_SRCR21 (CPG_BASE + 0x2C54U) // R/W 32 Software reset register 21
#define CPG_SRCR22 (CPG_BASE + 0x2C58U) // R/W 32 Software reset register 22
#define CPG_SRCR23 (CPG_BASE + 0x2C5CU) // R/W 32 Software reset register 23
#define CPG_SRSTCLR0 (CPG_BASE + 0x2C80U) // W 32 Software reset clearing register 0
#define CPG_SRSTCLR1 (CPG_BASE + 0x2C84U) // W 32 Software reset clearing register 1
#define CPG_SRSTCLR2 (CPG_BASE + 0x2C88U) // W 32 Software reset clearing register 2
#define CPG_SRSTCLR3 (CPG_BASE + 0x2C8CU) // W 32 Software reset clearing register 3
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) // W 32 Software reset clearing register 4
#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U) // W 32 Software reset clearing register 5
#define CPG_SRSTCLR6 (CPG_BASE + 0x2C98U) // W 32 Software reset clearing register 6
#define CPG_SRSTCLR7 (CPG_BASE + 0x2C9CU) // W 32 Software reset clearing register 7
#define CPG_SRSTCLR8 (CPG_BASE + 0x2CA0U) // W 32 Software reset clearing register 8
#define CPG_SRSTCLR9 (CPG_BASE + 0x2CA4U) // W 32 Software reset clearing register 9
#define CPG_SRSTCLR10 (CPG_BASE + 0x2CA8U) // W 32 Software reset clearing register 10
#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) // W 32 Software reset clearing register 11
#define CPG_SRSTCLR12 (CPG_BASE + 0x2CB0U) // W 32 Software reset clearing register 12
#define CPG_SRSTCLR13 (CPG_BASE + 0x2CB4U) // W 32 Software reset clearing register 13
#define CPG_SRSTCLR14 (CPG_BASE + 0x2CB8U) // W 32 Software reset clearing register 14
#define CPG_SRSTCLR15 (CPG_BASE + 0x2CBCU) // W 32 Software reset clearing register 15
#define CPG_SRSTCLR16 (CPG_BASE + 0x2CC0U) // W 32 Software reset clearing register 16
#define CPG_SRSTCLR17 (CPG_BASE + 0x2CC4U) // W 32 Software reset clearing register 17
#define CPG_SRSTCLR18 (CPG_BASE + 0x2CC8U) // W 32 Software reset clearing register 18
#define CPG_SRSTCLR19 (CPG_BASE + 0x2CCCU) // W 32 Software reset clearing register 19
#define CPG_SRSTCLR20 (CPG_BASE + 0x2CD0U) // W 32 Software reset clearing register 20
#define CPG_SRSTCLR21 (CPG_BASE + 0x2CD4U) // W 32 Software reset clearing register 21
#define CPG_SRSTCLR22 (CPG_BASE + 0x2CD8U) // W 32 Software reset clearing register 22
#define CPG_SRSTCLR23 (CPG_BASE + 0x2CDCU) // W 32 Software reset clearing register 23
#define CPG_MSTPCR0 (CPG_BASE + 0x2D00U) // R/W 32 Domain0 module stop control register 0
#define CPG_MSTPCR1 (CPG_BASE + 0x2D04U) // R/W 32 Domain0 module stop control register 1
#define CPG_MSTPCR2 (CPG_BASE + 0x2D08U) // R/W 32 Domain0 module stop control register 2
#define CPG_MSTPCR3 (CPG_BASE + 0x2D0CU) // R/W 32 Domain0 module stop control register 3
#define CPG_MSTPCR4 (CPG_BASE + 0x2D10U) // R/W 32 Domain0 module stop control register 4
#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U) // R/W 32 Domain0 module stop control register 5
#define CPG_MSTPCR6 (CPG_BASE + 0x2D18U) // R/W 32 Domain0 module stop control register 6
#define CPG_MSTPCR7 (CPG_BASE + 0x2D1CU) // R/W 32 Domain0 module stop control register 7
#define CPG_MSTPCR8 (CPG_BASE + 0x2D20U) // R/W 32 Domain0 module stop control register 8
#define CPG_MSTPCR9 (CPG_BASE + 0x2D24U) // R/W 32 Domain0 module stop control register 9
#define CPG_MSTPCR10 (CPG_BASE + 0x2D28U) // R/W 32 Domain0 module stop control register 10
#define CPG_MSTPCR11 (CPG_BASE + 0x2D2CU) // R/W 32 Domain0 module stop control register 11
#define CPG_MSTPCR12 (CPG_BASE + 0x2D30U) // R/W 32 Domain0 module stop control register 12
#define CPG_MSTPCR13 (CPG_BASE + 0x2D34U) // R/W 32 Domain0 module stop control register 13
#define CPG_MSTPCR14 (CPG_BASE + 0x2D38U) // R/W 32 Domain0 module stop control register 14
#define CPG_MSTPCR15 (CPG_BASE + 0x2D3CU) // R/W 32 Domain0 module stop control register 15
#define CPG_MSTPCR16 (CPG_BASE + 0x2D40U) // R/W 32 Domain0 module stop control register 16
#define CPG_MSTPCR17 (CPG_BASE + 0x2D44U) // R/W 32 Domain0 module stop control register 17
#define CPG_MSTPCR18 (CPG_BASE + 0x2D48U) // R/W 32 Domain0 module stop control register 18
#define CPG_MSTPCR19 (CPG_BASE + 0x2D4CU) // R/W 32 Domain0 module stop control register 19
#define CPG_MSTPCR20 (CPG_BASE + 0x2D50U) // R/W 32 Domain0 module stop control register 20
#define CPG_MSTPCR21 (CPG_BASE + 0x2D54U) // R/W 32 Domain0 module stop control register 21
#define CPG_MSTPCR22 (CPG_BASE + 0x2D58U) // R/W 32 Domain0 module stop control register 22
#define CPG_MSTPCR23 (CPG_BASE + 0x2D5CU) // R/W 32 Domain0 module stop control register 23
#define CPG_MSTPSR0 (CPG_BASE + 0x2E00U) // R 32 Module stop status register 0
#define CPG_MSTPSR1 (CPG_BASE + 0x2E04U) // R 32 Module stop status register 1
#define CPG_MSTPSR2 (CPG_BASE + 0x2E08U) // R 32 Module stop status register 2
#define CPG_MSTPSR3 (CPG_BASE + 0x2E0CU) // R 32 Module stop status register 3
#define CPG_MSTPSR4 (CPG_BASE + 0x2E10U) // R 32 Module stop status register 4
#define CPG_MSTPSR5 (CPG_BASE + 0x2E14U) // R 32 Module stop status register 5
#define CPG_MSTPSR6 (CPG_BASE + 0x2E18U) // R 32 Module stop status register 6
#define CPG_MSTPSR7 (CPG_BASE + 0x2E1CU) // R 32 Module stop status register 7
#define CPG_MSTPSR8 (CPG_BASE + 0x2E20U) // R 32 Module stop status register 8
#define CPG_MSTPSR9 (CPG_BASE + 0x2E24U) // R 32 Module stop status register 9
#define CPG_MSTPSR10 (CPG_BASE + 0x2E28U) // R 32 Module stop status register 10
#define CPG_MSTPSR11 (CPG_BASE + 0x2E2CU) // R 32 Module stop status register 11
#define CPG_MSTPSR12 (CPG_BASE + 0x2E30U) // R 32 Module stop status register 12
#define CPG_MSTPSR13 (CPG_BASE + 0x2E34U) // R 32 Module stop status register 13
#define CPG_MSTPSR14 (CPG_BASE + 0x2E38U) // R 32 Module stop status register 14
#define CPG_MSTPSR15 (CPG_BASE + 0x2E3CU) // R 32 Module stop status register 15
#define CPG_MSTPSR16 (CPG_BASE + 0x2E40U) // R 32 Module stop status register 16
#define CPG_MSTPSR17 (CPG_BASE + 0x2E44U) // R 32 Module stop status register 17
#define CPG_MSTPSR18 (CPG_BASE + 0x2E48U) // R 32 Module stop status register 18
#define CPG_MSTPSR19 (CPG_BASE + 0x2E4CU) // R 32 Module stop status register 19
#define CPG_MSTPSR20 (CPG_BASE + 0x2E50U) // R 32 Module stop status register 20
#define CPG_MSTPSR21 (CPG_BASE + 0x2E54U) // R 32 Module stop status register 21
#define CPG_MSTPSR22 (CPG_BASE + 0x2E58U) // R 32 Module stop status register 22
#define CPG_MSTPSR23 (CPG_BASE + 0x2E5CU) // R 32 Module stop status register 23
//LBSC.h
#define LBSC_CS0CTRL 0xEE220200 // R/W 32 Area 0 control register
#define LBSC_CS1CTRL 0xEE220204 // R/W 32 Area 1 control register
#define LBSC_CSWCR0 0xEE220230 // R/W 32 Area 0 RD/WE pulse control register
#define LBSC_CSWCR1 0xEE220234 // R/W 32 Area 1 RD/WE pulse control register
#define LBSC_CSPWCR0 0xEE220280 // R/W 32 Area 0 external wait control register
#define LBSC_CSPWCR1 0xEE220284 // R/W 32 Area 1 external wait control register
#define LBSC_EXWTSYNC 0xEE2202A0 // R/W 32 External wait input control register
#define LBSC_CS0BSTCTL 0xEE2202B0 // R/W 32 Area 0 burst control register
#define LBSC_CS0BTPH 0xEE2202B4 // R/W 32 Area 0 burst pitch set register
#define LBSC_CS1GDST 0xEE2202C0 // R/W 32 Area 1 guard setting register
#define LBSC_BCINTSR 0xEE220330 // R 32 BSC interrupt source status register
#define LBSC_BCINTCR 0xEE220334 // -/WC1 32 BSC interrupt source clear register
#define LBSC_BCINTMR 0xEE220338 // R/W 32 BSC interrupt enable register
#define LBSC_EXWTSTS 0xEE220344 // R 32 External wait status register
#define LBSC_EXBCT 0xEE2203C0 // R/W 32 EX-BUS wait timeout detection base counter register
#define LBSC_EXTCT 0xEE2203C4 // R/W 32 EX-BUS wait timeout detection counter register
#define LBSC_EXTSR 0xEE220010 // R/WC1 32 EX-BUS wait timeout detection access source indication register
#define LBSC_EXTADR 0xEE220014 // R/W 32 EX-BUS wait timeout detection address indication register
//PFC for S4
#define PFC_BASE (0xE6050000)
#define PFC_MCU_BASE (0xFFD90000)
#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */
#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */
#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */
#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */
#define PFC_SYS_GRP (0x00008000U)
#define PFC_PORT_GRP_MASK (0xFFFFF800U)
#define PFC_PMMR(addr) ((addr) & PFC_PORT_GRP_MASK + 0x0000U)
/* Port Group0 */
#define PFC_PMMR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0040U)
#define PFC_IP0SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0060U)
#define PFC_IP1SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0064U)
#define PFC_IP2SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0068U)
#define PFC_IP3SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x006CU)
#define PFC_DRV0CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0080U)
#define PFC_DRV1CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0084U)
#define PFC_DRV2CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0088U)
#define PFC_DRV3CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x008CU)
#define PFC_POC0 (PFC_BASE + PFC_PORT_GRP0 + 0x00A0U)
#define PFC_PUEN0 (PFC_BASE + PFC_PORT_GRP0 + 0x00C0U)
#define PFC_PUD0 (PFC_BASE + PFC_PORT_GRP0 + 0x00E0U)
#define PFC_MOD_SEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0100U)
#define GPIO_IOINTSEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0180U)
#define GPIO_INOUTSEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0184U)
#define GPIO_OUTDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x0188U)
#define GPIO_INDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x018CU)
#define GPIO_INTDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x0190U)
#define GPIO_INTCLR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0194U)
#define GPIO_INTMSK0 (PFC_BASE + PFC_PORT_GRP0 + 0x0198U)
#define GPIO_MSKCLR0 (PFC_BASE + PFC_PORT_GRP0 + 0x019CU)
#define GPIO_POSNEG0 (PFC_BASE + PFC_PORT_GRP0 + 0x01A0U)
/* Port Group1 */
#define PFC_PMMR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0000U)
#define PFC_GPSR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0040U)
#define PFC_IP0SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0060U)
#define PFC_IP1SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0064U)
#define PFC_IP2SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0068U)
#define PFC_IP3SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x006CU)
#define PFC_DRV0CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0080U)
#define PFC_DRV1CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0084U)
#define PFC_DRV2CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0088U)
#define PFC_DRV3CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x008CU)
#define PFC_POC1 (PFC_BASE + PFC_PORT_GRP1 + 0x00A0U)
#define PFC_PUEN1 (PFC_BASE + PFC_PORT_GRP1 + 0x00C0U)
#define PFC_PUD1 (PFC_BASE + PFC_PORT_GRP1 + 0x00E0U)
#define PFC_MOD_SEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0100U)
#define GPIO_IOINTSEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0180U)
#define GPIO_INOUTSEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0184U)
#define GPIO_OUTDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x0188U)
#define GPIO_INDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x018CU)
#define GPIO_INTDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x0190U)
#define GPIO_INTCLR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0194U)
#define GPIO_INTMSK1 (PFC_BASE + PFC_PORT_GRP1 + 0x0198U)
#define GPIO_MSKCLR1 (PFC_BASE + PFC_PORT_GRP1 + 0x019CU)
#define GPIO_POSNEG1 (PFC_BASE + PFC_PORT_GRP1 + 0x01A0U)
/* Port Group2 */
#define PFC_PMMR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0000U)
#define PFC_GPSR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0040U)
#define PFC_IP0SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0060U)
#define PFC_IP1SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0064U)
#define PFC_IP2SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0068U)
#define PFC_IP3SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x006CU)
#define PFC_DRV0CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0080U)
#define PFC_DRV1CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0084U)
#define PFC_DRV2CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0088U)
#define PFC_DRV3CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x008CU)
#define PFC_POC2 (PFC_BASE + PFC_PORT_GRP2 + 0x00A0U)
#define PFC_PUEN2 (PFC_BASE + PFC_PORT_GRP2 + 0x00C0U)
#define PFC_PUD2 (PFC_BASE + PFC_PORT_GRP2 + 0x00E0U)
#define PFC_MOD_SEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0100U)
#define GPIO_IOINTSEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0180U)
#define GPIO_INOUTSEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0184U)
#define GPIO_OUTDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x0188U)
#define GPIO_INDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x018CU)
#define GPIO_INTDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x0190U)
#define GPIO_INTCLR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0194U)
#define GPIO_INTMSK2 (PFC_BASE + PFC_PORT_GRP2 + 0x0198U)
#define GPIO_MSKCLR2 (PFC_BASE + PFC_PORT_GRP2 + 0x019CU)
#define GPIO_POSNEG2 (PFC_BASE + PFC_PORT_GRP2 + 0x01A0U)
/* Port Group3 */
#define PFC_PMMR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0000U)
#define PFC_GPSR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0040U)
#define PFC_IP0SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0060U)
#define PFC_IP1SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0064U)
#define PFC_IP2SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0068U)
#define PFC_IP3SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x006CU)
#define PFC_DRV0CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0080U)
#define PFC_DRV1CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0084U)
#define PFC_DRV2CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0088U)
#define PFC_DRV3CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x008CU)
#define PFC_POC3 (PFC_BASE + PFC_PORT_GRP3 + 0x00A0U)
#define PFC_PUEN3 (PFC_BASE + PFC_PORT_GRP3 + 0x00C0U)
#define PFC_PUD3 (PFC_BASE + PFC_PORT_GRP3 + 0x00E0U)
#define PFC_MOD_SEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0100U)
#define GPIO_IOINTSEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0180U)
#define GPIO_INOUTSEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0184U)
#define GPIO_OUTDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x0188U)
#define GPIO_INDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x018CU)
#define GPIO_INTDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x0190U)
#define GPIO_INTCLR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0194U)
#define GPIO_INTMSK3 (PFC_BASE + PFC_PORT_GRP3 + 0x0198U)
#define GPIO_MSKCLR3 (PFC_BASE + PFC_PORT_GRP3 + 0x019CU)
#define GPIO_POSNEG3 (PFC_BASE + PFC_PORT_GRP3 + 0x01A0U)
/* Port Group4 */
#define PFC_PMMR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0000U)
#define PFC_GPSR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0040U)
#define PFC_IP0SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0060U)
#define PFC_IP1SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0064U)
#define PFC_IP2SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0068U)
#define PFC_IP3SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x006CU)
#define PFC_DRV0CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0080U)
#define PFC_DRV1CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0084U)
#define PFC_DRV2CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0088U)
#define PFC_DRV3CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x008CU)
#define PFC_POC4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00A0U)
#define PFC_PUEN4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00C0U)
#define PFC_PUD4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00E0U)
#define PFC_MOD_SEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0100U)
#define GPIO_IOINTSEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0180U)
#define GPIO_INOUTSEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0184U)
#define GPIO_OUTDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0188U)
#define GPIO_INDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x018CU)
#define GPIO_INTDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0190U)
#define GPIO_INTCLR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0194U)
#define GPIO_INTMSK4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0198U)
#define GPIO_MSKCLR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x019CU)
#define GPIO_POSNEG4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x01A0U)
/* Port Group5 */
#define PFC_PMMR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0000U)
#define PFC_GPSR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0040U)
#define PFC_IP0SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0060U)
#define PFC_IP1SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0064U)
#define PFC_IP2SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0068U)
#define PFC_IP3SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x006CU)
#define PFC_DRV0CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0080U)
#define PFC_DRV1CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0084U)
#define PFC_DRV2CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0088U)
#define PFC_DRV3CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x008CU)
#define PFC_POC5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00A0U)
#define PFC_PUEN5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00C0U)
#define PFC_PUD5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00E0U)
#define PFC_MOD_SEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0100U)
#define GPIO_IOINTSEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0180U)
#define GPIO_INOUTSEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0184U)
#define GPIO_OUTDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0188U)
#define GPIO_INDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x018CU)
#define GPIO_INTDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0190U)
#define GPIO_INTCLR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0194U)
#define GPIO_INTMSK5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0198U)
#define GPIO_MSKCLR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x019CU)
#define GPIO_POSNEG5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x01A0U)
/* Port Group6 */
#define PFC_PMMR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0000U)
#define PFC_GPSR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0040U)
#define PFC_IP0SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0060U)
#define PFC_IP1SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0064U)
#define PFC_IP2SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0068U)
#define PFC_IP3SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x006CU)
#define PFC_DRV0CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0080U)
#define PFC_DRV1CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0084U)
#define PFC_DRV2CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0088U)
#define PFC_DRV3CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x008CU)
#define PFC_POC6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00A0U)
#define PFC_PUEN6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00C0U)
#define PFC_PUD6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00E0U)
#define PFC_MOD_SEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0100U)
#define GPIO_IOINTSEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0180U)
#define GPIO_INOUTSEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0184U)
#define GPIO_OUTDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0188U)
#define GPIO_INDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x018CU)
#define GPIO_INTDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0190U)
#define GPIO_INTCLR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0194U)
#define GPIO_INTMSK6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0198U)
#define GPIO_MSKCLR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x019CU)
#define GPIO_POSNEG6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x01A0U)
/* Port Group7 */
#define PFC_PMMR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0000U)
#define PFC_GPSR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0040U)
#define PFC_IP0SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0060U)
#define PFC_IP1SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0064U)
#define PFC_IP2SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0068U)
#define PFC_IP3SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x006CU)
#define PFC_DRV0CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0080U)
#define PFC_DRV1CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0084U)
#define PFC_DRV2CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0088U)
#define PFC_DRV3CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x008CU)
#define PFC_POC7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00A0U)
#define PFC_PUEN7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00C0U)
#define PFC_PUD7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00E0U)
#define PFC_MOD_SEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0100U)
#define GPIO_IOINTSEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0180U)
#define GPIO_INOUTSEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0184U)
#define GPIO_OUTDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0188U)
#define GPIO_INDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x018CU)
#define GPIO_INTDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0190U)
#define GPIO_INTCLR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0194U)
#define GPIO_INTMSK7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0198U)
#define GPIO_MSKCLR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x019CU)
#define GPIO_POSNEG7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x01A0U)
/* System Group0 */
#define PFC_PMMR8 (PFC_BASE + PFC_SYS_GRP + 0x0000U)
#define PFC_GPSR8 (PFC_BASE + PFC_SYS_GRP + 0x0040U)
#define PFC_IP0SR8 (PFC_BASE + PFC_SYS_GRP + 0x0060U)
#define PFC_IP1SR8 (PFC_BASE + PFC_SYS_GRP + 0x0064U)
#define PFC_IP2SR8 (PFC_BASE + PFC_SYS_GRP + 0x0068U)
#define PFC_IP3SR8 (PFC_BASE + PFC_SYS_GRP + 0x006CU)
#define PFC_DRV0CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0080U)
#define PFC_DRV1CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0084U)
#define PFC_DRV2CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0088U)
#define PFC_DRV3CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x008CU)
#define PFC_POC8 (PFC_BASE + PFC_SYS_GRP + 0x00A0U)
#define PFC_PUEN8 (PFC_BASE + PFC_SYS_GRP + 0x00C0U)
#define PFC_PUD8 (PFC_BASE + PFC_SYS_GRP + 0x00E0U)
#define PFC_MOD_SEL8 (PFC_BASE + PFC_SYS_GRP + 0x0100U)
#define GPIO_IOINTSEL8 (PFC_BASE + PFC_SYS_GRP + 0x0180U)
#define GPIO_INOUTSEL8 (PFC_BASE + PFC_SYS_GRP + 0x0184U)
#define GPIO_OUTDT8 (PFC_BASE + PFC_SYS_GRP + 0x0188U)
#define GPIO_INDT8 (PFC_BASE + PFC_SYS_GRP + 0x018CU)
#define GPIO_INTDT8 (PFC_BASE + PFC_SYS_GRP + 0x0190U)
#define GPIO_INTCLR8 (PFC_BASE + PFC_SYS_GRP + 0x0194U)
#define GPIO_INTMSK8 (PFC_BASE + PFC_SYS_GRP + 0x0198U)
#define GPIO_MSKCLR8 (PFC_BASE + PFC_SYS_GRP + 0x019CU)
#define GPIO_POSNEG8 (PFC_BASE + PFC_SYS_GRP + 0x01A0U)
/* System Group1 */
#define PFC_PMMR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0000U)
#define PFC_GPSR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0040U)
#define PFC_IP0SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0060U)
#define PFC_IP1SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0064U)
#define PFC_IP2SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0068U)
#define PFC_IP3SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x006CU)
#define PFC_DRV0CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0080U)
#define PFC_DRV1CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0084U)
#define PFC_DRV2CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0088U)
#define PFC_DRV3CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x008CU)
#define PFC_POC9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00A0U)
#define PFC_PUEN9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00C0U)
#define PFC_PUD9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00E0U)
#define PFC_MOD_SEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0100U)
#define GPIO_IOINTSEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0180U)
#define GPIO_INOUTSEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0184U)
#define GPIO_OUTDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0188U)
#define GPIO_INDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x018CU)
#define GPIO_INTDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0190U)
#define GPIO_INTCLR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0194U)
#define GPIO_INTMSK9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0198U)
#define GPIO_MSKCLR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x019CU)
#define GPIO_POSNEG9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x01A0U)
//V3M
#define PFC_IOCTRL30 0xE6060380 // R/W 32 MPOC control register 0
#define PFC_IOCTRL31 0xE6060384 // R/W 32 MPOC control register 0
#define PFC_IOCTRL32 0xE6060388 // R/W 32 MPOC control register 0
#define PFC_IOCTRL40 0xE60603C0 // R/W 32 MPOC control register 0
//RST
#if ACC_PROT_ENABLE == 0
#define RST_MODEMR0 0xE6160000 // R 32 Mode Monitor Register
#define RST_MODEMR1 0xE6160004 // R 32 Mode Monitor Register2
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define RST_MODEMR0 0x20E6160000 // R 32 Mode Monitor Register
#define RST_MODEMR1 0x20E6160004 // R 32 Mode Monitor Register2
#endif /* ACC_PROT_ENABLE == 0 */
#define RST_MODEMR 0xE6160060 // R 32 Mode Monitor Register
#define RST_CA57RESCNT 0xE6160040 // R/W 32 CA57 Reset Control Register
#define RST_CA53RESCNT 0xE6160044 // R/W 32 CA53 Reset Control Register
#define RST_WDTRSTCR 0xE6160054 // R/W 32 Watchdog Timer Reset Control Register
#define RST_RSTOUTCR 0xE6160058 // R/W 32 PRESETOUT# Control Register
#define RST_SBAR 0xE6160010 // R/W 32 SYS Boot Address Register
#define RST_SBAR2 0xE6160014 // R/W 32 SYS Boot Address Register2
#define RST_CA53BAR 0xE6160030 // R/W 32 CA53 Boot Address Register
#define RST_CA53BAR2 0xE6160034 // R/W 32 CA53 Boot Address Register2
#define RST_CA57BAR 0xE6160020 // R/W 32 CA57 Boot Address Register
#define RST_CA57BAR2 0xE6160024 // R/W 32 CA57 Boot Address Register2
#define RST_CR7BAR 0xE6160070 // R/W 32 CR7 Boot Address Register
#define RST_CR7BAR2 0xE6160074 // R/W 32 CR7 Boot Address Register2
#define RST_CA57CPU0BARH 0xE61600C0 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode H
#define RST_CA57CPU0BARL 0xE61600C4 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode L
#define RST_CA57CPU1BARH 0xE61600D0 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode H
#define RST_CA57CPU1BARL 0xE61600D4 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode L
#define RST_CA57CPU2BARH 0xE61600E0 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode H
#define RST_CA57CPU2BARL 0xE61600E4 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode L
#define RST_CA57CPU3BARH 0xE61600F0 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode H
#define RST_CA57CPU3BARL 0xE61600F4 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode L
#define RST_CA53CPU0BARH 0xE6160080 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode H
#define RST_CA53CPU0BARL 0xE6160084 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode L
#define RST_CA53CPU1BARH 0xE6160090 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode H
#define RST_CA53CPU1BARL 0xE6160094 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode L
#define RST_CA53CPU2BARH 0xE61600A0 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode H
#define RST_CA53CPU2BARL 0xE61600A4 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode L
#define RST_CA53CPU3BARH 0xE61600B0 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode H
#define RST_CA53CPU3BARL 0xE61600B4 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode L
#define RST_APBSFTYCHKR 0xE616005C // R/W 32 APB bus Safety Check Register
#define RST_STBCHR0 0xE6160100 // R/W 32 Standby Flag Register 0
#define RST_STBCHR1 0xE6160104 // R/W 32 Standby Flag Register 1
#define RST_STBCHR2 0xE6160108 // R/W 32 Standby Flag Register 2
#define RST_STBCHR3 0xE616010C // R/W 32 Standby Flag Register 3
#define RST_STBCHR4 0xE6160120 // R/W 32 Standby Flag Register 4
#define RST_STBCHR5 0xE6160124 // R/W 32 Standby Flag Register 5
#define RST_STBCHR6 0xE6160128 // R/W 32 Standby Flag Register 6
#define RST_STBCHR7 0xE616012C // R/W 32 Standby Flag Register 7
#define RST_SRESCR 0xE6160110 // R/W 32 Soft Power On Reset Control Register
#define RST_RRSTFR 0xE6160114 // R/W 32 RT Reset Flag Register
#define RST_SRSTFR 0xE6160118 // R/W 32 SYS Reset Flag Register
#define RST_SCPTCSR 0xE6160180 // R/W 32 Secure Protect Control/Status Register
#define RST_SCERMIDR 0xE6160184 // R 32 Secure Error Master ID Register
#define RST_SCERADR 0xE6160188 // R 32 Secure Error Address Register
#define RST_SAPTCSR 0xE6160190 // R/W 32 Safety Protect Control/Status Register
#define RST_SAERMIDR 0xE6160194 // R 32 Safety Error Master ID Register
#define RST_SAERADR 0xE6160198 // R 32 Safety Error Address Register
#define MODEMR_BOOT_CPU_MASK (0x000000C0U)
#define MODEMR_BOOT_CPU_CR7 (0x000000C0U)
#define MODEMR_BOOT_CPU_CA57 (0x00000000U)
#define MODEMR_BOOT_CPU_CA53 (0x00000040U)
#define MODEMR_BOOT_DEV_MASK (0x0000001EU)
#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU)
#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU)
#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU)
#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU)
#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU)
#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU)
#define MODEMR_BOOT_PLL_MASK (0x00006000U)
#define MODEMR_BOOT_PLL_SHIFT (13U)
#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
#define MODEMR0_MD31_V3U (0x80000000U)
#define MODEMR1_MD32_V3U (0x00000001U)
#define MODEMR_SCIF_115200_V3U (0x00000000U)
#define MODEMR_SCIF_921600_V3U (0x80000000U)
#define MODEMR_SCIF_1843200_V3U (0x00000001U)
#define MODEMR_SCIF_3000000_V3U (0x80000001U)
#define MODEMR0_MD31_GEN4 (0x80000000U)
#define MODEMR1_MD32_GEN4 (0x00000001U)
#define MODEMR_SCIF_115200_GEN4 (0x00000000U)
#define MODEMR_SCIF_921600_GEN4 (0x80000000U)
#define MODEMR_SCIF_1843200_GEN4 (0x00000001U)
#define MODEMR_SCIF_3000000_GEN4 (0x80000001U)
//
#define MFIS_SOFTMDR (0xE6260600U)
//SCIF0
#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register
#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register
#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register
#if ACC_PROT_ENABLE == 0
#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register
#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define SCIF0_SCFTDR 0x20E6E6000C // W 8 Transmit FIFO data register
#define SCIF0_SCFSR 0x20E6E60010 // R/W 16 Serial status register
#endif /* ACC_PROT_ENABLE == 0 */
#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register
#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register
#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register
#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register
#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register
#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register
#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register
//SCIF2
#define SCIF2_SCSMR 0xE6E88000 // R/W 16 Serial mode register
#define SCIF2_SCBRR 0xE6E88004 // R/W 8 Bit rate register
#define SCIF2_SCSCR 0xE6E88008 // R/W 16 Serial control register
#define SCIF2_SCFTDR 0xE6E8800C // W 8 Transmit FIFO data register
#define SCIF2_SCFSR 0xE6E88010 // R/W 16 Serial status register
#define SCIF2_SCFRDR 0xE6E88014 // R 8 Receive FIFO data register
#define SCIF2_SCFCR 0xE6E88018 // R/W 16 FIFO control register
#define SCIF2_SCFDR 0xE6E8801C // R 16 FIFO data count register
#define SCIF2_SCSPTR 0xE6E88020 // R/W 16 Serial port register
#define SCIF2_SCLSR 0xE6E88024 // R/W 16 Line status register
#define SCIF2_DL 0xE6E88030 // R/W 16 Frequency division register
#define SCIF2_CKS 0xE6E88034 // R/W 16 Clock Select register
//SCIF3
#if ACC_PROT_ENABLE == 0
#define SCIF3_BASE (0xE6C50000)
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define SCIF3_BASE (0x20E6C50000)
#endif /* ACC_PROT_ENABLE == 0 */
#define SCIF3_SCSMR (SCIF3_BASE + 0x0000U) // R/W 16 Serial mode register
#define SCIF3_SCBRR (SCIF3_BASE + 0x0004U) // R/W 8 Bit rate register
#define SCIF3_SCSCR (SCIF3_BASE + 0x0008U) // R/W 16 Serial control register
#define SCIF3_SCFTDR (SCIF3_BASE + 0x000CU) // W 8 Transmit FIFO data register
#define SCIF3_SCFSR (SCIF3_BASE + 0x0010U) // R/W 16 Serial status register
#define SCIF3_SCFRDR (SCIF3_BASE + 0x0014U) // R 8 Receive FIFO data register
#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) // R/W 16 FIFO control register
#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) // R 16 FIFO data count register
#define SCIF3_SCSPTR (SCIF3_BASE + 0x0020U) // R/W 16 Serial port register
#define SCIF3_SCLSR (SCIF3_BASE + 0x0024U) // R/W 16 Line status register
#define SCIF3_DL (SCIF3_BASE + 0x0030U) // R/W 16 Frequency division register
#define SCIF3_CKS (SCIF3_BASE + 0x0034U) // R/W 16 Clock Select register
/* HSCIF0 */
#define HSCIF0_HSSMR (0xE6540000U) // R/W 16 Serial mode register
#define HSCIF0_HSBRR (0xE6540004U) // R/W 8 Bit rate register
#define HSCIF0_HSSCR (0xE6540008U) // R/W 16 Serial control register
#if ACC_PROT_ENABLE == 0
#define HSCIF0_HSFTDR (0xE654000CU) // W 8 Transmit FIFO data register
#define HSCIF0_HSFSR (0xE6540010U) // R/W 16 Serial status register
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define HSCIF0_HSFTDR (0x20E654000CU) // W 8 Transmit FIFO data register
#define HSCIF0_HSFSR (0x20E6540010U) // R/W 16 Serial status register
#endif /* ACC_PROT_ENABLE == 0 */
#define HSCIF0_HSFRDR (0xE6540014U) // R 8 Receive FIFO data register
#define HSCIF0_HSFCR (0xE6540018U) // R/W 16 FIFO control register
#define HSCIF0_HSFDR (0xE654001CU) // R 16 FIFO data count register
#define HSCIF0_HSSPTR (0xE6540020U) // R/W 16 Serial port register
#define HSCIF0_HSLSR (0xE6540024U) // R/W 16 Line status register
#define HSCIF0_HSSRR (0xE6540040U) // R/W 16 Sampling rate register
/* BRG */
#define HSCIF0_DL (0xE6540030U) // R/W 16 Frequency division register
#define HSCIF0_CKS (0xE6540034U) // R/W 16 Clock select register
/* Appendix A. */
#if ACC_PROT_ENABLE == 0
#define PRR (0xFFF00044) /* Product Register */
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define PRR (0x20FFF00044) /* Product Register */
#endif /* ACC_PROT_ENABLE == 0 */
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#define PRR_PRODUCT_V3U (0x00005900U) /* R-Car V3U */
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
#define PRR_CUT_10 (0x00U)
#define PRR_CUT_11 (0x01U)
#define PRR_CUT_20 (0x10U)
#define PRR_CUT_30 (0x20U)
#define PRR_CUT_MAJOR_MASK (0x000000F0U)
#define PRR_CUT_MINOR_MASK (0x0000000FU)
#define PRR_PRODUCT_SHIFT (8U)
#define PRR_MAJOR_SHIFT (4U)
#define PRR_MINOR_SHIFT (0U)
#define PRR_MAJOR_OFFSET (1U)
#endif /* REG_RCARGEN3_H */

13
IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV0_H
#define SCIFDRV0_H
int32_t PutCharSCIF0(char outChar);
void PowerOnScif0(void);
void WaitPutScif0SendEnd(void);
void InitScif0_SCIFCLK(void);
#endif /* SCIFDRV0_H */

13
IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0_v3h.h Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV0_V3H_H
#define SCIFDRV0_V3H_H
int32_t PutCharSCIF0_v3h(char outChar);
void PowerOnScif0_v3h(void);
void WaitPutScif0_v3h_SendEnd(void);
void InitScif0_v3h_SCIFCLK(void);
#endif /* SCIFDRV0_V3H_H */

14
IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv2.h Normal file
View File

@@ -0,0 +1,14 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV2_H
#define SCIFDRV2_H
int32_t PutCharSCIF2(char outChar);
void PowerOnScif2(void);
void WaitPutScif2SendEnd(void);
void InitScif2_SCIFCLK(void);
void InitScif2_SCIFCLK_D3(void);
#endif /* SCIFDRV2_H */

46
IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv3.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Copyright (c) 2021, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

48
IPL/SDK/v4h/src/Dummy_CA76/include/timer.h Normal file
View File

@@ -0,0 +1,48 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : timer header
******************************************************************************/
/******************************************************************************
* @file timer.h
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 19.09.2023 0.01 First Release
*****************************************************************************/
#ifndef TIMER_H_
#define TIMER_H_
#include <stdint.h>
/* Prototype */
void generic_timer_init(void);
void micro_wait(uint64_t micro_sec);
#endif /* TIMER_H_ */

115
IPL/SDK/v4h/src/Dummy_CA76/include/types.h Normal file
View File

@@ -0,0 +1,115 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef TYPES_H
#define TYPES_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
/****************************************************************************
* File Name: types.h
* Contents : Types Define
****************************************************************************/
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef SUCCESS
#define SUCCESS 0UL
#endif
#ifndef YES
#define YES 1
#endif
#ifndef NO
#define NO 0
#endif
#ifndef NULL
#define NULL (void *)0UL
#endif
#define PFAR /**/
#define FFAR /**/
typedef signed char BYTE;
typedef signed short WORD;
typedef signed long DWORD;
#if 0
typedef unsigned long uint32;
typedef long int32;
typedef unsigned short uint16;
typedef short int16;
typedef unsigned char uint8;
typedef char int8;
typedef unsigned int uint;
typedef unsigned char bool8;
typedef unsigned long long uint64;
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef signed short int16_t;
typedef unsigned short uint16_t;
typedef signed long int32_t;
typedef unsigned long uint32_t;
typedef unsigned long long int uint64_t;
#endif
typedef signed char B; /* signed 8-bit integer */
typedef long W; /* signed 32-bit integer */
typedef unsigned char UB; /* unsigned 8-bit integer */
typedef unsigned long UW; /* unsigned 32-bit integer */
typedef short H; /* signed 16-bit integer */
typedef unsigned short UH; /* unsigned 16-bit integer */
typedef int INT;
typedef unsigned int UINT;
typedef INT BOOL;
typedef void (FFAR *FP)();
typedef INT FN;
typedef INT ID;
typedef INT BOOL_ID;
typedef INT HNO;
typedef INT RNO;
typedef INT RDVNO;
typedef UINT RDVPTN;
typedef UINT ATR;
typedef UINT MODE;
typedef INT ER;
typedef INT PRI;
typedef ER ER_ID;
typedef UINT STAT;
typedef INT ER_UINT;
typedef UINT TEXPTN;
typedef UINT FLGPTN;
typedef UINT INHNO;
typedef UINT INTNO;
typedef unsigned long SIZE;
typedef W TMO;
typedef W DLYTIME;
typedef DLYTIME RELTIM;
typedef void PFAR *VP;
typedef VP VP_INT;
#ifdef __cplusplus
}
#endif
#endif

12
IPL/SDK/v4h/src/Dummy_CA76/include/vmsatable.h Normal file
View File

@@ -0,0 +1,12 @@
/**********************************************************/
/* Sample program : VMSA Table Header */
/* File Name : vmsatable.h */
/* Copyright (C) Renesas Electronics Corp. 2015. */
/**********************************************************/
#ifndef _VMSATABLE_H_
#define _VMSATABLE_H_
uint32_t SetVmsaTable(void);
#endif

56
IPL/SDK/v4h/src/Dummy_CA76/init_scif.c Normal file
View File

@@ -0,0 +1,56 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "reg_rcargen3.h"
#include "common.h"
#include "scifdrv0.h"
#include "scifdrv3.h"
#include "init_scif.h"
#include "hscifdrv0.h"
void InitScif(void)
{
uint32_t product;
uint32_t modemr0;
uint32_t modemr1;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_S4:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
InitScif3_SCIFCLK();
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
InitHscif0_SCIFCLK();
break;
default:
break;
}
case PRR_PRODUCT_V4H:
case PRR_PRODUCT_V4M:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */
InitScif0_SCIFCLK();
break;
case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */
case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */
case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */
InitHscif0_SCIFCLK();
break;
default:
break;
}
default:
break;
}
}

286
IPL/SDK/v4h/src/Dummy_CA76/main.c Normal file
View File

@@ -0,0 +1,286 @@
/*
* Copyright (c) 2018-2023 Renesas Electronics Corporation. All rights reserved.
*/
#include <stdio.h>
#include "common.h"
#include "main.h"
#include "devdrv.h"
#include "reg_rcargen3.h"
#include "d_armasm.h"
#include "timer.h"
#define DUMMY_SECURE_MONITOR 1U
#define DUMMY_U_BOOT 2U
#define DUMMY_TEE 3U
#define NORMAL_END (0U)
#define ERROR_END (1U)
#define CL16MPHY (16660000U)
/* Input Dummy Program waiting time (us) */
#define WAIT_TIME_US (3000000U)
uint64_t gErrDdrAdd;
uint32_t gErrDdrData;
uint32_t gTrueDdrData;
static void StartMess(void);
static uint32_t CkExtendDdrRamCheck(void* ramAddr, uint64_t ramSize);
void bl2_init_generic_timer(void);
void rcar_set_log_time(void);
extern const uint8_t __RO_START__[1];
extern const uint8_t __STACKS_END__[1];
void Main(void)
{
volatile uint32_t i;
uint32_t ret;
char str[64];
uint32_t product;
#if (DUMMY == DUMMY_SECURE_MONITOR)
/* Generic Timer initialization is performed at only once. */
generic_timer_init();
#endif /* (DUMMY == DUMMY_SECURE_MONITOR) */
micro_wait(WAIT_TIME_US);
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
#if DUMMY == DUMMY_U_BOOT
#if SDRAM_CHECK == 1
#if DCACHE == 1
DCacheEnable();
#endif
/* 0x04_20000000 -- 0x04_FFFFFFFF */
rcar_set_log_time();
/* V4H DDR0 area: H'04_0000 0000 ~ H'04_7FFF FFFF (2 Gbytes) */
/* V4H DDR1 area: H'04_8000 0000 ~ H'04_FFFF FFFF (2 Gbytes) */
/* V4M DDR0 area: H'04_0000 0000 ~ H'04_FFFF FFFF (4 Gbytes) */
PutStr("SDRAM verify test 0x04_20000000 -- 0x04_CCCCFFFF",1);
ret = CkExtendDdrRamCheck((void*)0x0420000000U, 0xACCD0000U);
if (ret != NORMAL_END)
{
rcar_set_log_time();
PutStr("SDRAM verify NG",1);
rcar_set_log_time();
PutStr("Error Address:0x",0);
Data2HexAscii_64(gErrDdrAdd,str,8);
PutStr(str,1);
rcar_set_log_time();
PutStr("Error Data :0x",0);
Data2HexAscii(gErrDdrData,str,4);
PutStr(str,1);
rcar_set_log_time();
PutStr("Expected Data :0x",0);
Data2HexAscii(gTrueDdrData,str,4);
PutStr(str,1);
}
else
{
rcar_set_log_time();
PutStr("SDRAM verify OK",1);
}
rcar_set_log_time();
if (product == PRR_PRODUCT_V4H)
{
/* V4H DDR2 area: H'06_0000 0000 ~ H'06_7FFF FFFF (2 Gbytes) */
/* V4H DDR3 area: H'06_8000 0000 ~ H'06_FFFF FFFF (2 Gbytes) */
PutStr("SDRAM verify test 0x06_00000000 -- 0x06_CCCCFFFF",1);
ret = CkExtendDdrRamCheck((void*)0x0600000000U, 0x00CCCD0000U);
} else { /* (product == PRR_PRODUCT_V4M) */
/* V4M DDR1 area: H'05_0000 0000 ~ H'05_FFFF FFFF (4 Gbytes) */
PutStr("SDRAM verify test 0x05_00000000 -- 0x05_CCCCFFFF",1);
ret = CkExtendDdrRamCheck((void*)0x0500000000U, 0x00CCCD0000U);
}
if (ret != NORMAL_END)
{
rcar_set_log_time();
PutStr("SDRAM verify NG",1);
rcar_set_log_time();
PutStr("Error Address:0x",0);
Data2HexAscii_64(gErrDdrAdd,str,8);
PutStr(str,1);
rcar_set_log_time();
PutStr("Error Data :0x",0);
Data2HexAscii(gErrDdrData,str,4);
PutStr(str,1);
rcar_set_log_time();
PutStr("Expected Data :0x",0);
Data2HexAscii(gTrueDdrData,str,4);
PutStr(str,1);
}
else
{
rcar_set_log_time();
PutStr("SDRAM verify OK",1);
}
#endif /* SDRAM_CHECK == 1 */
#endif /* DUMMY == DUMMY_U_BOOT */
StartMess();
#if DUMMY == DUMMY_U_BOOT
while(1) {
__asm__ volatile ("wfi");
}
#elif DUMMY == DUMMY_TEE
#elif DUMMY == DUMMY_SECURE_MONITOR
#endif
}
static void StartMess(void)
{
#if DUMMY == DUMMY_SECURE_MONITOR
PutStr(" ",1);
rcar_set_log_time();
PutStr("Dummy Secure Monitor",1);
rcar_set_log_time();
PutStr("Dummy Secure Monitor boot end",1);
#elif DUMMY == DUMMY_TEE
PutStr(" ",1);
rcar_set_log_time();
PutStr("Dummy TEE",1);
rcar_set_log_time();
PutStr("Dummy TEE boot end",1);
#else
PutStr(" ",1);
rcar_set_log_time();
PutStr("Dummy U-Boot",1);
rcar_set_log_time();
PutStr("Dummy U-Boot boot end",1);
#endif
}
uint32_t CkExtendDdrRamCheck(void* ramAddr, uint64_t ramSize)
{
//#ifdef COM_DDRCK_ON
volatile uint64_t *read_adr;
uint64_t data;
uint32_t loop, i;
char str[64];
read_adr = (uintptr_t *)ramAddr;
/* Write */
data = 0x5A5A5A5A5A5A5A5A;
for (loop = 0; loop < ramSize/8; loop++) {
read_adr[loop] = data;
}
/* Verify */
data = 0x5A5A5A5A5A5A5A5A;
for (loop = 0; loop < ramSize/8; loop++) {
if (read_adr[loop] != data) {
gErrDdrAdd = (uintptr_t)&read_adr[loop];
gErrDdrData = read_adr[loop];
gTrueDdrData = data;
return(ERROR_END);
}
}
/* Write */
data = 0xA5A5A5A5A5A5A5A5;
for (loop = 0; loop < ramSize/8; loop++) {
read_adr[loop] = data;
}
/* Verify */
data = 0xA5A5A5A5A5A5A5A5;
for (loop = 0; loop < ramSize/8; loop++) {
if (read_adr[loop] != data) {
gErrDdrAdd = (uintptr_t)&read_adr[loop];
gErrDdrData = read_adr[loop];
gTrueDdrData = data;
return(ERROR_END);
}
}
/* Write */
data = 0x0123456789ABCDEF;
for (loop = 0; loop < ramSize/8; loop++) {
read_adr[loop] = data;
data += 0x1111111111111111;
}
/* Verify */
data = 0x0123456789ABCDEF;
for (loop = 0; loop < ramSize/8; loop++) {
if (read_adr[loop] != data) {
gErrDdrAdd = (uintptr_t)&read_adr[loop];
gErrDdrData = read_adr[loop];
gTrueDdrData = data;
return(ERROR_END);
}
data += 0x1111111111111111;
}
return(NORMAL_END);
}
void rcar_set_log_time(void)
{
uint64_t now_time;
uint64_t freq;
uint64_t second;
uint64_t micro_sec;
uint64_t t_log[2][15];
int32_t i;
int32_t start_counter;
__asm__ volatile ("mrs %0, cntpct_el0" : "=r" (now_time));
__asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq));
if (freq == 0U) { /* for zero division */
second = 0U;
micro_sec = 0U;
} else {
second = now_time / freq;
micro_sec = ((now_time % freq) * 1000000U) / freq;
}
i = 14; /* counter initialize */
do {
t_log[0][i] = second % 10U;
second = second / 10U;
i--;
} while (second != 0U);
for (; i >= 10; i--) {
t_log[0][i] = (int)' ';
}
start_counter = i + 1;
t_log[1][0] = micro_sec / 100000U;
micro_sec %= 100000U;
t_log[1][1] = micro_sec / 10000U;
micro_sec %= 10000U;
t_log[1][2] = micro_sec / 1000U;
micro_sec %= 1000U;
t_log[1][3] = micro_sec / 100U;
micro_sec %= 100U;
t_log[1][4] = micro_sec / 10U;
t_log[1][5] = micro_sec % 10U;
(void)PutChar((int)'[');
for (i = start_counter; i < 15; i++) {
if (t_log[0][i] <= 9) {
(void)PutChar((int)((int)t_log[0][i] + (int)0x30));
} else {
(void)PutChar((int)' ');
}
}
(void)PutChar((int)'.');
for (i = 0; i < 6; i++) {
(void)PutChar((int)((int)t_log[1][i] + (int)0x30));
}
(void)PutChar((int)']');
(void)PutChar((int)' ');
}

234
IPL/SDK/v4h/src/Dummy_CA76/makefile Normal file
View File

@@ -0,0 +1,234 @@
#
# Copyright (c) 2020-2025 Renesas Electronics Corporation. All rights reserved.
#
#/* Select BOOT("CR7"or"ICUMXA")*************************
ifeq ("$(BOOT)", "")
BOOT = ICUMXA
endif
#/* Select dummy program(1:Secure Monitor/2:U-boot)*************************
ifeq ("$(DUMMY)", "1")
else
ifeq ("$(DUMMY)", "2")
DUMMY_FILE = 2
else ifeq ("$(DUMMY)", "3")
DUMMY_FILE = 3
else
DUMMY:=1
endif
endif
#/* Select AArch("64"or"32" )***************************************************
ifeq ("$(AArch)", "")
AArch = 64
endif
#/* Select D-Cache(0:Disable/1:Enable)******************************************
ifndef DCACHE
DCACHE := 0
endif
$(eval $(call add_define,DCACHE))
ifndef SDRAM_CHECK
SDRAM_CHECK := 0
endif
$(eval $(call add_define,SDRAM_CHECK))
ifndef ACC_PROT_ENABLE
ACC_PROT_ENABLE := 0
endif
$(eval $(call add_define,ACC_PROT_ENABLE))
ifndef OPTEE_LOAD_ENABLE
OPTEE_LOAD_ENABLE := 1
endif
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
#CPU
ifeq ("$(AArch)", "64")
CPU = -march=armv8-a
endif
ifeq ("$(AArch)", "32")
CPU = -mcpu=cortex-r7
endif
ifeq ("$(AArch)", "32")
THUMB = -marm
AS_NEON =
CC_NEON =
ALIGN = -mno-unaligned-access
endif
ifeq ("$(AArch)", "64")
THUMB =
AS_NEON =
CC_NEON = -mgeneral-regs-only
ALIGN = -mstrict-align
endif
ifeq ("$(AArch)", "32")
AArch32_64 = AArch32
BOOTDIR = AArch32_boot
OUTPUT_DIR = AArch32_output
OBJECT_DIR = AArch32_obj
CROSS_COMPILE ?= arm-eabi-
endif
ifeq ("$(AArch)", "64")
AArch32_64 = AArch64
BOOTDIR = AArch64_boot
OUTPUT_DIR = AArch64_output
OBJECT_DIR = AArch64_obj
CROSS_COMPILE ?= aarch64-elf-
endif
ifeq ("$(BOOT)", "CR7")
# BOOT_DEF = Writer
MEMORY_DEF = memory_cr7.def
FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA76_Program$(FILENAME_ADD)
endif
ifeq ("$(BOOT)", "ICUMXA")
# BOOT_DEF = Writer
ifeq ("$(DUMMY)", "2")
ifeq ("$(ACC_PROT_ENABLE)", "0")
MEMORY_DEF = memory_u_boot.def
else
MEMORY_DEF = memory_u_boot_rgid_on.def
endif
else ifeq ("$(DUMMY)", "3")
ifeq ("$(ACC_PROT_ENABLE)", "0")
ifeq ("$(OPTEE_LOAD_ENABLE)", "1")
MEMORY_DEF = memory_tee.def
else
$(error "Error:DUMMY=${DUMMY} && OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
endif
else
ifeq ("$(OPTEE_LOAD_ENABLE)", "1")
MEMORY_DEF = memory_tee_rgid_on.def
else
$(error "Error:DUMMY=${DUMMY} && OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
endif
endif
else
ifeq ("$(ACC_PROT_ENABLE)", "0")
MEMORY_DEF = memory_smon.def
else
MEMORY_DEF = memory_smon_rgid_on.def
endif
endif
FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA76_Program$(DUMMY_FILE)$(FILENAME_ADD)
endif
LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc
LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc
INCLUDE_DIR = include
OUTPUT_FILE = $(FILE_NAME).axf
#Object file
OBJ_FILE_BOOT = \
$(OBJECT_DIR)/boot_mon.o \
$(OBJECT_DIR)/stack.o
SRC_FILE := \
main.c \
init_scif.c \
hscifdrv0.c \
scifdrv0.c \
scifdrv3.c \
devdrv.c \
common.c \
mem_io.c \
generic_timer.c
ifeq ("$(DCACHE)", "1")
OBJ_FILE_BOOT += $(OBJECT_DIR)/d_armasm.o
SRC_FILE += vmsatable.c
endif
ifeq ("$(BOOT)", "WRITER_WITH_CERT")
SRC_FILE += cert_param.c
endif
OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE)))
#Dependency File
DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d))
###################################################
#C compiler
CC = $(CROSS_COMPILE)gcc
#Assembler
AS = $(CROSS_COMPILE)as
#Linker
LD = $(CROSS_COMPILE)ld
#Liblary
AR = $(CROSS_COMPILE)ar
#Object dump
OBJDMP = $(CROSS_COMPILE)objdump
#Object copy
OBJCOPY = $(CROSS_COMPILE)objcopy
#clean
CL = rm -rf
###################################################
# Suffixes
.SUFFIXES : .s .c .o
###################################################
# Command
.PHONY: all
all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE)
#------------------------------------------
# Make Directory
#------------------------------------------
$(OBJECT_DIR):
-mkdir "$(OBJECT_DIR)"
$(OUTPUT_DIR):
-mkdir "$(OUTPUT_DIR)"
#------------------------------------------
# Compile
#------------------------------------------
$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s
$(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0 --defsym DUMMY=$(DUMMY) --defsym ACC_PROT_ENABLE=$(ACC_PROT_ENABLE) --defsym OPTEE_LOAD_ENABLE=$(OPTEE_LOAD_ENABLE)
$(OBJECT_DIR)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
$(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 -DDUMMY=$(DUMMY) -DSDRAM_CHECK=$(SDRAM_CHECK) -DDCACHE=$(DCACHE) $(CFLAGS) -DACC_PROT_ENABLE=$(ACC_PROT_ENABLE) -DOPTEE_LOAD_ENABLE=$(OPTEE_LOAD_ENABLE)
#------------------------------------------
# Linker
#------------------------------------------
$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF)
$(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) \
-T '$(MEMORY_DEF)' \
-o '$(OUTPUT_FILE)' \
-Map '$(FILE_NAME).map' \
-static \
$(LIBS)
# Make SREC file
$(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).srec"
# Make Binary file
$(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin"
# Dis assemble
$(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt"
# Time Stamp
@echo ========== %date% %time% ==========
@echo ========== !!! Compile Complete !!! ==========
.PHONY: clean
clean:
$(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/*
-include $(DEPEND_FILE)

74
IPL/SDK/v4h/src/Dummy_CA76/mem_io.c Normal file
View File

@@ -0,0 +1,74 @@
/*******************************************************************************
* Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : memory access driver
******************************************************************************/
#include <stdint.h>
#include <mem_io.h>
void mem_write8(uintptr_t addr, uint8_t data)
{

38
IPL/SDK/v4h/src/Dummy_CA76/memory_cr7.def Normal file
View File

@@ -0,0 +1,38 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x44000000, LENGTH = 0x00014000
}
SECTIONS
{
.text : {
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}

39
IPL/SDK/v4h/src/Dummy_CA76/memory_smon.def Normal file
View File

@@ -0,0 +1,39 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x46400000, LENGTH = 0x00080000
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}

39
IPL/SDK/v4h/src/Dummy_CA76/memory_smon_rgid_on.def Normal file
View File

@@ -0,0 +1,39 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x2046400000, LENGTH = 0x00080000
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}

43
IPL/SDK/v4h/src/Dummy_CA76/memory_tee.def Normal file
View File

@@ -0,0 +1,43 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x44100000, LENGTH = 0x00100000
MMU_CPU0 : ORIGIN = 0x50080000, LENGTH = 16K
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}
MMU_BASE_CPU0 = ORIGIN(MMU_CPU0);

43
IPL/SDK/v4h/src/Dummy_CA76/memory_tee_rgid_on.def Normal file
View File

@@ -0,0 +1,43 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x2044100000, LENGTH = 0x00100000
MMU_CPU0 : ORIGIN = 0x2050080000, LENGTH = 16K
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}
MMU_BASE_CPU0 = ORIGIN(MMU_CPU0);

43
IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot.def Normal file
View File

@@ -0,0 +1,43 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x50000000, LENGTH = 0x00100000
MMU_CPU0 : ORIGIN = 0x50080000, LENGTH = 16K
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}
MMU_BASE_CPU0 = ORIGIN(MMU_CPU0);

43
IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot_rgid_on.def Normal file
View File

@@ -0,0 +1,43 @@
MEMORY {
RAM (rwxa): ORIGIN = 0x2050000000, LENGTH = 0x00100000
MMU_CPU0 : ORIGIN = 0x2050080000, LENGTH = 16K
}
SECTIONS
{
.text : {
__RO_START__ = .;
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}
MMU_BASE_CPU0 = ORIGIN(MMU_CPU0);

91
IPL/SDK/v4h/src/Dummy_CA76/scifdrv0.c Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv0.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF0) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF0(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) ));
*((volatile uint8_t*)SCIF0_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif0(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR2);
if(dataL & BIT7){ // case SCIF0
dataL &= ~BIT7;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_MSTPCR2) = dataL;
while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0
}
}
void WaitPutScif0SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF0_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif0PinFunction(void)
{
uint32_t dataL;
/* SCIF0 */
dataL = *((volatile uint32_t*)PFC_IP3SR7);
dataL &= ~(0x0FF00000);
dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */
*((volatile uint32_t*)PFC_IP3SR7) = ~dataL;
*((volatile uint32_t*)PFC_IP3SR7) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_IP3SR7) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif0_SCIFCLK(void)
{
uint16_t dataW;
PowerOnScif0();
InitScif0PinFunction();
dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
*((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */
SoftDelay(100);
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}

91
IPL/SDK/v4h/src/Dummy_CA76/scifdrv0_v3h.c Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv0.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF0) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF0_v3h(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) ));
*((volatile uint8_t*)SCIF0_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif0_v3h(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR2);
if(dataL & BIT7){ // case SCIF0
dataL &= ~BIT7;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR2) = dataL;
while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0
}
}
void WaitPutScif0_v3h_SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF0_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif0_v3h_PinFunction(void)
{
uint32_t dataL;
/* SCIF0 */
dataL = *((volatile uint32_t*)PFC_IPSR7);
dataL &= ~(0x0FF00000);
dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR7) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif0_v3h_SCIFCLK(void)
{
uint16_t dataW;
PowerOnScif0_v3h();
InitScif0_v3h_PinFunction();
dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
*((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */
SoftDelay(100);
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}

158
IPL/SDK/v4h/src/Dummy_CA76/scifdrv2.c Normal file
View File

@@ -0,0 +1,158 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv2.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF2) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF2(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR) ));
*((volatile unsigned char*)SCIF2_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif2(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR3);
if(dataL & BIT10){ // case SCIF2(IrDA) Standby
dataL &= ~BIT10;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR3) = dataL;
while( BIT10 & *((volatile uint32_t*)CPG_MSTPSR3) ); // wait bit=0
}
}
void WaitPutScif2SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF2_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif2PinFunction(void)
{
uint32_t dataL;
/* SCIF2 */
dataL = *((volatile uint32_t*)PFC_IPSR13);
dataL &= ~0x000000FF; /* IP13[7:4]=4'b0000, IP13[3:0]=4'b0000 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR13) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR5);
dataL |= 0x00000C00; /* GP5[11],GP5[10] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR5) = dataL;
}
void InitScif2_SCIFCLK(void)
{
uint16_t dataW;
uint32_t prr;
PowerOnScif2();
InitScif2PinFunction();
dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
#ifdef Writer
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */
#else /* Writer */
prr = *((volatile uint32_t*)PRR);
prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if (prr == PRR_PRODUCT_H3 | PRR_CUT_10) {
*((volatile uint8_t*)SCIF2_SCBRR) = 0x08; /* 115200bps@33MHz */
} else {
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */
}
#endif /* Writer */
SoftDelay(100);
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}
void InitScif2PinFunction_D3(void)
{
uint32_t dataL;
/* SCIF2 */
dataL = *((volatile uint32_t*)PFC_IPSR12);
dataL &= ~0x00000F00U; /* IP12[11:8]=4'b0000 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR12) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x0C000000U; /* GP4[27],GP4[26] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif2_SCIFCLK_D3(void)
{
uint16_t dataW;
uint32_t md;
uint32_t sscg;
PowerOnScif2();
InitScif2PinFunction_D3();
md = *((volatile uint32_t*)RST_MODEMR);
sscg = (md & 0x00001000) >> 12;
dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, S3D4/1 */
SoftDelay(100);
if(sscg == 0x0){ //MD12=0 (SSCG off) : S3D4C=66.6MHz
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200 bit-rate */
}
else if(sscg == 0x1){ //MD12=1 (SSCG on) : S3D4C=62.5MHz
*((volatile uint8_t*)SCIF2_SCBRR) = 0x10; /* 115200 bit-rate */
}
SoftDelay(100);
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SCK pin is not used */
SoftDelay(100);
}

192
IPL/SDK/v4h/src/Dummy_CA76/scifdrv3.c Normal file
View File

@@ -0,0 +1,192 @@
/*
* Copyright (c) 2021, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "common.h"
#include "scifdrv3.h"
#include "bit.h"
#include "reg_rcargen3.h"
#include "mem_io.h"
/* Pin function setting value */
#define POC_TX ((uint32_t)1U << 3U) /* TX3 */
#define POC_RX ((uint32_t)1U << 2U) /* RX3 */
#define GPSR_TX ((uint32_t)1U << 3U) /* TX3 */
#define GPSR_RX ((uint32_t)1U << 2U) /* RX3 */
#define POC_TX_33V ((uint32_t)1U << 3U) /* TX3 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 2U) /* RX3 3.3V setting value */
#define POC_TX_18V ((uint32_t)0U << 3U) /* TX3 1.8V setting value */
#define POC_RX_18V ((uint32_t)0U << 2U) /* RX3 1.8V setting value */
#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */
#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */
#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */
#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3 RX/TX */
#define PFC_POC_SCIF_18V (uint32_t)(POC_TX_18V | POC_RX_18V) /* SCIF3 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3 RX/TX */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3 RX/TX */
#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3 RX/TX) */
#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */
/********************************************************************************/
/* */
/* Debug Seirial(SCIF3) */
/* */
/********************************************************************************/
int32_t PutCharSCIF3(char outChar)
{
while(!(0x60U & *((volatile uint16_t*)SCIF3_SCFSR) ));
*((volatile uint8_t*)SCIF3_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF3_SCFSR) &= ~0x60U; /* TEND,TDFE clear */
return(0);
}
int32_t GetCharSCIF3(char *inChar)
{
do{
if(0x91U & *((volatile uint16_t *)SCIF3_SCFSR))
*((volatile uint16_t *)SCIF3_SCFSR) &= ~0x91U;
if(0x01U & *((volatile uint16_t *)SCIF3_SCLSR))
{
PutStr("ORER",1U);
*((volatile uint16_t *)SCIF3_SCLSR) &= ~0x01U;
}
}while( !(0x02U & *((volatile uint16_t *)SCIF3_SCFSR)) );
*inChar = *((volatile char*)SCIF3_SCFRDR);
*((volatile uint16_t*)SCIF3_SCFSR) &= ~0x02U;
return(0);
}
void PowerOnSCIF3(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR7);
if(dataL & BIT4){
dataL &= ~BIT4;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_MSTPCR7) = dataL;

283
IPL/SDK/v4h/src/Dummy_CA76/vmsatable.c Normal file
View File

@@ -0,0 +1,283 @@
/**********************************************************/
/* Sample program : VMSA Table Generate */
/* File Name : vmsatable.c */
/* Copyright (C) Renesas Electronics Corp. 2015. */
/**********************************************************/
#include "common.h"
#include "vmsatable.h"
#include "d_armasm.h"
#ifdef AArch64
extern const char MMU_BASE_CPU0[];
#endif
#ifdef AArch32
#define MMU_BASE_CPU0 0xE6300000
#endif
#define TBL_SIZE 4096
#define TBL_NUM (TBL_SIZE/8)
#define Lvl1VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x0000) // +0kB
#define Lvl2VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x1000) // +4kB
#define Lvl3VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x2000) // +8kB
#define Lvl1StartAddr (0x0000000000)
#define Lvl1BlockSize (0x0040000000) // 1GB
#define Lvl1BlockShift (30) // BIT30
#define Lvl2StartAddr (0x00C0000000)
#define Lvl2BlockSize (0x0000200000) // 2MB
#define Lvl2BlockShift (21) // BIT21
#define Lvl3StartAddr (0x00E6200000)
#define Lvl3BlockSize (0x0000001000) // 4KB
#define Lvl3BlockShift (12) // BIT12
#define BIT47_12 0x0000FFFFFFFFF000
typedef struct vmsaTable{
uint64_t vAddr;
uint64_t pAddr;
uint64_t unit;
uint64_t upperAttr;
uint64_t lowerAttr;
}vmsaTable;
//------------------------------------------------------------------
// Referenced: DDI0487A_f_armv8_arm.pdf
// D4.4 VMSAv8-64 translation table format descriptors
//------------------------------------------------------------------
#define ATTR_TBL 0x444444FF0C080400 // MAIR_EL1
// // [63:56]Attr7=0x44 : ----------------- (Blank)
// // [55:48]Attr6=0x44 : ----------------- (Blank)
// // [47:40]Attr5=0x44 : NORMAL_NON_CACHEABLE Normal Memory Non-Cacheable
// // [39:32]Attr4=0x77 : NORMAL_WRITE_BACK Normal Memory Write-back transient
// // [31:24]Attr3=0x0C : DEVICE_GRE_MEM Device-GRE memory
// // [23:16]Attr2=0x08 : DEVICE_NGRE_MEM Device-nGRE memory
// // [15: 8]Attr1=0x04 : DEVICE_NGNRE_MEM Device-nGnRE memory
// // [ 7: 0]Attr0=0x00 : DEVICE_NGNRNE_MEM Device-nGnRnE memory
// CPU0 VMSA table Level1 (4kB)
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR4ch[] = {
// [MEM]Memory Address ...BIT[1:0]=01
// [TBL]Next Level Table Address ...BIT[1:0]=11
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0500000000, 0x0500000000, 4, 0x000, 0x411 }, // [MEM]DDR1 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0700000000, 0x0700000000, 4, 0x000, 0x411 }, // [MEM]DDR3 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
// CPU0 VMSA table Level1 (4kB)
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR2ch[] = {
// [MEM]Memory Address ...BIT[1:0]=01
// [TBL]Next Level Table Address ...BIT[1:0]=11
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
// CPU0 VMSA table Level1 (4kB)
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR1ch[] = {
// [MEM]Memory Address ...BIT[1:0]=01
// [TBL]Next Level Table Address ...BIT[1:0]=11
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
// CPU0 VMSA table Level2 (4kB)
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl2Cpu0[] = {
// [MEM]Memory Address ...BIT[1:0]=01
// [TBL]Next Level Table Address ...BIT[1:0]=11
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (2MBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x00E6200000, Lvl3VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 2MB 0 0 00 00 0 000 11 (Next Level Table)
{ 0x00EB200000, 0x00EB200000, 1, 0x000, 0x411 }, // [MEM]RT-SRAM 2MB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) @V3U
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
#ifdef SYSTEM_DEF_FALCON
// CPU0 VMSA table Level3 (4kB) @V3U CPUボード到着後に上のvmsaTable ArmVmsaTblLvl3Cpu0[]と入れ替え
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl3Cpu0[] = {
// [INV]Invalid ...BIT[1:0]=x0
// [RES]Reserved ...BIT[1:0]=01
// [MEM]Memory Address ...BIT[1:0]=11 <-- Select
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
{ 0x00E6300000, 0x00E6300000, 256, 0x000, 0x413 }, // [MEM]SystemRAM 1MB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) @V3U
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
#else
// CPU0 VMSA table Level3 (4kB) @V3H
// Virtual address == Physical Address
const vmsaTable ArmVmsaTblLvl3Cpu0[] = {
// [INV]Invalid ...BIT[1:0]=x0
// [RES]Reserved ...BIT[1:0]=01
// [MEM]Memory Address ...BIT[1:0]=11 <-- Select
// Virtual Address Physical Address BLOCK Upper Lower Attr
// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
// Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0]
{ 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
{ 0x00E6300000, 0x00E6300000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient)
{ 0x00E6330000, 0x00E6330000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient)
{ 0x00E6360000, 0x00E6360000, 160, 0x000, 0x403 }, // [MEM]SystemRAM 640KB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
};
#endif
static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift);
uint32_t SetVmsaTable(void)
{
uint64_t *vmsaTblSadd;
vmsaTable *vmsaSrcTbl;
uint64_t startAddr;
uint64_t blockShift;
// TCR_EL3, Translation Control Register (EL3)
// [31] Reserved-1: 1
// [30:29] Reserved-0: 0
//
// When ARMv8.2-TTPBHA is implemented
// [28] HWU62 : 0 :Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
// [27] HWU61 : 0 :Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
// [26] HWU60 : 0 :Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
// [25] HWU59 : 0 :Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
// -The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.
// -This field resets to an architecturally UNKNOWN value.
// [24] HPD : 0 :Hierarchical Permission Disables.
// Otherwise
// [28:24] Reserved-0: 00000
//
// [23] Reserved-1: 1
// When ARMv8.1-TTHM is implemented
// [22] HD : 0 :Hardware management of dirty state in stage 1 translations from EL3.
// [21] HA : 0 :Hardware Access flag update in stage 1 translations from EL3.
// Otherwise
// [22:21] Reserved-0: 00
//
// [20] TBI : 0 : Top Byte used in the address calculation.
// [19] Reserved-0: 0
// [18:16] PS : 001 : Physical Address Size 000=32bit, 001=36bit, 010=40bit, 011=42bit, 100=44bit, 101=48bit
// [15:14] TG0 : 00 : translation table 00=4KB, 01=64KB, 10=16KB
// [13:12] SH0 : 10 : translation table memory 00=Non-shareable, 10=Outer Shareable, 11=Inner Shareable
// [11:10] ORGN0 : 01 : Outer 01=Write-Back Write-Allocate Cacheable
// [09:08] IRGN0 : 01 : Inner 01=Write-Back Write-Allocate Cacheable
// [07:06] Reserved : 00
// [05:00] T0SZ : 011100 : The region size is 2^(64-T0SZ) byte. 2^(64-28)=2^36=0x10_0000_0000
WriteTCR_EL3(0x8081251C);
WriteMAIR_EL3(ATTR_TBL);
WriteTTBR0_EL3((uint64_t)Lvl1VmsaTbl); // ASID=0
#ifdef SYSTEM_DEF_FALCON
// VMSA Table Level1 for Main
vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch;
#else
// VMSA Table Level1 for Main
// if( CHK_H3 && (!CHK_H3N) ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; } // 4ch : H3
// else if( CHK_M3 ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : M3
// else if( CHK_H3N ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : H3N
// else { vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR1ch; } // 1ch : M3N,V3H,V3M,D3,E3
#endif
vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch;
vmsaTblSadd = (uint64_t*)Lvl1VmsaTbl;
startAddr = Lvl1StartAddr;
blockShift = Lvl1BlockShift;
MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
// VMSA Table Level2 for IPs
vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl2Cpu0;
vmsaTblSadd = (uint64_t*)Lvl2VmsaTbl;
startAddr = Lvl2StartAddr;
blockShift = Lvl2BlockShift;
MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
// VMSA Table Level3 for IPs
vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl3Cpu0;
vmsaTblSadd = (uint64_t*)Lvl3VmsaTbl;
startAddr = Lvl3StartAddr;
blockShift = Lvl3BlockShift;
MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
return 0;
}
static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift)
{
uint32_t i,j;
uint64_t setData;
uint64_t *setAddr;
uint64_t upperAttr; // Attribute fields for VMSAv8-64 ([63:52])
uint64_t lowerAttr; // Attribute fields for VMSAv8-64 ([11:0])
uint64_t virAdd;
uint64_t phyAdd;
uint64_t block;
uint64_t blockSize;
blockSize = (1<<blockShift);
// Level1 : make default table (non-cacheable)
upperAttr = 0x000; // [63:52] : [52]=Contiguous=1? (T.B.D.)
lowerAttr = 0x401; // [11:0] : nG=0, AF=1, SH=00, AP=00, NS=0, AttrIndx=000, [1:0]=01
setAddr = vmsaTblSadd;
setData = (upperAttr<<52)|(startAddr&BIT47_12)|(lowerAttr);
for(i=0;i<TBL_NUM;i++){
*setAddr = setData;
setAddr++; // Virtual Address (+1GB)(+2MB)
setData += blockSize; // Physical Address (+1GB)(+2MB)
}
// Level1 :
// Descriptor Address[47:12] = TTBR[47:12]
// Descriptor Address[11:03] = Input Address[38:30]
// Descriptor Address[02:00] = 0,0,0
// ----------
// Descriptor[47:12] = Physical Address[47:12] or Level2 table address[47:12]
for(i=0; vmsaSrcTbl[i].unit!=0 ;i++){
virAdd = vmsaSrcTbl[i].vAddr;
phyAdd = vmsaSrcTbl[i].pAddr;
setAddr = (uint64_t*)(uintptr_t)((uintptr_t)vmsaTblSadd + ((virAdd-startAddr)>>(blockShift-3)));
setData = vmsaSrcTbl[i].upperAttr<<52; // [63:52]
setData |= phyAdd; // [47:12]
setData |= vmsaSrcTbl[i].lowerAttr; // [11:00]
block = vmsaSrcTbl[i].unit;
for(j=0; j<block; j++){
*setAddr = setData;
setAddr++; // Virtual Address (+1GB)(+2MB)
setData += blockSize; // Physical Address (+1GB)(+2MB)
}
}
}

127
IPL/SDK/v4h/src/Dummy_FW/Makefile Normal file
View File

@@ -0,0 +1,127 @@
# ******************************************************************************
# * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
# *
# * DESCRIPTION : makefile for Dummy FW
# ******************************************************************************
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude
OUTDIR := build
#output file name
FILE_NAME = dummy_fw
OUTPUT_FILE = $(FILE_NAME).elf
#object file name
OBJ_FILE = common/mem_io.o \
common/scif.o \
common/log.o \
common/micro_wait.o \
common/remap.o \
common/wdt.o \
fw/dummy_fw_main.o \
fw/dummy_fw.o \
fw/vecttbl.o
#linker script name
MEMORY_DEF = fw/dummy_fw.ld
###################################################
# Debug build
DEBUG:=0
# Process DEBUG flag
$(eval $(call assert_boolean,DEBUG))
$(eval $(call add_define,DEBUG))
ifeq (${DEBUG},0)
$(eval $(call add_define,NDEBUG))
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Ogeneral
else
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Odebug
endif
###################################################
OUTDIR_REL := $(OUTDIR)/release
OUTDIR_OBJ := $(OUTDIR)/obj
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
CC = cxrh850
AS = cxrh850
LD = cxrh850
OC = gsrec
OD = gdump
ASFLAGS += -asm="-preprocess_assembly_files" \
-asm="-nostartfiles" \
-D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -nostartfiles \
-c99 \
$(INCLUDE_DIR) $(DEFINES)
LDFLAGS = -nostartfiles
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c
@$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
@$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
-T $(MEMORY_DEF) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
$(LDFLAGS) \
-map=$(OUTDIR_REL)/$(FILE_NAME).map
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
@$(OD) -full -ytext $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
###################################################
# Compile
###################################################
$(OUTDIR_OBJ)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(CC) $(CFLAGS) -o $@ -c $<
$(OUTDIR_OBJ)/%.o:%.S
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(AS) $(ASFLAGS) -o $@ -c $<
.PHONY: clean
clean:
@rm -rf $(OUTDIR)

34
IPL/SDK/v4h/src/Dummy_FW/common/log.c Normal file
View File

@@ -0,0 +1,34 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Log driver
******************************************************************************/
#include <stdarg.h>
#include <stdint.h>
#include <log.h>
#include <scif.h>
void local_printf(const char *fmt, ...)
{
va_list ap;
static char buffer[1024];
int32_t num;
uint32_t loop;
va_start(ap, fmt);
num = vsprintf(buffer, fmt, ap);
va_end(ap);
if (0 < num) {
for (loop = 0; loop < num; loop++) {
(void)console_putc(buffer[loop]);
if (buffer[loop] == '\n') {
(void)console_putc('\r');
}
}
} else {
panic();
}
}

48
IPL/SDK/v4h/src/Dummy_FW/common/mem_io.c Normal file
View File

@@ -0,0 +1,48 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : memory access driver
******************************************************************************/
#include <stdint.h>
void mem_write8(uintptr_t addr, uint8_t data)
{
*(volatile uint8_t*)addr = data;
}
uint8_t mem_read8(uintptr_t addr)
{
return (*(volatile uint8_t*)addr);
}
void mem_write16(uintptr_t addr, uint16_t data)
{
*(volatile uint16_t*)addr = data;
}
uint16_t mem_read16(uintptr_t addr)
{
return (*(volatile uint16_t*)addr);
}
void mem_write32(uintptr_t addr, uint32_t data)
{
*(volatile uint32_t*)addr = data;
}
uint32_t mem_read32(uintptr_t addr)
{
return (*(volatile uint32_t*)addr);
}
void mem_write64(uintptr_t addr, uint64_t data)
{
*(volatile uint64_t*)addr = data;
}
uint64_t mem_read64(uintptr_t addr)
{
return (*(volatile uint64_t*)addr);
}
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
}

72
IPL/SDK/v4h/src/Dummy_FW/common/micro_wait.c Normal file
View File

@@ -0,0 +1,72 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Time wait driver
******************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (*(volatile uint16_t*)0xFFFEEA14U)
#define INTCR_RF (1U <<12)
#define OSTM0_BASE (0xFFFEE000UL)
#define OSTM0CMP (*(volatile uint32_t*)(OSTM0_BASE))
#define OSTM0CNT (*(volatile uint32_t*)(OSTM0_BASE + 0x4UL))
#define OSTM0TE (*(volatile uint8_t*)(OSTM0_BASE + 0x10UL))
#define OSTM0TS (*(volatile uint8_t*)(OSTM0_BASE + 0x14UL))
#define OSTM0TT (*(volatile uint8_t*)(OSTM0_BASE + 0x18UL))
#define OSTM0CTL (*(volatile uint8_t*)(OSTM0_BASE + 0x20L))
#define OSTM0EMU (*(volatile uint32_t*)(OSTM0_BASE + 0x24L))
#define OSTM0TS_TS (1U) /* b0:1: Start */
#define OSTM0TT_TT (1U) /* b0:1: Stop */
#define OSTM0TE_TE (1U) /* b0:1: Counter enabled */
#define OSTM0CMP_MICRO_VALUE (0x190UL) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (0x2U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
/************************************************************************************************/
/* Prototypes */
/************************************************************************************************/
static void start_microtimer(uint32_t val);
static void stop_microtimer(void);
static void start_microtimer(uint32_t val)
{
OSTM0TT = OSTM0TT_TT;
OSTM0CMP = val;
OSTM0CTL = OSTM0CTL_MD10;
OSTM0TS = OSTM0TS_TS;
}
static void stop_microtimer(void)
{
OSTM0TT = OSTM0TT_TT;
}
void micro_wait(uint32_t count_us)
{
uint32_t val;
if (count_us == 0) {
return;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
start_microtimer(val);
while (1) {
if (INTICUOSTM0 & INTCR_RF) {
INTICUOSTM0 &= (uint16_t)(~INTCR_RF);
stop_microtimer();
break;
}
}
}

171
IPL/SDK/v4h/src/Dummy_FW/common/remap.c Normal file
View File

@@ -0,0 +1,171 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap driver
******************************************************************************/
#include <stdint.h>
#include <remap.h>
#include <remap_register.h>
#include <mem_io.h>
#include <log.h>
typedef struct {
uint8_t number;
uint32_t address;
}REMAP_ADDRESS_TABLE;
#define REMAP_TBL_MAX (sizeof(remap_tbl)/sizeof(remap_tbl[0]))
static REMAP_ADDRESS_TABLE remap_tbl[] = {
[0] = {0xFF, 0x00000000U},
[1] = {0xFF, 0x00000000U},
[2] = {0xFF, 0x00000000U},
[3] = {0xFF, 0x00000000U},
[4] = {0xFF, 0x00000000U},
[5] = {0xFF, 0x00000000U},
[6] = {6, 0xE7200000U},
[7] = {7, 0xE6400000U},
[8] = {8, 0xFFC10000U},
[9] = {9, 0xE6C00000U},
[10] = {10, 0xFFC10000U},
[11] = {11, 0xEE200000U},
[12] = {12, 0xE6200000U},
[13] = {13, 0xE6000000U},
[14] = {14, 0xE6600000U},
[15] = {15, 0xEB200000U},
};
void remap_write_SICREMAP2M(uint32_t num, uint32_t value)
{
/* Write-Protected Register Write Procedure */
do {
mem_write32(ICUMX_PROT0PCMD, PROTCMD_START);
mem_write32(SICREMAP2M(num), value);
mem_write32(SICREMAP2M(num), ~value);
mem_write32(SICREMAP2M(num), value);
} while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR);
}
uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr)
{
uint32_t loop;
uint32_t loop2;
uint32_t map_num;
uint32_t set_addr;
for (loop = 0; loop < REMAP_TBL_MAX; ++loop) {
if (0xFF == remap_tbl[loop].number) {
map_num = (addr & REMAP_2M_MASK) + size;
map_num = (map_num + REMAP_2M_MASK)
/ (1 << REMAP_2M_BITS);
for (loop2 = 0; loop2 < map_num; ++loop2) {
if (0xFF != remap_tbl[loop].number) {
break;
}
}
if (map_num <= loop2) {
break;
}
}
}
if (REMAP_TBL_MAX <= loop) {
return 2;
}
__asm__ __volatile__ ("SYNCM");
set_addr = addr & ~REMAP_2M_MASK;
for (loop2 = loop; loop2 < (map_num + loop); ++loop2) {
remap_tbl[loop2].address = set_addr;
remap_tbl[loop2].number = loop;
remap_write_SICREMAP2M(loop2, set_addr);
set_addr += (1 << REMAP_2M_BITS);
}
__asm__ __volatile__ ("SYNCM");
*remap_addr = ICU_REMAP_CALC(loop);
*remap_addr += addr & REMAP_2M_MASK;
return 0;
}
uint32_t remap_unregister(uint32_t remap_addr)
{
uint32_t loop;
uint32_t loop2;
uint32_t remove_num;
for (loop = 0; loop < REMAP_TBL_MAX; ++loop) {
if ((0xFF != remap_tbl[loop].number)
&& ((ICU_REMAP_CALC(loop) <= remap_addr)
&& (remap_addr < ICU_REMAP_CALC(loop+1)))) {
break;
}
}
if (REMAP_TBL_MAX <= loop) {
return 1;
}
__asm__ __volatile__ ("SYNCM");
remove_num = remap_tbl[loop].number;
for (loop2 = remove_num; loop2 < REMAP_TBL_MAX; ++loop2) {
if (remap_tbl[loop2].number != remove_num) {
break;
}
remap_tbl[loop2].address = 0;
remap_tbl[loop2].number = 0xFF;
remap_write_SICREMAP2M(loop2, ICU_REMAP_CALC(loop2));
}
__asm__ __volatile__ ("SYNCM");
return 0;
}
uint32_t remap_get_phys_addr(uint32_t remap_addr)
{
uint32_t phys_addr;
uint32_t reg;
if ((ICU_REMAP0 > remap_addr)
|| (ICU_REMAP_CALC(REMAP_REG_MAX) <= remap_addr)) {
ERROR("remap address Error\n");
panic();
}
phys_addr = remap_addr - ICU_REMAP0;
phys_addr >>= REMAP_2M_BITS;
reg = SICREMAP2M(phys_addr);
reg = mem_read32(reg);
phys_addr = reg + (remap_addr & REMAP_2M_MASK);
return phys_addr;
}
uint32_t remap_get_remap_addr(uint32_t phys_addr)
{
uint32_t remap_addr;
uint32_t reg;
uint32_t loop;
for (loop = 0; loop < REMAP_REG_MAX; loop++) {
reg = mem_read32(SICREMAP2M(loop));
if ((reg <= phys_addr)
&& (phys_addr <= (reg + REMAP_2M_MASK))) {
break;
}
}
if (REMAP_REG_MAX <= loop) {
ERROR("remap address Error\n");
panic();
}
remap_addr = ICU_REMAP_CALC(loop);
remap_addr += phys_addr - reg;
return remap_addr;
}

416
IPL/SDK/v4h/src/Dummy_FW/common/scif.c Normal file
View File

@@ -0,0 +1,416 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF driver
******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <scif_register.h>
#include <rcar_def.h>
#include <scif.h>
#include <mem_io.h>
#include <micro_wait.h>
#include <rst_register.h>
/* Define */
#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U)
#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U)
#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN)
#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U)
#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U)
#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U)
#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN)
#define SCIF_SCFCR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCSMR_INIT_DATA (uint16_t)(0x0000U)
/* Pclk(66MHz)/1, 115.2kBps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 921.6kBps*/
/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */
#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 1.8432MBps*/
/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */
#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U)
#define SCIF_SCBRR_HW_INIT (uint8_t)(0xFFU)
#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U)
#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */
#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8)
#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U)
#define HSCIF_CKS_SC_CLK_EXT (uint16_t)(0x0000U)
#define MODEMR_SCIF_DLMODE (0x00000000U)
#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U)
#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
static void (*put_char)(uint8_t);
static void scif_console_putc(uint8_t outchar);
static void hscif_console_putc(uint8_t outchar);
void scif_init(void)
{
// volatile uint16_t reg;
uint32_t modemr;
uint32_t product;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_S4:
modemr = (((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U)
| ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U));
if(modemr == MODEMR_SCIF_DLMODE)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(SCIF_SCFCR_3, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(SCIF_SCLSR_3, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR_3, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(SCIF_SCSMR_3, SCIF_SCSMR_INIT_DATA);
/* Baud rate 115200bps*/
mem_write16(SCIF_SCBRR_3, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(SCIF_SCFCR_3, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = scif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 921600bps*/
mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 1843200bps*/
mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* external clock, SC_CLK pin used for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* 24MHz / (3000000 * 8) = 1 */
mem_write16(HSCIF_DL, HSCIF_DL_DIV1);
mem_write16(HSCIF_CKS, HSCIF_CKS_SC_CLK_EXT);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=external */
mem_write16(HSCIF_HSSCR, mem_read16(HSCIF_HSSCR) | SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else
{
/* No process */
}
break;
case PRR_PRODUCT_V4H:
case PRR_PRODUCT_V4M:
modemr = (((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U)
| ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U));
if(modemr == MODEMR_SCIF_DLMODE)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(SCIF_SCFCR_0, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(SCIF_SCLSR_0, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR_0, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(SCIF_SCSMR_0, SCIF_SCSMR_INIT_DATA);
/* Baud rate 115200bps*/
mem_write16(SCIF_SCBRR_0, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(SCIF_SCFCR_0, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = scif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 921600bps*/
mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 1843200bps*/
mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* external clock, SC_CLK pin used for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA);
/* 24MHz / (3000000 * 8) = 1 */
mem_write16(HSCIF_DL, HSCIF_DL_DIV1);
mem_write16(HSCIF_CKS, HSCIF_CKS_SC_CLK_EXT);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=external */
mem_write16(HSCIF_HSSCR, mem_read16(HSCIF_HSSCR) | SCIF_SCSCR_INIT_DATA);
/* Set the pointer to a function that outputs one character. */
put_char = hscif_console_putc;
}
else
{
/* No process */
}
break;
default:
break;
}
}
void console_puts(char *str,char rtn)
{
while (*str) {
console_putc(*str);
str++;
}
if(rtn == 1){
console_putc(CR_CODE);
console_putc(LF_CODE);
}
}
void console_putc(uint8_t outchar)
{
put_char(outchar);
}
static void scif_console_putc(uint8_t outchar)
{
uint16_t reg;
uint32_t product;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_S4:
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR_3)) == TRANS_END_CHECK)){
}
mem_write8(SCIF_SCFTDR_3, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR_3);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR_3, reg);
break;
case PRR_PRODUCT_V4H:
case PRR_PRODUCT_V4M:
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR_0)) == TRANS_END_CHECK)){
}
mem_write8(SCIF_SCFTDR_0, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR_0);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR_0, reg);
break;
}
}
static void hscif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)){
}
mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */
reg = mem_read16(HSCIF_HSFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(HSCIF_HSFSR, reg);
}

59
IPL/SDK/v4h/src/Dummy_FW/common/wdt.c Normal file
View File

@@ -0,0 +1,59 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : window watchdog timer driver
******************************************************************************/
/******************************************************************************
* @file wdt.c
* - Version : 0.01
* @brief Window Watchdog Timer driver
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <wdt.h>
#include <mem_io.h>
#define ICUMX_WDTA0_BASE (0xFFFEE080U) /* Watchdog Timer base */
#define ICUMX_WDTA0EVAC (ICUMX_WDTA0_BASE+0x0004U)
#define ICUMX_WDTA0REF (ICUMX_WDTA0_BASE+0x0008U)
/* Activation code */
#define WDT_ACT_CODE (0xACU)
void wdt_restart(void)
{
uint8_t reg;
reg = mem_read8(ICUMX_WDTA0REF);
/* Watchdog Timer restart. */
/* Subtract ICUMX_WDTA0REF from activation code when VAC(Variable Activation Code) is enabled. */
mem_write8(ICUMX_WDTA0EVAC, WDT_ACT_CODE - reg);
}
/* End of function wdt_restart(void) */

59
IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.S Normal file
View File

@@ -0,0 +1,59 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW start code
******************************************************************************/
.global code_start
.global _dummy_fw_main
.global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */
.section ".text"
.align 2
code_start:
mov r0, r1
mov r0, r2
mov r0, r3
mov r0, r4
mov r0, r5
mov r0, r6
mov r0, r7
mov r0, r8
mov r0, r9
mov r0, r10
mov r0, r11
mov r0, r12
mov r0, r13
mov r0, r14
mov r0, r15
mov r0, r16
mov r0, r17
mov r0, r18
mov r0, r19
mov r0, r20
mov r0, r21
mov r0, r22
mov r0, r23
mov r0, r24
mov r0, r25
mov r0, r26
mov r0, r27
mov r0, r28
mov r0, r29
ldsr r0, 0, 0
ldsr r0, 16, 0
mov ___ghsend_RT_stack, sp
jarl _dummy_fw_main, lp
jmp [r10]
nop
halt
.section ".padding"
.align 4

79
IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.ld Normal file
View File

@@ -0,0 +1,79 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW linker directive
******************************************************************************/
DEFAULTS {
remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000)
remap_size = 1M //RT-SRAM size
rt_sram_addr = 0xEB200000 //RT-SRAM address
// fw_size = 110K //Dummy FW size
fw_size = 93K //Dummy FW size
fw_rom_size = 89K
fw_stack_size = 4K //Dummy FW stack size
fw_addr = 0xFDE40000 //Dummy FW start address
fw_stack_addr = fw_addr + fw_rom_size //Dummy FW stack address
fw_phy_addr = 0xEB240000 //Dummy FW physical start address
fw_phy_stack_addr = fw_phy_addr + fw_rom_size //Dummy FW physical stack address
}
MEMORY
{
fw_start : ORIGIN = fw_addr, LENGTH = fw_rom_size //Dummy FW ROM(Start address)
stack : ORIGIN = fw_stack_addr, LENGTH = fw_stack_size//Dummy FW stack
fw_phys_start : ORIGIN = fw_phy_addr, LENGTH = fw_rom_size //Dummy FW(RT-SRAM)
}
//
// Program layout for starting in ROM, copying data to RAM,
// and continuing to execute out of ROM.
//
SECTIONS
{
//
// ROM SECTIONS(Remap)
//
// Place .text into fast_memory. Fail if it does not fit.
.reset ALIGN(4) : > fw_start
.EIINTTBL_ICU ALIGN(4) : > .
.version ALIGN(1024) :{*(.version)} > .
.text ALIGN(16) : > .
.data ALIGN(4) : > .
.rosdata ALIGN(4) : > .
.rodata ALIGN(4) : > .
.bss ALIGN(4) : > .
.sdata ALIGN(4) : > .
.tdata ALIGN(4) : > .
.sdabase ALIGN(4) : > .
.secinfo ALIGN(4) : > .
.padding ALIGN(16) MIN_SIZE(16): > .
// .note.renesas ALIGN(4) : > .
// .linfix ALIGN(4) : > .
// .gstackfix ALIGN(4) : > .
// ROM mirror SECTIONS(RT-SRAM)
_start = fw_phy_addr;
.ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > fw_phys_start
.ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > .
.ROM_NOCOPY.version ROM_NOCOPY(.version) ALIGN(1024) : > .
.ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > .
.ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > .
.ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > .
.ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > .
.ROM_NOCOPY.bss ROM_NOCOPY(.bss) ALIGN(4) : > .
.ROM_NOCOPY.sdata ROM_NOCOPY(.sdata) ALIGN(4) : > .
.ROM_NOCOPY.tdata ROM_NOCOPY(.tdata) ALIGN(4) : > .
.ROM_NOCOPY.sdabase ROM_NOCOPY(.sdabase) ALIGN(4) : > .
.ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > .
.ROM_NOCOPY.padding ROM_NOCOPY(.padding) ALIGN(16) : > .
//
// RAM SECTIONS
//
.RT.stack ALIGN(4) PAD(fw_stack_size) ABS : > stack
}

45
IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw_main.c Normal file
View File

@@ -0,0 +1,45 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : dummy fw main function
******************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <log.h>
#include <dummy_fw_main.h>
#include <mem_io.h>
#include <remap.h>
#include <remap_register.h>
#include <rcar_def.h>
#include <scif.h>
#include <rst_register.h>
#include <wdt.h>
/* Software version */
#define SW_VERSION_DUMMY_FW (0x00000001U)
/* Global */
extern const char build_message[];
static void boot_message(void);
__attribute__ ((section (".version"))) const uint32_t sw_version[1] = {
[0] = SW_VERSION_DUMMY_FW,
};
uint32_t dummy_fw_main(void)
{
scif_init();
boot_message();
while(1){
wdt_restart();
}
}
static void boot_message(void)
{
/* boot message */
console_puts("",1);
console_puts("Dummy FW Program",1);
console_puts("Dummy FW Program boot end",1);
}

98
IPL/SDK/v4h/src/Dummy_FW/fw/vecttbl.S Normal file
View File

@@ -0,0 +1,98 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW vector table
******************************************************************************/
.global code_start
.section ".reset"
.align 512
.align 16
_start:
jr32 code_start //RESET
.align 16
jr32 _Dummy //SYSERR
.align 16
jr32 _Dummy //HVTRAP
.align 16
jr32 _Dummy //FETRAP
.align 16
jr32 _Dummy //TRAP0
.align 16
jr32 _Dummy //TRAP1
.align 16
jr32 _Dummy //RIE
.align 16
jr32 _Dummy //FPP/FPI
.align 16
jr32 _Dummy //UCPOP
.align 16
jr32 _Dummy //MIP/MDP
.align 16
jr32 _Dummy //PIE
.align 16
jr32 _Dummy //Debug
.align 16
jr32 _Dummy //MAE
.align 16
jr32 _Dummy //(R.F.U)
.align 16
jr32 _Dummy //FENMI
.align 16
jr32 _Dummy //FEINT
.align 16
jr32 _Dummy //INTn(priority0)
.align 16
jr32 _Dummy //INTn(priority1)
.align 16
jr32 _Dummy //INTn(priority2)
.align 16
jr32 _Dummy //INTn(priority3)
.align 16
jr32 _Dummy //INTn(priority4)
.align 16
jr32 _Dummy //INTn(priority5)
.align 16
jr32 _Dummy //INTn(priority6)
.align 16
jr32 _Dummy //INTn(priority7)
.align 16
jr32 _Dummy //INTn(priority8)
.align 16
jr32 _Dummy //INTn(priority9)
.align 16
jr32 _Dummy //INTn(priority10)
.align 16
jr32 _Dummy //INTn(priority11)
.align 16
jr32 _Dummy //INTn(priority12)
.align 16
jr32 _Dummy //INTn(priority13)
.align 16
jr32 _Dummy //INTn(priority14)
.align 16
jr32 _Dummy //INTn(priority15)
.section ".EIINTTBL_ICU", const
.align 512
.rept 7
.word _Dummy_EI //INTn
.endr
.word _Dummy_EI //OSTM0
.rept 20
.word _Dummy_EI //INTn
.endr
.word _Dummy_EI //_Dummy
.word _Dummy_EI //_Dummy
.rept 98
.word _Dummy_EI //INTn
.endr
.section ".text"
.align 2
_Dummy:
br _Dummy
_Dummy_EI:
br _Dummy_EI

16
IPL/SDK/v4h/src/Dummy_FW/include/dummy_fw_main.h Normal file
View File

@@ -0,0 +1,16 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW main header
******************************************************************************/
#ifndef DUMMY_FW_MAIN_H_
#define DUMMY_FW_MAIN_H_
/* define */
#define VERSION "1.0.0"
/* prototype */
uint32_t dummy_fw_main(void);
#endif /* DUMMY_FW_MAIN_H_ */

64
IPL/SDK/v4h/src/Dummy_FW/include/log.h Normal file
View File

@@ -0,0 +1,64 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Log driver header
******************************************************************************/
#ifndef LOG_H__
#define LOG_H__
#include <stdint.h>
#include <stdio.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#ifndef LOG_LEVEL
#define LOG_LEVEL (LOG_WARNING)
#endif
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) local_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) local_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) local_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) local_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) local_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#define panic(...) \
do { \
local_printf("P:%s[%d]\n", __func__, __LINE__); \
while(1); \
} while (0)
#define FORCE(...) local_printf(__VA_ARGS__)
void local_printf(const char *fmt, ...);
#endif /* LOG_H__ */

29
IPL/SDK/v4h/src/Dummy_FW/include/mem_io.h Normal file
View File

@@ -0,0 +1,29 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Memory access driver header
******************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
/* Prototype */
void mem_write8(uintptr_t addr, uint8_t data);
uint8_t mem_read8(uintptr_t addr);
void mem_write16(uintptr_t addr, uint16_t data);
uint16_t mem_read16(uintptr_t addr);
void mem_write32(uintptr_t addr, uint32_t data);
uint32_t mem_read32(uintptr_t addr);
void mem_write64(uintptr_t addr, uint64_t data);
uint64_t mem_read64(uintptr_t addr);
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set);
#if defined(__RH850G3K__)
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif
#endif /* MEM_IO_H_ */

18
IPL/SDK/v4h/src/Dummy_FW/include/micro_wait.h Normal file
View File

@@ -0,0 +1,18 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Time wait driver header
******************************************************************************/
#ifndef MICRO_WAIT_H_
#define MICRO_WAIT_H_
#include <stdint.h>
/* Define */
/* Prototype */
void micro_wait(uint32_t count_us);
#endif /* MICRO_WAIT_H_ */

28
IPL/SDK/v4h/src/Dummy_FW/include/rcar_def.h Normal file
View File

@@ -0,0 +1,28 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : R-Car common header
******************************************************************************/
#ifndef RCAR_DEF_H_
#define RCAR_DEF_H_
/* Product Register */
#define PRR (0xFFF00044U) /* PRR register */
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */
#define PRR_MAJOR_OFFSET (1U)
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
#define PRR_PRODUCT_10 (0x00U)
#endif /* RCAR_DEF_H_ */

20
IPL/SDK/v4h/src/Dummy_FW/include/remap.h Normal file
View File

@@ -0,0 +1,20 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap driver header
******************************************************************************/
#ifndef REMAP_H_
#define REMAP_H_
#define REMAP_SIZE_MIN (2*1024*1024)
#define REMAP_ALIGN_MASK (~((1 << 21) - 1))
void remap_write_SICREMAP2M(uint32_t num, uint32_t value);
uint32_t remap_get_phys_addr(uint32_t remap_addr);
uint32_t remap_get_remap_addr(uint32_t phys_addr);
uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr);
uint32_t remap_unregister(uint32_t remap_addr);
#endif /* REMAP_H_ */

195
IPL/SDK/v4h/src/Dummy_FW/include/remap_register.h Normal file
View File

@@ -0,0 +1,195 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap register header
******************************************************************************/
#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_
#define REMAP_BASE (0xFF1FC400U)
#define REMAP_2M_BITS (21U)
#define REMAP_2M_MASK ((1 << REMAP_2M_BITS) - 1U)
#define REMAP_REG_MAX (16U)
#define SICREMAP2M(a) (REMAP_BASE + ((a) * (0x4U)))
#define ICUMX_PROT0PCMD (0xFFFEE090U)
#define ICUMX_PROT0PS (0xFFFEE094U)
#define PROTCMD_START (0x000000A5U)
#define PROTS0ERR (0x00000001U)
/* REMAP setting */
/* Remap ID(0 -- 15) */
#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */
#define ICU_REMAP_NUM_CC (14U) /* CC63S */
#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */
#define ICU_REMAP_NUM_RPC (11U) /* RPC */
#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */
#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */
#define ICU_REMAP_NUM_MMC (8U) /* MMC */
#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */
#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */
#define ICU_REMAP_NUM_PRR (5U) /* PRR */
#define ICU_REMAP_NUM_RTACT (4U) /* RT-ACT */
/* SICREMAP2M15 */
#define ICU_REMAP_RTRAM (0xEB200000U) /* RTRAM */
/* SICREMAP2M14 */
#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */
/* SICREMAP2M13 */
#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
/* SICREMAP2M12 */
#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */
/* SICREMAP2M11 */
#define ICU_REMAP_RPC (0xEE200000U) /* RPC */
/* SICREMAP2M10 */
#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF */
/* SICREMAP2M9 */
#define ICU_REMAP_MMC (0xEE000000U) /* MMC */
/* SICREMAP2M8 */
#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */
/* SICREMAP2M7 */
#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */
/* SICREMAP2M6 */
#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */
/* SICREMAP2M5 */
#define ICU_REMAP_PRR (0xFFE00000U) /* PRR */
/* SICREMAP2M4 */
#define ICU_REMAP_RTACT (0xFFC00000U) /* RT-ACT */
#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */
#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */
#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */
#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */
#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */
#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */
#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */
#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */
#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */
#define ICU_REMAP5_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection*/
#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */
/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define ICU_REMAP_OFFSET_RTRAM (0x000000U)
/* REMAP14(0xE6600000U) */
#define ICU_REMAP_OFFSET_CC63S (0x000000U)
#define ICU_REMAP_OFFSET_AXI (0x184000U) /* (0xE6784000U) */
#define ICU_REMAP_OFFSET_DBSC (0x190000U) /* (0xE6790000U) */
#define ICU_REMAP_OFFSET_MSTAT (0x1e0000U) /* (0xE67e0000U) */
#define ICU_REMAP_OFFSET_QOS (0x1F0000U) /* (0xE67F0000U) */
/* REMAP13(0xE6000000U) */
/* GPIO */
#define ICU_REMAP_OFFSET_GPIO0 (0x050000U)
#define ICU_REMAP_OFFSET_GPIO1 (0x051000U)
#define ICU_REMAP_OFFSET_GPIO2 (0x052000U)
#define ICU_REMAP_OFFSET_GPIO3 (0x053000U)
#define ICU_REMAP_OFFSET_GPIO4 (0x054000U)
#define ICU_REMAP_OFFSET_GPIO5 (0x055000U)
/* PFC */
#define ICU_REMAP_OFFSET_PFC (0x060000U)
/* LIFEC */
#define ICU_REMAP_OFFSET_LIFEC (0x110000U)
/* CPGA */
#define ICU_REMAP_OFFSET_CPGA (0x150000U)
/* RESET */
#define ICU_REMAP_OFFSET_RESET (0x160000U)
/* SYSC */
#define ICU_REMAP_OFFSET_SYSC (0x180000U)
/* THS1 */
#define ICU_REMAP_OFFSET_THS1 (0x198000U) /* (0xE6198000U) */
/* REMAP12(0xE6200000U) */
/* MFIS */
#define ICU_REMAP_OFFSET_MFIS (0x060000U)
/* REMAP11(0xEE200000U) */
/*RPC*/
#define ICU_REMAP_OFFSET_RPC (0x000000U)
/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define ICU_REMAP_OFFSET_RTDMA (0x010000U)
/* REMAP9(0xE6C00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF_0 (0x060000U)
#define ICU_REMAP_OFFSET_SCIF_3 (0x050000U)
/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define ICU_REMAP_OFFSET_SDHI (0x140000U)
/* REMAP7(0xE6400000U) */
/* HSCIF */
#define ICU_REMAP_OFFSET_HSCIF0 (0x140000U)
/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define ICU_REMAP_OFFSET_SYSDMAC (0x100000U)
/* REMAP5(0xFFE00000U) */
/* PRR */
#define ICU_REMAP_OFFSET_PRR (0x100044U)
/* REMAP4(0xFFE00000U) */
/* RT-ACT */
#define ICU_REMAP_OFFSET_RTACT (0x050800U)
/* Calculate the base address of each register after remapping */
#define ICU_REMAP0 (0xFC000000U)
#define ICU_REMAP_CALC( val ) (ICU_REMAP0 + (val * 0x200000U))
/* REMAP15(0xEB200000U) */
#define BASE_RTRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTRAM)
/* REMAP14(0xE6600000U) */
#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI)
#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT)
#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
/* REMAP13(0xE6000000U) */
#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0)
#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC)
#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1)
/* REMAP12(0xE6200000U) */
#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS)
/* REMAP11(0xEE200000U) */
#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA)
/* REMAP9(0xE6C00000U or 0xE6E00000U) */
#define BASE_SCIF_ADDR_0 (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF_0)
#define BASE_SCIF_ADDR_3 (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF_3)
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP5(0xFFE00000U) */
#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR)
/* REMAP4(0xFFE00000U) */
#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTACT) + ICU_REMAP_OFFSET_RTACT)
/* MFIS */
#define MFIS_MFISSOFTMDR (BASE_MFIS_ADDR + 0x0600U) /* SOFTMD register */
#define MFIS_MFISBTSTSR (BASE_MFIS_ADDR + 0x0604U) /* (0xE6260604U) */
#define MFIS_MFISWACNTR (BASE_MFIS_ADDR + 0x0904U) /* (0xE6260904U) */ /* Write Access Control Register */
#endif /* REMAP_REGISTER_H_ */

25
IPL/SDK/v4h/src/Dummy_FW/include/rst_register.h Normal file
View File

@@ -0,0 +1,25 @@
/*******************************************************************************
* Copyright (c) 2020 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : RST register header
******************************************************************************/
#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_
#include <remap_register.h>
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */
#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */
#define RST_MODEMR0_MD31 (1U << 31U)
#define RST_MODEMR1_MD32 (1U << 0U)
#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU)
#endif /* RST_REGISTER_H_ */

25
IPL/SDK/v4h/src/Dummy_FW/include/scif.h Normal file
View File

@@ -0,0 +1,25 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF driver header
******************************************************************************/
#ifndef SCIF_H_
#define SCIF_H_
/* Define */
#define PFC_GPSR_SCIF_MASK (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_GPSR_SCIF_VAL (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_IPSR_SCIF_MASK (0x0FF00000UL) /* SCIF0 RX/TX */
#define PFC_IPSR_SCIF_VAL (0x04400000UL) /* SCIF0 RX/TX */
#define BIT7 (uint32_t)(1U << 7U) /* Module Stop 2 bit7(SCIF0) */
#define CR_CODE (0x0DU)
#define LF_CODE (0x0AU)
/* Prototype */
void scif_init(void);
void console_puts(char* str,char rtn);
void console_putc(uint8_t outchar);
#endif /* SCIF_H_ */

77
IPL/SDK/v4h/src/Dummy_FW/include/scif_register.h Normal file
View File

@@ -0,0 +1,77 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF register header
******************************************************************************/
#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_
#include <remap_register.h>
/* SCIF0 base address */
/* 0xE6E60000 */
#define SCIF_BASE_0 (BASE_SCIF_ADDR_0)
#define SCIF_SCSMR_0 (SCIF_BASE_0 + 0x00U) /* 16 Serial mode register */
#define SCIF_SCBRR_0 (SCIF_BASE_0 + 0x04U) /* 8 Bit rate register */
#define SCIF_SCSCR_0 (SCIF_BASE_0 + 0x08U) /* 16 Serial control register */
#define SCIF_SCFTDR_0 (SCIF_BASE_0 + 0x0CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR_0 (SCIF_BASE_0 + 0x10U) /* 16 Serial status register */
#define SCIF_SCFRDR_0 (SCIF_BASE_0 + 0x14U) /* 8 Receive FIFO data register */
#define SCIF_SCFCR_0 (SCIF_BASE_0 + 0x18U) /* 16 FIFO control register */
#define SCIF_SCFDR_0 (SCIF_BASE_0 + 0x1CU) /* 16 FIFO data count register */
#define SCIF_SCSPTR_0 (SCIF_BASE_0 + 0x20U) /* 16 Serial port register */
#define SCIF_SCLSR_0 (SCIF_BASE_0 + 0x24U) /* 16 Line status register */
#define SCIF_DL_0 (SCIF_BASE_0 + 0x30U) /* 16 Frequency division register */
#define SCIF_CKS_0 (SCIF_BASE_0 + 0x34U) /* 16 Clock Select register */
#define SCIF_SCFER_0 (SCIF_BASE_0 + 0x44U) /* 16 FIFO error count register */
#define SCIF_SCSMRIR_0 (SCIF_BASE_0 + 0x40U) /* 16 Serial mode register */
/* SCIF3 base address */
/* 0xE6C50000 */
#define SCIF_BASE_3 (BASE_SCIF_ADDR_3)
#define SCIF_SCSMR_3 (SCIF_BASE_3 + 0x00U) /* 16 Serial mode register */
#define SCIF_SCBRR_3 (SCIF_BASE_3 + 0x04U) /* 8 Bit rate register */
#define SCIF_SCSCR_3 (SCIF_BASE_3 + 0x08U) /* 16 Serial control register */
#define SCIF_SCFTDR_3 (SCIF_BASE_3 + 0x0CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR_3 (SCIF_BASE_3 + 0x10U) /* 16 Serial status register */
#define SCIF_SCFRDR_3 (SCIF_BASE_3 + 0x14U) /* 8 Receive FIFO data register */
#define SCIF_SCFCR_3 (SCIF_BASE_3 + 0x18U) /* 16 FIFO control register */
#define SCIF_SCFDR_3 (SCIF_BASE_3 + 0x1CU) /* 16 FIFO data count register */
#define SCIF_SCSPTR_3 (SCIF_BASE_3 + 0x20U) /* 16 Serial port register */
#define SCIF_SCLSR_3 (SCIF_BASE_3 + 0x24U) /* 16 Line status register */
#define SCIF_DL_3 (SCIF_BASE_3 + 0x30U) /* 16 Frequency division register */
#define SCIF_CKS_3 (SCIF_BASE_3 + 0x34U) /* 16 Clock Select register */
#define SCIF_SCFER_3 (SCIF_BASE_3 + 0x44U) /* 16 FIFO error count register */
#define SCIF_SCSMRIR_3 (SCIF_BASE_3 + 0x40U) /* 16 Serial mode register */
/*HSCIF0 base address*/
/* 0xE6540000 */
#define HSCIF_BASE (BASE_HSCIF_ADDR)
#define HSCIF_HSSMR (HSCIF_BASE + 0x00U) /* 16 Serial mode register */
#define HSCIF_HSBRR (HSCIF_BASE + 0x04U) /* 8 Bit rate register */
#define HSCIF_HSSCR (HSCIF_BASE + 0x08U) /* 16 Serial control register */
#define HSCIF_HSFTDR (HSCIF_BASE + 0x0CU) /* 8 Transmit FIFO data register */
#define HSCIF_HSFSR (HSCIF_BASE + 0x10U) /* 16 Serial status register */
#define HSCIF_HSFRDR (HSCIF_BASE + 0x14U) /* 8 Receive FIFO data register */
#define HSCIF_HSFCR (HSCIF_BASE + 0x18U) /* 16 FIFO control register */
#define HSCIF_HSFDR (HSCIF_BASE + 0x1CU) /* 16 FIFO data count register */
#define HSCIF_HSSPTR (HSCIF_BASE + 0x20U) /* 16 Serial port register */
#define HSCIF_HSLSR (HSCIF_BASE + 0x24U) /* 16 Line status register */
#define HSCIF_HSSRR (HSCIF_BASE + 0x40U) /* 16 Sampling rate register */
#define HSCIF_HSRER (HSCIF_BASE + 0x44U) /* 16 Serial error register */
#define HSCIF_HSRTGR (HSCIF_BASE + 0x50U) /* 16 RTS output active trigger register */
#define HSCIF_HSRTRGR (HSCIF_BASE + 0x54U) /* 16 Receive FIFO data count trigger register */
#define HSCIF_HSTTRGR (HSCIF_BASE + 0x58U) /* 16 Transmit FIFO data count trigger register */
#define HSCIF_DL (HSCIF_BASE + 0x30U) /* 16 Frequency division register */
#define HSCIF_CKS (HSCIF_BASE + 0x34U) /* 16 Clock Select register */
#endif /* SCIF_REGISTER_H_ */

33
IPL/SDK/v4h/src/Dummy_FW/include/wdt.h Normal file
View File

@@ -0,0 +1,33 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : window watchdog timer function header
******************************************************************************/
#ifndef WDT_H__
#define WDT_H__
void wdt_restart(void);
#endif /* WDT_H__ */

138
IPL/SDK/v4h/src/Dummy_RTOS/Makefile Normal file
View File

@@ -0,0 +1,138 @@
###################################################
# makefile
###################################################
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude
# Process CR52_CORE flag
# 0:core0 1:core1 2:core2
ifndef CR52_CORE
CR52_CORE := 0
$(eval $(call add_define,CR52_CORE))
else
ifeq (${CR52_CORE},0)
$(eval $(call add_define,CR52_CORE))
else ifeq (${CR52_CORE},1)
$(eval $(call add_define,CR52_CORE))
else ifeq (${CR52_CORE},2)
$(eval $(call add_define,CR52_CORE))
else
$(error "Error:CR52_CORE=${CR52_CORE} is not supported.")
endif
endif
#output file name
ifeq (${CR52_CORE},0)
FILE_NAME = dummy_rtos
else ifeq (${CR52_CORE},1)
FILE_NAME = dummy_rtos1
else ifeq (${CR52_CORE},2)
FILE_NAME = dummy_rtos2
endif
OUTPUT_FILE = $(FILE_NAME).elf
OUTPUT_DIR = output
OBJECT_DIR = obj
#object file name
OBJ_FILE = common/scif.o \
common/div.o \
common/generic_timer.o \
rtos/rtos.o \
rtos/rtos_main.o
#linker script name
ifeq (${CR52_CORE},0)
MEMORY_DEF = rtos/rtos.ld.S
else ifeq (${CR52_CORE},1)
MEMORY_DEF = rtos/rtos_core1.ld.S
else ifeq (${CR52_CORE},2)
MEMORY_DEF = rtos/rtos_core2.ld.S
endif
###################################################
# Process LOG_LEVEL flag
ifndef LOG_LEVEL
LOG_LEVEL := 20
endif
$(eval $(call add_define,LOG_LEVEL))
###################################################
CC = $(CROSS_COMPILE)gcc
CPP = ${CROSS_COMPILE}cpp
AS = ${CROSS_COMPILE}gcc
AR = ${CROSS_COMPILE}ar
LD = $(CROSS_COMPILE)ld
OC = ${CROSS_COMPILE}objcopy
OD = ${CROSS_COMPILE}objdump
ASFLAGS = -marm -march=armv8-r \
-nostdinc -ffreestanding -Wa,--fatal-warnings \
-Werror -Wmissing-include-dirs \
-c -D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS = -marm -march=armv8-r \
-nostdinc -ffreestanding -Wall \
-Werror -Wmissing-include-dirs \
-std=c99 -c -Os \
-ffunction-sections -fdata-sections \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -g
ASFLAGS += -g -Wa,--gdwarf-2
LDFLAGS = --fatal-warnings -O1 --gc-sections
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OUTPUT_FILE)
###################################################
# Make Directory
###################################################
$(OBJECT_DIR):
mkdir -p $(OBJECT_DIR)
$(OUTPUT_DIR):
mkdir -p $(OUTPUT_DIR)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
$(LD) $(OBJ_FILE) \
-T $(MEMORY_DEF) \
-o $(OUTPUT_FILE) \
$(LDFLAGS) \
-Map $(FILE_NAME).map
$(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec
$(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin
$(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump
###################################################
# Compile
###################################################
%.o:../%.c
$(CC) $(CFLAGS) -o $@ $<
%.o:../%.s
$(AS) $(ASFLAGS) -o $@ $<
.PHONY: clean
clean:
$(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(FILE_NAME)*

66
IPL/SDK/v4h/src/Dummy_RTOS/common/div.s Normal file
View File

@@ -0,0 +1,66 @@
/*
* Copyright (c) 2015-2016, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
.global __aeabi_uidivmod
/*****************************************************************************
* input:
* r0: divided
* r1: divisor
*
* output
* r0: quot
* r1: rem
*****************************************************************************/
__aeabi_uidivmod:
push {r4, r5}
mov r4, #0
mov r5, #1
clz r2, r1
mov r3, r1, LSL r2
1:
cmp r3, r0
subls r0, r0, r3
addls r4, r5, LSL r2
lsr r3, r3, #1
subs r2, r2, #1
bpl 1b
mov r1, r0
mov r0, r4
pop {r4, r5}
bx lr
.end

108
IPL/SDK/v4h/src/Dummy_RTOS/common/generic_timer.c Normal file
View File

@@ -0,0 +1,108 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : generic timer
******************************************************************************/
/******************************************************************************
* @file generic_timer.c
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 14.09.2023 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <timer.h>
#include "scif.h"
#define RCAR_CNTC_EXTAL (16666600U) /* V4H/V4M : 16.666600MHz */
#define RCAR_CONV_MICROSEC (1000000U)
static inline uint32_t get_cntfrq(void)
{
uint32_t freq;
__asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
return(freq);
}
static inline void set_cntfrq(uint32_t reg_cntfid)
{
__asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid));
}
static inline uint64_t get_cntpct(void)
{
uint64_t base_count;
__asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count));
return(base_count);
}
void generic_timer_init(void)
{
/* Update memory mapped and register based freqency */
/* AArch32:cntfrq */
set_cntfrq(RCAR_CNTC_EXTAL);
}
/* End of function generic_timer_init(void) */
void micro_wait(uint64_t micro_sec)
{
uint64_t base_count = 0U;
uint64_t get_count = 0U;
uint64_t wait_time = 0U;
uint32_t freq = 0U;
/* cntfrq */
freq = get_cntfrq();
/* cntpct */
base_count = get_cntpct();
micro_sec *= freq;
while (micro_sec > wait_time)
{
/* cntpct */
get_count = get_cntpct();
/* INT30-C Pre confirmation */
if (get_count < base_count)
{
PutStr("micro_wait(Timer value error!!).", 1U);
while(1U); /* panic */
}
else
{
wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC);
}
}
}
/* End of function micro_wait(uint64_t micro_sec) */

139
IPL/SDK/v4h/src/Dummy_RTOS/common/scif.c Normal file
View File

@@ -0,0 +1,139 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <scif.h>
#include "reg_rcar_gen3.h"
#define RST_MODEMR0 0xE6160000 // R 32 Mode Monitor Register
#define RST_MODEMR1 0xE6160004 // R 32 Mode Monitor Register2
#define MODEMR0_MD31_V3U (0x80000000U)
#define MODEMR1_MD32_V3U (0x00000001U)
#define MODEMR_SCIF_115200_V3U (0x00000000U)
#define MODEMR_SCIF_921600_V3U (0x80000000U)
#define MODEMR_SCIF_1843200_V3U (0x00000001U)
#define MODEMR_SCIF_3000000_V3U (0x80000001U)
static void (*putc)(char);
static void scif0_PutChar(char outchar);
static void scif3_PutChar(char outchar);
static void hscif_PutChar(char outchar);
/************************************************************************/
/*NAME : PutStr */
/************************************************************************/
void PutStr(const char *str,char rtn)
{
while(*str){
PutChar(*str);
str++;
}
if(rtn == 1){
PutChar(CR_CODE);
PutChar(LF_CODE);
}
}
void scif_init(void)
{
uint32_t product;
uint32_t modemr0;
uint32_t modemr1;
product = *((volatile uint32_t*)RCAR_PRR) & RCAR_PRODUCT_MASK;
switch (product) {
case RCAR_PRODUCT_S4:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_V3U: /* 0x00000000 */
putc = scif3_PutChar;
break;
case MODEMR_SCIF_921600_V3U: /* 0x80000000 */
case MODEMR_SCIF_1843200_V3U: /* 0x00000001 */
case MODEMR_SCIF_3000000_V3U: /* 0x80000001 */
putc = hscif_PutChar;
break;
default:
break;
}
break;
case RCAR_PRODUCT_V4H:
case RCAR_PRODUCT_V4M:
modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */
modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */
switch (modemr0 | modemr1) {
case MODEMR_SCIF_115200_V3U: /* 0x00000000 */
putc = scif0_PutChar;
break;
case MODEMR_SCIF_921600_V3U: /* 0x80000000 */
case MODEMR_SCIF_1843200_V3U: /* 0x00000001 */
case MODEMR_SCIF_3000000_V3U: /* 0x80000001 */
putc = hscif_PutChar;
break;
default:
break;
}
break;
default:
break;
}
}
void PutChar(char outChar)
{
putc(outChar);
}
static void scif0_PutChar(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF_SCFSR_0) ));
*((volatile uint8_t*)SCIF_SCFTDR_0) = outChar;
*((volatile uint16_t*)SCIF_SCFSR_0) &= ~0x60; /* TEND,TDFE clear */
}
static void scif3_PutChar(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF_SCFSR_3) ));
*((volatile uint8_t*)SCIF_SCFTDR_3) = outChar;
*((volatile uint16_t*)SCIF_SCFSR_3) &= ~0x60; /* TEND,TDFE clear */
}
static void hscif_PutChar(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)HSCIF_HSFSR) ));
*((volatile uint8_t*)HSCIF_HSFTDR) = outChar;
*((volatile uint16_t*)HSCIF_HSFSR) &= ~0x60; /* TEND,TDFE clear */
}

89
IPL/SDK/v4h/src/Dummy_RTOS/include/debug.h Normal file
View File

@@ -0,0 +1,89 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DEBUG_H__
#define __DEBUG_H__
#include <stdio.h>
/* The log output macros print output to the console. These macros produce
* compiled log output only if the LOG_LEVEL defined in the makefile (or the
* make command line) is greater or equal than the level required for that
* type of log output.
* The format expected is the same as for printf(). For example:
* INFO("Info %s.\n", "message") -> INFO: Info message.
* WARN("Warning %s.\n", "message") -> WARNING: Warning message.
*/
#define LOG_LEVEL_NONE 0
#define LOG_LEVEL_ERROR 10
#define LOG_LEVEL_NOTICE 20
#define LOG_LEVEL_WARNING 30
#define LOG_LEVEL_INFO 40
#define LOG_LEVEL_VERBOSE 50
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_ERROR
# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_WARNING
# define WARN(...) tf_printf("WARNING: " __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_INFO
# define INFO(...) tf_printf("INFO: " __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
void __dead2 do_panic(void);
#define panic() do_panic()
void tf_printf(const char *fmt, ...) __printflike(1, 2);
#endif /* __DEBUG_H__ */

164
IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_stdint.h Normal file
View File

@@ -0,0 +1,164 @@
/*-
* Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## L)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## UL)
#define INTMAX_C(c) INT64_C(c)
#define UINTMAX_C(c) UINT64_C(c)
#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
/*
* ISO/IEC 9899:1999
* 7.18.2.1 Limits of exact-width integer types
*/
/* Minimum values of exact-width signed integer types. */
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffUL
/*
* ISO/IEC 9899:1999
* 7.18.2.2 Limits of minimum-width integer types
*/
/* Minimum values of minimum-width signed integer types. */
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
/* Maximum values of minimum-width signed integer types. */
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
/* Maximum values of minimum-width unsigned integer types. */
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.3 Limits of fastest minimum-width integer types
*/
/* Minimum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MIN INT32_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
/* Maximum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MAX INT32_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
/* Maximum values of fastest minimum-width unsigned integer types. */
#define UINT_FAST8_MAX UINT32_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.4 Limits of integer types capable of holding object pointers
*/
#define INTPTR_MIN INT64_MIN
#define INTPTR_MAX INT64_MAX
#define UINTPTR_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.5 Limits of greatest-width integer types
*/
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.3 Limits of other integer types
*/
/* Limits of ptrdiff_t. */
#define PTRDIFF_MIN INT64_MIN
#define PTRDIFF_MAX INT64_MAX
/* Limits of sig_atomic_t. */
#define SIG_ATOMIC_MIN INT32_MIN
#define SIG_ATOMIC_MAX INT32_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT64_MAX
#ifndef WCHAR_MIN /* Also possibly defined in <wchar.h> */
/* Limits of wchar_t. */
#define WCHAR_MIN INT32_MIN
#define WCHAR_MAX INT32_MAX
#endif
/* Limits of wint_t. */
#define WINT_MIN INT32_MIN
#define WINT_MAX INT32_MAX
#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
#endif /* !_MACHINE__STDINT_H_ */

110
IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_types.h Normal file
View File

@@ -0,0 +1,110 @@
/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
* $FreeBSD$
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#ifndef _SYS_CDEFS_H_
#error this file needs sys/cdefs.h as a prerequisite
#endif
/*
* Basic types upon which most other types are built.
*/
typedef __signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
typedef long long __int64_t;
typedef unsigned long long __uint64_t;
/*
* Standard type definitions.
*/
typedef __int32_t __clock_t; /* clock()... */
typedef __int32_t __critical_t;
typedef double __double_t;
typedef float __float_t;
typedef __int32_t __intfptr_t;
typedef __int32_t __intmax_t;
typedef __int32_t __intptr_t;
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int32_t __int_fast64_t;
typedef __int8_t __int_least8_t;
typedef __int16_t __int_least16_t;
typedef __int32_t __int_least32_t;
typedef __int64_t __int_least64_t;
typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */
typedef __int32_t __register_t;
typedef __int32_t __segsz_t; /* segment size (in pages) */
typedef __uint32_t __size_t; /* sizeof() */
typedef __int32_t __ssize_t; /* byte count or error */
typedef __int32_t __time_t; /* time()... */
typedef __uint32_t __uintfptr_t;
typedef __uint64_t __uintmax_t;
typedef __uint32_t __uintptr_t;
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint8_t __uint_least8_t;
typedef __uint16_t __uint_least16_t;
typedef __uint32_t __uint_least32_t;
typedef __uint64_t __uint_least64_t;
typedef __uint32_t __u_register_t;
typedef __uint32_t __vm_offset_t;
typedef __int32_t __vm_ooffset_t;
typedef __uint32_t __vm_paddr_t;
typedef __uint32_t __vm_pindex_t;
typedef __uint32_t __vm_size_t;
/*
* Unusual type definitions.
*/
#ifdef __GNUCLIKE_BUILTIN_VARARGS
typedef __builtin_va_list __va_list; /* internally known to gcc */
#else
typedef char * __va_list;
#endif /* __GNUCLIKE_BUILTIN_VARARGS */
#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \
&& !defined(__NO_GNUC_VA_LIST)
#define __GNUC_VA_LIST
typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/
#endif
#endif /* !_MACHINE__TYPES_H_ */

136
IPL/SDK/v4h/src/Dummy_RTOS/include/reg_rcar_gen3.h Normal file
View File

@@ -0,0 +1,136 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __H_REG_RCAR_GEN3_
#define __H_REG_RCAR_GEN3_
/*********************** RCarGen3_MFI *************************/
#define MFISSOFTMDR 0xE6260600 //SOFTMD register
#define MFISSHESTSR 0xE6260604 //SHE status register
/*********************** RCarGen3_LIFEC *************************/
#define LIFEC_CC_LCS 0xE6110028 // cc_lcs Life cycle state read
/*********************** RCarGen3_RST *************************/
#define RST_MODEMR 0xE6160060 // Mode Monitor Register
/*********************** RCarGen3_DMA *************************/
#define DMA_DMAOR 0xE6700060 //DMA operation register (for west channel)
#define DMA_CHCLR 0xE6700080 //DMA channel clear register (for west channel)
#define DMA_SAR0 0xE6708000 //DMA source address register
#define DMA_DAR0 0xE6708004 //DMA destination address register
#define DMA_TCR0 0xE6708008 //DMA transfer count register
#define DMA_CHCR0 0xE670800C //DMA channel control register
#define DMA_DMARS0 0xE6708040 //DMA extended resource register
/*********************** RCarGen3_RPC/QSPI *************************/
//RPC/QSPI
#define RPC_BASE 0xEE200000
#define RPC_CMNCR (RPC_BASE + 0x0000) //
//#define RPC_DRCR (RPC_BASE + 0x000C) //
//#define RPC_DRCMR (RPC_BASE + 0x0010) //
//#define RPC_DRENR (RPC_BASE + 0x001C) //
#define RPC_SMCR (RPC_BASE + 0x0020) //
#define RPC_SMCMR (RPC_BASE + 0x0024) //
#define RPC_SMENR (RPC_BASE + 0x0030) //
#define RPC_CMNSR (RPC_BASE + 0x0048) //
//#define RPC_DRDMCR (RPC_BASE + 0x0058) //
//#define RPC_DRDRENR (RPC_BASE + 0x005C) //
//#define RPC_PHY_OFFSET1 (RPC_BASE + 0x0080) //
#define RPC_PHY_INT (RPC_BASE + 0x0088) //
/*********************** RCarH3_PFC *************************/
// 5 . PFC
#define PFC_BASE 0xE6060000
#define RCarH3_PFC_PMMR (PFC_BASE + 0x0000) // LSI Multiplexed Pin Setting Mask Register
#define RCarH3_PFC_GPSR5 (PFC_BASE + 0x0114) // GPIO/peripheral function select register 5
#define RCarH3_PFC_IPSR12 (PFC_BASE + 0x0230) // Peripheral function select register 12
#define RCarH3_PFC_MOD_SEL1 (PFC_BASE + 0x0504) // Module select register 1
/*********************** RCarH3_SCIF ****************************************************/
// 51 . Serial Communication Interface with FIFO (SCIF)
/* H3 SCIF2 */
#define H3_SCIF2_BASE 0xE6E88000
#define RCarH3_SCIF2_SCSMR (H3_SCIF2_BASE + 0x00) // 16 Serial mode register
#define RCarH3_SCIF2_SCBRR (H3_SCIF2_BASE + 0x04) // 8 Bit rate register
#define RCarH3_SCIF2_SCSCR (H3_SCIF2_BASE + 0x08) // 16 Serial control register
#define RCarH3_SCIF2_SCFTDR (H3_SCIF2_BASE + 0x0C) // 8 Transmit FIFO data register
#define RCarH3_SCIF2_SCFSR (H3_SCIF2_BASE + 0x10) // 16 Serial status register
#define RCarH3_SCIF2_SCFRDR (H3_SCIF2_BASE + 0x14) // 8 Receive FIFO data register
#define RCarH3_SCIF2_SCFCR (H3_SCIF2_BASE + 0x18) // 16 FIFO control register
#define RCarH3_SCIF2_SCFDR (H3_SCIF2_BASE + 0x1C) // 16 FIFO data count register
#define RCarH3_SCIF2_SCSPTR (H3_SCIF2_BASE + 0x20) // 16 Serial port register
#define RCarH3_SCIF2_SCLSR (H3_SCIF2_BASE + 0x24) // 16 Line status register
#define RCarH3_SCIF2_DL (H3_SCIF2_BASE + 0x30) // 16 Frequency division register
#define RCarH3_SCIF2_CKS (H3_SCIF2_BASE + 0x34) // 16 Clock Select register
#define RCarH3_SCIF2_SCFER (H3_SCIF2_BASE + 0x44) // 16 FIFO error count register
#define RCarH3_SCIF2_SCSMRIR (H3_SCIF2_BASE + 0x40) // 16 Serial mode register
/*********************** RCarH3_CPG_Module Standby, Software Reset *************************/
// 7A . Module Standby, Software Reset
#define H3_CPG_MSTPRST_BASE 0xE6150000
#define RCarH3_CPG_MSTPSR3 (H3_CPG_MSTPRST_BASE+0x0048) // Module stop status register 3
#define RCarH3_CPG_SMSTPCR3 (H3_CPG_MSTPRST_BASE+0x013C) // System module stop control register 3
//#define RCarH3_CPG_SRCR3 (H3_CPG_MSTPRST_BASE+0x00B8) // Software reset register 3
#define RCarH3_CPG_CPGWPCR (H3_CPG_MSTPRST_BASE+0x0904) // CPG Write Protect Control Register
#define RCarH3_CPG_CPGWPR (H3_CPG_MSTPRST_BASE+0x0900) // CPG Write Protect Register
/*********************** RCarGen4_PRR *************************/
#define RCAR_PRR (0xFFF00044U) /* Product register */
#define RCAR_PRODUCT_MASK (0x00007F00U)
#define RCAR_CUT_MASK (0x000000FFU)
#define RCAR_PRODUCT_H3 (0x00004F00U)
#define RCAR_PRODUCT_M3 (0x00005200U)
#define RCAR_PRODUCT_S4 (0x00005A00U)
#define RCAR_PRODUCT_V4H (0x00005C00U)
#define RCAR_PRODUCT_V4M (0x00005D00U)
#define RCAR_CUT_ES10 (0x00000000U)
#define RCAR_CUT_ES11 (0x00000001U)
#define RCAR_MAJOR_MASK (0x000000F0U)
#define RCAR_MINOR_MASK (0x0000000FU)
#define RCAR_PRODUCT_SHIFT (8U)
#define RCAR_MAJOR_SHIFT (4U)
#define RCAR_MINOR_SHIFT (0U)
#define RCAR_MAJOR_OFFSET (1U)
#endif /* __H_REG_RCAR_GEN3_ */

91
IPL/SDK/v4h/src/Dummy_RTOS/include/scif.h Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SCIF_H__
#define __SCIF_H__
//SCIF0
#define SCIF_BASE_0 (0xE6E60000U)
#define SCIF_SCSMR_0 (SCIF_BASE_0 + 0x0000) // R/W 16 Serial mode register
#define SCIF_SCBRR_0 (SCIF_BASE_0 + 0x0004) // R/W 8 Bit rate register
#define SCIF_SCSCR_0 (SCIF_BASE_0 + 0x0008) // R/W 16 Serial control register
#define SCIF_SCFTDR_0 (SCIF_BASE_0 + 0x000C) // W 8 Transmit FIFO data register
#define SCIF_SCFSR_0 (SCIF_BASE_0 + 0x0010) // R/W 16 Serial status register
#define SCIF_SCFRDR_0 (SCIF_BASE_0 + 0x0014) // R 8 Receive FIFO data register
#define SCIF_SCFCR_0 (SCIF_BASE_0 + 0x0018) // R/W 16 FIFO control register
#define SCIF_SCFDR_0 (SCIF_BASE_0 + 0x001C) // R 16 FIFO data count register
#define SCIF_SCSPTR_0 (SCIF_BASE_0 + 0x0020) // R/W 16 Serial port register
#define SCIF_SCLSR_0 (SCIF_BASE_0 + 0x0024) // R/W 16 Line status register
#define SCIF_DL_0 (SCIF_BASE_0 + 0x0030) // R/W 16 Frequency division register
#define SCIF_CKS_0 (SCIF_BASE_0 + 0x0034) // R/W 16 Clock Select register
//SCIF3
#define SCIF_BASE_3 (0xE6C50000U)
#define SCIF_SCSMR_3 (SCIF_BASE_3 + 0x0000) // R/W 16 Serial mode register
#define SCIF_SCBRR_3 (SCIF_BASE_3 + 0x0004) // R/W 8 Bit rate register
#define SCIF_SCSCR_3 (SCIF_BASE_3 + 0x0008) // R/W 16 Serial control register
#define SCIF_SCFTDR_3 (SCIF_BASE_3 + 0x000C) // W 8 Transmit FIFO data register
#define SCIF_SCFSR_3 (SCIF_BASE_3 + 0x0010) // R/W 16 Serial status register
#define SCIF_SCFRDR_3 (SCIF_BASE_3 + 0x0014) // R 8 Receive FIFO data register
#define SCIF_SCFCR_3 (SCIF_BASE_3 + 0x0018) // R/W 16 FIFO control register
#define SCIF_SCFDR_3 (SCIF_BASE_3 + 0x001C) // R 16 FIFO data count register
#define SCIF_SCSPTR_3 (SCIF_BASE_3 + 0x0020) // R/W 16 Serial port register
#define SCIF_SCLSR_3 (SCIF_BASE_3 + 0x0024) // R/W 16 Line status register
#define SCIF_DL_3 (SCIF_BASE_3 + 0x0030) // R/W 16 Frequency division register
#define SCIF_CKS_3 (SCIF_BASE_3 + 0x0034) // R/W 16 Clock Select register
/* HSCIF0 */
#define HSCIF_BASE (0xE6540000U)
#define HSCIF_HSSMR (HSCIF_BASE + 0x0000U) // R/W 16 Serial mode register
#define HSCIF_HSBRR (HSCIF_BASE + 0x0004U) // R/W 8 Bit rate register
#define HSCIF_HSSCR (HSCIF_BASE + 0x0008U) // R/W 16 Serial control register
#define HSCIF_HSFTDR (HSCIF_BASE + 0x000CU) // W 8 Transmit FIFO data register
#define HSCIF_HSFSR (HSCIF_BASE + 0x0010U) // R/W 16 Serial status register
#define HSCIF_HSFRDR (HSCIF_BASE + 0x0014U) // R 8 Receive FIFO data register
#define HSCIF_HSFCR (HSCIF_BASE + 0x0018U) // R/W 16 FIFO control register
#define HSCIF_HSFDR (HSCIF_BASE + 0x001CU) // R 16 FIFO data count register
#define HSCIF_HSSPTR (HSCIF_BASE + 0x0020U) // R/W 16 Serial port register
#define HSCIF_HSLSR (HSCIF_BASE + 0x0024U) // R/W 16 Line status register
#define HSCIF_HSSRR (HSCIF_BASE + 0x0040U) // R/W 16 Sampling rate register
/* BRG */
#define HSCIF_DL (HSCIF_BASE + 0x0030U) // R/W 16 Frequency division register
#define HSCIF_CKS (HSCIF_BASE + 0x0034U) // R/W 16 Clock select register
#define CR_CODE (0x0DU)
#define LF_CODE (0x0AU)
void scif_init(void);
void PutStr(const char *str,char rtn);
void PutChar(char outChar);
#endif /* __SCIF_H__ */

75
IPL/SDK/v4h/src/Dummy_RTOS/include/stdarg.h Normal file
View File

@@ -0,0 +1,75 @@
/*-
* Copyright (c) 2002 David E. O'Brien. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_STDARG_H_
#define _MACHINE_STDARG_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
#ifndef _VA_LIST_DECLARED
#define _VA_LIST_DECLARED
typedef __va_list va_list;
#endif
#ifdef __GNUCLIKE_BUILTIN_STDARG
#define va_start(ap, last) \
__builtin_va_start((ap), (last))
#define va_arg(ap, type) \
__builtin_va_arg((ap), type)
#define __va_copy(dest, src) \
__builtin_va_copy((dest), (src))
#if __ISO_C_VISIBLE >= 1999
#define va_copy(dest, src) \
__va_copy(dest, src)
#endif
#define va_end(ap) \
__builtin_va_end(ap)
#elif defined(lint)
/* Provide a fake implementation for lint's benefit */
#define __va_size(type) \
(((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long))
#define va_start(ap, last) \
((ap) = (va_list)&(last) + __va_size(last))
#define va_arg(ap, type) \
(*(type *)((ap) += __va_size(type), (ap) - __va_size(type)))
#define va_end(ap)
#else
#error this file needs to be ported to your compiler
#endif
#endif /* !_MACHINE_STDARG_H_ */

64
IPL/SDK/v4h/src/Dummy_RTOS/include/stddef.h Normal file
View File

@@ -0,0 +1,64 @@
/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)stddef.h 8.1 (Berkeley) 6/2/93
*
* $FreeBSD$
*/
#ifndef _STDDEF_H_
#define _STDDEF_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
typedef __ptrdiff_t ptrdiff_t;
#if __BSD_VISIBLE
#ifndef _RUNE_T_DECLARED
typedef __rune_t rune_t;
#define _RUNE_T_DECLARED
#endif
#endif
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef __cplusplus
#ifndef _WCHAR_T_DECLARED
typedef __wchar_t wchar_t;
#define _WCHAR_T_DECLARED
#endif
#endif
#define offsetof(type, member) __offsetof(type, member)
#endif /* _STDDEF_H_ */

74
IPL/SDK/v4h/src/Dummy_RTOS/include/stdint.h Normal file
View File

@@ -0,0 +1,74 @@
/*-
* Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS_STDINT_H_
#define _SYS_STDINT_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
#include <machine/_stdint.h>
#include <sys/_stdint.h>
typedef __int_least8_t int_least8_t;
typedef __int_least16_t int_least16_t;
typedef __int_least32_t int_least32_t;
typedef __int_least64_t int_least64_t;
typedef __uint_least8_t uint_least8_t;
typedef __uint_least16_t uint_least16_t;
typedef __uint_least32_t uint_least32_t;
typedef __uint_least64_t uint_least64_t;
typedef __int_fast8_t int_fast8_t;
typedef __int_fast16_t int_fast16_t;
typedef __int_fast32_t int_fast32_t;
typedef __int_fast64_t int_fast64_t;
typedef __uint_fast8_t uint_fast8_t;
typedef __uint_fast16_t uint_fast16_t;
typedef __uint_fast32_t uint_fast32_t;
typedef __uint_fast64_t uint_fast64_t;
#ifndef _INTMAX_T_DECLARED
typedef __intmax_t intmax_t;
#define _INTMAX_T_DECLARED
#endif
#ifndef _UINTMAX_T_DECLARED
typedef __uintmax_t uintmax_t;
#define _UINTMAX_T_DECLARED
#endif
/* GNU and Darwin define this and people seem to think it's portable */
#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX)
#define __WORDSIZE 64
#else
#define __WORDSIZE 32
#endif
#endif /* !_SYS_STDINT_H_ */

78
IPL/SDK/v4h/src/Dummy_RTOS/include/stdio.h Normal file
View File

@@ -0,0 +1,78 @@
/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Chris Torek.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)stdio.h 8.5 (Berkeley) 4/29/95
* $FreeBSD$
*/
/*
* Portions copyright (c) 2013-2014, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef _STDIO_H_
#define _STDIO_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef _SSIZE_T_DECLARED
#define _SSIZE_T_DECLARED
typedef __ssize_t ssize_t;
#endif
#define EOF (-1)
int printf(const char * __restrict, ...) __printflike(1, 2);
int putchar(int);
int puts(const char *);
int sprintf(char * __restrict, const char * __restrict, ...)
__printflike(2, 3);
int vsprintf(char * __restrict, const char * __restrict,
__va_list) __printflike(2, 0);
int sscanf(const char *__restrict, char const *__restrict, ...);
#if __ISO_C_VISIBLE >= 1999
int snprintf(char * __restrict, size_t, const char * __restrict,
...) __printflike(3, 4);
int vsnprintf(char * __restrict, size_t, const char * __restrict,
__va_list) __printflike(3, 0);
#endif
#endif /* !_STDIO_H_ */

66
IPL/SDK/v4h/src/Dummy_RTOS/include/string.h Normal file
View File

@@ -0,0 +1,66 @@
/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)string.h 8.1 (Berkeley) 6/2/93
* $FreeBSD$
*/
/*
* Portions copyright (c) 2013-2014, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef _STRING_H_
#define _STRING_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
__BEGIN_DECLS
void *memchr(const void *, int, size_t) __pure;
int memcmp(const void *, const void *, size_t) __pure;
void *memcpy(void * __restrict, const void * __restrict, size_t);
void *memmove(void *, const void *, size_t);
void *memset(void *, int, size_t);
char *strchr(const char *, int) __pure;
int strcmp(const char *, const char *) __pure;
size_t strlen(const char *) __pure;
int strncmp(const char *, const char *, size_t) __pure;
int strcasecmp(const char *, const char *);
__END_DECLS
#endif /* _STRING_H_ */

47
IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_null.h Normal file
View File

@@ -0,0 +1,47 @@
/*-
* Copyright (c) 2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef NULL
#if !defined(__cplusplus)
#define NULL ((void *)0)
#else
#if __cplusplus >= 201103L
#define NULL nullptr
#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4
#define NULL __null
#else
#if defined(__LP64__)
#define NULL (0L)
#else
#define NULL 0
#endif /* __LP64__ */
#endif /* __GNUG__ */
#endif /* !__cplusplus */
#endif

82
IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_stdint.h Normal file
View File

@@ -0,0 +1,82 @@
/*-
* Copyright (c) 2011 David E. O'Brien <obrien@FreeBSD.org>
* Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS__STDINT_H_
#define _SYS__STDINT_H_
#ifndef _INT8_T_DECLARED
typedef __int8_t int8_t;
#define _INT8_T_DECLARED
#endif
#ifndef _INT16_T_DECLARED
typedef __int16_t int16_t;
#define _INT16_T_DECLARED
#endif
#ifndef _INT32_T_DECLARED
typedef __int32_t int32_t;
#define _INT32_T_DECLARED
#endif
#ifndef _INT64_T_DECLARED
typedef __int64_t int64_t;
#define _INT64_T_DECLARED
#endif
#ifndef _UINT8_T_DECLARED
typedef __uint8_t uint8_t;
#define _UINT8_T_DECLARED
#endif
#ifndef _UINT16_T_DECLARED
typedef __uint16_t uint16_t;
#define _UINT16_T_DECLARED
#endif
#ifndef _UINT32_T_DECLARED
typedef __uint32_t uint32_t;
#define _UINT32_T_DECLARED
#endif
#ifndef _UINT64_T_DECLARED
typedef __uint64_t uint64_t;
#define _UINT64_T_DECLARED
#endif
#ifndef _INTPTR_T_DECLARED
typedef __intptr_t intptr_t;
#define _INTPTR_T_DECLARED
#endif
#ifndef _UINTPTR_T_DECLARED
typedef __uintptr_t uintptr_t;
#define _UINTPTR_T_DECLARED
#endif
#endif /* !_SYS__STDINT_H_ */

106
IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_types.h Normal file
View File

@@ -0,0 +1,106 @@
/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS__TYPES_H_
#define _SYS__TYPES_H_
#include <sys/cdefs.h>
#include <machine/_types.h>
/*
* Standard type definitions.
*/
typedef __uint32_t __blksize_t; /* file block size */
typedef __int64_t __blkcnt_t; /* file block count */
typedef __int32_t __clockid_t; /* clock_gettime()... */
typedef __uint32_t __cap_rights_t; /* capability rights */
typedef __uint32_t __fflags_t; /* file flags */
typedef __uint32_t __fsblkcnt_t;
typedef __uint32_t __fsfilcnt_t;
typedef __uint32_t __gid_t;
typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */
typedef __uint32_t __ino_t; /* inode number */
typedef long __key_t; /* IPC key (for Sys V IPC) */
typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */
typedef __uint16_t __mode_t; /* permissions */
typedef int __accmode_t; /* access permissions */
typedef int __nl_item;
typedef __uint16_t __nlink_t; /* link count */
typedef __int32_t __off_t; /* file offset */
typedef __int32_t __pid_t; /* process [group] */
typedef __int32_t __rlim_t; /* resource limit - intentionally */
/* signed, because of legacy code */
/* that uses -1 for RLIM_INFINITY */
typedef __uint8_t __sa_family_t;
typedef __uint32_t __socklen_t;
typedef long __suseconds_t; /* microseconds (signed) */
typedef struct __timer *__timer_t; /* timer_gettime()... */
typedef struct __mq *__mqd_t; /* mq_open()... */
typedef __uint32_t __uid_t;
typedef unsigned int __useconds_t; /* microseconds (unsigned) */
typedef int __cpuwhich_t; /* which parameter for cpuset. */
typedef int __cpulevel_t; /* level parameter for cpuset. */
typedef int __cpusetid_t; /* cpuset identifier. */
/*
* Unusual type definitions.
*/
/*
* rune_t is declared to be an ``int'' instead of the more natural
* ``unsigned long'' or ``long''. Two things are happening here. It is not
* unsigned so that EOF (-1) can be naturally assigned to it and used. Also,
* it looks like 10646 will be a 31 bit standard. This means that if your
* ints cannot hold 32 bits, you will be in trouble. The reason an int was
* chosen over a long is that the is*() and to*() routines take ints (says
* ANSI C), but they use __ct_rune_t instead of int.
*
* NOTE: rune_t is not covered by ANSI nor other standards, and should not
* be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and
* rune_t must be the same type. Also, wint_t must be no narrower than
* wchar_t, and should be able to hold all members of the largest
* character set plus one extra value (WEOF), and must be at least 16 bits.
*/
typedef int __ct_rune_t; /* arg type for ctype funcs */
typedef __ct_rune_t __rune_t; /* rune_t (see above) */
typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */
typedef __ct_rune_t __wint_t; /* wint_t (see above) */
typedef __uint32_t __dev_t; /* device number */
typedef __uint32_t __fixpt_t; /* fixed point number */
/*
* mbstate_t is an opaque object to keep conversion state during multibyte
* stream conversions.
*/
typedef union {
char __mbstate8[128];
__int64_t _mbstateL; /* for alignment */
} __mbstate_t;
#endif /* !_SYS__TYPES_H_ */

686
IPL/SDK/v4h/src/Dummy_RTOS/include/sys/cdefs.h Normal file
View File

@@ -0,0 +1,686 @@
/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Berkeley Software Design, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)cdefs.h 8.8 (Berkeley) 1/9/95
* $FreeBSD$
*/
#ifndef _SYS_CDEFS_H_
#define _SYS_CDEFS_H_
#if defined(__cplusplus)
#define __BEGIN_DECLS extern "C" {
#define __END_DECLS }
#else
#define __BEGIN_DECLS
#define __END_DECLS
#endif
/*
* This code has been put in place to help reduce the addition of
* compiler specific defines in FreeBSD code. It helps to aid in
* having a compiler-agnostic source tree.
*/
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
#define __GNUCLIKE_ASM 3
#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS
#else
#define __GNUCLIKE_ASM 2
#endif
#define __GNUCLIKE___TYPEOF 1
#define __GNUCLIKE___OFFSETOF 1
#define __GNUCLIKE___SECTION 1
#ifndef __INTEL_COMPILER
# define __GNUCLIKE_CTOR_SECTION_HANDLING 1
#endif
#define __GNUCLIKE_BUILTIN_CONSTANT_P 1
# if defined(__INTEL_COMPILER) && defined(__cplusplus) \
&& __INTEL_COMPILER < 800
# undef __GNUCLIKE_BUILTIN_CONSTANT_P
# endif
#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER)
# define __GNUCLIKE_BUILTIN_VARARGS 1
# define __GNUCLIKE_BUILTIN_STDARG 1
# define __GNUCLIKE_BUILTIN_VAALIST 1
#endif
#if defined(__GNUC__)
# define __GNUC_VA_LIST_COMPATIBILITY 1
#endif
#ifndef __INTEL_COMPILER
# define __GNUCLIKE_BUILTIN_NEXT_ARG 1
# define __GNUCLIKE_MATH_BUILTIN_RELOPS
#endif
#define __GNUCLIKE_BUILTIN_MEMCPY 1
/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
#define __CC_SUPPORTS_INLINE 1
#define __CC_SUPPORTS___INLINE 1
#define __CC_SUPPORTS___INLINE__ 1
#define __CC_SUPPORTS___FUNC__ 1
#define __CC_SUPPORTS_WARNING 1
#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
#endif /* __GNUC__ || __INTEL_COMPILER */
/*
* Macro to test if we're using a specific version of gcc or later.
*/
#if defined(__GNUC__) && !defined(__INTEL_COMPILER)
#define __GNUC_PREREQ__(ma, mi) \
(__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi))
#else
#define __GNUC_PREREQ__(ma, mi) 0
#endif
/*
* The __CONCAT macro is used to concatenate parts of symbol names, e.g.
* with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
* The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
* mode -- there must be no spaces between its arguments, and for nested
* __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also
* concatenate double-quoted strings produced by the __STRING macro, but
* this only works with ANSI C.
*
* __XSTRING is like __STRING, but it expands any macros in its argument
* first. It is only available with ANSI C.
*/
#if defined(__STDC__) || defined(__cplusplus)
#define __P(protos) protos /* full-blown ANSI C */
#define __CONCAT1(x,y) x ## y
#define __CONCAT(x,y) __CONCAT1(x,y)
#define __STRING(x) #x /* stringify without expanding x */
#define __XSTRING(x) __STRING(x) /* expand x, then stringify */
#define __const const /* define reserved names to standard */
#define __signed signed
#define __volatile volatile
#if defined(__cplusplus)
#define __inline inline /* convert to C++ keyword */
#else
#if !(defined(__CC_SUPPORTS___INLINE))
#define __inline /* delete GCC keyword */
#endif /* ! __CC_SUPPORTS___INLINE */
#endif /* !__cplusplus */
#else /* !(__STDC__ || __cplusplus) */
#define __P(protos) () /* traditional C preprocessor */
#define __CONCAT(x,y) x/**/y
#define __STRING(x) "x"
#if !defined(__CC_SUPPORTS___INLINE)
#define __const /* delete pseudo-ANSI C keywords */
#define __inline
#define __signed
#define __volatile
/*
* In non-ANSI C environments, new programs will want ANSI-only C keywords
* deleted from the program and old programs will want them left alone.
* When using a compiler other than gcc, programs using the ANSI C keywords
* const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
* When using "gcc -traditional", we assume that this is the intent; if
* __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
*/
#ifndef NO_ANSI_KEYWORDS
#define const /* delete ANSI C keywords */
#define inline
#define signed
#define volatile
#endif /* !NO_ANSI_KEYWORDS */
#endif /* !__CC_SUPPORTS___INLINE */
#endif /* !(__STDC__ || __cplusplus) */
/*
* Compiler-dependent macros to help declare dead (non-returning) and
* pure (no side effects) functions, and unused variables. They are
* null except for versions of gcc that are known to support the features
* properly (old versions of gcc-2 supported the dead and pure features
* in a different (wrong) way). If we do not provide an implementation
* for a given compiler, let the compile fail if it is told to use
* a feature that we cannot live without.
*/
#ifdef lint
#define __dead2
#define __pure2
#define __unused
#define __packed
#define __aligned(x)
#define __section(x)
#else
#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
#define __dead2
#define __pure2
#define __unused
#endif
#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused
/* XXX Find out what to do for __packed, __aligned and __section */
#endif
#if __GNUC_PREREQ__(2, 7)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused __attribute__((__unused__))
#define __used __attribute__((__used__))
#define __packed __attribute__((__packed__))
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#endif
#if defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused __attribute__((__unused__))
#define __used __attribute__((__used__))
#define __packed __attribute__((__packed__))
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#endif
#endif
#if !__GNUC_PREREQ__(2, 95)
#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b)
#endif
/*
* Keywords added in C11.
*/
#if defined(__cplusplus) && __cplusplus >= 201103L
#define _Alignas(e) alignas(e)
#define _Alignof(e) alignof(e)
#define _Noreturn [[noreturn]]
#define _Static_assert(e, s) static_assert(e, s)
/* FIXME: change this to thread_local when clang in base supports it */
#define _Thread_local __thread
#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
/* Do nothing. They are language keywords. */
#else
/* Not supported. Implement them using our versions. */
#define _Alignas(x) __aligned(x)
#define _Alignof(x) __alignof(x)
#define _Noreturn __dead2
#define _Thread_local __thread
#ifdef __COUNTER__
#define _Static_assert(x, y) __Static_assert(x, __COUNTER__)
#define __Static_assert(x, y) ___Static_assert(x, y)
#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1]
#else
#define _Static_assert(x, y) struct __hack
#endif
#endif
/*
* Emulation of C11 _Generic(). Unlike the previously defined C11
* keywords, it is not possible to implement this using exactly the same
* syntax. Therefore implement something similar under the name
* __generic(). Unlike _Generic(), this macro can only distinguish
* between a single type, so it requires nested invocations to
* distinguish multiple cases.
*/
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
#define __generic(expr, t, yes, no) \
_Generic(expr, t: yes, default: no)
#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
#define __generic(expr, t, yes, no) \
__builtin_choose_expr( \
__builtin_types_compatible_p(__typeof(expr), t), yes, no)
#endif
#if __GNUC_PREREQ__(2, 96)
#define __malloc_like __attribute__((__malloc__))
#define __pure __attribute__((__pure__))
#else
#define __malloc_like
#define __pure
#endif
#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
#define __always_inline __attribute__((__always_inline__))
#else
#define __always_inline
#endif
#if __GNUC_PREREQ__(3, 1)
#define __noinline __attribute__ ((__noinline__))
#else
#define __noinline
#endif
#if __GNUC_PREREQ__(3, 3)
#define __nonnull(x) __attribute__((__nonnull__(x)))
#else
#define __nonnull(x)
#endif
#if __GNUC_PREREQ__(3, 4)
#define __fastcall __attribute__((__fastcall__))
#else
#define __fastcall
#endif
#if __GNUC_PREREQ__(4, 1)
#define __returns_twice __attribute__((__returns_twice__))
#else
#define __returns_twice
#endif
/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __func__ NULL
#endif
#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901
#define __LONG_LONG_SUPPORTED
#endif
/* C++11 exposes a load of C99 stuff */
#if defined(__cplusplus) && __cplusplus >= 201103L
#define __LONG_LONG_SUPPORTED
#ifndef __STDC_LIMIT_MACROS
#define __STDC_LIMIT_MACROS
#endif
#ifndef __STDC_CONSTANT_MACROS
#define __STDC_CONSTANT_MACROS
#endif
#endif
/*
* GCC 2.95 provides `__restrict' as an extension to C90 to support the
* C99-specific `restrict' type qualifier. We happen to use `__restrict' as
* a way to define the `restrict' type qualifier without disturbing older
* software that is unaware of C99 keywords.
*/
#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint)
#define __restrict
#else
#define __restrict restrict
#endif
#endif
/*
* GNU C version 2.96 adds explicit branch prediction so that
* the CPU back-end can hint the processor and also so that
* code blocks can be reordered such that the predicted path
* sees a more linear flow, thus improving cache behavior, etc.
*
* The following two macros provide us with a way to utilize this
* compiler feature. Use __predict_true() if you expect the expression
* to evaluate to true, and __predict_false() if you expect the
* expression to evaluate to false.
*
* A few notes about usage:
*
* * Generally, __predict_false() error condition checks (unless
* you have some _strong_ reason to do otherwise, in which case
* document it), and/or __predict_true() `no-error' condition
* checks, assuming you want to optimize for the no-error case.
*
* * Other than that, if you don't know the likelihood of a test
* succeeding from empirical or other `hard' evidence, don't
* make predictions.
*
* * These are meant to be used in places that are run `a lot'.
* It is wasteful to make predictions in code that is run
* seldomly (e.g. at subsystem initialization time) as the
* basic block reordering that this affects can often generate
* larger code.
*/
#if __GNUC_PREREQ__(2, 96)
#define __predict_true(exp) __builtin_expect((exp), 1)
#define __predict_false(exp) __builtin_expect((exp), 0)
#else
#define __predict_true(exp) (exp)
#define __predict_false(exp) (exp)
#endif
#if __GNUC_PREREQ__(4, 2)
#define __hidden __attribute__((__visibility__("hidden")))
#define __exported __attribute__((__visibility__("default")))
#else
#define __hidden
#define __exported
#endif
/*
* We define this here since <stddef.h>, <sys/queue.h>, and <sys/types.h>
* require it.
*/
#if __GNUC_PREREQ__(4, 1)
#define __offsetof(type, field) __builtin_offsetof(type, field)
#else
#ifndef __cplusplus
#define __offsetof(type, field) \
((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field))
#else
#define __offsetof(type, field) \
(__offsetof__ (reinterpret_cast <__size_t> \
(&reinterpret_cast <const volatile char &> \
(static_cast<type *> (0)->field))))
#endif
#endif
#define __rangeof(type, start, end) \
(__offsetof(type, end) - __offsetof(type, start))
/*
* Given the pointer x to the member m of the struct s, return
* a pointer to the containing structure. When using GCC, we first
* assign pointer x to a local variable, to check that its type is
* compatible with member m.
*/
#if __GNUC_PREREQ__(3, 1)
#define __containerof(x, s, m) ({ \
const volatile __typeof(((s *)0)->m) *__x = (x); \
__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
})
#else
#define __containerof(x, s, m) \
__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
#endif
/*
* Compiler-dependent macros to declare that functions take printf-like
* or scanf-like arguments. They are null except for versions of gcc
* that are known to support the features properly (old versions of gcc-2
* didn't permit keeping the keywords out of the application namespace).
*/
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __printflike(fmtarg, firstvararg)
#define __scanflike(fmtarg, firstvararg)
#define __format_arg(fmtarg)
#define __strfmonlike(fmtarg, firstvararg)
#define __strftimelike(fmtarg, firstvararg)
#else
#define __printflike(fmtarg, firstvararg) \
__attribute__((__format__ (__printf__, fmtarg, firstvararg)))
#define __scanflike(fmtarg, firstvararg) \
__attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))
#define __strfmonlike(fmtarg, firstvararg) \
__attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
#define __strftimelike(fmtarg, firstvararg) \
__attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
#endif
/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER)
#define __printf0like(fmtarg, firstvararg) \
__attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
#else
#define __printf0like(fmtarg, firstvararg)
#endif
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#ifndef __INTEL_COMPILER
#define __strong_reference(sym,aliassym) \
extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
#endif
#ifdef __STDC__
#define __weak_reference(sym,alias) \
__asm__(".weak " #alias); \
__asm__(".equ " #alias ", " #sym)
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning." #sym); \
__asm__(".asciz \"" msg "\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@" #verid)
#define __sym_default(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@@" #verid)
#else
#define __weak_reference(sym,alias) \
__asm__(".weak alias"); \
__asm__(".equ alias, sym")
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning.sym"); \
__asm__(".asciz \"msg\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver impl, sym@verid")
#define __sym_default(impl,sym,verid) \
__asm__(".symver impl, sym@@verid")
#endif /* __STDC__ */
#endif /* __GNUC__ || __INTEL_COMPILER */
#define __GLOBL1(sym) __asm__(".globl " #sym)
#define __GLOBL(sym) __GLOBL1(sym)
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"")
#else
/*
* The following definition might not work well if used in header files,
* but it should be better than nothing. If you want a "do nothing"
* version, then it should generate some harmless declaration, such as:
* #define __IDSTRING(name,string) struct __hack
*/
#define __IDSTRING(name,string) static const char name[] __unused = string
#endif
/*
* Embed the rcs id of a source file in the resulting library. Note that in
* more recent ELF binutils, we use .ident allowing the ID to be stripped.
* Usage:
* __FBSDID("$FreeBSD$");
*/
#ifndef __FBSDID
#if !defined(lint) && !defined(STRIP_FBSDID)
#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s)
#else
#define __FBSDID(s) struct __hack
#endif
#endif
#ifndef __RCSID
#ifndef NO__RCSID
#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s)
#else
#define __RCSID(s) struct __hack
#endif
#endif
#ifndef __RCSID_SOURCE
#ifndef NO__RCSID_SOURCE
#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s)
#else
#define __RCSID_SOURCE(s) struct __hack
#endif
#endif
#ifndef __SCCSID
#ifndef NO__SCCSID
#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s)
#else
#define __SCCSID(s) struct __hack
#endif
#endif
#ifndef __COPYRIGHT
#ifndef NO__COPYRIGHT
#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s)
#else
#define __COPYRIGHT(s) struct __hack
#endif
#endif
#ifndef __DECONST
#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var))
#endif
#ifndef __DEVOLATILE
#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var))
#endif
#ifndef __DEQUALIFY
#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var))
#endif
/*-
* The following definitions are an extension of the behavior originally
* implemented in <sys/_posix.h>, but with a different level of granularity.
* POSIX.1 requires that the macros we test be defined before any standard
* header file is included.
*
* Here's a quick run-down of the versions:
* defined(_POSIX_SOURCE) 1003.1-1988
* _POSIX_C_SOURCE == 1 1003.1-1990
* _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option
* _POSIX_C_SOURCE == 199309 1003.1b-1993
* _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995,
* and the omnibus ISO/IEC 9945-1: 1996
* _POSIX_C_SOURCE == 200112 1003.1-2001
* _POSIX_C_SOURCE == 200809 1003.1-2008
*
* In addition, the X/Open Portability Guide, which is now the Single UNIX
* Specification, defines a feature-test macro which indicates the version of
* that specification, and which subsumes _POSIX_C_SOURCE.
*
* Our macros begin with two underscores to avoid namespace screwage.
*/
/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */
#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1
#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */
#define _POSIX_C_SOURCE 199009
#endif
/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */
#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 199209
#endif
/* Deal with various X/Open Portability Guides and Single UNIX Spec. */
#ifdef _XOPEN_SOURCE
#if _XOPEN_SOURCE - 0 >= 700
#define __XSI_VISIBLE 700
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200809
#elif _XOPEN_SOURCE - 0 >= 600
#define __XSI_VISIBLE 600
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200112
#elif _XOPEN_SOURCE - 0 >= 500
#define __XSI_VISIBLE 500
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 199506
#endif
#endif
/*
* Deal with all versions of POSIX. The ordering relative to the tests above is
* important.
*/
#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE)
#define _POSIX_C_SOURCE 198808
#endif
#ifdef _POSIX_C_SOURCE
#if _POSIX_C_SOURCE >= 200809
#define __POSIX_VISIBLE 200809
#define __ISO_C_VISIBLE 1999
#elif _POSIX_C_SOURCE >= 200112
#define __POSIX_VISIBLE 200112
#define __ISO_C_VISIBLE 1999
#elif _POSIX_C_SOURCE >= 199506
#define __POSIX_VISIBLE 199506
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199309
#define __POSIX_VISIBLE 199309
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199209
#define __POSIX_VISIBLE 199209
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199009
#define __POSIX_VISIBLE 199009
#define __ISO_C_VISIBLE 1990
#else
#define __POSIX_VISIBLE 198808
#define __ISO_C_VISIBLE 0
#endif /* _POSIX_C_SOURCE */
#else
/*-
* Deal with _ANSI_SOURCE:
* If it is defined, and no other compilation environment is explicitly
* requested, then define our internal feature-test macros to zero. This
* makes no difference to the preprocessor (undefined symbols in preprocessing
* expressions are defined to have value zero), but makes it more convenient for
* a test program to print out the values.
*
* If a program mistakenly defines _ANSI_SOURCE and some other macro such as
* _POSIX_C_SOURCE, we will assume that it wants the broader compilation
* environment (and in fact we will never get here).
*/
#if defined(_ANSI_SOURCE) /* Hide almost everything. */
#define __POSIX_VISIBLE 0
#define __XSI_VISIBLE 0
#define __BSD_VISIBLE 0
#define __ISO_C_VISIBLE 1990
#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */
#define __POSIX_VISIBLE 0
#define __XSI_VISIBLE 0
#define __BSD_VISIBLE 0
#define __ISO_C_VISIBLE 1999
#else /* Default environment: show everything. */
#define __POSIX_VISIBLE 200809
#define __XSI_VISIBLE 700
#define __BSD_VISIBLE 1
#define __ISO_C_VISIBLE 1999
#endif
#endif
#ifndef __has_feature
#define __has_feature(x) 0
#endif
#ifndef __has_include
#define __has_include(x) 0
#endif
#ifndef __has_builtin
#define __has_builtin(x) 0
#endif
#if defined(__mips) || defined(__powerpc64__) || defined(__arm__)
#define __NO_TLS 1
#endif
#endif /* !_SYS_CDEFS_H_ */

48
IPL/SDK/v4h/src/Dummy_RTOS/include/timer.h Normal file
View File

@@ -0,0 +1,48 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : timer header
******************************************************************************/
/******************************************************************************
* @file timer.h
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 19.09.2023 0.01 First Release
*****************************************************************************/
#ifndef TIMER_H_
#define TIMER_H_
#include <stdint.h>
/* Prototype */
void generic_timer_init(void);
void micro_wait(uint64_t micro_sec);
#endif /* TIMER_H_ */

298
IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.S Normal file
View File

@@ -0,0 +1,298 @@
/*
* Copyright (c) 2015-2024, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define DRAM_BASE (0x40000000)
#define SYSRAM_BASE (0xE6300000)
#define DTCM_BASE (0xE2020000)
#define STACK_BASE_ABT (DTCM_BASE | 0x7080)
#define STACK_BASE_UND (DTCM_BASE | 0x7100)
#define STACK_BASE_FIQ (DTCM_BASE | 0x7180)
#define STACK_BASE_IRQ (DTCM_BASE | 0x7200)
#define STACK_BASE_SVC (DTCM_BASE | 0x8000)
.global Vector
.global Start
.local rtos_stacks
/*****************************************************************************
* Vector table
*****************************************************************************/
.align 5
Vector:
b Start /* Reset */
b Undef /* Undefined Instruction */
b SWI /* Supervisor Call */
b PAbort /* Prefetch Abort */
b DAbort /* Data Abort */
nop /* Not used */
b IRQ /* IRQ interrupt */
b FIQ /* FIQ interrupt */
/*****************************************************************************
* Reset Hander
*****************************************************************************/
Start:
/* initialize registers*/
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11, #0
mov r12, #0
mov lr, #0
#if ((CR52_CORE == 0) || (CR52_CORE == 2))
/* MPU setting is required only for RTOS#0 and RTOS#2. */
/* CR52_CONFIGURE_MPU */
;# MPU setting was given from BootROM team
;# Memory Attribute setting
LDR r0, =0xFF00 ;# Attr1[15:8]=FF:Write-Back, Attr0[7:0]=00:Device-nGnRnE memory
MCR p15, 0, r0, c10, c2, 0 ;# MAIR0
MCR p15, 4, r0, c10, c2, 0 ;# HMAIR0
;# region 0: 0x00000000--0x3FFFFFFF AttrIndx=1(Write-Back)
LDR r0, =0x00000002 ;# SH=b'00/AP=b'01/XN=b'0
MCR p15, 0, r0, c6, c8, 0 ;# PRBAR0
MCR p15, 4, r0, c6, c8, 0 ;# HPRBAR0
LDR r0, =0x3FFFFFC3 ;# AttrIndx=1(Write-Back)
MCR p15, 0, r0, c6, c8, 1 ;# PRLAR0
MCR p15, 4, r0, c6, c8, 1 ;# HPRLAR0
;# region 1: 0x40000000--0xBFFFFFFF AttrIndx=1(Write-Back)
LDR r0, =0x40000002 ;# SH=b'00/AP=b'01/XN=b'0
MCR p15, 0, r0, c6, c8, 4 ;# PRBAR1
MCR p15, 4, r0, c6, c8, 4 ;# HPRBAR1
LDR r0, =0xBFFFFFC3 ;# AttrIndx=1(Write-Back)
MCR p15, 0, r0, c6, c8, 5 ;# PRLAR1
MCR p15, 4, r0, c6, c8, 5 ;# HPRLAR1
;# region 2: 0xC0000000--0xDFFFFFFF AttrIndx=0(Device)
LDR r0, =0xC0000003 ;# SH=b'00/AP=b'01/XN=b'1
MCR p15, 0, r0, c6, c9, 0 ;# PRBAR2
MCR p15, 4, r0, c6, c9, 0 ;# HPRBAR2
LDR r0, =0xDFFFFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c9, 1 ;# PRLAR2
MCR p15, 4, r0, c6, c9, 1 ;# HPRLAR2
;# region 3: 0xE0000000--0xE1FFFFFF AttrIndx=0(Device)
;# LDR r0, =0xE0000003 ;# SH=b'00/AP=b'01/XN=b'1
LDR r0, =0xE0000002 ;# SH=b'00/AP=b'01/XN=b'0 ;# Enable RT-VRAM1 for V4H
MCR p15, 0, r0, c6, c9, 4 ;# PRBAR3
MCR p15, 4, r0, c6, c9, 4 ;# HPRBAR3
LDR r0, =0xE1FFFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c9, 5 ;# PRLAR3
MCR p15, 4, r0, c6, c9, 5 ;# HPRLAR3
;# region 4: 0xE2000000--0xE42FFFFF AttrIndx=1(Write-Back)
LDR r0, =0xE2000002 ;# SH=b'00/AP=b'01/XN=b'0
MCR p15, 0, r0, c6, c10, 0 ;# PRBAR4
MCR p15, 4, r0, c6, c10, 0 ;# HPRBAR4
LDR r0, =0xE42FFFC3 ;# AttrIndx=(Write-Back)
MCR p15, 0, r0, c6, c10, 1 ;# PRLAR4
MCR p15, 4, r0, c6, c10, 1 ;# HPRLAR4
;# region 5: 0xE4300000--0xE62FFFFF AttrIndx=0(Device)
LDR r0, =0xE4300003 ;# SH=b'00/AP=b'01/XN=b'1
MCR p15, 0, r0, c6, c10, 4 ;# PRBAR5
MCR p15, 4, r0, c6, c10, 4 ;# HPRBAR5
LDR r0, =0xE62FFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c10, 5 ;# PRLAR5
MCR p15, 4, r0, c6, c10, 5 ;# HPRLAR5
;# region 6: 0xE6300000--0xE63FFFFF AttrIndx=1(Write-Back)
LDR r0, =0xE6300002 ;# SH=b'00/AP=b'01/XN=b'0
MCR p15, 0, r0, c6, c11, 0 ;# PRBAR6
MCR p15, 4, r0, c6, c11, 0 ;# HPRBAR6
LDR r0, =0xE63FFFC3 ;# AttrIndx=(Write-Back)
MCR p15, 0, r0, c6, c11, 1 ;# PRLAR6
MCR p15, 4, r0, c6, c11, 1 ;# HPRLAR6
;# region 7: 0xE6400000--0xEB0FFFFF AttrIndx=0(Device)
LDR r0, =0xE6400003 ;# SH=b'00/AP=b'01/XN=b'1
MCR p15, 0, r0, c6, c11, 4 ;# PRBAR7
MCR p15, 4, r0, c6, c11, 4 ;# HPRBAR7
LDR r0, =0xEB0FFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c11, 5 ;# PRLAR7
MCR p15, 4, r0, c6, c11, 5 ;# HPRLAR7
;# region 8: 0xEB100000--0xEB127FFF AttrIndx=1(Write-Back)
LDR r0, =0xEB100006 ;# SH=b'00/AP=b'10/XN=b'0
MCR p15, 0, r0, c6, c12, 0 ;# PRBAR8
MCR p15, 4, r0, c6, c12, 0 ;# HPRBAR8
LDR r0, =0xEB127FC3 ;# AttrIndx=(Write-Back)
MCR p15, 0, r0, c6, c12, 1 ;# PRLAR8
MCR p15, 4, r0, c6, c12, 1 ;# HPRLAR8
;# region 9: 0xEB128000--0xEB1FFFFF AttrIndx=0(Device)
LDR r0, =0xEB128003 ;# SH=b'00/AP=b'01/XN=b'1
MCR p15, 0, r0, c6, c12, 4 ;# PRBAR9
MCR p15, 4, r0, c6, c12, 4 ;# HPRBAR9
LDR r0, =0xEB1FFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c12, 5 ;# PRLAR9
MCR p15, 4, r0, c6, c12, 5 ;# HPRLAR9
;# region 10: 0xEB200000--0xEB3FFFFF AttrIndx=1(Write-Back)
LDR r0, =0xEB200002 ;# SH=b'00/AP=b'01/XN=b'0
MCR p15, 0, r0, c6, c13, 0 ;# PRBAR10
MCR p15, 4, r0, c6, c13, 0 ;# HPRBAR10
LDR r0, =0xEB3FFFC3 ;# AttrIndx=(Write-Back)
MCR p15, 0, r0, c6, c13, 1 ;# PRLAR10
MCR p15, 4, r0, c6, c13, 1 ;# HPRLAR10
;# region 11: 0xEB400000--0xFFFFFFFF AttrIndx=0(Device)
LDR r0, =0xEB400003 ;# SH=b'00/AP=b'01/XN=b'1
MCR p15, 0, r0, c6, c13, 4 ;# PRBAR11
MCR p15, 4, r0, c6, c13, 4 ;# HPRBAR11
LDR r0, =0xFFFFFFC1 ;# AttrIndx=0(Device)
MCR p15, 0, r0, c6, c13, 5 ;# PRLAR11
MCR p15, 4, r0, c6, c13, 5 ;# HPRLAR11
;#CR52_SET_MPU_ON
MRC p15, 4, r0, c1, c0, 0 ;# HSCTLR
ORR r0, r0, #0x00000001 ;# EL2-controlled MPU enable
DSB
MCR p15, 4, r0, c1, c0, 0
ISB
MRC p15, 0, r0, c1, c0, 0 ;# SCTLR
ORR r0, r0, #0x00000001 ;# EL1-controlled MPU enable
DSB
MCR p15, 0, r0, c1, c0, 0
ISB
#endif /* ((CR52_CORE == 0) || (CR52_CORE == 2)) */
LDR PC, =STACK_INIT
STACK_INIT:
/* stack initialize */
ldr r0, =__STACKS_END__
;# msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */
;# mov sp, r0 /* STACK_BASE_ABT */
;# msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */
;# sub r0, r0, #0x80 /* STACK_BASE_UND */
;# mov sp, r0
;# msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */
;# sub r0, r0, #0x80 /* STACK_BASE_FIQ */
;# mov sp, r0
;# msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */
;# sub r0, r0, #0x80 /* STACK_BASE_IRQ */
;# mov sp, r0
;# msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */
;# sub r0, r0, #0x80 /* STACK_BASE_SVC */
mov sp, r0
/* Loader Main */
BL rtos_main
NO_BOOT:
nop
1:
;# wfe
b 1b
/*****************************************************************************
* Exception Handers
*****************************************************************************/
/* Undefined Instruction */
Undef:
nop
1:
wfe
b 1b
/* Supervisor Call */
SWI:
nop
1:
wfe
b 1b
/* Prefetch Abort */
PAbort:
nop
1:
wfe
b 1b
/* Data Abort */
DAbort:
nop
1:
wfe
b 1b
/* IRQ interrupt */
IRQ:
nop
1:
wfe
b 1b
/* FIQ interrupt */
FIQ:
nop
1:
wfe
b 1b
/*****************************************************************************
* Define stack
*****************************************************************************/
.section tzfw_normal_stacks, "aw"
.align 6
rtos_stacks:
.space 4 * 1024
.end

92
IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.ld.S Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Vector)
MEMORY {
RAM (rwxa): ORIGIN = 0xE2100000, LENGTH = 0x00400000
}
SECTIONS
{
. = 0xE2100000;
ASSERT(. == ALIGN(4096),
"CR7 dummy rtos address is not aligned on a page boundary.")
ro . : {
__RO_START__ = .;
*rtos.o(.text*)
*rtos_main.o(.text*)
. = NEXT(32768);
*(.text*)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
. = NEXT(16384);
__RO_END__ = .;
} >RAM
.data . : {
__DATA_START__ = .;
*(.data*)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(tzfw_normal_stacks))
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
__BSS_SIZE__ = SIZEOF(.bss);
ASSERT(. <= 0xE24FE800, "CR7 dummy rtos has exceeded its limit.")
}

92
IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core1.ld.S Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (c) 2015-2024, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Vector)
MEMORY {
RAM (rwxa): ORIGIN = 0xE3100000, LENGTH = 0x00200000 /* 2MiB */
}
SECTIONS
{
. = 0xE3100000;
ASSERT(. == ALIGN(4096),
"CR7 dummy rtos address is not aligned on a page boundary.")
ro . : {
__RO_START__ = .;
*rtos.o(.text*)
*rtos_main.o(.text*)
. = NEXT(32768);
*(.text*)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
. = NEXT(16384);
__RO_END__ = .;
} >RAM
.data . : {
__DATA_START__ = .;
*(.data*)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(tzfw_normal_stacks))
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
__BSS_SIZE__ = SIZEOF(.bss);
ASSERT(. <= 0xE32FF800, "CR7 dummy rtos has exceeded its limit.")
}

92
IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core2.ld.S Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (c) 2015-2024, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Vector)
MEMORY {
RAM (rwxa): ORIGIN = 0xE2000000, LENGTH = 0x00010000 /* 64KiB */
}
SECTIONS
{
. = 0xE2000000;
ASSERT(. == ALIGN(4096),
"CR7 dummy rtos address is not aligned on a page boundary.")
ro . : {
__RO_START__ = .;
*rtos.o(.text*)
*rtos_main.o(.text*)
. = NEXT(32768);
*(.text*)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
. = NEXT(16384);
__RO_END__ = .;
} >RAM
.data . : {
__DATA_START__ = .;
*(.data*)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(tzfw_normal_stacks))
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
__BSS_SIZE__ = SIZEOF(.bss);
ASSERT(. <= 0xE200F800, "CR7 dummy rtos has exceeded its limit.")
}

103
IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_main.c Normal file
View File

@@ -0,0 +1,103 @@
/*
* Copyright (c) 2015-2024, Renesas Electronics Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of Renesas nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include "scif.h"
#include "timer.h"
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
/************************************************************************************************/
/* Unions */
/************************************************************************************************/
/************************************************************************************************/
/* Structs */
/************************************************************************************************/
/************************************************************************************************/
/* Globals */
/************************************************************************************************/
/************************************************************************************************/
/* Macros */
/************************************************************************************************/
#define MIDR_PN_SHIFT (0x4U)
#define MIDR_PN_MASK (0X0FFFU)
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
#define MIDR_CR7 (0x0C17U << MIDR_PN_SHIFT)
/* Input Dummy Program waiting time (us) */
#if (CR52_CORE == 0) /* RTOS#0 */
#define WAIT_TIME_US (2000000U) /* 3.0[s] */
#elif (CR52_CORE == 1) /* RTOS#1 */
#define WAIT_TIME_US (1U) /* 1.0[us] */
#elif (CR52_CORE == 2) /* RTOS#2 */
#define WAIT_TIME_US (1000000U) /* 2.0[s] */
#endif
/************************************************************************************************/
/* Prototypes */
/************************************************************************************************/
uint32_t rtos_main(void);
uint32_t rtos_main(void)
{
scif_init();
generic_timer_init();
micro_wait(WAIT_TIME_US);
#if (CR52_CORE == 0) /* RTOS#0 */
PutStr(" ",1);
PutStr("Dummy RTOS#0 Program",1);
PutStr("Dummy RTOS#0 Program boot end",1);
#elif (CR52_CORE == 1) /* RTOS#1 */
PutStr(" ",1);
PutStr("Dummy RTOS#1 Program",1);
PutStr("Dummy RTOS#1 Program boot end",1);
#elif (CR52_CORE == 2) /* RTOS#2 */
PutStr(" ",1);
PutStr("Dummy RTOS#2 Program",1);
PutStr("Dummy RTOS#2 Program boot end",1);
#endif
return 0U;
}

646
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/Makefile Normal file
View File

@@ -0,0 +1,646 @@
#/*******************************************************************************
# * DISCLAIMER
# * This software is supplied by Renesas Electronics Corporation and is only
# * intended for use with Renesas products. No other uses are authorized. This
# * software is owned by Renesas Electronics Corporation and is protected under
# * all applicable laws, including copyright laws.
# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
# * Renesas reserves the right, without notice, to make changes to this software
# * and to discontinue the availability of this software. By using this software,
# * you agree to the additional terms and conditions found by accessing the
# * following link:
# * http://www.renesas.com/disclaimer
# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
# *******************************************************************************/
#
# *******************************************************************************
# * DESCRIPTION : makefile for Loader
# ******************************************************************************
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude \
-Iip/ddr
OUTDIR := build
# LSI setting common define
RCAR_S4 := 0
RCAR_V4H := 1
RCAR_V4M := 2
$(eval $(call add_define,RCAR_S4))
$(eval $(call add_define,RCAR_V4H))
$(eval $(call add_define,RCAR_V4M))
#/* Select LSI("S4" or "V4H" or "V4M" )********************************
ifeq ("$(LSI)", "")
LSI = S4
endif
ifeq (${LSI},S4)
RCAR_LSI:=${RCAR_S4}
DIR_NAME_SA9 = s4
OBJ_FILE += loader/loader_main_s4.o \
cnf_tbl/cnf_tbl_s4.o \
ip/qos/qos.o \
ip/rtvram/rtvram.o \
ip/ddr/s4/lpddr4x/ecc_enable_s4.o
INCLUDE_DIR += -Imcu
include ip/ddr/ddr.mk
else ifeq (${LSI},V4H)
RCAR_LSI:=${RCAR_V4H}
DIR_NAME_SA9 = v4h
OBJ_FILE += loader/loader_main_v4h.o \
ip/fcpr/fcpr.o \
cnf_tbl/cnf_tbl_v4h.o \
ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \
ip/ddr/v4h/lpddr5/ecm_enable_v4h.o
else ifeq (${LSI},V4M)
RCAR_LSI:=${RCAR_V4M}
DIR_NAME_SA9 = v4m
OBJ_FILE += loader/loader_main_v4m.o \
ip/fcpr/fcpr.o \
cnf_tbl/cnf_tbl_v4m.o \
ip/sysc/sysc.o \
ip/avs/avs.o \
ip/i2c/i2c.o \
ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \
ip/ddr/v4m/lpddr5/ecm_enable_v4m.o
else
$(error "Error: ${LSI} is not supported.")
endif
$(eval $(call add_define,RCAR_LSI))
#output file name
FILE_NAME = icumx_loader
FILE_NAME_SA0 = bootparam_sa0
FILE_NAME_SA9 = cert_header_sa9
FILE_NAME_TFMV_TBL = tfmv_ver_tbl
FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl
OUTPUT_FILE = $(FILE_NAME).elf
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf
OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf
OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf
#object file name
OBJ_FILE += cpu_on/cpu_on.o \
common/log/log.o \
common/log/scif.o \
common/timer/micro_wait.o \
image_load/image_load.o \
intc/intc.o \
intc/vecttbl.o \
intc/vect_set.o \
ip/ip_control.o \
ip/cpg/cpg.o \
ip/emmc/emmc_boot.o \
ip/wdt/wdt.o \
loader/loader.o \
loader/loader_main_common.o \
protect/ram_protection.o \
protect/region_id.o \
protect/stack_protect.o \
remap/remap.o \
rom_api/rom_api.o
OBJ_FILE_SA0 = tools/dummy_create/sa0.o
OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o
OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o
OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o
#linker script name
ifeq (${LSI},V4M)
MEMORY_DEF = loader/icumx_loader_v4m.ld
else
MEMORY_DEF = loader/icumx_loader.ld
endif
MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld
MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld
MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld
MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld
###################################################
# Debug build
DEBUG:=0
# Process DEBUG flag
$(eval $(call assert_boolean,DEBUG))
$(eval $(call add_define,DEBUG))
ifeq (${DEBUG},0)
$(eval $(call add_define,NDEBUG))
CFLAGS += -Onone
else
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Odebug
endif
# MISRA Option
#------ MISRA ------
ifndef MISRA
MISRA := MANDATORY
endif
ifeq ("$(MISRA)", "DISABLE")
MISRA_OPTION = DISABLE
else ifeq ("$(MISRA)", "FULL")
MISRA_OPTION = FULL
else ifeq ("$(MISRA)", "MANDATORY")
MISRA_OPTION = MANDATORY
else ifeq ("$(MISRA)", "REQUIRED")
MISRA_OPTION = REQUIRED
endif
CFLAGS_MISRA_FULL = \
--misra_adv=warn \
--misra_req=warn \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
CFLAGS_MISRA_REQUIRED = \
--misra_adv=silent \
--misra_req=warn \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
CFLAGS_MISRA_MANDATORY = \
--misra_adv=silent \
--misra_req=silent \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
# MISRA 2012 Rule 3.1 is confirmed with static analysis
ifeq ("$(MISRA_OPTION)", "FULL")
CFLAGS += $(CFLAGS_MISRA_FULL)
else ifeq ("$(MISRA)", "REQUIRED")
CFLAGS += $(CFLAGS_MISRA_REQUIRED)
else ifeq ("$(MISRA)", "MANDATORY")
CFLAGS += $(CFLAGS_MISRA_MANDATORY)
endif
# Process LOG_LEVEL
ifndef LOG_LEVEL
LOG_LEVEL := 2
endif
$(eval $(call add_define,LOG_LEVEL))
ifeq (${LOG_LEVEL},0)
LDFLAGS += -nostdlib
endif
# Process SET_FCPR_PARAM flag
# 0:Disable, 1:Enable (Support V4H / V4M Linux OS)
ifeq ($(filter ${LSI},V4H V4M),${LSI})
ifndef SET_FCPR_PARAM
SET_FCPR_PARAM := 0
$(eval $(call add_define,SET_FCPR_PARAM))
else
ifeq (${SET_FCPR_PARAM},0)
$(eval $(call add_define,SET_FCPR_PARAM))
else ifeq (${SET_FCPR_PARAM},1)
$(eval $(call add_define,SET_FCPR_PARAM))
else
$(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.")
endif
endif
else
SET_FCPR_PARAM := 0
$(eval $(call add_define,SET_FCPR_PARAM))
endif
# Process BOOT_MCU flag (S4 only)
# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH
ifeq (${LSI},S4)
ifndef BOOT_MCU
BOOT_MCU :=3
$(eval $(call add_define,BOOT_MCU))
else
ifeq (${BOOT_MCU},0)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},1)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},2)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},3)
$(eval $(call add_define,BOOT_MCU))
else
$(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.")
endif
endif
else
BOOT_MCU :=0
$(eval $(call add_define,BOOT_MCU))
endif
ifneq (${BOOT_MCU},0)
OBJ_FILE += mcu/cpu_on_for_mcu.o \
mcu/sdmac.o \
mcu/loader_main_mcu.o \
mcu/image_load_for_mcu.o \
mcu/codesram_ecc.o
endif
# Process RTVRAM_EXTEND flag
ifeq (${LSI},S4)
ifndef RTVRAM_EXTEND
RTVRAM_EXTEND := 1
$(eval $(call add_define,RTVRAM_EXTEND))
else
ifeq (${RTVRAM_EXTEND},0)
$(eval $(call add_define,RTVRAM_EXTEND))
else ifeq (${RTVRAM_EXTEND},1)
$(eval $(call add_define,RTVRAM_EXTEND))
else
$(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.")
endif
endif
endif
# Process QSPI_DDR_MODE flag
# 0:SDR, 1:DDR
ifndef QSPI_DDR_MODE
QSPI_DDR_MODE := 0
$(eval $(call add_define,QSPI_DDR_MODE))
else
ifeq (${QSPI_DDR_MODE},0)
$(eval $(call add_define,QSPI_DDR_MODE))
else ifeq (${QSPI_DDR_MODE},1)
$(eval $(call add_define,QSPI_DDR_MODE))
else
$(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.")
endif
endif
# RCAR_QSPI_DDR_DUMMY_CYCLE
ifndef RCAR_QSPI_DDR_DUMMY_CYCLE
RCAR_QSPI_DDR_DUMMY_CYCLE := 9
endif
$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE))
# Process RCAR_SA9_TYPE flag
# 0:Flash, 1:eMMC
ifeq (${LSI},S4)
ifndef RCAR_SA9_TYPE
RCAR_SA9_TYPE := 0
$(eval $(call add_define,RCAR_SA9_TYPE))
else
ifeq (${RCAR_SA9_TYPE},0)
$(eval $(call add_define,RCAR_SA9_TYPE))
else ifeq (${RCAR_SA9_TYPE},1)
$(eval $(call add_define,RCAR_SA9_TYPE))
else
$(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.")
endif
endif
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
RCAR_SA9_TYPE := 0
$(eval $(call add_define,RCAR_SA9_TYPE))
endif
ifeq (${RCAR_SA9_TYPE},1)
OBJ_FILE += image_load/image_load_emmc.o \
ip/emmc/emmc_cmd.o \
ip/emmc/emmc_init.o \
ip/emmc/emmc_interrupt.o \
ip/emmc/emmc_mount.o \
ip/emmc/emmc_multiboot.o \
ip/emmc/emmc_read.o \
ip/emmc/emmc_utility.o
else ifeq (${RCAR_SA9_TYPE},0)
OBJ_FILE += image_load/image_load_flash.o \
ip/dma/dma.o \
ip/rpc/rpc.o \
ip/mfis/mfis.o
endif
# Process CA_LOAD_TYPE flag
# 0:CA Loader 1:BL31 (or Secure Monitor)
ifeq (${LSI},S4)
ifndef CA_LOAD_TYPE
CA_LOAD_TYPE := 0
$(eval $(call add_define,CA_LOAD_TYPE))
else
ifeq (${CA_LOAD_TYPE},0)
$(eval $(call add_define,CA_LOAD_TYPE))
else ifeq (${CA_LOAD_TYPE},1)
$(eval $(call add_define,CA_LOAD_TYPE))
else
$(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.")
endif
endif
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
CA_LOAD_TYPE := 0
$(eval $(call add_define,CA_LOAD_TYPE))
endif
ifeq (${RCAR_SA9_TYPE},1)
ifeq (${CA_LOAD_TYPE},0)
$(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.")
endif
endif
# Process MCU_SECURE_BOOT flag (S4 only)
ifndef MCU_SECURE_BOOT
MCU_SECURE_BOOT := 0
$(eval $(call add_define,MCU_SECURE_BOOT))
else
ifeq (${MCU_SECURE_BOOT},0)
$(eval $(call add_define,MCU_SECURE_BOOT))
else ifeq (${MCU_SECURE_BOOT},1)
ifeq (${BOOT_MCU},0)
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.")
else
$(eval $(call add_define,MCU_SECURE_BOOT))
endif
else
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.")
endif
endif
# Process SW_VERSION_CHECK flag
# 0:Disable 1:Enable
ifndef SW_VERSION_CHECK
SW_VERSION_CHECK := 0
$(eval $(call add_define,SW_VERSION_CHECK))
else
ifeq (${SW_VERSION_CHECK},0)
$(eval $(call add_define,SW_VERSION_CHECK))
else ifeq (${SW_VERSION_CHECK},1)
$(eval $(call add_define,SW_VERSION_CHECK))
else
$(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.")
endif
endif
# Process access protection flag
# 0:Disable 1:Enable
ifndef ACC_PROT_ENABLE
ACC_PROT_ENABLE := 0
$(eval $(call add_define,ACC_PROT_ENABLE))
else
ifeq (${ACC_PROT_ENABLE},0)
$(eval $(call add_define,ACC_PROT_ENABLE))
else ifeq (${ACC_PROT_ENABLE},1)
$(eval $(call add_define,ACC_PROT_ENABLE))
else
$(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.")
endif
endif
ifeq (${MCU_SECURE_BOOT},1)
include mcu_secureboot/mcu_secureboot.mk
endif
# Process ADD_HOTPLUG_MAGIC flag
ifndef ADD_HOTPLUG_MAGIC
ADD_HOTPLUG_MAGIC := 0
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else
ifeq (${ADD_HOTPLUG_MAGIC},0)
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else ifeq (${ADD_HOTPLUG_MAGIC},1)
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else
$(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.")
endif
endif
# Process STACK_PROTECT flag
ifndef STACK_PROTECT
STACK_PROTECT := 0
$(eval $(call add_define,STACK_PROTECT))
else
ifeq (${STACK_PROTECT},0)
$(eval $(call add_define,STACK_PROTECT))
else ifeq (${STACK_PROTECT},1)
$(eval $(call add_define,STACK_PROTECT))
CFLAGS += -stack_protector
else
$(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.")
endif
endif
# Process RTOS_LOAD_NUM flag
# 1:RTOS#0 only 3:RTOS#0,#1,#2
ifndef RTOS_LOAD_NUM
RTOS_LOAD_NUM := 1
$(eval $(call add_define,RTOS_LOAD_NUM))
else
ifeq (${RTOS_LOAD_NUM},1)
$(eval $(call add_define,RTOS_LOAD_NUM))
else ifeq (${RTOS_LOAD_NUM},3)
$(eval $(call add_define,RTOS_LOAD_NUM))
else
$(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.")
endif
endif
# Process OPTEE_LOAD_ENABLE flag
ifeq ($(filter ${LSI},V4H V4M),${LSI})
ifndef OPTEE_LOAD_ENABLE
OPTEE_LOAD_ENABLE := 1
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else
ifeq (${OPTEE_LOAD_ENABLE},0)
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else ifeq (${OPTEE_LOAD_ENABLE},1)
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else
$(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
endif
endif
endif
###################################################
# pass SecureMonitor parametor
###################################################
# Process SET_CA_PARAM flag
ifeq (${LSI},S4)
ifndef SET_CA_PARAM
SET_CA_PARAM := 1
$(eval $(call add_define,SET_CA_PARAM))
else
ifeq (${SET_CA_PARAM},0)
$(eval $(call add_define,SET_CA_PARAM))
else ifeq (${SET_CA_PARAM},1)
$(eval $(call add_define,SET_CA_PARAM))
else
$(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.")
endif
endif
endif
# Process ECM_ENABLE
ifndef ECM_ENABLE
ECM_ENABLE:= 0
$(eval $(call add_define,ECM_ENABLE))
else
ifeq (${ECM_ENABLE},0)
$(eval $(call add_define,ECM_ENABLE))
else ifeq (${ECM_ENABLE},1)
$(eval $(call add_define,ECM_ENABLE))
else
$(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.")
endif
endif
# Process ECM_ERROR_ENABLE flag
ifndef ECM_ERROR_ENABLE
ECM_ERROR_ENABLE := 1
$(eval $(call add_define,ECM_ERROR_ENABLE))
else
ifeq (${ECM_ERROR_ENABLE},0)
$(eval $(call add_define,ECM_ERROR_ENABLE))
else ifeq (${ECM_ERROR_ENABLE},1)
$(eval $(call add_define,ECM_ERROR_ENABLE))
else
$(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.")
endif
endif
# Process DBSC HUNGUP WA
ifndef WA_OTLINT5579
WA_OTLINT5579:= 1
endif
$(eval $(call add_define,WA_OTLINT5579))
###################################################
OUTDIR_REL := $(OUTDIR)/release
OUTDIR_OBJ := $(OUTDIR)/obj
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
CC = cxrh850
AS = cxrh850
LD = cxrh850
OC = gsrec
OD = gdump
ASFLAGS += -asm="-preprocess_assembly_files" \
-asm="-nostartfiles" \
-D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -nostartfiles \
-c99 \
$(INCLUDE_DIR) $(DEFINES) \
--ghstd=last \
-Wundef \
--diag_error=193 \
--prototype_errors
# --ghstd=last : Enable Green Hills Standard Mode
# -Wundef : Output warning if there are any undefined symbols
# --diag_error=193 : Error if zero is applied to undefined symbol
# --prototype_errors : Error if there are no any prototype declaration
ifeq (${LOG_LEVEL},0)
# There are no any additional options
else
CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant
endif
LDFLAGS += -nostartfiles -Mu
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c
@$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
@$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
-T $(MEMORY_DEF) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
$(LDFLAGS) \
-map=$(OUTDIR_REL)/$(FILE_NAME).map
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
@$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
@$(LD) $(OBJ_FILE_SA0) \
-T $(MEMORY_DEF_SA0) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin)
$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9)
@$(LD) $(OBJ_FILE_SA9) \
-T $(MEMORY_DEF_SA9) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin)
$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL)
@$(LD) $(OBJ_FILE_TFMV_TBL) \
-T $(MEMORY_DEF_TFMV_TBL) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \
-map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \
-nostdlib
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin)
$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL)
@$(LD) $(OBJ_FILE_NTFMV_TBL) \
-T $(MEMORY_DEF_NTFMV_TBL) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \
-map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \
-nostdlib
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin)
###################################################
# Compile
###################################################
$(OUTDIR_OBJ)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(CC) $(CFLAGS) -o $@ -c $<
$(OUTDIR_OBJ)/%.o:%.S
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(AS) $(ASFLAGS) -o $@ -c $<
.PHONY: clean
clean:
@rm -rf $(OUTDIR)

2468
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c Normal file
View File

File diff suppressed because it is too large Load Diff

4084
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c Normal file
View File

File diff suppressed because it is too large Load Diff

3552
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c Normal file
View File

File diff suppressed because it is too large Load Diff

100
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/log.c Normal file
View File

@@ -0,0 +1,100 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver
******************************************************************************/
/******************************************************************************
* @file log.c
* - Version : 0.03
* @brief Log driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 06.01.2022 0.02 Static analysis support
* : 04,04,2023 0.03 Fixed to not use the standard input/output
* library when LOG_LEVEL=0.
*****************************************************************************/
#include <stdint.h>
#include <log.h>
#include <scif.h>
#if LOG_LEVEL >= LOG_ERROR
#include <stdarg.h>
#define VSPRINTF_OK (0)
void local_printf(const char *fmt, ...)
{
va_list ap;
static char s_buffer[1024];
int32_t num;
uint32_t loop;
/* Convert all arguments to one string */
va_start(ap, fmt);
num = vsprintf(s_buffer, fmt, ap);
va_end(ap);
/* String output */
if (VSPRINTF_OK <= num)
{
for (loop = 0U; loop < num; loop++)
{
(void)console_putc((uint8_t)s_buffer[loop]);
/* If the outputted character is LF, output CR */
if (s_buffer[loop] == 0x0A) /* \n */
{
(void)console_putc((uint8_t)'\r');
}
}
}
else
{
while(1)
{
/* loop due to error detection. */
}
}
}
/* End of function local_printf(const char *fmt, ...) */
#endif
void panic_printf(const char *str)
{
const uint8_t *p = (const uint8_t *)str;
/* Output one character at a time until the data in the argument is null-terminated string. */
while(*p != (uint8_t)'\0')
{
(void)console_putc(*p);
p++;
}
/* output character is CR and LF */
(void)console_putc((uint8_t)'\r');
(void)console_putc((uint8_t)'\n');
}
/* End of function panic_printf(const char *str) */

618
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/scif.c Normal file
View File

@@ -0,0 +1,618 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver
******************************************************************************/
/******************************************************************************
* @file scif.c
* - Version : 0.08
* @brief 1. Initial setting of SCIF.
* 2. Initial setting of HSCIF.
* 3. Log output function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify the timing of MODEMR judgement.
* : 15.10.2021 0.03 Modify register access to read modify write.
* : 03.12.2021 0.04 Fix incorrect configuration process.
* : 06.01.2022 0.05 Static analysis support
* : 23.05.2022 0.06 Integration of S4 and V4H
* : 20.12.2022 0.07 Modify writing bit size to SCBRR register.
* : 21.08.2023 0.08 Add support for V4M.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <cpg.h>
#include <pfc.h>
#include <scif.h>
#include <mem_io.h>
#include <micro_wait.h>
#include <rst_register.h>
/* Define */
#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U)
#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U)
#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN)
#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U)
#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U)
#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U)
#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN)
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCSMR_CHR (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCSMR_PE (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSMR_STOP (uint16_t)((uint16_t)1U << 3U)
#define SCIF_SCSMR_CKS (uint16_t)((uint16_t)3U << 0U)
#define SCIF_SCSMR_INIT_DATA ~((uint16_t)(SCIF_SCSMR_CHR | SCIF_SCSMR_PE | SCIF_SCSMR_STOP | SCIF_SCSMR_CKS))
/* Pclk(66MHz)/1, 115.2kbps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 921.6kbps*/
/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */
#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 1.8432Mbps*/
/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */
#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U)
#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U)
#define HSCIF_HSSRR_SRCYC (uint16_t)(0x1FU << 0U)
#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */
#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8)
#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U)
#define HSCIF_CKS_CKS (uint16_t)(1U << 15U)
#define HSCIF_CKS_XIN (uint16_t)(1U << 14U)
#define HSCIF_CKS_SC_CLK_EXT ~((uint16_t)(HSCIF_CKS_CKS | HSCIF_CKS_XIN))
/* module start setting value */
#if (RCAR_LSI == RCAR_S4)
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 4U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 2U)
#endif /* RCAR_LSI == RCAR_S4 */
/* Pin function setting value */
#if (RCAR_LSI == RCAR_S4)
#define GPSR_TX ((uint32_t)1U << 3U) /* HTX0 / TX3 */
#define GPSR_RX ((uint32_t)1U << 2U) /* HRX0 / RX3 */
#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */
#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */
#define POC_TX_33V ((uint32_t)1U << 3U) /* HTX0 / TX3 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 2U) /* HRX0 / RX3 3.3V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX/TX) */
#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */
#define PFC_IPSR_HSCIF_VAL (uint32_t)(0x00000000U) /* HSCIF0 RX/TX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 0U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 0U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00000001U) /* Mask value of IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_VAL (uint32_t)(1U << 0U) /* IPSR (External Clock) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define GPSR_TX ((uint32_t)1U << 12U) /* HTX0 / TX0 */
#define GPSR_RX ((uint32_t)1U << 16U) /* HRX0 / RX0 */
#define IPSR_RX_VAL ((uint32_t)1U << 0U) /* RX0 */
#define IPSR_TX_VAL ((uint32_t)1U << 16U) /* TX0 */
#define POC_TX_33V ((uint32_t)1U << 12U) /* HTX0 / TX0 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 16U) /* HRX0 / RX0 3.3V setting value */
#define POC_TX_18V ((uint32_t)0U << 12U) /* HTX0 / TX0 1.8V setting value */
#define POC_RX_18V ((uint32_t)0U << 16U) /* HRX0 / RX0 1.8V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 0U) /* IPSR bit[3:0] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 16U) /* IPSR bit[19:16] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK1 (uint32_t)(IPSR_TX_MASK) /* Mask value of IPSR (SCIF0/HSCIF0 TX) */
#define PFC_IPSR_SCIF_VAL1 (uint32_t)(IPSR_TX_VAL) /* SCIF0 TX */
#define PFC_IPSR_SCIF_MASK2 (uint32_t)(IPSR_RX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX) */
#define PFC_IPSR_SCIF_VAL2 (uint32_t)(IPSR_RX_VAL) /* SCIF0 RX */
#define PFC_IPSR_HSCIF_VAL1 (uint32_t)(0x00000000U) /* HSCIF0 TX */
#define PFC_IPSR_HSCIF_VAL2 (uint32_t)(0x00000000U) /* HSCIF0 RX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 4U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 4U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00020000U) /* Mask value of IPSR (External Clock) */
#endif /* RCAR_LSI == RCAR_S4 */
static void (*rcar_putc)(uint8_t outchar);
static void scif_module_start(uint32_t modemr);
static void scif_pfc_init(uint32_t modemr);
static void scif_console_init(uint32_t modemr);
static void scif_console_putc(uint8_t outchar);
static void hscif_console_putc(uint8_t outchar);
static void scif_module_start(uint32_t modemr)
{
uint32_t reg;
if(modemr == MODEMR_SCIF_DLMODE)
{
reg = mem_read32(CPG_MSTPSR7D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_SCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_SCIF);
cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg);
}
}
else
{
reg = mem_read32(CPG_MSTPSR5D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_HSCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_HSCIF);
cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg);
}
}
}
/* End of function scif_module_start(void) */
static void scif_pfc_init(uint32_t modemr)
{
uint32_t reg;
#if (RCAR_LSI == RCAR_S4)
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set RX / TX of SCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_SCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR0_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR0_RW, reg);
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set TX of SCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_SCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set RX of SCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_SCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP2SR1_RW, reg);
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR1_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR1_RW, reg);
#endif /* RCAR_LSI == RCAR_S4 */
}
/* End of function scif_pfc_init(void) */
static void scif_console_init(uint32_t modemr)
{
uint16_t reg;
switch(modemr)
{
case MODEMR_HSCIF_DLMODE_3000000:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* external clock, SC_CLK pin used for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* 24MHz / (3000000 * 8) = 1 */
mem_write16(HSCIF_DL, HSCIF_DL_DIV1);
reg = mem_read16(HSCIF_CKS);
reg &= HSCIF_CKS_SC_CLK_EXT;
mem_write16(HSCIF_CKS, reg);
/* Sampling rate 8 */
reg = mem_read16(HSCIF_HSSRR);
reg &= ~(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC);
reg |= HSCIF_HSSRR_VAL;
mem_write16(HSCIF_HSSRR, reg);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_1843200:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 1843200bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_921600:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 921600bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_SCIF_DLMODE:
default:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(SCIF_SCFCR, reg);
/* clear ORER bit */
mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(SCIF_SCSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(SCIF_SCSMR, reg);
/* Baud rate 115200bps*/
mem_write8(SCIF_SCBRR, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(SCIF_SCFCR, reg);
/* enable TE, RE; SC_CLK=no output */
reg = mem_read16(SCIF_SCSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(SCIF_SCSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = scif_console_putc;
break;
}
}
}
/* End of function scif_console_init(void) */
void scif_init(void)
{
uint32_t modemr;
modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U);
modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
scif_module_start(modemr);
scif_pfc_init(modemr);
scif_console_init(modemr);
}
/* End of function scif_init(void) */
void console_putc(uint8_t outchar)
{
rcar_putc(outchar);
}
/* End of function console_putc(void) */
static void scif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function scif_console_putc(uint8_t outchar) */
static void hscif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */
reg = mem_read16(HSCIF_HSFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(HSCIF_HSFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function hscif_console_putc(uint8_t outchar) */

109
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/timer/micro_wait.c Normal file
View File

@@ -0,0 +1,109 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver
******************************************************************************/
/******************************************************************************
* @file micro_wait.c
* - Version : 0.03
* @brief Wait of micro second
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 15.10.2021 0.02 modify register access to read modify write.
* : 03.12.2021 0.03 fix incorrect configuration process.
*****************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
#include <mem_io.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (0xFFFEEA14U)
#define INTCR_RF ((uint16_t)1U << 12U)
#define INTCR_RF_NO_REQ ((uint16_t)0U << 12U)
#define OSTM0_BASE (0xFFFEE000U)
#define OSTM0CMP (OSTM0_BASE)
#define OSTM0TS (OSTM0_BASE + 0x0014U)
#define OSTM0TT (OSTM0_BASE + 0x0018U)
#define OSTM0CTL (OSTM0_BASE + 0x0020U)
#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */
#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */
#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */
void micro_wait(uint32_t count_us)
{
uint32_t val;
uint16_t reg16;
uint8_t reg8;
if (count_us != 0U)
{
/* When the timer count is an argument that exceeds 0xFFFFFFFF */
if(MAX_MICRO_WAIT < count_us)
{
count_us = MAX_MICRO_WAIT;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
/* timer start */
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
mem_write32(OSTM0CMP, val);
reg8 = mem_read8(OSTM0CTL);
reg8 |= OSTM0CTL_MD10;
mem_write8(OSTM0CTL, reg8);
reg8 = mem_read8(OSTM0TS);
reg8 |= OSTM0TS_TS;
mem_write8(OSTM0TS, reg8);
while (1)
{
reg16 = mem_read16(INTICUOSTM0);
if ((reg16 & (INTCR_RF)) != INTCR_RF_NO_REQ)
{
/* timer stop */
reg16 = (reg16 & (uint16_t)(~(INTCR_RF)));
mem_write16(INTICUOSTM0, reg16);
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
break;
}
}
}
}
/* End of function micro_wait(uint32_t count_us) */

237
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cpu_on/cpu_on.c Normal file
View File

@@ -0,0 +1,237 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Power management driver
******************************************************************************/
/******************************************************************************
* @file cpu_on.c
* - Version : 0.09
* @brief Boot process of ARM CPU core.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* : 08.09.2021 0.03 Removed the reset process of BOOT_CTRL and
* OPBT_CTRL register.
* : 06.01.2022 0.04 Static analysis support
* : 23.05.2022 0.05 Integration of S4 and V4H
* : 21.06.2022 0.06 Remove functions for MCU.
* : 21.08.2023 0.07 Add support for V4M.
* : 17.11.2023 0.08 Move a part of definitions to cpu_on.h.
* : 09.12.2024 0.09 Update OTP_MEM_OTPMONITOR60 register to
* OTP_MEM_OTPMONITOR17 register for V4M.
* And Improve the adj_cr_variant_freq function.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <mem_io.h>
#include <cpu_on.h>
#include <cpg.h>
#include <cpg_register.h>
#include <ap_system_core_register.h>
#include <inline_asm.h>
/* ARM */
#define CA_CORE0_WUP_REQ (0x00000001U)
#define CA_CORE0_VLD_RVBARP (0x00000001U)
#define CR_VLD_BARP (0x00000001U << 0U)
#define CR_BAREN_VALID (0x00000001U << 4U)
#define CRRST_BIT (0x00000001U)
#if (RCAR_LSI == RCAR_V4H)
#define V4H_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4H_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4H_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
#elif (RCAR_LSI == RCAR_V4M)
#define V4M_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4M_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4M_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
#define V4M_2_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
# endif /* RCAR_LSI == RCAR_V4H */
#define CPG_PLL6CR0_KICK_BIT (0x80000000U)
#define CPG_PLLECR_PLL6ST_BIT (0x00008000U)
#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U)
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
{
if(RCAR_PWR_TARGET_CR == target)
{
/* CR Boot address set */
mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP));
mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
}
else if(RCAR_PWR_TARGET_CA == target)
{
/* CA Boot address set */
mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
mem_write32(APMU_RVBARPHC0, 0x00000000U);
}
else
{
/* No Process */
}
}
/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
void arm_cpu_on(uint32_t target, uint32_t boot_addr)
{
uint32_t res_data;
if(RCAR_PWR_TARGET_CR == target)
{
/* CR Boot address set. */
arm_cpu_set_address(target, boot_addr);
synci();
/* CR reset. */
res_data = mem_read32(APMU_CRRSTCTRL);
res_data &= ~(CRRST_BIT);
mem_write32(APMU_CRRSTCTRL, res_data);
}
else if(RCAR_PWR_TARGET_CA == target)
{
/* CA Boot address set. */
arm_cpu_set_address(target, boot_addr);
/* AP-System core initialize */
res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U));
res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data);
res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
#if (RCAR_LSI == RCAR_V4H)
res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
#endif /* RCAR_LSI == RCAR_V4H */
synci();
/* CA core0 wake up sequence. */
res_data = mem_read32(APMU_PWRCTRLC0);
res_data |= CA_CORE0_WUP_REQ;
mem_write32(APMU_PWRCTRLC0, res_data);
/* Wait until CA core0 wake up sequence finished. */
do
{
res_data = mem_read32(APMU_PWRCTRLC0);
}while(FALSE != (CA_CORE0_WUP_REQ & res_data));
}
else
{
/* No Process */
}
}
/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
void adj_cr_variant_freq(void)
{
uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
uint32_t pll6_freq = mem_read32(CPG_PLL6CR0);
#if (RCAR_LSI == RCAR_V4H)
/* Set the CPU frequency division ratio according to the type of variant. */
switch (product)
{
case VARIANT_V4H_7:
/* Default value, do nothing */;
break;
case VARIANT_V4H_5:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U));
break;
case VARIANT_V4H_3:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U));
break;
default:
; /* Do nothing */
break;
}
if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
{
/* Write Division value to FRQCRC0 register */
mem_write32(CPG_CPGWPR, ~(pll6_freq));
mem_write32(CPG_PLL6CR0, pll6_freq);
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
{
;
}
}
#elif (RCAR_LSI == RCAR_V4M)
/* Set the CPU frequency division ratio according to the type of variant. */
switch (product)
{
case VARIANT_V4M_7:
/* Default value, do nothing */;
break;
case VARIANT_V4M_5:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U));
break;
case VARIANT_V4M_3:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U));
break;
case VARIANT_V4M_2:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U));
break;
default:
; /* Do nothing */
break;
}
if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
{
/* Write Division value to FRQCRC0 register */
mem_write32(CPG_CPGWPR, ~(pll6_freq));
mem_write32(CPG_PLL6CR0, pll6_freq);
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
{
;
}
}
#endif /* RCAR_LSI == RCAR_V4H */
}
/* End of function adj_cpu_variant_freq(void) */

525
IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load.c Normal file
View File

@@ -0,0 +1,525 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file image_load.c
* - Version : 0.14
* @brief Loading image driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* : 30.09.2021 0.03 Support of eMMC boot.
* : 15.10.2021 0.04 Fix a problem with overwriting the load area
* information in RTOS.
* modify Error log of check_load_area.
* Modify the process of outputting load
* information of Optionbyte to function.
* : 03.12.2021 0.05 Modify function "check_load_area" to check the
* boundary value of RT-VRAM(for virtual buffer).
* Fixed judgment of the top/end of the
* forwarding destination.
* : 06.01.2022 0.06 Support for two-stage boot of G4MH.
* : 23.05.2022 0.07 Support for updating the memory map.
* : 21.06.2022 0.08 Modify some function's arguments and add
* macros.
* : 05.08.2022 0.09 Add TFMV/NTFMV minimum version table
* information to load_init function.
* : 22.09.2022 0.10 Fix address range check for V4H.
* : 21.08.2023 0.11 Add support for V4M.
* : 15.01.2024 0.12 Add image_id initialization to load_init
* function.
* : 19.12.2024 0.13 Add RTOS#1, RTOS#2 image.
* : 26.05.2025 0.14 Change key cert address of [CA_OPTIONAL_ID+2].
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <image_load.h>
#include <remap.h>
#include <mem_io.h>
#include <log.h>
#include <rom_api.h>
#include <ram_def.h>
#if (RCAR_SA9_TYPE == FLASH_BOOT)
#include <image_load_flash.h>
#include <dma.h>
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
#include <image_load_emmc.h>
#include <emmc_multiboot.h>
#include <emmc_def.h>
#endif
#define KEY_SIZE_FLG_MSK (0x00000003U)
#define KEY_SIZE_4096 (0x00000002U)
#define KEY_SIZE_3072 (0x00000001U)
#define KEY_SIZE_2048 (0x00000000U)
#define WORD_TO_BYTE (4U)
#define ERROR_PARAM (0U)
#define NOT_OVERLAP_FLAG (0U)
#define OVERLAP_FLAG (1U)
#define RAM_RANGE_OK (0U)
#define RAM_RANGE_NG (1U)
#if (BOOT_MCU != 0U)
#define RAM_MAX (5U)
#else
#define RAM_MAX (4U)
#endif /* (BOOT_MCU != 0U) */
/* Load Parameter of Secure data */
#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB (SRC_TOP + 0x00340000U)
#define DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB (0xEB2E0000U)
#if (BOOT_MCU != 0U)
#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH (SRC_TOP + 0x00440000U)
/* The destination address of Flash to RAM in the ICUMH Secure data is the top address of RT-VRAM. */
#endif
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uint32_t *dest_addr);
static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end);
static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end);
static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end);
uint32_t load_content_cert(void)
{
uint32_t load_num;
#if (RCAR_SA9_TYPE == FLASH_BOOT)
load_num = load_content_cert_for_flash();
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
load_num = load_content_cert_for_emmc();
#else
/* NoProcess */
#endif
return load_num;
}
/* End of function load_content_cert(void) */
void load_image(LOAD_INFO* li)
{
/* log output of load image for information */
#if (RCAR_SA9_TYPE == FLASH_BOOT)
load_image_info_print_for_flash(li);
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
load_image_info_print_for_emmc(li);
#endif
/* Check transfer range of image. */
check_load_area(li);
/* Image load start. */
load_start(li);
}
/* End of function load_image(LOAD_INFO* li) */
void load_init(LOAD_INFO* li)
{
uint32_t loop;
uint32_t buf;
const char *image_name[MAX_PLACED] = {
[SECURE_FW_ID] = "Secure FW",
[RTOS_ID] = "RTOS",
[CA_PROGRAM_ID] = "Cx IPL",
[ICUMH_PROGRAM_ID] = "ICUMH",
[G4MH_PROGRAM_ID] = "G4MH(1st)",
[G4MH_PROGRAM_ID + 1] = "G4MH(2nd)",
[CA_OPTIONAL_ID] = "CA Program #1",
[CA_OPTIONAL_ID + 1] = "CA Program #2",
[CA_OPTIONAL_ID + 2] = "CA Program #3",
[CA_OPTIONAL_ID + 3] = "CA Program #4",
[CA_OPTIONAL_ID + 4] = "CA Program #5",
[CA_OPTIONAL_ID + 5] = "CA Program #6",
[CA_OPTIONAL_ID + 6] = "CA Program #7",
[CA_OPTIONAL_ID + 7] = "CA Program #8",
[TFMV_MIN_VER_TBL_ID] = "TFMV minimum version table",
[NTFMV_MIN_VER_TBL_ID] = "NTFMV minimum version table",
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
[RTOS1_ID] = "RTOS#1",
[RTOS2_ID] = "RTOS#2"
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
};
const uint32_t key_cert[MAX_PLACED] = {
[SECURE_FW_ID] = TFMV_KEY_CERT_ADDR,
[RTOS_ID] = TFMV_KEY_CERT_ADDR,
[CA_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[ICUMH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[G4MH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[G4MH_PROGRAM_ID + 1] = TFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR,
#if (RCAR_LSI == RCAR_S4)
[CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR,
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
[CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR,
#endif
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
[CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR,
#else
[CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR,
#endif
[CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR,
[TFMV_MIN_VER_TBL_ID] = TFMV_KEY_CERT_ADDR,
[NTFMV_MIN_VER_TBL_ID] = NTFMV_KEY_CERT_ADDR,
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
[RTOS1_ID] = TFMV_KEY_CERT_ADDR,
[RTOS2_ID] = TFMV_KEY_CERT_ADDR
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
};
/* Set Load info parameter */
for (loop = 0; loop < MAX_PLACED; loop++)
{
li[loop].name = image_name[loop];
li[loop].key_cert_addr = key_cert[loop];
li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
buf = get_src_addr_offset_in_cert(loop);
li[loop].src_addr = (SRC_TOP + mem_read32(buf));
li[loop].image_id = loop;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
buf = get_part_num_in_cert(loop);
li[loop].part_num = mem_read32(buf);
#endif
}
}/* End of function load_init(LOAD_INFO* li) */
void check_load_area(const LOAD_INFO* li)
{
uint32_t src;
uint32_t dst;
uint32_t len;
uint32_t src_end;
uint32_t dst_end;
src = li->src_addr;
dst = li->boot_addr;
len = li->image_size;
/* Check whether source is overflow. */
check_overflow(src, len, &src_end, __func__);
/* Check whether destination is overflow. */
check_overflow(dst, len, &dst_end, __func__);
/* Check source address range. */
check_src_addr_range(src, len, src_end);
/* Check destination address range. */
check_dst_addr_range(dst, len, dst_end);
/* Check whether overlap destination address and images that have been loaded. */
check_overlap_images(dst, len, dst_end);
}
/* End of function check_load_area(const LOAD_INFO* li) */
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uint32_t *dest_addr)
{
uint32_t val;
uint32_t certInfo1;
uint32_t pSize;
uint32_t pDestL;
/* Get key length of content certificate. */
val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET);
certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK;
/* Get the transfer address and transfer size from
the certificate in accordance with the key length. */
if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET2;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET2;
*dest_addr = mem_read32(pDestL);
}
else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET1;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET1;
*dest_addr = mem_read32(pDestL);
}
else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET;
*dest_addr = mem_read32(pDestL);
}
else
{
*size = ERROR_PARAM;
*dest_addr = ERROR_PARAM;
}
}
/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */
void load_start(const LOAD_INFO* li)
{
#if (RCAR_SA9_TYPE == FLASH_BOOT)
dma_trans_start(li->boot_addr, li->src_addr, li->image_size);
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
uint32_t rtn_val;
uint32_t sector_count;
uint32_t fraction;
/* Converted to number of sectors transferred. */
sector_count = li->image_size >> EMMC_SECTOR_SIZE_SHIFT;
fraction = li->image_size % EMMC_SECTOR_SIZE;
/* Add 1 if there is a fraction */
if(0U != fraction)
{
sector_count += 1U;
}
rtn_val = emmc_trans_data(li->part_num, (li->src_addr >> EMMC_SECTOR_SIZE_SHIFT),
li->boot_addr, sector_count);
if(EMMC_DEV_OK != rtn_val)
{
ERROR("load_start(emmc_trans_data error).\r\n");
panic;
}
#else
/* NoProcess */
#endif
}/* End of function load_start(LOAD_INFO* li) */
void load_end(void)
{
#if (RCAR_SA9_TYPE == FLASH_BOOT)
dma_trans_end_check();
#else
/* NoProcess */
#endif
}/* End of function load_end(void) */
void load_securedata(uint32_t target_id)
{
LOAD_INFO tmp_li;
if(target_id == SECURE_FW_ID) /* When secure data transfer for ICUMXB FW. */
{
tmp_li.image_size = SECUREDATA_SIZE;
tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB;
tmp_li.boot_addr =DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
tmp_li.part_num = EMMC_PARTITION_1;
#endif
}
#if (BOOT_MCU != 0U)
else if(target_id == ICUMH_PROGRAM_ID) /* When secure data transfer for ICUMH FW. */
{
tmp_li.image_size = SECUREDATA_SIZE;
tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH;
tmp_li.boot_addr = RTVRAM_BASE;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
tmp_li.part_num = EMMC_PARTITION_1;
#endif
}
#endif
else
{
ERROR("Failed input parameter.\n");
panic;
}
load_start(&tmp_li);
}/* End of function load_securedata(uint32_t target_id) */
void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name)
{
/* Pre confirmation */
if (addr > (UINT32_MAX - len))
{
ERROR("1:overflow is occurred in %s.\n", func_name);
ERROR("1:address = 0x%x size = 0x%x\n", addr, len);
panic;
}
else
{
*end_addr = addr + len - 1U;
}
/* Post confirmation */
if (*end_addr < addr)
{
ERROR("2:overflow is occurred in %s.\n", func_name);
ERROR("2:address = 0x%x size = 0x%x\n", addr, len);
panic;
}
}
/* End of function check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, char *func_name) */
static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end)
{
/* Check image size */
if (len == 0U)
{
ERROR("image size error\n");
panic;
}
#if (RCAR_SA9_TYPE == FLASH_BOOT)
if ((src < SRC_TOP) || (SRC_END < src_end))
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
if (SRC_END < src_end)
#endif
{
ERROR("check load area (source address)\n");
ERROR("source address = 0x%x image size = 0x%x\n", src, len);
panic;
}
}
/* End of function check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) */
static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end)
{
uint32_t rge_chk_flg;
uint32_t loop;
/* The memory range of destination. */
const ADDRESS_RANGE add_list[RAM_MAX] = {
[TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END},
[TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END},
[TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END},
[TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END},
#if (BOOT_MCU != 0U)
[TARGET_MEM_CODESRAM] = {CODESRAM_BASE, CODESRAM_END}
#endif /* (BOOT_MCU != 0U) */
};
/* Check image size */
if (len == 0U)
{
ERROR("image size error\n");
panic;
}
rge_chk_flg = RAM_RANGE_NG;
for(loop = 0; loop < RAM_MAX; loop++)
{
if (add_list[loop].topadd <= dst)
{
if(dst_end <= add_list[loop].endadd)
{
rge_chk_flg = RAM_RANGE_OK;
break;
}
}
}
if(rge_chk_flg != RAM_RANGE_OK)
{
ERROR("check load area (destination address)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst, len);
panic;
}
}
/* End of function check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) */
static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end)
{
uint32_t overlap;
uint32_t loop;
static uint32_t s_num = 1U;
static ADDRESS_RANGE s_placed_image[MAX_PLACED + 1] = {
[0] = {IPL_TOP, IPL_END},
[1] = {0U,0U},
[2] = {0U,0U},
[3] = {0U,0U},
[4] = {0U,0U},
[5] = {0U,0U},
[6] = {0U,0U},
[7] = {0U,0U},
[8] = {0U,0U},
[9] = {0U,0U},
[10] = {0U,0U},
[11] = {0U,0U},
[12] = {0U,0U},
[13] = {0U,0U},
[14] = {0U,0U},
[15] = {0U,0U},
[16] = {0U,0U}
};
overlap = NOT_OVERLAP_FLAG;
loop = 0U;
do
{
/* check overlap */
if ((dst >= s_placed_image[loop].topadd) && (dst <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst_end >= s_placed_image[loop].topadd) && (dst_end <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst < s_placed_image[loop].topadd) && (s_placed_image[loop].endadd < dst_end))
{
overlap = OVERLAP_FLAG;
}
else
{
loop++;
}
} while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG));
/* Check the overlap flag. *
* Parameters are error if overwrite occurred. *
* Otherwise, add parameters of the image to be loaded into Placed_image. */
if (overlap == NOT_OVERLAP_FLAG)
{
s_placed_image[s_num].topadd = dst;
s_placed_image[s_num].endadd = dst_end;
INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num,
s_placed_image[s_num].topadd, s_placed_image[s_num].endadd);
s_num++;
}
else
{
ERROR("check load area (overlap)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst, len);
ERROR("overlapped image is [%x]\n", loop);
ERROR("top address = 0x%x end address = 0x%x\n",
s_placed_image[loop].topadd, s_placed_image[loop].endadd);
panic;
}
}
/* End of function check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) */

Some files were not shown because too many files have changed in this diff Show More