92 lines
4.7 KiB
C
92 lines
4.7 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* - Neither the name of Renesas nor the names of its contributors may be
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* used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SCIF_H__
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#define __SCIF_H__
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//SCIF0
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#define SCIF_BASE_0 (0xE6E60000U)
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#define SCIF_SCSMR_0 (SCIF_BASE_0 + 0x0000) // R/W 16 Serial mode register
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#define SCIF_SCBRR_0 (SCIF_BASE_0 + 0x0004) // R/W 8 Bit rate register
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#define SCIF_SCSCR_0 (SCIF_BASE_0 + 0x0008) // R/W 16 Serial control register
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#define SCIF_SCFTDR_0 (SCIF_BASE_0 + 0x000C) // W 8 Transmit FIFO data register
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#define SCIF_SCFSR_0 (SCIF_BASE_0 + 0x0010) // R/W 16 Serial status register
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#define SCIF_SCFRDR_0 (SCIF_BASE_0 + 0x0014) // R 8 Receive FIFO data register
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#define SCIF_SCFCR_0 (SCIF_BASE_0 + 0x0018) // R/W 16 FIFO control register
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#define SCIF_SCFDR_0 (SCIF_BASE_0 + 0x001C) // R 16 FIFO data count register
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#define SCIF_SCSPTR_0 (SCIF_BASE_0 + 0x0020) // R/W 16 Serial port register
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#define SCIF_SCLSR_0 (SCIF_BASE_0 + 0x0024) // R/W 16 Line status register
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#define SCIF_DL_0 (SCIF_BASE_0 + 0x0030) // R/W 16 Frequency division register
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#define SCIF_CKS_0 (SCIF_BASE_0 + 0x0034) // R/W 16 Clock Select register
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//SCIF3
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#define SCIF_BASE_3 (0xE6C50000U)
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#define SCIF_SCSMR_3 (SCIF_BASE_3 + 0x0000) // R/W 16 Serial mode register
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#define SCIF_SCBRR_3 (SCIF_BASE_3 + 0x0004) // R/W 8 Bit rate register
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#define SCIF_SCSCR_3 (SCIF_BASE_3 + 0x0008) // R/W 16 Serial control register
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#define SCIF_SCFTDR_3 (SCIF_BASE_3 + 0x000C) // W 8 Transmit FIFO data register
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#define SCIF_SCFSR_3 (SCIF_BASE_3 + 0x0010) // R/W 16 Serial status register
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#define SCIF_SCFRDR_3 (SCIF_BASE_3 + 0x0014) // R 8 Receive FIFO data register
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#define SCIF_SCFCR_3 (SCIF_BASE_3 + 0x0018) // R/W 16 FIFO control register
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#define SCIF_SCFDR_3 (SCIF_BASE_3 + 0x001C) // R 16 FIFO data count register
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#define SCIF_SCSPTR_3 (SCIF_BASE_3 + 0x0020) // R/W 16 Serial port register
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#define SCIF_SCLSR_3 (SCIF_BASE_3 + 0x0024) // R/W 16 Line status register
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#define SCIF_DL_3 (SCIF_BASE_3 + 0x0030) // R/W 16 Frequency division register
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#define SCIF_CKS_3 (SCIF_BASE_3 + 0x0034) // R/W 16 Clock Select register
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/* HSCIF0 */
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#define HSCIF_BASE (0xE6540000U)
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#define HSCIF_HSSMR (HSCIF_BASE + 0x0000U) // R/W 16 Serial mode register
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#define HSCIF_HSBRR (HSCIF_BASE + 0x0004U) // R/W 8 Bit rate register
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#define HSCIF_HSSCR (HSCIF_BASE + 0x0008U) // R/W 16 Serial control register
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#define HSCIF_HSFTDR (HSCIF_BASE + 0x000CU) // W 8 Transmit FIFO data register
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#define HSCIF_HSFSR (HSCIF_BASE + 0x0010U) // R/W 16 Serial status register
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#define HSCIF_HSFRDR (HSCIF_BASE + 0x0014U) // R 8 Receive FIFO data register
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#define HSCIF_HSFCR (HSCIF_BASE + 0x0018U) // R/W 16 FIFO control register
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#define HSCIF_HSFDR (HSCIF_BASE + 0x001CU) // R 16 FIFO data count register
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#define HSCIF_HSSPTR (HSCIF_BASE + 0x0020U) // R/W 16 Serial port register
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#define HSCIF_HSLSR (HSCIF_BASE + 0x0024U) // R/W 16 Line status register
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#define HSCIF_HSSRR (HSCIF_BASE + 0x0040U) // R/W 16 Sampling rate register
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/* BRG */
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#define HSCIF_DL (HSCIF_BASE + 0x0030U) // R/W 16 Frequency division register
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#define HSCIF_CKS (HSCIF_BASE + 0x0034U) // R/W 16 Clock select register
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#define CR_CODE (0x0DU)
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#define LF_CODE (0x0AU)
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void scif_init(void);
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void PutStr(const char *str,char rtn);
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void PutChar(char outChar);
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#endif /* __SCIF_H__ */
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