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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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55
IPL/Customer/Mobis/V4H_Cx_Loader/loader/asm_macros.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : macro
******************************************************************************/
/******************************************************************************
* @file asm_macros.S
* - Version : 0.03
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 07.02.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
* : 17.02.2023 0.03 Modified instruction to lower case.
*****************************************************************************/
#ifndef ASM_MACROS_S
#define ASM_MACROS_S
.macro mov_imm _reg, _val
.if (\_val) > 65535
mov \_reg, (\_val >> 0) & 0xffff
movk \_reg, (\_val >> 16) & 0xffff, lsl #16
movk \_reg, (\_val >> 32) & 0xffff, lsl #32
movk \_reg, (\_val >> 48) & 0xffff, lsl #48
.else
mov \_reg, (\_val)
.endif
.endm
#endif /* ASM_MACROS_S */

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IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_exceptions.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file loader_exceptions.S
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.08.2022 0.01 First Release
* : 31.10.2022 0.02 License notation change.
*****************************************************************************/
#define SYNC_SP_EL0 (0x0U)
#define IRQ_SP_EL0 (0x1U)
#define FIQ_SP_EL0 (0x2U)
#define SERROR_SP_EL0 (0x3U)
#define SYNC_SP_ELX (0x4U)
#define IRQ_SP_ELX (0x5U)
#define FIQ_SP_ELX (0x6U)
#define SERROR_SP_ELX (0x7U)
#define SYNC_AARCH64 (0x8U)
#define IRQ_AARCH64 (0x9U)
#define FIQ_AARCH64 (0xAU)
#define SERROR_AARCH64 (0xBU)
#define SYNC_AARCH32 (0xCU)
#define IRQ_AARCH32 (0xDU)
#define FIQ_AARCH32 (0xEU)
#define SERROR_AARCH32 (0xFU)
.global loader_exceptions
.global SyncSP0
.global IrqSP0
.global FiqSP0
.global SErrorSP0
.global SyncSPx
.global IrqSPx
.global FiqSPx
.global SErrorSPx
.global SyncA64
.global IrqA64
.global FiqA64
.global SErrorA64
.global SyncA32
.global IrqA32
.global FiqA32
.global SErrorA32
/* Pre macro for a vector */
.macro bigin_vector label, section_name=.vectors
.cfi_sections .debug_frame
.section \section_name, "ax"
.align 7, 0
.type \label, %function
.cfi_startproc
\label:
.endm
/* Post macro for a vector */
.macro end_vector label
.cfi_endproc
.fill \label + (32 * 4) - .
.endm
/*****************************************************************************/
/* Exception Vector Table */
/*****************************************************************************/
.section .vectors, "ax"
.align 11, 0
loader_exceptions:
/***********************/
/* Current EL with SP0 */
/***********************/
bigin_vector SyncSP0
mov x0, #SYNC_SP_EL0
msr spsel, #0
bl handler_error
end_vector SyncSP0
bigin_vector IrqSP0
mov x0, #IRQ_SP_EL0
msr spsel, #0
bl handler_error
end_vector IrqSP0
bigin_vector FiqSP0
mov x0, #FIQ_SP_EL0
msr spsel, #0
b handler_fiq
end_vector FiqSP0
bigin_vector SErrorSP0
mov x0, #SERROR_SP_EL0
msr spsel, #0
bl handler_error
end_vector SErrorSP0
/***********************/
/* Current EL with SPx */
/***********************/
bigin_vector SyncSPx
mov x0, #SYNC_SP_ELX
msr spsel, #0
bl handler_error
end_vector SyncSPx
bigin_vector IrqSPx
mov x0, #IRQ_SP_ELX
msr spsel, #0
bl handler_error
end_vector IrqSPx
bigin_vector FiqSPx
mov x0, #FIQ_SP_ELX
msr spsel, #0
bl handler_error
end_vector FiqSPx
bigin_vector SErrorSPx
mov x0, #SERROR_SP_ELX
msr spsel, #0
bl handler_error
end_vector SErrorSPx
/**************************/
/* Lower EL using AArch64 */
/**************************/
bigin_vector SyncA64
mov x0, #SYNC_AARCH64
msr spsel, #0
bl handler_error
end_vector SyncA64
bigin_vector IrqA64
mov x0, #IRQ_AARCH64
msr spsel, #0
bl handler_error
end_vector IrqA64
bigin_vector FiqA64
mov x0, #FIQ_AARCH64
msr spsel, #0
bl handler_error
end_vector FiqA64
bigin_vector SErrorA64
mov x0, #SERROR_AARCH64
msr spsel, #0
bl handler_error
end_vector SErrorA64
/**************************/
/* Lower EL using AArch32 */
/**************************/
bigin_vector SyncA32
mov x0, #SYNC_AARCH32
msr spsel, #0
bl handler_error
end_vector SyncA32
bigin_vector IrqA32
mov x0, #IRQ_AARCH32
msr spsel, #0
bl handler_error
end_vector IrqA32
bigin_vector FiqA32
mov x0, #FIQ_AARCH32
msr spsel, #0
bl handler_error
end_vector FiqA32
bigin_vector SErrorA32
mov x0, #SERROR_AARCH32
msr spsel, #0
bl handler_error
end_vector SErrorA32

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IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main function
******************************************************************************/
/******************************************************************************
* @file loader_main.c
* - Version : 0.17
* @brief 1. IP initialization.
* 2. Transfer image.
* 3. Release of used resources.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 30.11.2021 0.01 First Release
* : 14.02.2022 0.02 Changed log output
* Added device version log output
* Removed Include in micro_wait.h
* Removed the parameter setting process to BL31
* Removed LCS judgement
* Memory map change
* : 17.02.2022 0.03 Support AArch32
* : 22.03.2022 0.04 Support for GSCE[5.4a, 5.4b],[10.3b]
* Support for coverity
* cid:3430806, 3307617, 3430797
* Changed comment
* : 10.05.2022 0.05 Integrated processing
* Changed to processing for each device
* Change log output
* Add argument of load_init()
* : 16.06.2022 0.06 Change log output
* Support secure boot for S4
* : 31.10.2022 0.07 License notation change.
* : 07.11.2022 0.08 Added the parameter setting process to BL31
* Added DDR initialization/QOS initialization
* : 07.12.2022 0.09 Warning support when log output is disabled
* : 15.12.2022 0.10 Support RegionID check
* : 04.04.2023 0.11 Removed stdio.h.
* : 21.08.2023 0.12 Add support for V4M.
* : 23.01.2024 0.13 Add calling of ram_protection_check function.
* Move calling of final_hash_cmp function.
* : 10.09.2024 0.14 Updated Region ID and RAM protection setting
* for QNX.
* : 11.10.2024 0.15 Updated Region ID and RAM protection setting
* for QNX for V4M.
* : 19.12.2024 0.16 Add loading RTOS#1 and RTOS#2 process.
* Add calling ecm_error_enable() function.
* : 26.05.2025 0.17 Add argument of OP-TEE boot address to
* smoni_set_param function.
*****************************************************************************/
#include <stdint.h>
#include <loader_main.h>
#include <rst_register.h>
#include <image_load.h>
#include <ip_control.h>
#include <rcar_def.h>
#include <mem_io.h>
#include <log.h>
#include <string.h>
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#include "cpu_on.h"
#include "qos.h"
#include "rtvram.h"
#include "loader_main_common.h"
#include "../ip/ddr/boot_init_dram.h"
#include "access_protection.h"
#if (ECC_ENABLE == 1)
#if (RCAR_LSI == RCAR_V4H)
#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h"
#elif (RCAR_LSI == RCAR_V4M)
#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h"
#endif /* RCAR_LSI == RCAR_V4H */
#endif /* ECC_ENABLE == 1 */
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
#if (BOOT_MODE == SECURE)
#include "secure_boot.h"
#endif /* BOOT_MODE == SECURE */
/* Time analysis */
#if (1 == (MEASURE_TIME))
#include <scmt.h>
#include <scmt_checkpoint.h>
#else
#define scmt_wait_ticks(x)
#define store_time_checkpoint(x,y)
#define print_time_checkpoints(x)
#endif
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
#include "axmm_register.h"
#include "ram_protection.h"
#endif
#if (ECM_ERROR_ENABLE == 1)
#if (RCAR_LSI == RCAR_V4H)
#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h"
#elif (RCAR_LSI == RCAR_V4M)
#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h"
#endif /* RCAR_LSI == RCAR_V4H */
#endif /* ECM_ERROR_ENABLE == 1 */
#include <android_ab.h>
#include <emmc_def.h>
#include <emmc_boot.h>
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
#define AXMM_DPTSECCR_NUM (SDRAM_PROTECT_AREA) /* set 0 to 15 */
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
#define AXMM_DPTSECCR_NUM2 (SDRAM_PROTECT_AREA2) /* set 0 to 15 */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U)
#define AXMM_DPTSECCR_SECGRP_SEC (0x00000400U)
#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU)
#define AXMM_DPTSECCR_SECGWP_SEC (0x00000004U)
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define DPTRGNCR_PROTECT_AREA (3U)
#define DPTRGNCR_LINUX_AREA (6U)
#else
#define DPTRGNCR_PROTECT_AREA (4U)
#define DPTRGNCR_LINUX_AREA (9U)
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#define SECCTRWD_AREA0 (0U)
#define SECCTRWD_AREA2 (2U)
#define AXMM_DPTRGNCR_RGN0RP_MASK (0x00010000U)
#define AXMM_DPTRGNCR_RGN0RP (0x00010000U)
#define AXMM_DPTRGNCR_RGN0WP_MASK (0x00000001U)
#define AXMM_DPTRGNCR_RGN0WP (0x00000001U)
#define SECCTRWD_SAFG15WP_MASK (0x00000005U)
#define SECCTRWD_SAFG15WP (0x00000005U)
static void remove_rgid0_previlege(void);
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
static void sdram_protection(uint32_t num);
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
uint32_t loader_main(void)
{
uint32_t ca_load_num; /* number of load for CA program */
uint32_t loop;
uint32_t reg; /* store register value */
#ifdef MOBIS_PRK3
int slot = 0;
#endif
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
int32_t result; /* store result of ddr_init() */
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
__attribute__((unused))const char *str;
#if (RCAR_LSI == RCAR_S4)
const char *product_s4 = "S4";
#elif (RCAR_LSI == RCAR_V4H)
const char *product_v4h = "V4H";
#elif (RCAR_LSI == RCAR_V4M)
const char *product_v4m = "V4M";
#endif /* RCAR_LSI == RCAR_S4 */
const char *unknown = "unknown";
#if (BOOT_MODE == SECURE)
uint32_t bootmode; /* store boot mode */
#endif /* BOOT_MODE == SECURE */
LOAD_INFO li[MAX_PLACED];
#if (1 == (MEASURE_TIME))
scmt_module_start();
store_time_checkpoint("loader_main", 0);
#endif
/*****************************************************************************
* Initialize Hardware
*****************************************************************************/
/* IP initialize */
ip_init();
/*****************************************************************************
* Output boot message
*****************************************************************************/
#if (RCAR_LSI == RCAR_S4)
NOTICE("CA55 Loader Program Rev.%s\n", IPL_VERSION);
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
NOTICE("CR52 Loader Program Rev.%s\n", IPL_VERSION);
#endif /* RCAR_LSI == RCAR_S4 */
NOTICE("%s\n", build_message);
/* Get PRR */
reg = mem_read32(PRR);
switch (reg & PRR_PRODUCT_MASK)
{
#if (RCAR_LSI == RCAR_S4)
case PRR_PRODUCT_S4:
{
str = product_s4;
break;
}
#elif (RCAR_LSI == RCAR_V4H)
case PRR_PRODUCT_V4H:
{
str = product_v4h;
break;
}
#elif (RCAR_LSI == RCAR_V4M)
case PRR_PRODUCT_V4M:
{
str = product_v4m;
break;
}
#endif /* RCAR_LSI == RCAR_S4 */
default:
{
str = unknown;
break;
}
}
NOTICE("PRR is R-Car %s Ver.%d.%d\n", str,
((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT)
+ PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK));
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
/* Notice the ecc enable */
NOTICE("Access Protection Enable\n");
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
store_time_checkpoint("init_done", 0);
/*****************************************************************************
* DDR Initialization
*****************************************************************************/
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* DDR initialize */
result = R_DRAM_Init();
if (INITDRAM_OK != result)
{
ERROR("Failed to DRAM initialize (%d).\n", (int)result);
panic;
}
#if (ECM_ERROR_ENABLE == 1)
ecm_error_enable();
#endif /* ECM_ERROR_ENABLE == 1 */
#if (ECC_ENABLE == 1)
/* ECC Protection */
ecc_sdram_enable();
#endif /* ECC_ENABLE == 1 */
/* QoS configuration */
qos_init();
/* RT-VRAM Extend mode */
rtvram_extendmode();
/* memory copy */
memcpy((void *)DISK_BUFFER_ADDR, (void *)DISK_BUFFER__IPL, 4096);
memset((void *)DISK_BUFFER__IPL, 0xFF, 4096);
memcpy((void *)AB_INFO_FLAG_ADDR, (void *)AB_INFO_FLAG__IPL, 4);
memset((void *)AB_INFO_FLAG__IPL, 0xFF, 4);
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
store_time_checkpoint("DDR_and_Bus_init_done", 0);
/*****************************************************************************
* Load Certficate
*****************************************************************************/
/* Load content certificate */
ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR);
/* Get load information */
load_init(li, ca_load_num);
#if (BOOT_MODE == SECURE)
/*****************************************************************************
* Check SecureBoot
*****************************************************************************/
secureboot_init();
/* LCS judgement for secure boot */
bootmode = judge_bootmode();
if (NORMAL_BOOT != bootmode)
{
/* Content cert certification */
#if (BL2_LOAD_ENABLE == BL2_DISABLE)
secureboot_verify(li, CA_OPTIONAL_ID, CA_OPTIONAL_ID + ca_load_num);
#else
secureboot_verify(li, CA_BL2_ID, CA_BL2_ID + 1);
#endif
store_time_checkpoint("verify_cert_done", 0);
}
#endif /* BOOT_MODE == SECURE */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/*****************************************************************************
* Load RTOS#2
*****************************************************************************/
/* Start loading RTOS#2 image */
load_image(&li[RTOS2_ID]);
store_time_checkpoint("load_RTOS#2_done", li[RTOS2_ID].image_size);
#if (BOOT_MODE == SECURE)
/* Decryption image and Image cerfification */
if (NORMAL_BOOT != bootmode)
{
secureboot_image(&li[RTOS2_ID], 1);
store_time_checkpoint("verify_RTOS#2_done", 0);
}
#endif /* BOOT_MODE == SECURE */
/* boot CR core2 */
arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS2_ID].boot_addr, 2);
store_time_checkpoint("started_RTOS#2", 0);
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/*****************************************************************************
* Load RTOS#0
*****************************************************************************/
#define _IPL_END (0xEB22FFF4)
#ifdef MOBIS_PRK3
emmc_initialize();
store_time_checkpoint("emmc_initialize", 0);
#if (BL2_LOAD_ENABLE == BL2_ENABLE) /* do not clear eMMC */
export_mmc_drv_obj();
#endif
reg = mem_read32(AB_INFO_FLAG_ADDR);
if (reg & AB_INFO_SELECT_2nd)
slot = 1;
// slot = ab_select_slot();
load_update_part_num(li, ca_load_num, slot);
NOTICE("slot: %d\n", slot);
mem_write32(_IPL_END, 0x0);
#endif
/* Start loading RTOS#0 image */
load_image(&li[RTOS_ID]);
store_time_checkpoint("load_RTOS#0_done", li[RTOS_ID].image_size);
#if (BOOT_MODE == SECURE)
/* Decryption image and Image cerfification */
if (NORMAL_BOOT != bootmode)
{
/* WARNING! WARNING! WARNING! WARNING! */
/* TODO: set 1 to panic! later */
secureboot_image(&li[RTOS_ID], 0);
store_time_checkpoint("verify_RTOS#0_done", 0);
}
#endif /* BOOT_MODE == SECURE */
/* boot CR core0 */
arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, -1);
#ifdef MOBIS_PRK3
/* enable CR-52 Core 2 */
arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, 2);
store_time_checkpoint("started_RTOS#0", 0);
#endif
#if (BOOT_TIME_CHECK != 0)
gpio_N1305(2);
#endif
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
/*****************************************************************************
* Load CA Program#2--#8
*****************************************************************************/
#if (BL2_LOAD_ENABLE == BL2_DISABLE)
/* Start loading CA Program#n image */
for (loop = 0U; loop < ca_load_num; loop++)
#else
/* load bl2 */
loop = (CA_BL2_ID - CA_OPTIONAL_ID);
#endif
{
/* Loading start */
NOTICE("Loading %s...\n", li[CA_OPTIONAL_ID + loop].name);
load_image(&li[CA_OPTIONAL_ID + loop]);
store_time_checkpoint("load_CA_#_done", li[CA_OPTIONAL_ID + loop].image_size);
#if (BOOT_MODE == SECURE)
/* Decryption image and Image certification */
if (NORMAL_BOOT != bootmode)
{
secureboot_image(&li[CA_OPTIONAL_ID + loop], 1);
store_time_checkpoint("verify_CA_#_done", 0);
}
#endif /* BOOT_MODE == SECURE */
}
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* Set Secure Monitor parameter */
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */
li[CA_OPTIONAL_ID + 1U].boot_addr); /* U-Boot */
#else
#if (BL2_LOAD_ENABLE == BL2_DISABLE) /* BL2 will load these */
smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */
li[CA_OPTIONAL_ID + 1U].boot_addr, /* U-Boot */
li[CA_OPTIONAL_ID + 2U].boot_addr); /* OP-TEE */
#endif
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
/* Before Boot CPU, Set the division ratio for CPU operating frequency */
adj_ca_variant_freq();
/* boot CA */
#if (BL2_LOAD_ENABLE == BL2_DISABLE)
arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_OPTIONAL_ID].boot_addr, -1);
#else /* run BL2, not BL31 */
arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_BL2_ID].boot_addr, -1);
#endif
store_time_checkpoint("started_CA_core", 0);
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/*****************************************************************************
* Load RTOS#1
*****************************************************************************/
/* Start loading RTOS#1 image */
load_image(&li[RTOS1_ID]);
store_time_checkpoint("load_RTOS#1_done", li[RTOS1_ID].image_size);
#if (BOOT_MODE == SECURE)
/* Decryption image and Image cerfification */
if (NORMAL_BOOT != bootmode)
{
secureboot_image(&li[RTOS1_ID], 1);
store_time_checkpoint("verify_RTOS#1_done", 0);
}
#endif /* BOOT_MODE == SECURE */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
sdram_protection(AXMM_DPTSECCR_NUM);
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
sdram_protection(AXMM_DPTSECCR_NUM2);
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
remove_rgid0_previlege();
/*
* SAN(Safety Application Note) 6.23.5 Operation
* Checker processor :
* Check RegionID/LifeC & memory area protection settings (including order & content of intermediate updates)
* done by ICUMX.
*/
rgid_protection_check();
ram_protection_check();
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
#if (BOOT_MODE == SECURE)
if (NORMAL_BOOT != bootmode)
{
/* Compare Hash verified at ICUMX IPL (V4H only). (Target images are Secure FW and Cx 2nd IPL.) */
/*
* SAN(Safety Application Note) 6.23.5 Operation
* Checker processor :
* Re-do comparison of hash in Flash vs hash generated by ICUMX to confirm proper comparison.
*/
final_hash_cmp();
store_time_checkpoint("final_verify_done", 0);
}
#endif /* BOOT_MODE == SECURE */
NOTICE("Load finish.(CR52 Loader)\n");
#elif (RCAR_LSI == RCAR_S4)
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
sdram_protection(AXMM_DPTSECCR_NUM);
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
NOTICE("Load finish.(CA55 Loader)\n");
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
// ip_release();
store_time_checkpoint("Cx_done_starting_RTOS#1", 0);
// scmt_wait_ticks(SCMT_MS2TICKS(1000));
print_time_checkpoints();
#if (BOOT_TIME_CHECK != 0)
gpio_N1305(2);
#endif
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
#ifdef MOBIS_PRK3
return li[RTOS_ID].boot_addr;
#else
return li[CA_OPTIONAL_ID].boot_addr;
#endif
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
return li[RTOS1_ID].boot_addr;
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
}
/* End of function loader_main(void) */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
static void sdram_protection(uint32_t num)
{
uint32_t val;
uint32_t addr;
/* Calculation of the address of the DPTSECCR register. */
addr = (AXMM_DPTSECCR + (num * 4U));
val = mem_read32(addr);
val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK);
val |= (AXMM_DPTSECCR_SECGRP_SEC | AXMM_DPTSECCR_SECGWP_SEC);
mem_write32(addr, val);
}/* End of function void sdram_protection(void) */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
static void remove_rgid0_previlege(void)
{
uint32_t val;
uint32_t addr;
/* Calculation of the address of the DPTRGNCR register. */
addr = get_dptrgncr_addr(DPTRGNCR_PROTECT_AREA);
val = mem_read32(addr);
val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */
mem_write32(addr, val);
/* Calculation of the address of the DPTRGNCR register. */
addr = get_dptrgncr_addr(DPTRGNCR_LINUX_AREA);
val = mem_read32(addr);
val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */
mem_write32(addr, val);
/* Calculation of the address of the SECCTRW0D_1 register. */
addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA0);
val = mem_read32(addr);
val &= ~(SECCTRWD_SAFG15WP_MASK);
val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area0. */
mem_write32(addr, val);
/* Calculation of the address of the SECCTRW2D_1 register. */
addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA2);
val = mem_read32(addr);
val &= ~(SECCTRWD_SAFG15WP_MASK);
val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area2. */
mem_write32(addr, val);
}
/* End of function void remove_rgid0_previlege(void) */
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main common function
******************************************************************************/
/******************************************************************************
* @file loader_main_common.c
* - Version : 0.05
* @brief 1.Set BL31 parameter.
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 15.11.2022 0.01 First Release
* : 04.04.2023 0.02 Removed stdio.h.
* : 13.09.2024 0.03 Updated smoni_ep_info->ulpc_high to 0x20,
* smoni_ipl_param->pnonsecepinfo_high to 0x20.
* : 11.10.2024 0.04 Updated Region ID and RAM protection setting
* for QNX for V4M.
* : 26.05.2025 0.05 Added optee_ep_info parameter.
*****************************************************************************/
#include <stdint.h>
#include <mem_io.h>
#include <loader_main_common.h>
#include <image_load.h>
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#include "access_protection.h"
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#define SMONI_IPL_PARAM_OFFSET (0x00022200U)
#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U)
#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U)
#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U)
#define BL31_COLD_BOOT (0x0000000000000000U)
#define BL31_WARM_BOOT (0x0000000000000001U)
#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU)
/* struct */
typedef struct{
uint8_t uctype;
uint8_t ucversion;
uint16_t ussize;
uint32_t uiattr;
uint32_t psecmonimageinfo_low;
uint32_t psecmonimageinfo_high;
uint32_t psecoptepinfo_low;
uint32_t psecoptepinfo_high;
uint32_t psecoptimageinfo_low;
uint32_t psecoptimageinfo_high;
uint32_t pnonsecepinfo_low;
uint32_t pnonsecepinfo_high;
uint32_t pnonsecimageinfo_low;
uint32_t pnonsecimageinfo_high;
}st_smoni_iplparams_t;
typedef struct{
uint8_t uctype;
uint8_t ucversion;
uint16_t ussize;
uint32_t uiattr;
uint32_t ulpc_low;
uint32_t ulpc_high;
uint32_t ulspsr_low;
uint32_t ulspsr_high;
uint32_t ularg0_low;
uint32_t ularg0_high;
uint32_t ularg1_low;
uint32_t ularg1_high;
uint32_t ularg2_low;
uint32_t ularg2_high;
uint32_t ularg3_low;
uint32_t ularg3_high;
uint32_t ularg4_low;
uint32_t ularg4_high;
uint32_t ularg5_low;
uint32_t ularg5_high;
uint32_t ularg6_low;
uint32_t ularg6_high;
uint32_t ularg7_low;
uint32_t ularg7_high;
}st_smoni_entrypointinfo_t;
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
void smoni_set_param(uintptr_t smoni_entry_point,
uintptr_t uboot_entry_point)
#else
void smoni_set_param(uintptr_t smoni_entry_point,
uintptr_t uboot_entry_point,
uintptr_t tee_entry_point)
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
{
st_smoni_iplparams_t *smoni_ipl_param;
st_smoni_entrypointinfo_t *smoni_ep_info;
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
st_smoni_entrypointinfo_t *optee_ep_info;
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
#ifdef AARCH64
union {
uintptr_t ptr;
struct {
uint32_t low;
uint32_t high;
} u32;
} _tmp;
#endif
/* set struct address */
smoni_ipl_param = (st_smoni_iplparams_t *)
(smoni_entry_point + SMONI_IPL_PARAM_OFFSET);
smoni_ep_info = (st_smoni_entrypointinfo_t *)
(smoni_entry_point + SMONI_EP_INFO_OFFSET);
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
optee_ep_info = (st_smoni_entrypointinfo_t *)
(smoni_entry_point + OPTEE_EP_INFO_OFFSET);
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
/* set parameter */
smoni_ipl_param->uctype = 0x03U;
smoni_ipl_param->ucversion = 0x01U;
smoni_ipl_param->ussize = 0x0030U;
smoni_ipl_param->uiattr = 0x00000000U;
smoni_ipl_param->psecmonimageinfo_low = 0x00000000U;
smoni_ipl_param->psecmonimageinfo_high = 0x00000000U;
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
smoni_ipl_param->psecoptepinfo_low = 0x00000000U;
#else
#ifdef AARCH64
_tmp.ptr = (uintptr_t)optee_ep_info;
smoni_ipl_param->psecoptepinfo_low = _tmp.u32.low;
#else
smoni_ipl_param->psecoptepinfo_low = (uint32_t)optee_ep_info;
#endif
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
smoni_ipl_param->psecoptepinfo_high = 0x00000020U; /* OP-TEE entry point information 0x20_46422288 */
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
smoni_ipl_param->psecoptepinfo_high = 0x00000000U;
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
#else
smoni_ipl_param->psecoptepinfo_high = 0x00000000U;
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
smoni_ipl_param->psecoptimageinfo_low = 0x00000000U;
smoni_ipl_param->psecoptimageinfo_high = 0x00000000U;
#ifdef AARCH64
_tmp.ptr = (uintptr_t)smoni_ep_info;
smoni_ipl_param->pnonsecepinfo_low = _tmp.u32.low;
#else
smoni_ipl_param->pnonsecepinfo_low = (uint32_t)smoni_ep_info;
#endif
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
smoni_ipl_param->pnonsecepinfo_high = 0x00000020U; /* Secure monitor entry point 0x20_XXXXXXXX */
smoni_ipl_param->pnonsecepinfo_high = 0x00000020U; /* Secure monitor entry point 0x20_46400000 */
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
smoni_ipl_param->pnonsecepinfo_high = 0x00000000U;
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
#else
smoni_ipl_param->pnonsecepinfo_high = 0x00000000U;
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U;
smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U;
smoni_ep_info->uctype = 0x01U;
smoni_ep_info->ucversion = 0x01U;
smoni_ep_info->ussize = 0x0058U; /* structure size */
smoni_ep_info->uiattr = 0x00000001U; /* SECURE */
#ifdef AARCH64
_tmp.ptr = (uintptr_t)uboot_entry_point;
smoni_ep_info->ulpc_low = _tmp.u32.low;
#else
smoni_ep_info->ulpc_low = uboot_entry_point;
#endif
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
smoni_ep_info->ulpc_high = 0x00000020U; /* U-boot entry point 0x20_50000000 */
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
smoni_ep_info->ulpc_high = 0x00000000U;
#endif
#else
smoni_ep_info->ulpc_high = 0x00000000U;
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
/* SPSR_EL3.E[9] = b1 (BigEndian) *
* .A[8] = b1 (DataAbort MASK) *
* .I[7] = b1 (IRQ MASK) *
* .F[6] = b1 (FIQ MASK) *
* .M[4] = b0 (AArcch64) *
* .M[3:1] = b0101 (EL1h) */
smoni_ep_info->ulspsr_low = 0x000003C5U;
smoni_ep_info->ulspsr_high = 0x00000000U;
smoni_ep_info->ularg0_low = 0x00000000U;
smoni_ep_info->ularg0_high = 0x00000000U;
smoni_ep_info->ularg1_low = 0x00000000U;
smoni_ep_info->ularg1_high = 0x00000000U;
smoni_ep_info->ularg2_low = 0x00000000U;
smoni_ep_info->ularg2_high = 0x00000000U;
smoni_ep_info->ularg3_low = 0x00000000U;
smoni_ep_info->ularg3_high = 0x00000000U;
smoni_ep_info->ularg4_low = 0x00000000U;
smoni_ep_info->ularg4_high = 0x00000000U;
smoni_ep_info->ularg5_low = 0x00000000U;
smoni_ep_info->ularg5_high = 0x00000000U;
smoni_ep_info->ularg6_low = 0x00000000U;
smoni_ep_info->ularg6_high = 0x00000000U;
smoni_ep_info->ularg7_low = 0x00000000U;
smoni_ep_info->ularg7_high = 0x00000000U;
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
optee_ep_info->uctype = 0x01U;
optee_ep_info->ucversion = 0x02U;
optee_ep_info->ussize = 0x0058U;
optee_ep_info->uiattr = 0x00000008U;
#ifdef AARCH64
_tmp.ptr = (uintptr_t)tee_entry_point;
optee_ep_info->ulpc_low = _tmp.u32.low;
#else
optee_ep_info->ulpc_low = tee_entry_point;
#endif
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
optee_ep_info->ulpc_high = 0x00000020U; /* OP-TEE entry point 0x20_44100000 */
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
optee_ep_info->ulpc_high = 0x00000000U;
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
#else
optee_ep_info->ulpc_high = 0x00000000U;
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
optee_ep_info->ulspsr_low = 0x000003C5U;
optee_ep_info->ulspsr_high = 0x00000000U;
optee_ep_info->ularg0_low = 0x00000000U;
optee_ep_info->ularg0_high = 0x00000000U;
optee_ep_info->ularg1_low = 0x00000000U;
optee_ep_info->ularg1_high = 0x00000000U;
optee_ep_info->ularg2_low = 0x00000000U;
optee_ep_info->ularg2_high = 0x00000000U;
optee_ep_info->ularg3_low = 0x00000000U;
optee_ep_info->ularg3_high = 0x00000000U;
optee_ep_info->ularg4_low = 0x00000000U;
optee_ep_info->ularg4_high = 0x00000000U;
optee_ep_info->ularg5_low = 0x00000000U;
optee_ep_info->ularg5_high = 0x00000000U;
optee_ep_info->ularg6_low = 0x00000000U;
optee_ep_info->ularg6_high = 0x00000000U;
optee_ep_info->ularg7_low = 0x00000000U;
optee_ep_info->ularg7_high = 0x00000000U;
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
smoni_entry_point += BL31_KIND_BOOT_ADDR;
mem_write32((smoni_entry_point), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU));
mem_write32(((smoni_entry_point) + 0x4U),
(uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU));
}
/* End of function smoni_set_param(uint32_t smoni_entry_point) */

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IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file loader_s4.S
* - Version : 0.06
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 27.06.2022 0.02 Remove unused definitions
* : 02.08.2022 0.03 Support WDT
* : 31.10.2022 0.04 License notation change.
* : 14.12.2022 0.05 Support MMU
* : 17.02.2023 0.06 Modified instruction and General purpose
* register to lower case.
*****************************************************************************/
#include "asm_macros.S"
/* SCTLR definitions */
#define SCTLR_M_BIT (1 << 0)
#define SCTLR_A_BIT (1 << 1)
#define SCTLR_SA_BIT (1 << 3)
#define SCTLR_I_BIT (1 << 12)
#define SCTLR_WXN_BIT (1 << 19)
#define SCTLR_EE_BIT (1 << 25)
#define SCTLR_RESET_VAL (SCTLR_SA_BIT)
#define SCTLR_MMU_ON (SCTLR_M_BIT)
#define SCTLR_OFF ~(SCTLR_M_BIT | SCTLR_I_BIT | SCTLR_A_BIT)
/* SCR definitions */
#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
#define SCR_TWEDEL_SHIFT (30)
#define SCR_TWEDEL_MASK (0xf)
#define SCR_AMVOFFEN_BIT (1 << 35)
#define SCR_TWEDEn_BIT (1 << 29)
#define SCR_ECVEN_BIT (1 << 28)
#define SCR_FGTEN_BIT (1 << 27)
#define SCR_ATA_BIT (1 << 26)
#define SCR_FIEN_BIT (1 << 21)
#define SCR_EEL2_BIT (1 << 18)
#define SCR_API_BIT (1 << 17)
#define SCR_APK_BIT (1 << 16)
#define SCR_TERR_BIT (1 << 15)
#define SCR_TWE_BIT (1 << 13)
#define SCR_TWI_BIT (1 << 12)
#define SCR_ST_BIT (1 << 11)
#define SCR_RW_BIT (1 << 10)
#define SCR_SIF_BIT (1 << 9)
#define SCR_HCE_BIT (1 << 8)
#define SCR_SMD_BIT (1 << 7)
#define SCR_EA_BIT (1 << 3)
#define SCR_FIQ_BIT (1 << 2)
#define SCR_IRQ_BIT (1 << 1)
#define SCR_NS_BIT (1 << 0)
#define SCR_VALID_BIT_MASK (0x2f8f)
#define SCR_RESET_VAL SCR_RES1_BITS
/* CPSR/SPSR definitions */
#define DAIF_FIQ_BIT (1 << 0)
#define DAIF_IRQ_BIT (1 << 1)
#define DAIF_ABT_BIT (1 << 2)
#define DAIF_DBG_BIT (1 << 3)
#define SPSR_DAIF_SHIFT (6)
#define SPSR_DAIF_MASK (0xf)
#define SPSR_AIF_SHIFT (6)
#define SPSR_AIF_MASK (0x7)
#define SPSR_E_SHIFT (9)
#define SPSR_E_MASK (0x1)
#define SPSR_E_LITTLE (0x0)
#define SPSR_E_BIG (0x1)
#define SPSR_T_SHIFT (5)
#define SPSR_T_MASK (0x1)
#define SPSR_T_ARM (0x0)
#define SPSR_T_THUMB (0x1)
#define SPSR_M_SHIFT (4)
#define SPSR_M_MASK (0x1)
#define SPSR_M_AARCH64 (0x0)
#define SPSR_M_AARCH32 (0x1)
#define SPSR_EL_SHIFT (2)
#define SPSR_EL_WIDTH (2)
/* TCR definitions */
#define TCR_BIT31_RES1 (1 << 31)
#define TCR_BIT23_RES1 (1 << 23)
#define TCR_PS (0 << 16)
#define TCR_TG0 (0 << 14)
#define TCR_SH0 (3 << 12)
#define TCR_ORGN0 (3 << 10)
#define TCR_IRGN0 (3 << 8)
#define TCR_T0SZ (32 << 0)
#define TCR_VAL \
(TCR_BIT31_RES1 | TCR_BIT23_RES1 | TCR_PS | TCR_TG0 | TCR_SH0 | TCR_ORGN0 | TCR_IRGN0 | TCR_T0SZ)
/* MAIR definitions */
#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */
#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
#define MAIR_ATTR3 (0x00 << 24)
#define MAIR_ATTR4 (0x00 << 32)
#define MAIR_ATTR5 (0x00 << 40)
#define MAIR_ATTR6 (0x00 << 48)
#define MAIR_ATTR7 (0x00 << 56)
#define MAIR_VAL \
(MAIR_ATTR7 | MAIR_ATTR6 | MAIR_ATTR5 | MAIR_ATTR4 | MAIR_ATTR3 | MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0)
#define MAIR_INIT_VAL (0x44E048E000098AA4)
#define BIT_64Cx(nr) (1 << (nr))
#define SPSR_SSBS_BIT_AARCH64 BIT_64Cx(12)
#define SPSR_SSBS_BIT_AARCH32 BIT_64Cx(23)
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
#define MODE_RW_SHIFT (0x4)
#define MODE_SP_MASK (0x1)
#define MODE_SP_SHIFT (0x0)
#define MODE_EL_MASK (0x3)
#define MODE_EL_SHIFT (0x2)
#define MODE_EL3 (0x3)
#define MODE_RW_64 (0x0)
#define MODE_SP_ELX (0x1)
#define SPSR_64 (((MODE_RW_64 << MODE_RW_SHIFT) | \
((MODE_EL3 & MODE_EL_MASK) << MODE_EL_SHIFT) | \
((MODE_SP_ELX & MODE_SP_MASK) << MODE_SP_SHIFT) | \
((DISABLE_ALL_EXCEPTIONS & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
(~(SPSR_SSBS_BIT_AARCH64)))
.global Startup
/*****************************************************************************
* Reset Hander
*****************************************************************************/
Startup:
/* initialize registers*/
ldr x0, =0
ldr x1, =0
ldr x2, =0
ldr x3, =0
ldr x4, =0
ldr x5, =0
ldr x6, =0
ldr x7, =0
ldr x8, =0
ldr x9, =0
ldr x10, =0
ldr x11, =0
ldr x12, =0
ldr x13, =0
ldr x14, =0
ldr x15, =0
ldr x16, =0
ldr x17, =0
ldr x18, =0
ldr x19, =0
ldr x20, =0
ldr x21, =0
ldr x22, =0
ldr x23, =0
ldr x24, =0
ldr x25, =0
ldr x26, =0
ldr x27, =0
ldr x28, =0
ldr x29, =0
ldr x30, =0
ldr x0, =__STACKS_END__
mrs x1, sctlr_el3
mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
| SCTLR_SA_BIT | SCTLR_A_BIT))
orr x0, x0, x1
msr sctlr_el3, x0
isb
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el3
orr x0, x0, x1
msr sctlr_el3, x0
isb
mrs x1, scr_el3
mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | SCR_FIQ_BIT ) \
& ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
orr x0, x0, x1
msr scr_el3, x0
/* ---------------------------------------------------------------------
* Set the exception vectors.
* ---------------------------------------------------------------------
*/
adr x0, loader_exceptions
msr vbar_el3, x0
isb
msr daifclr, #(DAIF_ABT_BIT | DAIF_FIQ_BIT)
/* ---------------------------------------------------------------------
* Set the MMU table.
* ---------------------------------------------------------------------
*/
ldr x0 ,=TCR_VAL
msr tcr_el3, x0
ldr x0, =MAIR_VAL
msr mair_el3, x0
ldr x0, =g_loader_level1_table
msr ttbr0_el3, x0
/* ---------------------------------------------------------------------
* Enable MMU.
* ---------------------------------------------------------------------
*/
isb
tlbi alle3
isb
mrs x0, sctlr_el3
ldr x1 ,=SCTLR_MMU_ON
orr x0, x0, x1
msr sctlr_el3, x0
dsb sy
isb
tlbi alle3
isb
/* clear bss section */
mov x0, #0x0
ldr x1, =__BSS_START__
ldr x2, =__BSS_SIZE__
bss_loop:
subs x2, x2, #4
bcc bss_end
str w0, [x1, x2]
b bss_loop
bss_end:
/* copy data section */
ldr x0, =__DATA_COPY_START__
ldr x1, =__DATA_START__
ldr x2, =__DATA_SIZE__
data_loop:
subs x2, x2, #4
bcc data_end
ldr w3, [x0, x2]
str w3, [x1, x2]
b data_loop
data_end:
msr spsel, #0
ldr x0, =__STACKS_END__
mov sp, x0
bl loader_main
msr elr_el3, x0
mov x0, #SPSR_64
msr spsr_el3, x0
/* ---------------------------------------------------------------------
* Disable MMU.
* ---------------------------------------------------------------------
*/
mrs x0, sctlr_el3
ldr x1 ,=SCTLR_OFF
and x0, x0, x1
msr sctlr_el3, x0
dsb sy
isb
tlbi alle3
ic iallu
/* ---------------------------------------------------------------------
* Set initial value.
* ---------------------------------------------------------------------
*/
msr ttbr0_el3, xzr
ldr x0, =MAIR_INIT_VAL
msr mair_el3, x0
msr tcr_el3, xzr
msr vbar_el3, xzr
isb
eret
.end

140
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.ld Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader linker directive
******************************************************************************/
/******************************************************************************
* @file loader,ld
* - Version : 0.07
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 21.02.2022 0.02 Changed section name
* : 10.05.2022 0.03 Changed section name
* Added memory
* Change binary size to multiples of 16
* : 20.06.2022 0.04 Support secure boot for S4
* : 02.08.2022 0.05 Support WDT
* : 31.10.2022 0.06 License notation change.
* : 13.02.2023 0.07 Added sections for MMU table.
*****************************************************************************/
OUTPUT_FORMAT("elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(Startup)
MEMORY {
SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000
/* Must match with MMU_TBL_SYSRAM_ADDR defined in loader_mmu_table.c. */
MMU_LV3_STAT (rwa): ORIGIN = 0xE6310000, LENGTH = 0x00001000 /* level3:4KiB */
/* Must match with MMU_TBL_ADDR defined in loader_mmu_table.c. */
MMU_LV2_STAT (rwa): ORIGIN = 0xE6311000, LENGTH = 0x00001000 /* level2:4KiB */
MMU_LV1_STAT (rwa): ORIGIN = 0xE6312000, LENGTH = 0x00000100 /* level1:32byte */
CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00001000
CXIPLSTACK (rwa): ORIGIN = 0xE6331000, LENGTH = 0x00002000
SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000
SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000
}
SECTIONS
{
.loader_start : {
__RO_START__ = .;
build/obj/loader/loader_s4.o(.text*)
. = NEXT(2048);
*(.vectors)
. = ALIGN(4096);
} > SYSRAM
.loader_ro : {
*(.text*)
*(.rodata*)
. = ALIGN(8);
__CONST_START__ = .;
*(.constdata.CONFIG_DATA)
__RO_END_UNALIGNED__ = .;
. = NEXT(4096);
__RO_END__ = .;
__DATA_COPY_START__ = .;
} > SYSRAM
.lv3_tbl : {
build/obj/loader/loader_mmu_table.o(.rodata)
} > MMU_LV3_STAT
.lv2_tbl : {
build/obj/loader/loader_mmu_table.o(.rodata)
} > MMU_LV2_STAT
.lv1_tbl : {
build/obj/loader/loader_mmu_table.o(.rodata)
} > MMU_LV1_STAT
.data : {
__DATA_START__ = .;
*(.data*)
. = NEXT(16);
__DATA_END__ = .;
} > CXIPLDATA AT > SYSRAM
__DATA_SIZE__ = SIZEOF(.data);
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(Cx_loader_stack))
__STACKS_END__ = .;
} > CXIPLSTACK
.bss.SHARED_TOP : {
__SHARED_TOP_START__ = .;
*(.bss.SHARED_TOP)
*(.bss.SHARED_LCS)
*(.bss.SHARED_CMAC)
*(.bss.SHARED_HASH)
. = NEXT(0x00200000);
__SHARED__END__ = .;
} > SHARED_SDRAM
.SHARED_RAM : {
__FWRAM_START__ = .;
. += 0;
. = NEXT(0x0000C000);
__FWRAM_END__ = .;
} > SHARED_RAM
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} > CXIPLDATA
__BSS_SIZE__ = SIZEOF(.bss);
}

387
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file loader_v4h.S
* - Version : 0.07
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 17.02.2022 0.01 First Release
* : 09.05.2022 0.02 Removed the last nop instruction
* : 31.10.2022 0.03 License notation change.
* : 15.12.2022 0.04 V4H interrupt support.
* : 28.12.2022 0.05 MPU support.
* Address acquisition changes in interrupt handlers
* : 16.02.2023 0.06 Modified instruction to lower case.
* : 19.12.2024 0.07 Added the process that jump to RTOS#1.
*****************************************************************************/
/* SCTLR definitions */
#define SCTLR_I (1 << 12)
#define SCTLR_M (1 << 0)
/* MAIR definitions */
#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */
#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0)
#define SUP_EXCEPTION (0x2U)
#define HYP_EXCEPTION (0x5U)
#define IRQ_EXCEPTION (0x6U)
#define FIQ_EXCEPTION (0x7U)
#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */
#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
.global Startup
.global Vector
.global dabt_report_exception
.global pabt_report_exception
.extern dabort_error
.extern pabort_error
.extern Undefined_error
.extern handler_error
.align 5
Vector:
b Startup /* Reset */
b Undefined_Handler /* Undefined Instruction */
b Supervisor_Handler /* Supervisor Call */
b Prefetch_Handler /* Prefetch Abort */
b Abort_Handler /* Data Abort */
b HypTrap_Handler /* Hyp Trap */
b IRQ_Handler /* IRQ interrupt */
b FIQ_Handler /* FIQ interrupt */
/*****************************************************************************
* Reset Hander
*****************************************************************************/
Startup:
/* initialize registers*/
/* initialize registers*/
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11, #0
mov r12, #0
mov lr, #0
ldr r13, =__STACKS_END__
/* Instruction cache enable */
mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* SCTLR */
bic r0, r0, #SCTLR_M /* M=0 */
bic r1, r1, #SCTLR_M /* M=0 */
orr r0, r0, #SCTLR_I /* I=1 */
orr r1, r1, #SCTLR_I /* I=1 */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* SCTLR */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* CR52_CONFIGURE_MPU */
mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */
mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */
ldr r0, =MAIR_VAL /* Set MAIR */
ldr r1, =MAIR_VAL /* Set MAIR */
mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */
mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */
/* region 0: 0x00000000~0x3FFFFFFF */
ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */
ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
/* region 1: 0x40000000~0xBFFFFFFF */
ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
/* region 2: 0xC0000000~0xE3FFFFFF */
ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
/* region 3: 0xE4000000~0xE4FFFFFF */
ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
/* region 4: 0xE5000000~0xE62FFFFF */
ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */
mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */
mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */
mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */
/* region 5: 0xE6300000~0xE632FFFF */
ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */
ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */
mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */
/* region 6: 0xE6330000~0xE635FFFF */
ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
/* region 7: 0xE6360000~0xEB1FFFFF */
ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */
mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */
mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */
mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */
/* region 8: 0xEB200000~0xEB3FFFFF */
ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
/* region 9: 0xEB400000~0xFFFFFFFF */
ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */
mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */
mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */
mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */
/* CR52_SET_MPU_ON */
mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
orr r0, r0, #SCTLR_M /* MPU enable */
orr r1, r1, #SCTLR_M /* MPU enable */
mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* Jump to physical address from mirror address */
ldr r0, =JUMP_MAIN
bx r0
JUMP_MAIN:
ldr r0, =Vector
mcr p15, 4, r0, c12, c0, 0 /* HVBAR */
/* clear bss section */
mov r0, #0x0
ldr r1, =__BSS_START__
ldr r2, =__BSS_SIZE__
bss_loop:
subs r2, r2, #4
bcc bss_end
str r0, [r1, +r2]
b bss_loop
bss_end:
/* copy data section */
ldr r0, =__DATA_COPY_START__
ldr r1, =__DATA_START__
ldr r2, =__DATA_SIZE__
data_loop:
subs r2, r2, #4
bcc data_end
ldr r3, [r0, +r2]
str r3, [r1, +r2]
b data_loop
data_end:
/* Loader Main */
bl loader_main
#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
/* Keep return value from loader_main function (Boot address of RTOS#1) */
mov r11, r0
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* region 0: 0x00000000~0x3FFFFFFF */
ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
/* region 1: 0x40000000~0xBFFFFFFF */
ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
/* region 2: 0xC0000000~0xE3FFFFFF */
/* Change MPU setting for RTOS#1. */
ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* region 3: 0xE4000000~0xE4FFFFFF */
ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
/* region 5: 0xE6300000~0xE632FFFF */
ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */
/* region 6: 0xE6330000~0xE635FFFF */
ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
/* region 8: 0xEB200000~0xEB3FFFFF */
ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* Instruction cache disable */
mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
bic r0, r0, #SCTLR_I /* I=0 */
bic r1, r1, #SCTLR_I /* I=0 */
mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
isb
#if defined(MOBIS_PRK3)
/* declare IPL-2nd is finished */
ldr r0, =0xEB22FFF4
ldr r1, =0xE632FFFF
str r1, [r0]
#endif
#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
/* Jump to RTOS#1 */
bx r11
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
loader_end:
wfi
b loader_end
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
anker:
wfi
b anker
/* Undefined Instruction */
Undefined_Handler:
mrs r0, ELR_hyp
b Undefined_error
/* Supervisor Call */
Supervisor_Handler:
mov r0, #SUP_EXCEPTION
b handler_error
/* Prefetch Abort */
Prefetch_Handler:
b pabt_report_exception
/* Data Abort */
Abort_Handler:
mrs r0, ELR_hyp
b dabt_report_exception
/* Hyp Trap */
HypTrap_Handler:
mov r0, #HYP_EXCEPTION
b handler_error
/*IRQ interrupt */
IRQ_Handler:
mov r0, #IRQ_EXCEPTION
b handler_error
/* FIQ interrupt */
FIQ_Handler:
mov r0, #FIQ_EXCEPTION
b handler_error
/********************************************************
* abort exception
********************************************************/
dabt_report_exception:
mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */
mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */
b dabort_error
pabt_report_exception:
mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */
mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */
b pabort_error
.end

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader linker directive
******************************************************************************/
/******************************************************************************
* @file AArch32_loader,ld
* - Version : 0.05
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 17.02.2022 0.01 First Release
* : 21.02.2022 0.02 Changed section name
* : 10.05.2022 0.03 Changed section name
* Added memory
* Change binary size to multiples of 16
* : 31.10.2022 0.04 License notation change.
* : 07.11.2022 0.05 Changed the size of CXIPLDATA.
* Added Qos settings assignment.
* : 15.12.2022 0.10 Support RegionID check
*****************************************************************************/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Startup)
MEMORY {
SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000
CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000
CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000
SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000
SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000
}
SECTIONS
{
.loader_start : {
__RO_START__ = .;
build/obj/loader/loader_v4h.o(.text*)
. = NEXT(1024);
*(.vectors)
. = ALIGN(4096);
} > SYSRAM
.loader_ro : {
*(.text*)
*(.rodata*)
. = ALIGN(8);
__CONST_START__ = .;
. = ALIGN(16);
*(.qoswt_tbl)
. = ALIGN(8);
*(.qosbw_tbl)
. = ALIGN(8);
*(.constdata.CONFIG_DATA)
. = ALIGN(8);
*(.rgid_w_tbl)
. = ALIGN(8);
*(.rgid_r_tbl)
. = ALIGN(8);
*(.rgid_m_tbl)
. = ALIGN(8);
*(.rgid_sec_tbl)
. = ALIGN(8);
*(.rgid_axi_tbl)
__RO_END_UNALIGNED__ = .;
. = NEXT(4096);
__RO_END__ = .;
__DATA_COPY_START__ = .;
} > SYSRAM
.data : {
__DATA_START__ = .;
*(.data*)
. = NEXT(16);
__DATA_END__ = .;
} > CXIPLDATA AT > SYSRAM
__DATA_SIZE__ = SIZEOF(.data);
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(Cx_loader_stack))
__STACKS_END__ = .;
} > CXIPLSTACK
.bss.SHARED_TOP : {
__SHARED_TOP_START__ = .;
*(.bss.SHARED_TOP)
*(.bss.SHARED_LCS)
*(.bss.SHARED_CMAC)
*(.bss.SHARED_HASH)
. = NEXT(0x00200000);
__SHARED__END__ = .;
} > SHARED_SDRAM
.SHARED_RAM : {
__FWRAM_START__ = .;
. += 0;
. = NEXT(0x0000C000);
__FWRAM_END__ = .;
} > SHARED_RAM
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} > CXIPLDATA
__BSS_SIZE__ = SIZEOF(.bss);
}

375
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file loader_v4m.S
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
* : 19.12.2024 0.02 Added the process that jump to RTOS#1.
*****************************************************************************/
/* SCTLR definitions */
#define SCTLR_I (1 << 12)
#define SCTLR_M (1 << 0)
/* MAIR definitions */
#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */
#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0)
#define SUP_EXCEPTION (0x2U)
#define HYP_EXCEPTION (0x5U)
#define IRQ_EXCEPTION (0x6U)
#define FIQ_EXCEPTION (0x7U)
#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */
#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
.global Startup
.global Vector
.global dabt_report_exception
.global pabt_report_exception
.extern dabort_error
.extern pabort_error
.extern Undefined_error
.extern handler_error
.align 5
Vector:
b Startup /* Reset */
b Undefined_Handler /* Undefined Instruction */
b Supervisor_Handler /* Supervisor Call */
b Prefetch_Handler /* Prefetch Abort */
b Abort_Handler /* Data Abort */
b HypTrap_Handler /* Hyp Trap */
b IRQ_Handler /* IRQ interrupt */
b FIQ_Handler /* FIQ interrupt */
/*****************************************************************************
* Reset Hander
*****************************************************************************/
Startup:
/* initialize registers*/
/* initialize registers*/
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11, #0
mov r12, #0
mov lr, #0
ldr r13, =__STACKS_END__
/* Instruction cache enable */
mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* SCTLR */
bic r0, r0, #SCTLR_M /* M=0 */
bic r1, r1, #SCTLR_M /* M=0 */
orr r0, r0, #SCTLR_I /* I=1 */
orr r1, r1, #SCTLR_I /* I=1 */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* SCTLR */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* CR52_CONFIGURE_MPU */
mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */
mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */
ldr r0, =MAIR_VAL /* Set MAIR */
ldr r1, =MAIR_VAL /* Set MAIR */
mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */
mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */
/* region 0: 0x00000000~0x3FFFFFFF */
ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */
ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
/* region 1: 0x40000000~0xBFFFFFFF */
ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
/* region 2: 0xC0000000~0xE3FFFFFF */
ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
/* region 3: 0xE4000000~0xE4FFFFFF */
ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
/* region 4: 0xE5000000~0xE62FFFFF */
ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */
mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */
mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */
mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */
/* region 5: 0xE6300000~0xE632FFFF */
ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */
ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */
mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */
/* region 6: 0xE6330000~0xE635FFFF */
ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
/* region 7: 0xE6360000~0xEB1FFFFF */
ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */
mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */
mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */
mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */
/* region 8: 0xEB200000~0xEB3FFFFF */
ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
/* region 9: 0xEB400000~0xFFFFFFFF */
ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */
ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */
mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */
mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */
mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */
mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */
/* CR52_SET_MPU_ON */
mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
orr r0, r0, #SCTLR_M /* MPU enable */
orr r1, r1, #SCTLR_M /* MPU enable */
mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* Jump to physical address from mirror address */
ldr r0, =JUMP_MAIN
bx r0
JUMP_MAIN:
ldr r0, =Vector
mcr p15, 4, r0, c12, c0, 0 /* HVBAR */
/* clear bss section */
mov r0, #0x0
ldr r1, =__BSS_START__
ldr r2, =__BSS_SIZE__
bss_loop:
subs r2, r2, #4
bcc bss_end
str r0, [r1, +r2]
b bss_loop
bss_end:
/* copy data section */
ldr r0, =__DATA_COPY_START__
ldr r1, =__DATA_START__
ldr r2, =__DATA_SIZE__
data_loop:
subs r2, r2, #4
bcc data_end
ldr r3, [r0, +r2]
str r3, [r1, +r2]
b data_loop
data_end:
/* Loader Main */
bl loader_main
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/* Keep return value from loader_main function (Boot address of RTOS#1) */
mov r11, r0
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* region 0: 0x00000000~0x3FFFFFFF */
ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
/* region 1: 0x40000000~0xBFFFFFFF */
ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/* region 2: 0xC0000000~0xE3FFFFFF */
/* Change MPU setting for RTOS#1. */
ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* region 3: 0xE4000000~0xE4FFFFFF */
ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
/* region 5: 0xE6300000~0xE632FFFF */
ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */
/* region 6: 0xE6330000~0xE635FFFF */
ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
/* region 8: 0xEB200000~0xEB3FFFFF */
ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */
ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
isb
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
isb
/* Instruction cache disable */
mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
bic r0, r0, #SCTLR_I /* I=0 */
bic r1, r1, #SCTLR_I /* I=0 */
mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
isb
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/* Jump to RTOS#1 */
bx r11
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
loader_end:
wfi
b loader_end
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
anker:
wfi
b anker
/* Undefined Instruction */
Undefined_Handler:
mrs r0, ELR_hyp
b Undefined_error
/* Supervisor Call */
Supervisor_Handler:
mov r0, #SUP_EXCEPTION
b handler_error
/* Prefetch Abort */
Prefetch_Handler:
b pabt_report_exception
/* Data Abort */
Abort_Handler:
mrs r0, ELR_hyp
b dabt_report_exception
/* Hyp Trap */
HypTrap_Handler:
mov r0, #HYP_EXCEPTION
b handler_error
/*IRQ interrupt */
IRQ_Handler:
mov r0, #IRQ_EXCEPTION
b handler_error
/* FIQ interrupt */
FIQ_Handler:
mov r0, #FIQ_EXCEPTION
b handler_error
/********************************************************
* abort exception
********************************************************/
dabt_report_exception:
mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */
mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */
b dabort_error
pabt_report_exception:
mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */
mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */
b pabort_error
.end

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IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.ld Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader linker directive
******************************************************************************/
/******************************************************************************
* @file loader_v4m.ld
* - Version : 0.01
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
*****************************************************************************/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Startup)
MEMORY {
SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000
CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000
CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000
SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000
SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000
}
SECTIONS
{
.loader_start : {
__RO_START__ = .;
build/obj/loader/loader_v4m.o(.text*)
. = NEXT(1024);
*(.vectors)
. = ALIGN(4096);
} > SYSRAM
.loader_ro : {
*(.text*)
*(.rodata*)
. = ALIGN(8);
__CONST_START__ = .;
. = ALIGN(16);
*(.qoswt_tbl)
. = ALIGN(8);
*(.qosbw_tbl)
. = ALIGN(8);
*(.constdata.CONFIG_DATA)
. = ALIGN(8);
*(.rgid_w_tbl)
. = ALIGN(8);
*(.rgid_r_tbl)
. = ALIGN(8);
*(.rgid_m_tbl)
. = ALIGN(8);
*(.rgid_sec_tbl)
. = ALIGN(8);
*(.rgid_axi_tbl)
__RO_END_UNALIGNED__ = .;
. = NEXT(4096);
__RO_END__ = .;
__DATA_COPY_START__ = .;
} > SYSRAM
.data : {
__DATA_START__ = .;
*(.data*)
. = NEXT(16);
__DATA_END__ = .;
} > CXIPLDATA AT > SYSRAM
__DATA_SIZE__ = SIZEOF(.data);
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(Cx_loader_stack))
__STACKS_END__ = .;
} > CXIPLSTACK
.bss.SHARED_TOP : {
__SHARED_TOP_START__ = .;
*(.bss.SHARED_TOP)
*(.bss.SHARED_LCS)
*(.bss.SHARED_CMAC)
*(.bss.SHARED_HASH)
. = NEXT(0x00200000);
__SHARED__END__ = .;
} > SHARED_SDRAM
.SHARED_RAM : {
__FWRAM_START__ = .;
. += 0;
. = NEXT(0x0000C000);
__FWRAM_END__ = .;
} > SHARED_RAM
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} > CXIPLDATA
__BSS_SIZE__ = SIZEOF(.bss);
}

48
IPL/Customer/Mobis/V4H_Cx_Loader/loader/stack.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Make up stack space
******************************************************************************/
/******************************************************************************
* @file stack.S
* - Version : 0.04
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.02.2022 0.01 First Release
* : 21.02.2022 0.02 Changed stacks name
* : 09.05.2022 0.03 Changed stacks name
* : 31.10.2022 0.04 License notation change.
*****************************************************************************/
.section Cx_loader_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end