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woody
2025-12-24 17:21:08 +09:00
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commit 96dc62d8dc
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271
IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/ram_protection.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : memory protection function
******************************************************************************/
/******************************************************************************
* @file ram_protection.c
* - Version : 0.03
* @brief Access protection setting of memory.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 19.12.2022 0.01 First Release
* : 11.01.2024 0.02 Added icu_remove_write_access function.
* : 19.01.2024 0.03 Updated debug log.
* : 31.01.2024 0.04 Fixed the error in SECDIVn register
* setting value for ram_protect_init_4_rtsram()
* and ram_protect_init_4_rtvram.
*****************************************************************************/
#include <stdint.h>
#include <access_protection.h>
#include <ram_protection.h>
#include <mem_io.h>
#include <log.h>
#include <axmm_register.h>
#include <rtvram_register.h>
#include <rtsram_register.h>
#include <cnf_tbl.h>
/* Value for calculating the offset address to set in SECDIVD. */
#define RTSRAM_SECDIVD_SUBVALUE (0xE0000000U) /* RT-VRAM0 Base address */
#define RTVRAM_SECDIVD_SUBVALUE (0xE2000000U) /* RT-VRAM1 Base address */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
static void ram_protect_init_4_rtsram(void);
static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl);
static void ram_protect_init_4_sysram(void);
static void ram_protect_init_4_dram(void);
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
void ram_protection(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
/* RT-SRAM */
NOTICE("RT-SRAM Protection setting...\n");
ram_protect_init_4_rtsram();
NOTICE("finish!\n");
/* RT-VRAM */
NOTICE("RT-VRAM Protection setting...\n");
ram_protect_init_4_rtvram(g_rtvram1_protection_table_1);
NOTICE("finish!\n");
/* System RAM */
NOTICE("System RAM Protection setting...\n");
ram_protect_init_4_sysram();
NOTICE("finish!\n");
/* DRAM */
NOTICE("DRAM Protection setting...\n");
ram_protect_init_4_dram();
NOTICE("finish!\n");
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function ram_protection(void) */
#if (RCAR_LSI == RCAR_S4)
void ram_protection_final(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
NOTICE("RT-VRAM Protection setting(finally)...\n");
ram_protect_init_4_rtvram(g_rtvram1_protection_table_2);
NOTICE("finish!\n");
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function ram_protection_final(void) */
#endif /* #if (RCAR_LSI == RCAR_S4) */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
static void ram_protect_init_4_rtsram(void)
{
uint32_t loop;
uint32_t val;
uint32_t set_val;
uint32_t addr;
/* set division point for RT-SRAM */
for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop)
{
addr = get_rtsram_secdivd_addr(loop);
val = mem_read32(addr);
val &= ~(RTSRAM_SECDIVD_DIVADDR_MASK);
set_val = g_rtsram_protection_table[loop + 1U].addr - RTSRAM_SECDIVD_SUBVALUE;
val |= ((set_val & RTSRAM_ADDR_OFFSET_MASK) >> 12U);
mem_write32(addr, val);
INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
/* Set division area protection register for RT-SRAM */
for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop)
{
/* Read Access Configuration */
addr = get_rtsram_secctrrd_addr(loop);
val = mem_read32(addr);
val &= ~(RTSRAM_SECCTRRD_SECGRP_MASK | RTSRAM_SECCTRRD_SAFGRP_MASK);
val |= g_rtsram_protection_table[loop].setting_value.read_val;
mem_write32(addr, val);
INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
/* Write Access Configuration */
addr = get_rtsram_secctrwd_addr(loop);
val = mem_read32(addr);
val &= ~(RTSRAM_SECCTRWD_SECGRP_MASK | RTSRAM_SECCTRWD_SAFGRP_MASK);
val |= g_rtsram_protection_table[loop].setting_value.write_val;
mem_write32(addr, val);
INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
}
/* End of function ram_protect_init_4_rtsram(void) */
static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl)
{
uint32_t loop;
uint32_t val;
uint32_t set_val;
uint32_t addr;
/* set division point for RT-VRAM1 */
for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop)
{
addr = get_rtvram_secdivd_addr(loop);
val = mem_read32(addr);
val &= ~(RTVRAM_SECDIVD_DIVADDR_MASK);
set_val = cnf_tbl[loop + 1U].addr - RTVRAM_SECDIVD_SUBVALUE;
val |= ((set_val & RTVRAM_ADDR_MASK) >> 12U);
mem_write32(addr, val);
INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
/* Set division area protection register for RT-VRAM1 */
for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop)
{
/* Read Access Configuration */
addr = get_rtvram_secctrrd_addr(loop);
val = mem_read32(addr);
val &= ~(RTVRAM_SECCTRRD_SECGRP_MASK | RTVRAM_SECCTRRD_SAFGRP_MASK);
val |= cnf_tbl[loop].setting_value.read_val;
mem_write32(addr, val);
INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
/* Write Access Configuration */
addr = get_rtvram_secctrwd_addr(loop);
val = mem_read32(addr);
val &= ~(RTVRAM_SECCTRWD_SECGRP_MASK | RTVRAM_SECCTRWD_SAFGRP_MASK);
val |= cnf_tbl[loop].setting_value.write_val;
mem_write32(addr, val);
INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
}
/* End of function ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl) */
static void ram_protect_init_4_sysram(void)
{
uint32_t loop;
uint32_t val;
uint32_t addr;
/* set division point for SystemRAM */
for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop)
{
addr = get_sptdivcr_addr(loop);
val = mem_read32(addr);
val &= ~(AXMM_SPTDIVCR_DIVADDR_MASK);
val |= ((g_system_ram_protection_table[loop + 1U].addr & SYSTEM_RAM_ADDR_MASK) >> 12U);
mem_write32(addr, val);
INFO("SPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
/* Set division area protection register for RT-VRAM */
for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop)
{
/* Read / Write Access Configuration */
addr = get_sptrgncr_addr(loop);
val = g_system_ram_protection_table[loop].setting_value.rw_val;
mem_write32(addr, val);
INFO("SPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
/* Secure setting */
addr = get_sptseccr_addr(loop);
val = mem_read32(addr);
val &= ~(AXMM_SPTSECCR_SECGRP_MASK | AXMM_SPTSECCR_SECGWP_MASK);
val |= g_system_ram_protection_table[loop].setting_value.sec_val;
mem_write32(addr, val);
INFO("SPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
}
/* End of function ram_protect_init_4_sysram(void) */
static void ram_protect_init_4_dram(void)
{
uint32_t loop;
uint32_t val;
uint32_t addr;
/* set division point for SDRAM */
for (loop = 0U; loop < (DRAM_PROTECTION_MAX - 1U); ++loop)
{
addr = get_dptdivcr_addr(loop);
val = mem_read32(addr);
val &= ~(AXMM_DPTDIVCR_DIVADDR_MASK);
val |= ((g_dram_protection_table[loop + 1U].addr & SDRAM_ADDR_MASK) >> 16U);
mem_write32(addr, val);
INFO("DPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
/* Set division area protection register for RT-VRAM */
for (loop = 0U; loop < DRAM_PROTECTION_MAX; ++loop)
{
/* Read / Write Access Configuration */
addr = get_dptrgncr_addr(loop);
val = g_dram_protection_table[loop].setting_value.rw_val;
mem_write32(addr, val);
INFO("DPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
/* Secure setting */
addr = get_dptseccr_addr(loop);
val = mem_read32(addr);
val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK);
val |= g_dram_protection_table[loop].setting_value.sec_val;
mem_write32(addr, val);
INFO("DPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr));
}
}
/* End of function ram_protect_init_4_dram(void) */
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
void icu_remove_write_access(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
uint32_t reg;
uint32_t addr;
addr = get_sptrgncr_addr(SYSTEM_RAM_CX_2ND_IPL);
reg = mem_read32(addr);
reg |= REGIONID0_WRITE_PRIVILEGE; /* Remove write privilege to System RAM Area0 from RGID0(ICUMX). */
mem_write32(addr, reg);
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function icu_remove_write_access(void) */

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/region_id.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Region ID protection function
******************************************************************************/
/******************************************************************************
* @file region_id.c
* - Version : 0.08
* @brief Each module to R/W access protection by Region ID.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.03.2022 0.01 First Release
* : 23.05.2022 0.02 Modify remap address
* : 21.10.2022 0.03 Supported for V4H
* : 23.01.2023 0.04 Remove pre-process branch for S4N.
* Added a process for judgement the number of
* Clusters to the rgid_gid_setting function.
* Changed to temporarily sweeten the protection
* setting only when the IPL is running.
* : 21.08.2023 0.05 Add support for V4M.
* : 13.11.2023 0.06 Changed to use CCI MPU GID register setting
* table in rgid_gid_setting function.
* : 13.09.2024 0.07 Change setting order of Region ID.
* (Swap Write and Secure.)
* : 06.01.2025 0.08 Added IMP Region ID setting process.
* Added Domain protection setting process.
* Added IPMMU Region ID setting process.
*****************************************************************************/
#include <access_protection.h>
#include <cnf_tbl.h>
#include <remap.h>
#include <mem_io.h>
#include <micro_wait.h>
#include <dma_register.h>
#include <wdt.h>
#include <log.h>
#include <rcar_def.h>
#include <image_load.h>
#include <cpg.h>
#include <cpg_register.h>
#include <pfc.h>
#include <pfc_register.h>
#include <sysc.h>
/* Unregistered base address of Region ID in SIC Remap. */
#if (RCAR_LSI == RCAR_S4)
#define RGID_SICREMAP_NUM (1U)
#define RGID_BASE1 (0xFF800000U)
#define GID_SETTING_VALUE (0x0002BFC4U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define RGID_SICREMAP_NUM (5U)
#define RGID_BASE1 (0xFD800000U)
#define RGID_BASE2 (0xE7A00000U)
#define RGID_BASE3 (0xEB800000U)
#define RGID_BASE4 (0xFE600000U)
#define RGID_BASE5 (0xFF800000U)
/* For IPMMU Region ID setting */
#define RGID_IPMMU_SICREMAP_NUM (3U)
#define RGID_IPMMU_BASE1 (0xEE400000U)
#define RGID_IPMMU_BASE2 (0xEEC00000U)
#define RGID_IPMMU_BASE3 (0xEEE00000U)
#endif
#define RGID_M_SDHI (38U)
#define RGIDMEN_RTDM_BASE (0xFD441800U) /* 0xFFC41800:Remap 10 */
#define RGIDMEN_SYDM_BASE (0xFCB51800U) /* 0xE7751800:Remap 5 */
#define RGIDMEN_RGIDEN_MASK (0x0000FFFFU)
#define GID_BASE (0xF12F0000U)
#if (RCAR_LSI == RCAR_V4H)
#define IMP_IMPSLV_PRESET (0xFF902000U) /* PRESET Register (IMPSLV) */
#define IMPSLV_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */
#define IMP_SPMI_PRESET (0xFFA8E000U) /* PRESET Register (SPMI) */
#define SPMI_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */
#define IMP_SPMI_MBCTRL120 (0xFFA8C868U) /* Master Bus ConTRoL120 (SPMI) */
#define SPMI_MBCTRL120_INIT_SET_VAL (0x00030000U) /* Initial set value */
#define IMP_SPMI_MBCTRL130 (0xFFA8D028U) /* Master Bus ConTRoL130 (SPMI) */
#define SPMI_MBCTRL130_INIT_SET_VAL (0x00030000U) /* Initial set value */
#define IMP_SPMC_PRESET (0xFFAB2000U) /* PRESET Register (SPMC) */
#define SPMC_PRESET_INIT_SET_VAL (0x00000009U) /* Initial set value */
#endif /* (RCAR_LSI == RCAR_V4H) */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
static void rgid_rtdma_master_setting(void);
static void rgid_sysdma_master_setting(void);
static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch);
static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch);
static void rgid_gid_setting(void);
#if (RCAR_SA9_TYPE == FLASH_BOOT)
static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid);
#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
static void set_rgid_master(uint32_t id, uint32_t val);
#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
static void rgid_register_protection(void);
static void domain_protection_setting(void);
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
void rgid_protection(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
uint32_t loop;
REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
#endif
};
REMAP_TABLE ipmmu_rgid_remap_tbl[RGID_IPMMU_SICREMAP_NUM] = {
{RGID_IPMMU_BASE1, 0U},
{RGID_IPMMU_BASE2, 0U},
{RGID_IPMMU_BASE3, 0U},
};
/* Set domain protection registers */
domain_protection_setting();
/* Set RGID of DMA (Master) */
rgid_rtdma_master_setting();
rgid_sysdma_master_setting();
/* Set RGID of GID */
rgid_gid_setting();
/* Register of IPMMU Region ID Base */
for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++)
{
remap_register(ipmmu_rgid_remap_tbl[loop].base_addr, &ipmmu_rgid_remap_tbl[loop].rmp_addr);
}
/* IPMMU Region ID setting */
for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
{
/* Set access protection setting value of IPMMU */
mem_write32(g_ipmmu_rgid_tbl[loop].addr, g_ipmmu_rgid_tbl[loop].value);
INFO("IMRGID_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_tbl[loop].addr, mem_read32(g_ipmmu_rgid_tbl[loop].addr), g_ipmmu_rgid_tbl[loop].value);
}
for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
{
/* Set access protection setting value of IPMMU Secure */
mem_write32(g_ipmmu_rgid_sec_tbl[loop].addr, g_ipmmu_rgid_sec_tbl[loop].value);
INFO("IMSECGRP_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_sec_tbl[loop].addr, mem_read32(g_ipmmu_rgid_sec_tbl[loop].addr), g_ipmmu_rgid_sec_tbl[loop].value);
}
for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
{
/* Set access protection setting value of IPMMU Region ID Enable */
mem_write32(g_ipmmu_rgid_en_tbl[loop].addr, g_ipmmu_rgid_en_tbl[loop].value);
INFO("IMRGIDEN_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_en_tbl[loop].addr, mem_read32(g_ipmmu_rgid_en_tbl[loop].addr), g_ipmmu_rgid_en_tbl[loop].value);
}
/* Unregister of IPMMU Region ID Base */
for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++)
{
remap_unregister(ipmmu_rgid_remap_tbl[loop].rmp_addr);
}
/* Register of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
}
#if (RCAR_LSI == RCAR_V4H)
/* For the IMP Region ID setting flow, see "Table U34.3" in */
/* "R-Car Series, V4H Series User's Manual". */
/* Following setting is described as step7 in "Table U34.3". */
mem_write32(IMP_IMPSLV_PRESET, IMPSLV_PRESET_INIT_SET_VAL);
mem_write32(IMP_SPMI_PRESET, SPMI_PRESET_INIT_SET_VAL);
mem_write32(IMP_SPMI_MBCTRL120, SPMI_MBCTRL120_INIT_SET_VAL);
mem_write32(IMP_SPMI_MBCTRL130, SPMI_MBCTRL130_INIT_SET_VAL);
mem_write32(IMP_SPMC_PRESET, SPMC_PRESET_INIT_SET_VAL);
/* IMP Region ID setting */
for(loop = 0U; loop < IMP_MASTER_MAX; loop++)
{
/* Set access protection setting value of IMP (Master) */
mem_write32(g_imp_rgid_m_tbl[loop].addr, g_imp_rgid_m_tbl[loop].value);
INFO("IMP_Master[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_m_tbl[loop].addr, mem_read32(g_imp_rgid_m_tbl[loop].addr), g_imp_rgid_m_tbl[loop].value);
}
for(loop = 0U; loop < IMP_SLAVE_MAX; loop++)
{
/* Set access protection setting value of IMP (Slave) */
mem_write32(g_imp_rgid_s_tbl[loop].addr, g_imp_rgid_s_tbl[loop].value);
INFO("IMP_Slave[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_s_tbl[loop].addr, mem_read32(g_imp_rgid_s_tbl[loop].addr), g_imp_rgid_s_tbl[loop].value);
}
#endif /* (RCAR_LSI == RCAR_V4H) */
for(loop = 0U; loop < RGID_M_MAX; loop++)
{
/* Set access protection setting value of Region ID (Master) */
mem_write32(g_rgid_m_tbl[loop].addr, g_rgid_m_tbl[loop].value);
INFO("RGIDM[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_m_tbl[loop].addr, mem_read32(g_rgid_m_tbl[loop].addr), g_rgid_m_tbl[loop].value);
}
for(loop = 0U; loop < RGID_R_MAX; loop++)
{
/* Set access protection setting value of Region ID (READ) */
mem_write32(g_rgid_r_tbl[loop].addr, g_rgid_r_tbl[loop].value); /* Read */
INFO("RGIDR[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_r_tbl[loop].addr, mem_read32(g_rgid_r_tbl[loop].addr), g_rgid_r_tbl[loop].value);
}
wdt_restart();
for(loop = 0U; loop < RGID_SEC_MAX; loop++)
{
/* Set access protection setting value of Region ID (Secure) */
mem_write32(g_rgid_sec_tbl[loop].addr, g_rgid_sec_tbl[loop].value); /* Secure */
INFO("SEC_MODID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_sec_tbl[loop].addr, mem_read32(g_rgid_sec_tbl[loop].addr), g_rgid_sec_tbl[loop].value);
}
wdt_restart();
for(loop = 0U; loop < RGID_W_MAX; loop++)
{
/* Set access protection setting value of Region ID (Write) */
mem_write32(g_rgid_w_tbl[loop].addr, g_rgid_w_tbl[loop].value); /* Write */
INFO("RGIDW[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_w_tbl[loop].addr, mem_read32(g_rgid_w_tbl[loop].addr), g_rgid_w_tbl[loop].value);
}
wdt_restart();
/* Unregister of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_unregister(rgid_remap_tbl[loop].rmp_addr);
}
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function rgid_protection(void) */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
static void rgid_rtdma_master_setting(void)
{
uint32_t addr;
uint32_t val;
/* Region ID(Master) RT-DMAC set:Region ID (i = 0-3(S4/V4H) 0-1(V4M), j = 0-15) */
for(uint32_t module = 0U; module < RTDMA_MODULE_MAX; module++) {
for(uint32_t ch = 0U; ch < RTDMA_CH_MAX; ch++) {
addr = get_rgidmen_rtdm_addr(module, ch);
val = mem_read32(addr);
val &= ~(RGIDMEN_RGIDEN_MASK);
val |= g_rgid_rtdma_setting_value[module][ch][0U];
mem_write32(addr, val);
INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
addr = dma_get_rtdma_regionid_addr(module, ch);
val = mem_read32(addr);
val &= ~(DMA_REGIONID_MASK);
val |= g_rgid_rtdma_setting_value[module][ch][1U];
mem_write32(addr, val);
INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
}
}
}
/* End of function rgid_rtdma_master_setting(void) */
static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch)
{
return (RGIDMEN_RTDM_BASE + (module * 0x40U) + (ch * 0x04U));
}
/* End of function get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) */
static void rgid_sysdma_master_setting(void)
{
uint32_t addr;
uint32_t val;
/* Region ID(Master) SYSDMAC set:Region ID (i = 0, j = 0-15)(i = 1, j = 0-15(S4/V4H) 0-7(V4M)) */
for(uint32_t module = 0U; module < SYSDMA_MODULE_MAX; module++) {
for(uint32_t ch = 0U; ch < SYSDMA_CH_MAX; ch++) {
if (g_rgid_sysdma_setting_value[module][ch][1U] != RGID_INVALID)
{
addr = get_rgidmen_sydm_addr(module, ch);
val = mem_read32(addr);
val &= ~(RGIDMEN_RGIDEN_MASK);
val |= g_rgid_sysdma_setting_value[module][ch][0U];
mem_write32(addr, val);
INFO("RGIDMEN_SYDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
addr = dma_get_sysdma_regionid_addr(module, ch);
val = mem_read32(addr);
val &= ~(DMA_REGIONID_MASK);
val |= g_rgid_sysdma_setting_value[module][ch][1U];
mem_write32(addr, val);
INFO("SDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
}
}
}
}
/* End of function rgid_sysdma_master_setting(void) */
static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch)
{
return (RGIDMEN_SYDM_BASE + (module * 0x40U) + (ch * 0x04U));
}
/* End of function get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) */
static void rgid_gid_setting(void)
{
uint32_t rmp_addr;
/* Register of GID Base */
remap_register(GID_BASE, &rmp_addr);
for(uint32_t loop = 0U; loop < RGID_GID_MAX; loop++)
{
/* Set access protection setting value of CCI MPU GID register */
mem_write32(g_rgid_gid_tbl[loop].addr, g_rgid_gid_tbl[loop].value);
INFO("GID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_gid_tbl[loop].addr, mem_read32(g_rgid_gid_tbl[loop].addr), g_rgid_gid_tbl[loop].value);
}
/* Unregister of GID Base */
remap_unregister(rmp_addr);
}
/* End of function rgid_gid_setting(void) */
#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
/* Change the Region ID of the Master to be used for the transfer to the value of the argument. */
void set_master_rgid_4_tfr_mod(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
#if (RCAR_SA9_TYPE == FLASH_BOOT)
uint32_t module;
uint32_t ch;
module = 0U;
ch = 0U;
set_rgid_rtdma_master(module, ch, RGID_0);
#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
set_rgid_master(RGID_M_SDHI, RGID_0);
#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function set_master_rgid_4_tfr_mod(void) */
/* Set the final expected value of Region ID. */
void rgid_protection_final(void)
{
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
#if (RCAR_SA9_TYPE == FLASH_BOOT)
/* Updated Master authority for RT-DMA. */
rgid_rtdma_master_setting();
#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
/* Updated Master authority for SDHI. */
set_rgid_master(RGID_M_SDHI, RGID_2);
#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
/* Access protection setting function for AXI bus of Region ID register */
rgid_register_protection();
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
}
/* End of function rgid_protection_final(void) */
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
#if (RCAR_SA9_TYPE == FLASH_BOOT)
static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid)
{
uint32_t addr;
uint32_t val;
/* Region ID(Master) RT-DMAC set:Region ID */
addr = get_rgidmen_rtdm_addr(module, ch);
val = mem_read32(addr);
val |= (1UL << rgid);
mem_write32(addr, val);
INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
addr = dma_get_rtdma_regionid_addr(module, ch);
val = mem_read32(addr);
val &= ~(DMA_REGIONID_MASK);
val |= rgid;
mem_write32(addr, val);
INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
}
/* End of function set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) */
#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */
/* Individual setting function of RGIDM register */
static void set_rgid_master(uint32_t id, uint32_t rgid)
{
#if (RCAR_LSI == RCAR_S4)
uint32_t loop;
REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
};
/* Register of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
}
/* Set access protection setting value of Region ID (Master) */
mem_write32(g_rgid_m_tbl[id].addr, rgid);
INFO("RGIDM[%d](0x%08x) =\t0x%08x\n", id, g_rgid_m_tbl[id].addr, mem_read32(g_rgid_m_tbl[id].addr));
/* Unregister of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_unregister(rgid_remap_tbl[loop].rmp_addr);
}
#endif /* #if (RCAR_LSI == RCAR_S4) */
}
/* End of function set_rgid_master(uint32_t id, uint32_t rgid) */
#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */
/* Access protection setting function for AXI bus of Region ID register */
static void rgid_register_protection(void)
{
uint32_t loop;
REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
};
/* Register of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
}
for(loop = 0U; loop < RGID_AXI_MAX; loop++)
{
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
mem_write32(g_rgid_axi_tbl[loop].addr, g_rgid_axi_tbl[loop].value);
INFO("RGID_AXI[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_axi_tbl[loop].addr, mem_read32(g_rgid_axi_tbl[loop].addr), g_rgid_axi_tbl[loop].value);
}
/* Unregister of Region ID Base */
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
{
remap_unregister(rgid_remap_tbl[loop].rmp_addr);
}
}
/* End of function rgid_register_protection(void) */
static void domain_protection_setting(void)
{
uint32_t loop;
/* Set CPG domain write access control register */
for(loop = 0U; loop <= CPG_PROTECTION; loop++)
{
cpg_reg_write((CPG_D1WACRA00 + (loop * 4U)), (CPG_D1WACRA00 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D2WACRA00 + (loop * 4U)), (CPG_D2WACRA00 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D3WACRA00 + (loop * 4U)), (CPG_D3WACRA00 + (loop * 4U)), WRITE_ENABLE);
}
/* Set PFC domain write access control register */
/* Port Group0 */
pfc_reg_write(PFC_DM1PR0_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR0_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR0_RW, WRITE_ENABLE);
/* Port Group1 */
pfc_reg_write(PFC_DM1PR1_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR1_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR1_RW, WRITE_ENABLE);
/* Port Group2 */
pfc_reg_write(PFC_DM1PR2_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR2_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR2_RW, WRITE_ENABLE);
/* Port Group3 */
pfc_reg_write(PFC_DM1PR3_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR3_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR3_RW, WRITE_ENABLE);
/* Port Group4 */
pfc_reg_write(PFC_DM1PR4_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR4_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR4_RW, WRITE_ENABLE);
/* Port Group5 */
pfc_reg_write(PFC_DM1PR5_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR5_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR5_RW, WRITE_ENABLE);
/* Port Group6 */
pfc_reg_write(PFC_DM1PR6_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR6_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR6_RW, WRITE_ENABLE);
/* Port Group7 */
pfc_reg_write(PFC_DM1PR7_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR7_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR7_RW, WRITE_ENABLE);
#if (RCAR_LSI == RCAR_V4H)
/* Port Group8 */
pfc_reg_write(PFC_DM1PR8_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PR8_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PR8_RW, WRITE_ENABLE);
#endif/* #if (RCAR_LSI == RCAR_V4H) */
/* System Group */
pfc_reg_write(PFC_DM1PRSYS_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM2PRSYS_RW, WRITE_ENABLE);
pfc_reg_write(PFC_DM3PRSYS_RW, WRITE_ENABLE);
/* Set SYSC domain write access control register */
for(loop = 0U; loop <= SYSC_PROTECTION; loop++)
{
mem_write32((SYSC_SYSCD1WACR0 + (loop * 4U)), WRITE_ENABLE);
mem_write32((SYSC_SYSCD2WACR0 + (loop * 4U)), WRITE_ENABLE);
mem_write32((SYSC_SYSCD3WACR0 + (loop * 4U)), WRITE_ENABLE);
}
/* Set Reset domain write access control register */
for(loop = 0U; loop <= RESET_PROTECTION; loop++)
{
cpg_reg_write((CPG_D1WACR_MSTPCR0 + (loop * 4U)), (CPG_D1WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D1WACR_RAHSR0 + (loop * 4U)), (CPG_D1WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D1WACR_SRCR0 + (loop * 4U)), (CPG_D1WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D1WACR_SRSTCLR0 + (loop * 4U)), (CPG_D1WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D2WACR_MSTPCR0 + (loop * 4U)), (CPG_D2WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D2WACR_RAHSR0 + (loop * 4U)), (CPG_D2WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D2WACR_SRCR0 + (loop * 4U)), (CPG_D2WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D2WACR_SRSTCLR0 + (loop * 4U)), (CPG_D2WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D3WACR_MSTPCR0 + (loop * 4U)), (CPG_D3WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D3WACR_RAHSR0 + (loop * 4U)), (CPG_D3WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D3WACR_SRCR0 + (loop * 4U)), (CPG_D3WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
cpg_reg_write((CPG_D3WACR_SRSTCLR0 + (loop * 4U)), (CPG_D3WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
}
}
/* End of function domain_protection_setting(void) */
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */

86
IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/stack_protect.c Normal file
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@@ -0,0 +1,86 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Stack protect function
******************************************************************************/
/******************************************************************************
* @file stack_protect.c
* - Version : 0.01
* @brief Check for Stack Smashing Attacks.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 31.01.2023 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <log.h>
/* Specify fixed canary value as reference implementation. */
#define CANARY_VAL (0xB9DFF6A0U)
#define STACK_PROTECT_ENABLE (1U)
/* Save canary to __stack_chk_guard. */
extern uintptr_t __stack_chk_guard;
__attribute__((section(".canary"))) uintptr_t __stack_chk_guard;
/* Prototype */
extern void __ghs_set_stack_chk_guard(void);
#if (STACK_PROTECT == STACK_PROTECT_ENABLE)
extern void __stack_chk_fail(void);
static inline uintptr_t *__ghs_get_stack_chk_guard_address(void);
#endif
void __ghs_set_stack_chk_guard(void)
{
#if (STACK_PROTECT == STACK_PROTECT_ENABLE)
/* Initialize the stack canary before any code that may require a stack canary. */
/* So don't add valiables larger than 8-bytes to this function. */
/* Don't call function that uses stack canaries from this function. */
/* If customize CANARY_VAL to random value, don't allow the function */
/* to be inlined or this function may require a canary. */
*__ghs_get_stack_chk_guard_address() = (uintptr_t)CANARY_VAL;
#endif
}
/* End of function __ghs_set_stack_chk_guard(void) */
#if (STACK_PROTECT == STACK_PROTECT_ENABLE)
static inline uintptr_t *__ghs_get_stack_chk_guard_address(void)
{
/* Don't modify this function. */
return &__stack_chk_guard;
}
/* End of function __ghs_get_stack_chk_guard_address(void) */
void __stack_chk_fail(void)
{
ERROR("Stack smashing detected\n");
panic;
}
/* End of function __stack_chk_fail(void) */
#endif /* (STACK_PROTECT == STACK_PROTECT_ENABLE) */