588 lines
23 KiB
C
588 lines
23 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Region ID protection function
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******************************************************************************/
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/******************************************************************************
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* @file region_id.c
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* - Version : 0.08
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* @brief Each module to R/W access protection by Region ID.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 03.03.2022 0.01 First Release
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* : 23.05.2022 0.02 Modify remap address
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* : 21.10.2022 0.03 Supported for V4H
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* : 23.01.2023 0.04 Remove pre-process branch for S4N.
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* Added a process for judgement the number of
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* Clusters to the rgid_gid_setting function.
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* Changed to temporarily sweeten the protection
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* setting only when the IPL is running.
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* : 21.08.2023 0.05 Add support for V4M.
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* : 13.11.2023 0.06 Changed to use CCI MPU GID register setting
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* table in rgid_gid_setting function.
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* : 13.09.2024 0.07 Change setting order of Region ID.
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* (Swap Write and Secure.)
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* : 06.01.2025 0.08 Added IMP Region ID setting process.
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* Added Domain protection setting process.
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* Added IPMMU Region ID setting process.
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*****************************************************************************/
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#include <access_protection.h>
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#include <cnf_tbl.h>
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#include <remap.h>
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#include <mem_io.h>
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#include <micro_wait.h>
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#include <dma_register.h>
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#include <wdt.h>
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#include <log.h>
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#include <rcar_def.h>
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#include <image_load.h>
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#include <cpg.h>
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#include <cpg_register.h>
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#include <pfc.h>
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#include <pfc_register.h>
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#include <sysc.h>
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/* Unregistered base address of Region ID in SIC Remap. */
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#if (RCAR_LSI == RCAR_S4)
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#define RGID_SICREMAP_NUM (1U)
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#define RGID_BASE1 (0xFF800000U)
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#define GID_SETTING_VALUE (0x0002BFC4U)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define RGID_SICREMAP_NUM (5U)
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#define RGID_BASE1 (0xFD800000U)
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#define RGID_BASE2 (0xE7A00000U)
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#define RGID_BASE3 (0xEB800000U)
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#define RGID_BASE4 (0xFE600000U)
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#define RGID_BASE5 (0xFF800000U)
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/* For IPMMU Region ID setting */
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#define RGID_IPMMU_SICREMAP_NUM (3U)
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#define RGID_IPMMU_BASE1 (0xEE400000U)
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#define RGID_IPMMU_BASE2 (0xEEC00000U)
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#define RGID_IPMMU_BASE3 (0xEEE00000U)
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#endif
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#define RGID_M_SDHI (38U)
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#define RGIDMEN_RTDM_BASE (0xFD441800U) /* 0xFFC41800:Remap 10 */
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#define RGIDMEN_SYDM_BASE (0xFCB51800U) /* 0xE7751800:Remap 5 */
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#define RGIDMEN_RGIDEN_MASK (0x0000FFFFU)
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#define GID_BASE (0xF12F0000U)
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#if (RCAR_LSI == RCAR_V4H)
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#define IMP_IMPSLV_PRESET (0xFF902000U) /* PRESET Register (IMPSLV) */
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#define IMPSLV_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */
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#define IMP_SPMI_PRESET (0xFFA8E000U) /* PRESET Register (SPMI) */
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#define SPMI_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */
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#define IMP_SPMI_MBCTRL120 (0xFFA8C868U) /* Master Bus ConTRoL120 (SPMI) */
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#define SPMI_MBCTRL120_INIT_SET_VAL (0x00030000U) /* Initial set value */
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#define IMP_SPMI_MBCTRL130 (0xFFA8D028U) /* Master Bus ConTRoL130 (SPMI) */
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#define SPMI_MBCTRL130_INIT_SET_VAL (0x00030000U) /* Initial set value */
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#define IMP_SPMC_PRESET (0xFFAB2000U) /* PRESET Register (SPMC) */
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#define SPMC_PRESET_INIT_SET_VAL (0x00000009U) /* Initial set value */
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#endif /* (RCAR_LSI == RCAR_V4H) */
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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static void rgid_rtdma_master_setting(void);
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static void rgid_sysdma_master_setting(void);
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static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch);
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static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch);
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static void rgid_gid_setting(void);
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#if (RCAR_SA9_TYPE == FLASH_BOOT)
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static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid);
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#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
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static void set_rgid_master(uint32_t id, uint32_t val);
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#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
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static void rgid_register_protection(void);
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static void domain_protection_setting(void);
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#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
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void rgid_protection(void)
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{
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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uint32_t loop;
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REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
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{RGID_BASE1, 0U},
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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{RGID_BASE2, 0U},
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{RGID_BASE3, 0U},
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{RGID_BASE4, 0U},
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{RGID_BASE5, 0U},
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#endif
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};
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REMAP_TABLE ipmmu_rgid_remap_tbl[RGID_IPMMU_SICREMAP_NUM] = {
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{RGID_IPMMU_BASE1, 0U},
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{RGID_IPMMU_BASE2, 0U},
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{RGID_IPMMU_BASE3, 0U},
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};
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/* Set domain protection registers */
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domain_protection_setting();
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/* Set RGID of DMA (Master) */
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rgid_rtdma_master_setting();
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rgid_sysdma_master_setting();
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/* Set RGID of GID */
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rgid_gid_setting();
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/* Register of IPMMU Region ID Base */
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for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++)
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{
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remap_register(ipmmu_rgid_remap_tbl[loop].base_addr, &ipmmu_rgid_remap_tbl[loop].rmp_addr);
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}
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/* IPMMU Region ID setting */
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for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
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{
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/* Set access protection setting value of IPMMU */
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mem_write32(g_ipmmu_rgid_tbl[loop].addr, g_ipmmu_rgid_tbl[loop].value);
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INFO("IMRGID_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_tbl[loop].addr, mem_read32(g_ipmmu_rgid_tbl[loop].addr), g_ipmmu_rgid_tbl[loop].value);
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}
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for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
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{
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/* Set access protection setting value of IPMMU Secure */
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mem_write32(g_ipmmu_rgid_sec_tbl[loop].addr, g_ipmmu_rgid_sec_tbl[loop].value);
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INFO("IMSECGRP_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_sec_tbl[loop].addr, mem_read32(g_ipmmu_rgid_sec_tbl[loop].addr), g_ipmmu_rgid_sec_tbl[loop].value);
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}
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for(loop = 0U; loop < IPMMU_RGID_MAX; loop++)
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{
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/* Set access protection setting value of IPMMU Region ID Enable */
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mem_write32(g_ipmmu_rgid_en_tbl[loop].addr, g_ipmmu_rgid_en_tbl[loop].value);
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INFO("IMRGIDEN_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_en_tbl[loop].addr, mem_read32(g_ipmmu_rgid_en_tbl[loop].addr), g_ipmmu_rgid_en_tbl[loop].value);
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}
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/* Unregister of IPMMU Region ID Base */
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for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++)
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{
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remap_unregister(ipmmu_rgid_remap_tbl[loop].rmp_addr);
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}
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/* Register of Region ID Base */
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for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
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{
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remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
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}
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#if (RCAR_LSI == RCAR_V4H)
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/* For the IMP Region ID setting flow, see "Table U34.3" in */
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/* "R-Car Series, V4H Series User's Manual". */
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/* Following setting is described as step7 in "Table U34.3". */
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mem_write32(IMP_IMPSLV_PRESET, IMPSLV_PRESET_INIT_SET_VAL);
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mem_write32(IMP_SPMI_PRESET, SPMI_PRESET_INIT_SET_VAL);
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mem_write32(IMP_SPMI_MBCTRL120, SPMI_MBCTRL120_INIT_SET_VAL);
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mem_write32(IMP_SPMI_MBCTRL130, SPMI_MBCTRL130_INIT_SET_VAL);
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mem_write32(IMP_SPMC_PRESET, SPMC_PRESET_INIT_SET_VAL);
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/* IMP Region ID setting */
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for(loop = 0U; loop < IMP_MASTER_MAX; loop++)
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{
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/* Set access protection setting value of IMP (Master) */
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mem_write32(g_imp_rgid_m_tbl[loop].addr, g_imp_rgid_m_tbl[loop].value);
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INFO("IMP_Master[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_m_tbl[loop].addr, mem_read32(g_imp_rgid_m_tbl[loop].addr), g_imp_rgid_m_tbl[loop].value);
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}
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for(loop = 0U; loop < IMP_SLAVE_MAX; loop++)
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{
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/* Set access protection setting value of IMP (Slave) */
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mem_write32(g_imp_rgid_s_tbl[loop].addr, g_imp_rgid_s_tbl[loop].value);
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INFO("IMP_Slave[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_s_tbl[loop].addr, mem_read32(g_imp_rgid_s_tbl[loop].addr), g_imp_rgid_s_tbl[loop].value);
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}
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#endif /* (RCAR_LSI == RCAR_V4H) */
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for(loop = 0U; loop < RGID_M_MAX; loop++)
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{
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/* Set access protection setting value of Region ID (Master) */
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mem_write32(g_rgid_m_tbl[loop].addr, g_rgid_m_tbl[loop].value);
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INFO("RGIDM[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_m_tbl[loop].addr, mem_read32(g_rgid_m_tbl[loop].addr), g_rgid_m_tbl[loop].value);
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}
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for(loop = 0U; loop < RGID_R_MAX; loop++)
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{
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/* Set access protection setting value of Region ID (READ) */
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mem_write32(g_rgid_r_tbl[loop].addr, g_rgid_r_tbl[loop].value); /* Read */
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INFO("RGIDR[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_r_tbl[loop].addr, mem_read32(g_rgid_r_tbl[loop].addr), g_rgid_r_tbl[loop].value);
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}
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wdt_restart();
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for(loop = 0U; loop < RGID_SEC_MAX; loop++)
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{
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/* Set access protection setting value of Region ID (Secure) */
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mem_write32(g_rgid_sec_tbl[loop].addr, g_rgid_sec_tbl[loop].value); /* Secure */
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INFO("SEC_MODID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_sec_tbl[loop].addr, mem_read32(g_rgid_sec_tbl[loop].addr), g_rgid_sec_tbl[loop].value);
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}
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wdt_restart();
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for(loop = 0U; loop < RGID_W_MAX; loop++)
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{
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/* Set access protection setting value of Region ID (Write) */
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mem_write32(g_rgid_w_tbl[loop].addr, g_rgid_w_tbl[loop].value); /* Write */
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INFO("RGIDW[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_w_tbl[loop].addr, mem_read32(g_rgid_w_tbl[loop].addr), g_rgid_w_tbl[loop].value);
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}
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wdt_restart();
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/* Unregister of Region ID Base */
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for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
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{
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remap_unregister(rgid_remap_tbl[loop].rmp_addr);
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}
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#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
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}
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/* End of function rgid_protection(void) */
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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static void rgid_rtdma_master_setting(void)
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{
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uint32_t addr;
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uint32_t val;
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/* Region ID(Master) RT-DMAC set:Region ID (i = 0-3(S4/V4H) 0-1(V4M), j = 0-15) */
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for(uint32_t module = 0U; module < RTDMA_MODULE_MAX; module++) {
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for(uint32_t ch = 0U; ch < RTDMA_CH_MAX; ch++) {
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addr = get_rgidmen_rtdm_addr(module, ch);
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val = mem_read32(addr);
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val &= ~(RGIDMEN_RGIDEN_MASK);
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val |= g_rgid_rtdma_setting_value[module][ch][0U];
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mem_write32(addr, val);
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INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
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addr = dma_get_rtdma_regionid_addr(module, ch);
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val = mem_read32(addr);
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val &= ~(DMA_REGIONID_MASK);
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val |= g_rgid_rtdma_setting_value[module][ch][1U];
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mem_write32(addr, val);
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INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
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}
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}
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}
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/* End of function rgid_rtdma_master_setting(void) */
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static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch)
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{
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return (RGIDMEN_RTDM_BASE + (module * 0x40U) + (ch * 0x04U));
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}
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/* End of function get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) */
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static void rgid_sysdma_master_setting(void)
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{
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uint32_t addr;
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uint32_t val;
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/* Region ID(Master) SYSDMAC set:Region ID (i = 0, j = 0-15)(i = 1, j = 0-15(S4/V4H) 0-7(V4M)) */
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for(uint32_t module = 0U; module < SYSDMA_MODULE_MAX; module++) {
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for(uint32_t ch = 0U; ch < SYSDMA_CH_MAX; ch++) {
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if (g_rgid_sysdma_setting_value[module][ch][1U] != RGID_INVALID)
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{
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addr = get_rgidmen_sydm_addr(module, ch);
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val = mem_read32(addr);
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val &= ~(RGIDMEN_RGIDEN_MASK);
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val |= g_rgid_sysdma_setting_value[module][ch][0U];
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mem_write32(addr, val);
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INFO("RGIDMEN_SYDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
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addr = dma_get_sysdma_regionid_addr(module, ch);
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val = mem_read32(addr);
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val &= ~(DMA_REGIONID_MASK);
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val |= g_rgid_sysdma_setting_value[module][ch][1U];
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mem_write32(addr, val);
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INFO("SDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
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}
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}
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}
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}
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/* End of function rgid_sysdma_master_setting(void) */
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static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch)
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{
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return (RGIDMEN_SYDM_BASE + (module * 0x40U) + (ch * 0x04U));
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}
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/* End of function get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) */
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static void rgid_gid_setting(void)
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{
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uint32_t rmp_addr;
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/* Register of GID Base */
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remap_register(GID_BASE, &rmp_addr);
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for(uint32_t loop = 0U; loop < RGID_GID_MAX; loop++)
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{
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/* Set access protection setting value of CCI MPU GID register */
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mem_write32(g_rgid_gid_tbl[loop].addr, g_rgid_gid_tbl[loop].value);
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INFO("GID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_gid_tbl[loop].addr, mem_read32(g_rgid_gid_tbl[loop].addr), g_rgid_gid_tbl[loop].value);
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}
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/* Unregister of GID Base */
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remap_unregister(rmp_addr);
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}
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/* End of function rgid_gid_setting(void) */
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#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
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/* Change the Region ID of the Master to be used for the transfer to the value of the argument. */
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void set_master_rgid_4_tfr_mod(void)
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{
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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#if (RCAR_SA9_TYPE == FLASH_BOOT)
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uint32_t module;
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uint32_t ch;
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module = 0U;
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ch = 0U;
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set_rgid_rtdma_master(module, ch, RGID_0);
|
|
#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
set_rgid_master(RGID_M_SDHI, RGID_0);
|
|
#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
|
|
}
|
|
/* End of function set_master_rgid_4_tfr_mod(void) */
|
|
|
|
/* Set the final expected value of Region ID. */
|
|
void rgid_protection_final(void)
|
|
{
|
|
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
|
#if (RCAR_SA9_TYPE == FLASH_BOOT)
|
|
/* Updated Master authority for RT-DMA. */
|
|
rgid_rtdma_master_setting();
|
|
#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
/* Updated Master authority for SDHI. */
|
|
set_rgid_master(RGID_M_SDHI, RGID_2);
|
|
#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
/* Access protection setting function for AXI bus of Region ID register */
|
|
rgid_register_protection();
|
|
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
|
|
}
|
|
/* End of function rgid_protection_final(void) */
|
|
|
|
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
|
#if (RCAR_SA9_TYPE == FLASH_BOOT)
|
|
static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid)
|
|
{
|
|
uint32_t addr;
|
|
uint32_t val;
|
|
|
|
/* Region ID(Master) RT-DMAC set:Region ID */
|
|
addr = get_rgidmen_rtdm_addr(module, ch);
|
|
val = mem_read32(addr);
|
|
val |= (1UL << rgid);
|
|
mem_write32(addr, val);
|
|
|
|
INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
|
|
|
|
addr = dma_get_rtdma_regionid_addr(module, ch);
|
|
val = mem_read32(addr);
|
|
val &= ~(DMA_REGIONID_MASK);
|
|
val |= rgid;
|
|
mem_write32(addr, val);
|
|
|
|
INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val);
|
|
}
|
|
/* End of function set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) */
|
|
#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
/* Individual setting function of RGIDM register */
|
|
static void set_rgid_master(uint32_t id, uint32_t rgid)
|
|
{
|
|
#if (RCAR_LSI == RCAR_S4)
|
|
uint32_t loop;
|
|
|
|
REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
|
|
{RGID_BASE1, 0U},
|
|
};
|
|
|
|
/* Register of Region ID Base */
|
|
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
|
|
{
|
|
remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
|
|
}
|
|
|
|
/* Set access protection setting value of Region ID (Master) */
|
|
mem_write32(g_rgid_m_tbl[id].addr, rgid);
|
|
INFO("RGIDM[%d](0x%08x) =\t0x%08x\n", id, g_rgid_m_tbl[id].addr, mem_read32(g_rgid_m_tbl[id].addr));
|
|
|
|
/* Unregister of Region ID Base */
|
|
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
|
|
{
|
|
remap_unregister(rgid_remap_tbl[loop].rmp_addr);
|
|
}
|
|
#endif /* #if (RCAR_LSI == RCAR_S4) */
|
|
}
|
|
/* End of function set_rgid_master(uint32_t id, uint32_t rgid) */
|
|
#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */
|
|
|
|
/* Access protection setting function for AXI bus of Region ID register */
|
|
static void rgid_register_protection(void)
|
|
{
|
|
uint32_t loop;
|
|
|
|
REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = {
|
|
{RGID_BASE1, 0U},
|
|
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
|
{RGID_BASE2, 0U},
|
|
{RGID_BASE3, 0U},
|
|
{RGID_BASE4, 0U},
|
|
{RGID_BASE5, 0U},
|
|
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
|
};
|
|
|
|
/* Register of Region ID Base */
|
|
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
|
|
{
|
|
remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr);
|
|
}
|
|
|
|
for(loop = 0U; loop < RGID_AXI_MAX; loop++)
|
|
{
|
|
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
|
|
mem_write32(g_rgid_axi_tbl[loop].addr, g_rgid_axi_tbl[loop].value);
|
|
|
|
INFO("RGID_AXI[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_axi_tbl[loop].addr, mem_read32(g_rgid_axi_tbl[loop].addr), g_rgid_axi_tbl[loop].value);
|
|
}
|
|
|
|
/* Unregister of Region ID Base */
|
|
for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++)
|
|
{
|
|
remap_unregister(rgid_remap_tbl[loop].rmp_addr);
|
|
}
|
|
}
|
|
/* End of function rgid_register_protection(void) */
|
|
|
|
static void domain_protection_setting(void)
|
|
{
|
|
uint32_t loop;
|
|
|
|
/* Set CPG domain write access control register */
|
|
for(loop = 0U; loop <= CPG_PROTECTION; loop++)
|
|
{
|
|
cpg_reg_write((CPG_D1WACRA00 + (loop * 4U)), (CPG_D1WACRA00 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D2WACRA00 + (loop * 4U)), (CPG_D2WACRA00 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D3WACRA00 + (loop * 4U)), (CPG_D3WACRA00 + (loop * 4U)), WRITE_ENABLE);
|
|
}
|
|
|
|
/* Set PFC domain write access control register */
|
|
/* Port Group0 */
|
|
pfc_reg_write(PFC_DM1PR0_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR0_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR0_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group1 */
|
|
pfc_reg_write(PFC_DM1PR1_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR1_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR1_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group2 */
|
|
pfc_reg_write(PFC_DM1PR2_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR2_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR2_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group3 */
|
|
pfc_reg_write(PFC_DM1PR3_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR3_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR3_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group4 */
|
|
pfc_reg_write(PFC_DM1PR4_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR4_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR4_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group5 */
|
|
pfc_reg_write(PFC_DM1PR5_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR5_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR5_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group6 */
|
|
pfc_reg_write(PFC_DM1PR6_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR6_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR6_RW, WRITE_ENABLE);
|
|
|
|
/* Port Group7 */
|
|
pfc_reg_write(PFC_DM1PR7_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR7_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR7_RW, WRITE_ENABLE);
|
|
|
|
#if (RCAR_LSI == RCAR_V4H)
|
|
/* Port Group8 */
|
|
pfc_reg_write(PFC_DM1PR8_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PR8_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PR8_RW, WRITE_ENABLE);
|
|
#endif/* #if (RCAR_LSI == RCAR_V4H) */
|
|
|
|
/* System Group */
|
|
pfc_reg_write(PFC_DM1PRSYS_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM2PRSYS_RW, WRITE_ENABLE);
|
|
pfc_reg_write(PFC_DM3PRSYS_RW, WRITE_ENABLE);
|
|
|
|
/* Set SYSC domain write access control register */
|
|
for(loop = 0U; loop <= SYSC_PROTECTION; loop++)
|
|
{
|
|
mem_write32((SYSC_SYSCD1WACR0 + (loop * 4U)), WRITE_ENABLE);
|
|
mem_write32((SYSC_SYSCD2WACR0 + (loop * 4U)), WRITE_ENABLE);
|
|
mem_write32((SYSC_SYSCD3WACR0 + (loop * 4U)), WRITE_ENABLE);
|
|
}
|
|
|
|
/* Set Reset domain write access control register */
|
|
for(loop = 0U; loop <= RESET_PROTECTION; loop++)
|
|
{
|
|
cpg_reg_write((CPG_D1WACR_MSTPCR0 + (loop * 4U)), (CPG_D1WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D1WACR_RAHSR0 + (loop * 4U)), (CPG_D1WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D1WACR_SRCR0 + (loop * 4U)), (CPG_D1WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D1WACR_SRSTCLR0 + (loop * 4U)), (CPG_D1WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D2WACR_MSTPCR0 + (loop * 4U)), (CPG_D2WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D2WACR_RAHSR0 + (loop * 4U)), (CPG_D2WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D2WACR_SRCR0 + (loop * 4U)), (CPG_D2WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D2WACR_SRSTCLR0 + (loop * 4U)), (CPG_D2WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D3WACR_MSTPCR0 + (loop * 4U)), (CPG_D3WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D3WACR_RAHSR0 + (loop * 4U)), (CPG_D3WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D3WACR_SRCR0 + (loop * 4U)), (CPG_D3WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE);
|
|
cpg_reg_write((CPG_D3WACR_SRSTCLR0 + (loop * 4U)), (CPG_D3WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE);
|
|
}
|
|
}
|
|
/* End of function domain_protection_setting(void) */
|
|
#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */
|
|
|