woody/Tool
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add IPL

Browse Source
This commit is contained in:
woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

228
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.c Normal file
View File

@@ -0,0 +1,228 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Control ECC and Address parity check for CodeSRAM
******************************************************************************/
/******************************************************************************
* @file codesram_ecc.c
* - Version : 0.01
* @brief 1. Enable / Disable ECC and Address parity check for CodeSRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 19.01.2023 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <codesram_ecc.h>
#include <mem_io.h>
#include <log.h>
#include <mcu_register.h>
#include <cpu_on_for_mcu.h>
#define CSRM_ECCCTL_EMCA_EN_MOD (0x00004000U)
#define CSRM_ECCCTL_APERR (0x00001000U)
#define CSRM_ECCCTL_ECERVF (0x00000040U)
#define CSRM_ECCCTL_EC1ECP (0x00000020U)
#define CSRM_ECCCTL_ECER2F (0x00000004U)
#define CSRM_ECCCTL_ECER1F (0x00000002U)
#define CSRM_APCTL_APCEN (0x00000001U)
#define CSRM_NO_ERROR (0x00000000U)
#define CODESRAM_BUS_NUM_SHIFT (20U)
void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
{
uint32_t loop;
uint32_t bus_num;
uint32_t set_num;
uint32_t reg;
/* Code-SRAMn ECC Control Register */
const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
MCU_CSRM1ECCCTL,
MCU_CSRM2ECCCTL,
MCU_CSRM3ECCCTL,
MCU_CSRM4ECCCTL,
MCU_CSRM5ECCCTL};
/* Code-SRAMn Address Parity Control Register */
const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
MCU_CSRM1APCTL,
MCU_CSRM2APCTL,
MCU_CSRM3APCTL,
MCU_CSRM4APCTL,
MCU_CSRM5APCTL};
/* Calculate the area used by Code SRAM. */
bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
for (loop = 0U; loop < set_num; loop++)
{
/* Disable ECC error detection and error correction for CodeSRAM. */
reg = mem_read32(eccctl_reg[bus_num + loop]);
reg &= ~(CSRM_ECCCTL_ECERVF);
reg |= CSRM_ECCCTL_EMCA_EN_MOD;
reg |= CSRM_ECCCTL_EC1ECP;
mem_write32(eccctl_reg[bus_num + loop], reg);
/* Disable Address parity check for CodeSRAM. */
reg = mem_read32(apctl_reg[bus_num + loop]);
reg &= ~(CSRM_APCTL_APCEN);
mem_write32(apctl_reg[bus_num + loop], reg);
}
}
/* End of function disable_codesram_ecc_parity */
void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
{
uint32_t loop;
uint32_t bus_num;
uint32_t set_num;
uint32_t reg;
/* Code-SRAMn ECC Control Register */
const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
MCU_CSRM1ECCCTL,
MCU_CSRM2ECCCTL,
MCU_CSRM3ECCCTL,
MCU_CSRM4ECCCTL,
MCU_CSRM5ECCCTL};
/* Code-SRAMn Address Parity Control Register */
const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
MCU_CSRM1APCTL,
MCU_CSRM2APCTL,
MCU_CSRM3APCTL,
MCU_CSRM4APCTL,
MCU_CSRM5APCTL};
/* Calculate the area used by Code SRAM. */
bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
for (loop = 0U; loop < set_num; loop++)
{
/* Enable ECC error detection and error correction for CodeSRAM. */
reg = mem_read32(eccctl_reg[bus_num + loop]);
reg &= ~(CSRM_ECCCTL_EC1ECP);
reg |= CSRM_ECCCTL_ECERVF;
reg |= CSRM_ECCCTL_EMCA_EN_MOD;
mem_write32(eccctl_reg[bus_num + loop], reg);
/* Enable Address parity check for CodeSRAM. */
reg = mem_read32(apctl_reg[bus_num + loop]);
reg |= CSRM_APCTL_APCEN;
mem_write32(apctl_reg[bus_num + loop], reg);
}
}
/* End of function enable_codesram_ecc_parity */
void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
{
uint32_t loop;
uint32_t bus_num;
uint32_t set_num;
uint32_t reg;
uint32_t err_chk;
/* Code-SRAMn ECC Control Register */
const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
MCU_CSRM1ECCCTL,
MCU_CSRM2ECCCTL,
MCU_CSRM3ECCCTL,
MCU_CSRM4ECCCTL,
MCU_CSRM5ECCCTL};
/* Calculate the area used by Code SRAM. */
bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
/* Check ECC error and Address parity error for CodeSRAM. */
for (loop = 0U; loop < set_num; loop++)
{
reg = mem_read32(eccctl_reg[bus_num + loop]);
err_chk = reg;
err_chk &= (CSRM_ECCCTL_ECER2F | CSRM_ECCCTL_ECER1F);
if(err_chk != CSRM_NO_ERROR)
{
/* ECC error occurred. */
ERROR("CodeSRAM ECC error detected !!\n");
panic;
}
err_chk = reg;
err_chk &= CSRM_ECCCTL_APERR;
if(err_chk != CSRM_NO_ERROR)
{
/* Address parity error occurred. */
ERROR("CodeSRAM Address parity error detected !!\n");
panic;
}
}
}
/* End of function chk_codesram_ecc_parity */
void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
{
uint32_t loop;
uint32_t bus_num;
uint32_t set_num;
uint32_t reg;
/* Code-SRAMn ECC Control Register */
const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
MCU_CSRM1ECCCTL,
MCU_CSRM2ECCCTL,
MCU_CSRM3ECCCTL,
MCU_CSRM4ECCCTL,
MCU_CSRM5ECCCTL};
/* Code-SRAMn Address Parity Control Register */
const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
MCU_CSRM1APCTL,
MCU_CSRM2APCTL,
MCU_CSRM3APCTL,
MCU_CSRM4APCTL,
MCU_CSRM5APCTL};
/* Calculate the area used by Code SRAM. */
bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
for (loop = 0U; loop < set_num; loop++)
{
/* Initialize ECC error detection and error correction setting for CodeSRAM. */
reg = mem_read32(eccctl_reg[bus_num + loop]);
reg &= ~(CSRM_ECCCTL_EC1ECP | CSRM_ECCCTL_ECERVF);
reg |= CSRM_ECCCTL_EMCA_EN_MOD;
mem_write32(eccctl_reg[bus_num + loop], reg);
/* Initialize Address parity check setting for CodeSRAM. */
reg = mem_read32(apctl_reg[bus_num + loop]);
reg |= CSRM_APCTL_APCEN;
mem_write32(apctl_reg[bus_num + loop], reg);
}
}
/* End of function initialize_codesram_ecc_parity */

39
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.h Normal file
View File

@@ -0,0 +1,39 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC and Address parity check for CodeSRAM header
******************************************************************************/
#ifndef CODESRAM_ECC_H__
#define CODESRAM_ECC_H__
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size);
void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size);
void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size);
void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size);
#endif /* CODESRAM_ECC_H__ */

300
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c Normal file
View File

@@ -0,0 +1,300 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MCU power management driver
******************************************************************************/
/******************************************************************************
* @file cpu_on.c
* - Version : 0.02
* @brief 1. Boot process of MCU CPU core.
* 2. Set Option Byte to OPBT.
* 3. Disable the Bus Guard.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.06.2022 0.01 First Release
* : 02.02.2023 0.02 Moved definitions to header file.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <mem_io.h>
#include <mcu_register.h>
#include <remap.h>
#include <cpu_on_for_mcu.h>
/* MCU */
#define MCU_OPBT_MAX (12U)
#define MCU_ICUM_OPBT_MAX (7U)
#define MCU_PBG_MAX (7U)
#define MCU_HBG_MAX (9U)
#define LOCAL_FLASH_BUS_MODE (0x12B9B0A1U)
#define MCU_RESET_READY (0x00000001U)
#define MCU_RCT_RUNNING (0x00000001U)
#define CODESRAM_ROUND_MASK (0x000FFFFFU)
#define OPBT_EMPTY_VALUE (0xFFFFFFFFU)
static void csrm_n_csifcode_protect(uint32_t bit_shift);
void mcu_cpu_on(uint32_t target)
{
uint32_t boot_ctrl = 0U;
uint32_t ret;
if(MCU_PWR_TARGET_G4MH == target)
{
#if ((BOOT_MCU & MCU_BOOT_G4MH) != 0U)
boot_ctrl = MCU_G4MH_BOOT_CTLR;
#endif /* ((BOOT_MCU & MCU_BOOT_G4MH) != 0U) */
}
else if(MCU_PWR_TARGET_ICUMH == target)
{
#if ((BOOT_MCU & MCU_BOOT_ICUMH) != 0U)
boot_ctrl = MCU_ICUMH_BOOT_CTLR;
#endif /* ((BOOT_MCU & MCU_BOOT_ICUMH) != 0) */
}
else
{
/* No Process */
}
/* Execute the reset process of MCU core. *
* If the register address is not set in "A", *
* exit the function without executing anything. */
if(boot_ctrl != 0U)
{
/* Release write protection of SCDS0 */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE);
/* MCU core reset */
ret = mem_read32(boot_ctrl);
ret |= MCU_RESET_READY;
mem_write32(boot_ctrl, ret);
ret = mem_read32(MCU_OPBT_CTRL);
ret |= MCU_RESET_READY;
mem_write32(MCU_OPBT_CTRL, ret);
/* Wait until the MCU status is set to start. */
do
{
ret = mem_read32(MCU_OPBT_STAT);
ret &= MCU_RCT_RUNNING;
} while (ret != MCU_RCT_RUNNING);
/* write protection of SCDS0 */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE);
}
}
/* End of function mcu_cpu_on(uint32_t target) */
void mcu_set_opbt(void)
{
uint32_t loop;
const uint32_t opbt_reg[MCU_OPBT_MAX] =
{ MCU_RESET_VECTOR_PE0,
MCU_RESET_VECTOR_PE1,
MCU_OPBT0,
MCU_OPBT1,
MCU_OPBT2,
MCU_OPBT3,
MCU_OPBT4,
MCU_OPBT6,
MCU_OPBT7,
MCU_OPBT8,
MCU_OPBT9,
MCU_OPBT96
};
uint32_t opbt_val[MCU_OPBT_MAX] =
{ 0x00000400U,
0x00000400U,
0x3D810010U,
0x00700000U,
0x707FFFFFU,
0x00000000U,
0x0C0C0C0FU,
0x00000F00U,
0x00000FFFU,
0x02000000U,
0x03000300U,
0x00000000U
};
for (loop = 0U; loop < MCU_OPBT_MAX; loop++)
{
mem_write32(opbt_reg[loop], opbt_val[loop]);
opbt_val[loop] = OPBT_EMPTY_VALUE;
}
}
/* End of function mcu_set_opbt(uint32_t g4mh_addr) */
void mcu_set_icum_opbt(void)
{
uint32_t loop;
const uint32_t opbt_reg[MCU_ICUM_OPBT_MAX] =
{ MCU_ICUM_OPBT0,
MCU_ICUM_OPBT1,
MCU_ICUM_OPBT2,
MCU_ICUM_OPBT4,
MCU_ICUM_OPBT5,
MCU_ICUM_OPBT6,
MCU_ICUM_OPBT7
};
#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH)
uint32_t opbt_val[MCU_ICUM_OPBT_MAX] =
{ 0x0FFFFFFFU,
0x00500000U,
0x00500000U,
0xFFFFFFEFU,
0x00600000U,
0xFFFFFFFFU,
0xFFFFFFFFU
};
#else
uint32_t opbt_val[MCU_ICUM_OPBT_MAX] =
{ OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE,
OPBT_EMPTY_VALUE
};
#endif
for (loop = 0U; loop < MCU_ICUM_OPBT_MAX; loop++)
{
mem_write32(opbt_reg[loop], opbt_val[loop]);
opbt_val[loop] = OPBT_EMPTY_VALUE;
}
}
/* End of function mcu_set_icum_opbt(uint32_t icumh_addr) */
void mcu_set_hbg(void)
{
uint32_t loop;
const uint32_t pbg_reg[MCU_PBG_MAX][2U] =
{ /* register address setting value */
{MCUAXI_PBG_PBGPROT0_0, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_1, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_2, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_3, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_4, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_5, 0x00000000U},
{MCUAXI_PBG_PBGPROT0_6, 0x00000000U}
};
const uint32_t hbg_reg[MCU_HBG_MAX][2U] =
{ /* register address setting value */
{MCU_HBG_CS0_HBGPROT0, 0x00000000U},
{MCU_HBG_CS1_HBGPROT0, 0x00000000U},
{MCU_HBG_CS2_HBGPROT0, 0x00000000U},
{MCU_HBG_CS3_HBGPROT0, 0x00000000U},
{MCU_HBG_CS4_HBGPROT0, 0x00000000U},
{MCU_HBG_CS5_HBGPROT0, 0x00000000U},
{MCU_HBG_DS_HBGPROT0, 0x00000000U},
{MCU_HBG_SOCM_HBGPROT0, 0x00000000U},
{MCU_HBG_SOCS_HBGPROT0, 0x00000000U}
};
const uint32_t hbg_prot_reg[MCU_HBG_MAX] =
{
MCU_HBGSLVER_CS0_HBGKCPROT,
MCU_HBGSLVER_CS1_HBGKCPROT,
MCU_HBGSLVER_CS2_HBGKCPROT,
MCU_HBGSLVER_CS3_HBGKCPROT,
MCU_HBGSLVER_CS4_HBGKCPROT,
MCU_HBGSLVER_CS5_HBGKCPROT,
MCU_HBGSLVER_DS_HBGKCPROT,
MCU_HBGSLVER_SOCM_HBGKCPROT,
MCU_HBGSLVER_SOCS_HBGKCPROT
};
/* Release write protection of SCDS0 */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE);
/* Set PBG register */
for (loop = 0U; loop < MCU_PBG_MAX; loop++)
{
mem_write32(pbg_reg[loop][0U], pbg_reg[loop][1U]);
}
/* write protection of SCDS0 */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE);
/* Set HBG register */
for (loop = 0U; loop < MCU_HBG_MAX; loop++)
{
hbg_reg_write(hbg_prot_reg[loop], hbg_reg[loop][0U], hbg_reg[loop][1U]);
}
}
/* End of function mcu_set_hbg(void) */
void mcu_set_csrm(uint32_t boot_addr, uint32_t size)
{
uint32_t loop;
uint32_t bus_num;
uint32_t set_num;
const uint32_t csrm_reg[MCU_CSRM_MAX] =
{ MCU_CSRM0CSIFCODE,
MCU_CSRM1CSIFCODE,
MCU_CSRM2CSIFCODE,
MCU_CSRM3CSIFCODE,
MCU_CSRM4CSIFCODE,
MCU_CSRM5CSIFCODE,
};
/* Calculate the area used by Code SRAM. */
bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> 20U);
set_num = ((size & CODESRAM_BUS_NUM_MASK) >> 20U);
/* Set CSRM register */
for (loop = 0U; loop < set_num; loop++)
{
mem_write32(csrm_reg[bus_num + loop], LOCAL_FLASH_BUS_MODE);
/* Write protection of CSRMnCSIFCODE registers */
csrm_n_csifcode_protect((bus_num + loop));
}
}
/* End of function mcu_set_csrm(void) */
void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val)
{
mem_write32(prot_reg_addr, MCU_HBG_REL_CODE);
mem_write32(reg_addr, val);
mem_write32(prot_reg_addr, MCU_HBG_PROT_CODE);
}
/* End of function hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val) */
static void csrm_n_csifcode_protect(uint32_t bit_shift)
{
/* Control CSIFCODE_LOCK to protect writing to CSRMnCSIFCODE during product mass production. */
}
/* End of function csrm_n_csifcode_protect(uint32_t bit_shift) */

62
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h Normal file
View File

@@ -0,0 +1,62 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MCU power management driver header
******************************************************************************/
#ifndef CPU_ON_FOR_MCU_H__
#define CPU_ON_FOR_MCU_H__
#define MCU_PWR_TARGET_G4MH (0U)
#define MCU_PWR_TARGET_ICUMH (1U)
#define MCU_BOOT_NONE (0U)
#define MCU_BOOT_G4MH (1U)
#define MCU_BOOT_ICUMH (2U)
#define MCU_BOOT_G4MH_ICUMH (3U)
#define MCU_HBG_REL_CODE (0xA5A5A501U)
#define MCU_HBG_PROT_CODE (0xA5A5A500U)
#define G4MH_PRG_1_BOOT_ADDR (0x10000000U)
#define G4MH_PRG_1_SIZE (0x00100000U)
#define G4MH_PRG_2_BOOT_ADDR (0x10100000U)
#define G4MH_PRG_2_SIZE (0x00400000U)
#define ICUMH_PRG_BOOT_ADDR (0x10500000U)
#define ICUMH_PRG_SIZE (0x00100000U)
#define MCU_CSRM_MAX (6U)
#define CODESRAM_BUS_NUM_MASK (0x00700000U)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void mcu_cpu_on(uint32_t target);
void mcu_set_opbt(void);
void mcu_set_icum_opbt(void);
void mcu_set_hbg(void);
void mcu_set_csrm(uint32_t boot_addr, uint32_t size);
void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val);
#endif /* CPU_ON_FOR_MCU_H__ */

117
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c Normal file
View File

@@ -0,0 +1,117 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function for MCU
******************************************************************************/
/******************************************************************************
* @file image_load_for_mcu.c
* - Version : 0.01
* @brief Loading image driver for MCU.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 04.07.2022 0.01 First Release
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <sdmac.h>
#include <image_load_for_mcu.h>
#include <loader_main_mcu.h>
#include <rom_api.h>
#if (RCAR_SA9_TYPE == FLASH_BOOT)
#include <image_load_flash.h>
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
#include <image_load_emmc.h>
#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */
void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify)
{
uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED;
if (is_verify != NORMAL_BOOT)
{
/* A flag whether MCU image is encrypted */
aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr);
}
if(aes_flg == MCU_IMG_NOT_ENCRYPTED)
{
/* Transfer by SDMAC on ICUMX */
icu_sdmac_trans_start(li);
}
else
{
/* Transfer by AES driver on ICUMX */
mcu_img_decrypt(li);
}
}
/* End of function image_load_for_mcu(const LOAD_INFO *li) */
void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify)
{
uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED;
if (is_verify != NORMAL_BOOT)
{
/* A flag whether MCU image is encrypted */
aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr);
}
if(aes_flg == MCU_IMG_NOT_ENCRYPTED)
{
icu_sdmac_trans_end();
}
else
{
mcu_img_decrypt_end(li);
}
}
/* End of function load_end_for_mcu(const LOAD_INFO *li) */
void load_image_info_print(const LOAD_INFO *li)
{
#if (RCAR_SA9_TYPE == FLASH_BOOT)
load_image_info_print_for_flash(li);
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
load_image_info_print_for_emmc(li);
#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */
}
/* End of function load_image_info_print(const LOAD_INFO *li) */
void load_securedata_for_mcu(void)
{
LOAD_INFO tmp_li;
tmp_li.image_size = SECUREDATA_SIZE;
tmp_li.src_addr = RTVRAM_BASE;
tmp_li.boot_addr = DATA_SRAM_BASE;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
tmp_li.part_num = EMMC_PARTITION_1;
#endif
/* */
icu_sdmac_trans_start(&tmp_li);
icu_sdmac_trans_end();
}/* End of function load_securedata(uint32_t target_id) */

67
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h Normal file
View File

@@ -0,0 +1,67 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function for MCU header
******************************************************************************/
#ifndef IMAGE_LOAD_FOR_MCU_H__
#define IMAGE_LOAD_FOR_MCU_H__
#include <stdint.h>
#include <image_load.h>
#include <loader_main_mcu.h>
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
#include <mem_io.h>
#include <dx_pal_types_plat.h>
#include <bootimagesverifier_def.h>
#include <bootimagesverifier_parser.h>
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify);
void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify);
void load_image_info_print(const LOAD_INFO *li);
void load_securedata_for_mcu(void);
/* Inline function */
static inline uint32_t get_aes_flg_in_cert(uint32_t cert_addr)
{
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
uint32_t aes_flg;
uint32_t val;
val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET);
aes_flg = ((val >> CERT_FLAG_ENCRYPTION_USED_BIT_LOCATION) & 0x1U);
return aes_flg;
#else
return MCU_IMG_NOT_ENCRYPTED;
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function get_aes_flg_in_cert(uint32_t cert_addr) */
#endif /* IMAGE_LOAD_FOR_MCU_H__ */

456
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c Normal file
View File

@@ -0,0 +1,456 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main for MCU
******************************************************************************/
/******************************************************************************
* @file loader_main_mcu.c
* - Version : 0.03
* @brief 1. Loading G4MH(1st) image including integrity check.
* 2. Loading ICUMH image including integrity check.
* 3. Loading G4MH(2nd) image including integrity check.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 22.06.2022 0.01 First Release
* : 05.08.2022 0.02 Add sw_version_check function call to
* : mcu_img_verify function.
* : 19.01.2023 0.03 Add ECC and Address parity check for CodeSRAM.
*****************************************************************************/
#include <stdint.h>
#include <string.h>
#include <types.h>
#include <mem_io.h>
#include <cpu_on_for_mcu.h>
#include <ram_def.h>
#include <mcu_register.h>
#include <micro_wait.h>
#include <image_load.h>
#include <cpu_on_for_mcu.h>
#include <loader_main_mcu.h>
#include <image_load_for_mcu.h>
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
#include <mcu_secureboot.h>
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
#include <remap.h>
#include <rom_api.h>
#include <codesram_ecc.h>
#define ICUMH_OPBT_OFFSET (0x200U)
#define MCU_TRANSFER_UNIT (0x00040000U) /* 256KiB */
#define RTVRAM_TMP_G4MH_TOP_A (0xE2080000U)
#define RTVRAM_TMP_G4MH_TOP_B (0xE20C0000U)
#define GREG120_CODE (0x5AA5A55AU)
#define G4MH_LOAD_FIN_CODE (0x0000001EU)
/* Prototype */
static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify);
static void load_icumh(const LOAD_INFO *li, uint32_t is_verify);
static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify);
static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify);
static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify);
static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify);
static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify);
static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify);
static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify)
{
LOAD_INFO tmp_li = {0U};
/* Copy li to tmporary structure. (Because original li members are required later.) */
(void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO));
/* Change boot_addr to RTVRAM_BASE. */
tmp_li.boot_addr = RTVRAM_BASE;
/* Output image info. */
load_image_info_print(li);
/* Check load information. */
check_load_area(li);
/* Release write protection of SCDS0. */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE);
mem_write32(MCU_GREG120, 0x00000000U);
/* Set G4MH Option Byte. */
mcu_set_opbt();
/* Set ICUMH Option Byte. */
mcu_set_icum_opbt();
mem_write32(MCU_GREG120, GREG120_CODE);
micro_wait(10U);
/* Write protection of SCDS0. */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE);
/* Load G4MH(1st) image from external flash to RT-VRAM. */
load_start(&tmp_li);
/* Verify Key Certificate. */
mcu_key_cert_check(&tmp_li, is_verify);
/* Disable bus guard of MCU. */
mcu_set_hbg();
/* Finish loading G4MH(1st) image from external flash to RT-VRAM. */
load_end();
/* Change src_addr from external flash to RT-VRAM. */
tmp_li.src_addr = tmp_li.boot_addr;
/* Change boot_addr from RT-VRAM to CodeSRAM. */
tmp_li.boot_addr = li->boot_addr;
/* Disable ECC error and Address parity error check for CodeSRAM. */
disable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE);
/* Load G4MH(1st) image from RT-VRAM to CodeSRAM. */
image_load_for_mcu(&tmp_li, is_verify);
/* Verify Content Certificate */
mcu_cnt_cert_check(&tmp_li, is_verify);
/* Finish loading G4MH(1st) image from RT-VRAM to CodeSRAM. */
load_end_for_mcu(&tmp_li, is_verify);
/* Enable ECC error and Address parity error check for CodeSRAM. */
enable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE);
/* Verify G4MH(1st) image. */
mcu_img_verify(&tmp_li, is_verify);
/* Check ECC error and Address parity error detection for CodeSRAM. */
chk_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE);
/* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */
initialize_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE);
/* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */
mcu_set_csrm(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE);
/* Boot G4MH */
mcu_cpu_on(MCU_PWR_TARGET_G4MH);
}
/* End of function load_g4mh_1st(const LOAD_INFO *li) */
static void load_icumh(const LOAD_INFO *li, uint32_t is_verify)
{
#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH)
LOAD_INFO tmp_li = {0U};
/* Copy li to tmporary structure. (Because original li members are required later.) */
(void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO));
/* Change boot_addr to RTVRAM_BASE. */
tmp_li.boot_addr = RTVRAM_BASE;
/* Output image info. */
load_image_info_print(li);
/* Check load information. */
check_load_area(li);
/* Load ICUMH image from external flash to RT-VRAM. */
load_start(&tmp_li);
/* Verify Key Certificate. */
mcu_key_cert_check(&tmp_li, is_verify);
/* Finish loading ICUMH image from external flash to RT-VRAM. */
load_end();
/* Change src_addr from external flash to RT-VRAM. */
tmp_li.src_addr = tmp_li.boot_addr;
/* Change boot_addr from RT-VRAM to CodeSRAM. */
tmp_li.boot_addr = li->boot_addr;
/* Disable ECC error and Address parity error check for CodeSRAM. */
disable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE);
/* Load ICUMH image from RT-VRAM to CodeSRAM. */
image_load_for_mcu(&tmp_li, is_verify);
/* Verify Content Certificate */
mcu_cnt_cert_check(&tmp_li, is_verify);
/* Finish loading ICUMH image from RT-VRAM to CodeSRAM. */
load_end_for_mcu(&tmp_li, is_verify);
/* Load Secure data from external flash to RT-VRAM */
load_securedata(ICUMH_PROGRAM_ID);
/* Enable ECC error and Address parity error check for CodeSRAM. */
enable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE);
/* Verify ICUMH image. */
mcu_img_verify(&tmp_li, is_verify);
/* Finish loading Secure data from external flash to RT-VRAM. */
load_end();
/* Check ECC error and Address parity error detection for CodeSRAM. */
chk_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE);
/* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */
initialize_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE);
/* Load Secure data from RT-VRAM to Data-SRAM. */
load_securedata_for_mcu();
/* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */
mcu_set_csrm(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE);
/* Boot ICUMH */
mcu_cpu_on(MCU_PWR_TARGET_ICUMH);
#endif /* (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) */
}
/* End of function load_icumh(const LOAD_INFO *li) */
static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify)
{
uint32_t count = 0U;
uint32_t dst_size = li->image_size;
uint32_t even_or_odd = 0U;
LOAD_INFO tmp_li = {0U};
void (*p_w_load_func[])(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify)
= {w_load_even, w_load_odd};
/* Copy li to tmporary structure. (Because original li members are required later.) */
(void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO));
/* A transfer unit is 256KiB. */
tmp_li.image_size = MCU_TRANSFER_UNIT;
/* Change boot_addr to 0xE2080000. */
tmp_li.boot_addr = RTVRAM_TMP_G4MH_TOP_A;
/* Output image info. */
load_image_info_print(li);
/* Check load information. */
check_load_area(li);
/* Load image from external flash to RT-VRAM. */
load_start(&tmp_li);
/* Verify Key Certificate. */
mcu_key_cert_check(&tmp_li, is_verify);
/* Finish loading image from external flash to RT-VRAM. */
load_end();
/* Disable ECC error and Address parity error check for CodeSRAM. */
disable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE);
if (dst_size <= tmp_li.image_size)
{
/* If image size is less than 256KiB. */
tmp_li.image_size = dst_size;
mcu_cnt_cert_check(li, is_verify);
}
else /* If image size is larger than 256KiB. */
{
/* dst_size - 256KiB */
dst_size -= tmp_li.image_size;
if (dst_size < tmp_li.image_size)
{
/* If remaining image size is less than 256KiB. */
count++;
even_or_odd = count;
tmp_li.image_size = dst_size;
dst_size = 0U;
}
else /* If remaining image size is still larger than 256KiB. */
{
count++;
even_or_odd = count;
dst_size -= tmp_li.image_size;
}
/* Load image(#count) from external flash to RT-VRAM. *
* Load image(#count-1) from RT-VRAM to CodeSRAM. */
p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify);
/* Verify Content Certificate */
mcu_cnt_cert_check(&tmp_li, is_verify);
/* Finish loading image(#count) from external flash to RT-VRAM. */
load_end();
/* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */
load_end_for_mcu(&tmp_li, is_verify);
/* Load remaining image. */
while (dst_size != 0U)
{
if (dst_size < tmp_li.image_size)
{
/* If remaining image size is less than 256KiB. */
count++;
even_or_odd = count % 2U;
tmp_li.image_size = dst_size;
dst_size = 0U;
}
else /* If remaining image size is still larger than 256KiB. */
{
count++;
even_or_odd = count % 2U;
dst_size -= tmp_li.image_size;
}
/* Load image(#count) from external flash to RT-VRAM. *
* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */
p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify);
/* Finish loading image(#count) from external flash to RT-VRAM. */
load_end();
/* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */
load_end_for_mcu(&tmp_li, is_verify);
}
}
tmp_li.src_addr = (RTVRAM_TMP_G4MH_TOP_A + (even_or_odd * MCU_TRANSFER_UNIT));
tmp_li.boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count)));
/* Load image from RT-VRAM to CodeSRAM (with decryption). */
image_load_for_mcu(&tmp_li, is_verify);
/* Finish loading image(bottom) from RT-VRAM to CodeSRAM. */
load_end_for_mcu(&tmp_li);
/* Enable ECC error and Address parity error check for CodeSRAM. */
enable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE);
/* Verify G4MH(2nd) image. */
mcu_img_verify(li, is_verify);
/* Check ECC error and Address parity error detection for CodeSRAM. */
chk_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE);
/* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */
initialize_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE);
/* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */
mcu_set_csrm(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE);
/* Release write protection of SCDS0. */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE);
mem_write32(MCU_BOOT_STAT, G4MH_LOAD_FIN_CODE);
/* Write protection of SCDS0. */
mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE);
hbg_reg_write(MCU_HBGSLVER_PFS_HBGKCPROT, MCU_HBG_PFS_HBGPROT0, 0x00000000U);
}
/* End of function load_g4mh_2nd(const LOAD_INFO *li) */
static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify)
{
tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count));
tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_A;
/* Load image(#count) from external flash to RT-VRAM. */
load_start(tmp_li);
tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_B;
tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U)));
/* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */
image_load_for_mcu(tmp_li, is_verify);
}
/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */
static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify)
{
tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count));
tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_B;
/* Load image(#count) from external flash to RT-VRAM. */
load_start(tmp_li);
tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_A;
tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U)));
/* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */
image_load_for_mcu(tmp_li, is_verify);
}
/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */
static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify)
{
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
if (is_verify != NORMAL_BOOT)
{
r_mcu_key_cert_check_api(li);
}
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify). */
static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify)
{
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
if (is_verify != NORMAL_BOOT)
{
r_mcu_cnt_cert_check_api(li);
}
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function mcu_key_cert_check(const LOAD_INFO *li, uint32_t is_verify) */
void mcu_img_decrypt(const LOAD_INFO *li)
{
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
r_mcu_img_decrypt_api(li);
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function mcu_img_decrypt(const LOAD_INFO *li, uint32_t is_verify) */
void mcu_img_decrypt_end(const LOAD_INFO *li)
{
/* Argument li is not used but compliant to MISRA Rule 2.2. */
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
r_mcu_img_decrypt_end();
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function mcu_img_decrypt_end(const LOAD_INFO *li) */
static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify)
{
#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE)
if (is_verify != NORMAL_BOOT)
{
r_mcu_img_verify_api(li);
sw_version_check(li);
}
#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */
}
/* End of function mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify) */
void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify)
{
load_g4mh_1st(&li[G4MH_PROGRAM_ID], is_verify); /* Load G4MH(1st) image. */
load_icumh(&li[ICUMH_PROGRAM_ID], is_verify); /* Load ICUMH image. */
load_g4mh_2nd(&li[G4MH_PROGRAM_ID + 1U], is_verify); /* Load G4MH(2nd) image. */
}
/* End of function mcu_load_main(const LOAD_INFO *li, uint32_t is_verify) */

45
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h Normal file
View File

@@ -0,0 +1,45 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MCU Secure Boot Main header
******************************************************************************/
#ifndef LOADER_MAIN_MCU_H__
#define LOADER_MAIN_MCU_H__
#include <stdint.h>
#include <image_load.h>
#define MCU_SEC_BOOT_ENABLE (1U)
#define MCU_IMG_NOT_ENCRYPTED (0U)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void mcu_img_decrypt(const LOAD_INFO *li);
void mcu_img_decrypt_end(const LOAD_INFO *li);
void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify);
#endif /* LOADER_MAIN_MCU_H__ */

110
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.c Normal file
View File

@@ -0,0 +1,110 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function by SDMAC on ICUMX
******************************************************************************/
/******************************************************************************
* @file sdmac.c
* - Version : 0.01
* @brief Driver of SCMAC on ICUMX.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.06.2022 0.01 First Release
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <mem_io.h>
#include <log.h>
#include <dma.h>
#include <sdmac.h>
#include <wdt.h>
void icu_sdmac_trans_start(const LOAD_INFO *li)
{
uint16_t reg;
uint32_t len = li->image_size;
/* src_addr and boot_addr must be 64-byte boundary. */
dma_address_align_check(li->boot_addr, li->src_addr);
/* If len is not 64-byte boundary, */
/* round up len to 64-byte boundary. */
len += SDMAC_FRACTION_MASK_64_BYTE;
len &= ~(SDMAC_FRACTION_MASK_64_BYTE);
/* Clear channel 0 registers */
mem_write32(ICUMX_DMACHRST, ICUMX_DMACHRST_CLR_CH0);
/* Clear flags */
mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT);
/* Round-robin mode / Enable DMA transfer */
mem_write16(ICUMX_DMAOR, ICUMX_DMAOR_INIT);
/* DMA Transfer mode *
* Slow speed mode : Normal mode *
* Priority setting : Disable *
* Transfer Request source : Auto Request *
* Destination Address mode : Fixed *
* Source address mode : Incremented *
* DMA destination transaction size : 64byte *
* DMA source transaction size : 64byte */
mem_write32(ICUMX_DMATMR_0, ICUMX_DMATMR_0_INIT);
/* Set destination address */
mem_write32(ICUMX_DMADAR_0, li->boot_addr);
/* Set source address */
mem_write32(ICUMX_DMASAR_0, li->src_addr);
/* Set transfer size */
mem_write32(ICUMX_DMATSR_0, len);
reg = mem_read16(ICUMX_DMACHCR_0);
/* Enable channel address error notification / Enable DMA */
reg |= ICUMX_DMACHCR_0_START;
mem_write16(ICUMX_DMACHCR_0, reg);
}
/* End of function icu_sdmac_trans_start(LOAD_INFO *li) */
void icu_sdmac_trans_end(void)
{
uint32_t reg;
wdt_restart();
/* Check end of DMA transfer. */
do
{
reg = mem_read32(ICUMX_DMACHSTA_0);
/* Check error of DMA transfer */
if ((reg & ICUMX_DMACHSTA_CAE) != DMACHSTA_CAE_BIT_NOERROR)
{
ERROR("SDMAC on ICUMX - Channel Address Error\n");
panic;
}
} while ((reg & ICUMX_DMACHSTA_TE) != DMACHSTA_TE_END_DMA);
/* Clear flags */
mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT);
}
/* End of function icu_sdmac_trans_end(void) */

99
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.h Normal file
View File

@@ -0,0 +1,99 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function by SDMAC on ICUMX header
******************************************************************************/
#ifndef SDMAC_H__
#define SDMAC_H__
#include <sdmac_register.h>
#include <image_load.h>
/* Prototype */
void icu_sdmac_trans_start(const LOAD_INFO *li);
void icu_sdmac_trans_end(void);
/* Definitions */
#define ICUMX_DMACHRST_CLR_CH0 (0x00000001U)
#define ICUMX_DMACHRST_CLR_CH1 (0x00000002U)
#define ICUMX_DMACHRST_CLR_CH2 (0x00000004U)
#define ICUMX_DMACHFCR_CAEC (0x00000008U)
#define ICUMX_DMACHFCR_TEC (0x00000002U)
#define ICUMX_DMACHFCR_DEC (0x00000001U)
#define ICUMX_DMACHFCR_INIT (ICUMX_DMACHFCR_CAEC | ICUMX_DMACHFCR_TEC | ICUMX_DMACHFCR_DEC)
#define ICUMX_DMAOR_PR_ROUND_ROBIN (0x0300U)
#define ICUMX_DMAOR_DME_ENABLE (0x0001U)
#define ICUMX_DMAOR_INIT (ICUMX_DMAOR_PR_ROUND_ROBIN | ICUMX_DMAOR_DME_ENABLE)
#define ICUMX_DMATMR_SLM_NORMAL (0x00000000U)
#define ICUMX_DMATMR_PRI_DISABLE (0x00000000U)
#define ICUMX_DMATMR_TRS_AT_REQ (0x00000000U)
#define ICUMX_DMATMR_TRS_HARD_REQ (0x00001000U)
#define ICUMX_DMATMR_DM_INC (0x00000400U)
#define ICUMX_DMATMR_SM_INC (0x00000100U)
#define ICUMX_DMATMR_DTS_64B (0x00000060U)
#define ICUMX_DMATMR_STS_64B (0x00000006U)
#define ICUMX_DMATMR_0_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE | ICUMX_DMATMR_TRS_AT_REQ \
| ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \
| ICUMX_DMATMR_STS_64B)
#define ICUMX_DMATMR_1_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \
| ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \
| ICUMX_DMATMR_STS_64B)
#define ICUMX_DMATMR_2_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \
| ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_DTS_64B \
| ICUMX_DMATMR_STS_64B)
#define ICUMX_DMACHCR_CAEE_ENABLE (0x0010U)
#define ICUMX_DMACHCR_CAIE_ENABLE (0x0008U)
#define ICUMX_DMACHCR_IE_ENABLE (0x0002U)
#define ICUMX_DMACHCR_DE_ENABLE (0x0001U)
#define ICUMX_DMACHCR_0_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_DE_ENABLE)
#define ICUMX_DMACHCR_1_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \
| ICUMX_DMACHCR_DE_ENABLE)
#define ICUMX_DMACHCR_2_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \
| ICUMX_DMACHCR_IE_ENABLE | ICUMX_DMACHCR_DE_ENABLE)
#define ICUMX_DMACHSTA_CAE (0x00000008U)
#define ICUMX_DMACHSTA_TE (0x00000002U)
#define DMACHSTA_CAE_BIT_NOERROR (0x00000000U)
#define DMACHSTA_TE_END_DMA (0x00000002U)
#define ICUMX_DMARS_TC_1 (0x00010000U)
#define ICUMX_DMARS_TL_TMR_DTS (0x00001000U)
#define ICUMX_DMARS_TL_TMR_STS (0x00000000U)
#define ICUMX_DMARS_FPT_DE_IS_1 (0x00000000U)
#define ICUMX_DMARS_PLE_ENABLE (0x00000400U)
#define ICUMX_DMARS_PLE_DISABLE (0x00000000U)
#define ICUMX_DMARS_RS_FOR_CH2 (0x00000001U)
#define ICUMX_DMARS_1_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_DTS | ICUMX_DMARS_FPT_DE_IS_1 \
| ICUMX_DMARS_PLE_ENABLE)
#define ICUMX_DMARS_2_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_STS | ICUMX_DMARS_FPT_DE_IS_1 \
| ICUMX_DMARS_PLE_DISABLE | ICUMX_DMARS_RS_FOR_CH2)
#define SDMAC_FRACTION_MASK_64_BYTE (0x3FU)
#endif /* SDMAC_H__ */

77
IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac_register.h Normal file
View File

@@ -0,0 +1,77 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Registers of SDMAC on ICUMX
******************************************************************************/
#ifndef SDMAC_REGISTER_H__
#define SDMAC_REGISTER_H__
/* SDMAC on ICUMX base address */
#define ICUMX_SDMAC_BASE (0xFF600000U)
/* Channel offset address */
#define ICUMX_SDMAC_CH0 (0x80U * 0U)
#define ICUMX_SDMAC_CH1 (0x80U * 1U)
#define ICUMX_SDMAC_CH2 (0x80U * 2U)
/* SDMAC Interrupt Status Register */
#define ICUMX_DMAISTA (ICUMX_SDMAC_BASE + 0x0020U)
/* SDMAC Operation Register */
#define ICUMX_DMAOR (ICUMX_SDMAC_BASE + 0x0060U)
/* SDMAC Channel Reset Register */
#define ICUMX_DMACHRST (ICUMX_SDMAC_BASE + 0x0080U)
/* SDMAC Source Address Register */
#define ICUMX_DMASAR_0 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0)
#define ICUMX_DMASAR_1 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1)
#define ICUMX_DMASAR_2 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2)
/* SDMAC Destination Address Register */
#define ICUMX_DMADAR_0 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0)
#define ICUMX_DMADAR_1 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1)
#define ICUMX_DMADAR_2 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2)
/* SDMAC Transfer Size Register */
#define ICUMX_DMATSR_0 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0)
#define ICUMX_DMATSR_1 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1)
#define ICUMX_DMATSR_2 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2)
/* SDMAC Transfer Mode Register */
#define ICUMX_DMATMR_0 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0)
#define ICUMX_DMATMR_1 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1)
#define ICUMX_DMATMR_2 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Control Register */
#define ICUMX_DMACHCR_0 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHCR_1 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHCR_2 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Status Register */
#define ICUMX_DMACHSTA_0 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHSTA_1 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHSTA_2 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Flag Clear Register */
#define ICUMX_DMACHFCR_0 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHFCR_1 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHFCR_2 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2)
/* SDMAC Resource Select Register */
#define ICUMX_DMARS_1 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1)
#define ICUMX_DMARS_2 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2)
#endif /* SDMAC_REGISTER_H__ */