78 lines
4.2 KiB
C
78 lines
4.2 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Registers of SDMAC on ICUMX
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******************************************************************************/
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#ifndef SDMAC_REGISTER_H__
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#define SDMAC_REGISTER_H__
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/* SDMAC on ICUMX base address */
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#define ICUMX_SDMAC_BASE (0xFF600000U)
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/* Channel offset address */
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#define ICUMX_SDMAC_CH0 (0x80U * 0U)
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#define ICUMX_SDMAC_CH1 (0x80U * 1U)
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#define ICUMX_SDMAC_CH2 (0x80U * 2U)
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/* SDMAC Interrupt Status Register */
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#define ICUMX_DMAISTA (ICUMX_SDMAC_BASE + 0x0020U)
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/* SDMAC Operation Register */
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#define ICUMX_DMAOR (ICUMX_SDMAC_BASE + 0x0060U)
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/* SDMAC Channel Reset Register */
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#define ICUMX_DMACHRST (ICUMX_SDMAC_BASE + 0x0080U)
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/* SDMAC Source Address Register */
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#define ICUMX_DMASAR_0 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMASAR_1 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMASAR_2 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2)
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/* SDMAC Destination Address Register */
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#define ICUMX_DMADAR_0 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMADAR_1 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMADAR_2 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2)
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/* SDMAC Transfer Size Register */
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#define ICUMX_DMATSR_0 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMATSR_1 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMATSR_2 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2)
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/* SDMAC Transfer Mode Register */
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#define ICUMX_DMATMR_0 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMATMR_1 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMATMR_2 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2)
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/* SDMAC Channel Control Register */
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#define ICUMX_DMACHCR_0 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMACHCR_1 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMACHCR_2 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2)
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/* SDMAC Channel Status Register */
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#define ICUMX_DMACHSTA_0 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0)
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#define ICUMX_DMACHSTA_1 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMACHSTA_2 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2)
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/* SDMAC Channel Flag Clear Register */
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#define ICUMX_DMACHFCR_0 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0)
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#define ICUMX_DMACHFCR_1 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1)
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#define ICUMX_DMACHFCR_2 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2)
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/* SDMAC Resource Select Register */
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#define ICUMX_DMARS_1 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1)
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#define ICUMX_DMARS_2 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2)
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#endif /* SDMAC_REGISTER_H__ */
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