add IPL

IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c_register.h

@@ -0,0 +1,99 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright 2023 Renesas Electronics Corporation All rights reserved.
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : I2C register header
+ ******************************************************************************/
+
+#ifndef I2C_REGISTER_H__
+#define I2C_REGISTER_H__
+
+#include <remap_register.h>
+
+/* I2C ch6 base address */
+#define I2C3_BASE       (BASE_I2C3_ADDR)    /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */
+
+/* Slave control register */
+#define I2C3_ICSCR      (I2C3_BASE + 0x0000U)
+/* Master control register */
+#define I2C3_ICMCR      (I2C3_BASE + 0x0004U)
+/* Slave status register */
+#define I2C3_ICSSR      (I2C3_BASE + 0x0008U)
+/* Master status register */
+#define I2C3_ICMSR      (I2C3_BASE + 0x000CU)
+/* Slave interrupt enable register */
+#define I2C3_ICSIER     (I2C3_BASE + 0x0010U)
+/* Master interrupt enable register */
+#define I2C3_ICMIER     (I2C3_BASE + 0x0014U)
+/* Clock control register */
+#define I2C3_ICCCR      (I2C3_BASE + 0x0018U)
+/* Slave address register */
+#define I2C3_ICSAR      (I2C3_BASE + 0x001CU)
+/* Master address register */
+#define I2C3_ICMAR      (I2C3_BASE + 0x0020U)
+/* Recieve data register */
+#define I2C3_ICRXD      (I2C3_BASE + 0x0024U)
+/* Transmit data register */
+#define I2C3_ICTXD      (I2C3_BASE + 0x0024U)
+/* Clock control register 2 */
+#define I2C3_ICCCR2     (I2C3_BASE + 0x0028U)
+
+
+/* I2C ch? base address */
+#define I2C5_BASE       (BASE_I2C5_ADDR)    /* Physical address:0xE66E0000, Logical address:0xFDCE0000 */
+
+/* Slave control register */
+#define I2C5_ICSCR      (I2C5_BASE + 0x0000U)
+/* Master control register */
+#define I2C5_ICMCR      (I2C5_BASE + 0x0004U)
+/* Slave status register */
+#define I2C5_ICSSR      (I2C5_BASE + 0x0008U)
+/* Master status register */
+#define I2C5_ICMSR      (I2C5_BASE + 0x000CU)
+/* Slave interrupt enable register */
+#define I2C5_ICSIER     (I2C5_BASE + 0x0010U)
+/* Master interrupt enable register */
+#define I2C5_ICMIER     (I2C5_BASE + 0x0014U)
+/* Clock control register */
+#define I2C5_ICCCR      (I2C5_BASE + 0x0018U)
+/* Slave address register */
+#define I2C5_ICSAR      (I2C5_BASE + 0x001CU)
+/* Master address register */
+#define I2C5_ICMAR      (I2C5_BASE + 0x0020U)
+/* Recieve data register */
+#define I2C5_ICRXD      (I2C5_BASE + 0x0024U)
+/* Transmit data register */
+#define I2C5_ICTXD      (I2C5_BASE + 0x0024U)
+/* Clock control register 2 */
+#define I2C5_ICCCR2     (I2C5_BASE + 0x0028U)
+/* SCL mask Control register */
+#define I2C5_ICMPR      (I2C5_BASE + 0x002CU)
+/* SCL high Control register */
+#define I2C5_ICHPR      (I2C5_BASE + 0x0030U)
+/* SCL low  Control register */
+#define I2C5_ICLPR      (I2C5_BASE + 0x0034U)
+/* First bit setup cycle register */
+#define I2C5_ICFBSCR    (I2C5_BASE + 0x0038U)
+
+#endif  /* I2C_REGISTER_H__ */
+