100 lines
4.1 KiB
C
100 lines
4.1 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : I2C register header
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******************************************************************************/
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#ifndef I2C_REGISTER_H__
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#define I2C_REGISTER_H__
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#include <remap_register.h>
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/* I2C ch6 base address */
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#define I2C3_BASE (BASE_I2C3_ADDR) /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */
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/* Slave control register */
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#define I2C3_ICSCR (I2C3_BASE + 0x0000U)
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/* Master control register */
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#define I2C3_ICMCR (I2C3_BASE + 0x0004U)
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/* Slave status register */
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#define I2C3_ICSSR (I2C3_BASE + 0x0008U)
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/* Master status register */
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#define I2C3_ICMSR (I2C3_BASE + 0x000CU)
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/* Slave interrupt enable register */
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#define I2C3_ICSIER (I2C3_BASE + 0x0010U)
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/* Master interrupt enable register */
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#define I2C3_ICMIER (I2C3_BASE + 0x0014U)
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/* Clock control register */
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#define I2C3_ICCCR (I2C3_BASE + 0x0018U)
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/* Slave address register */
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#define I2C3_ICSAR (I2C3_BASE + 0x001CU)
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/* Master address register */
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#define I2C3_ICMAR (I2C3_BASE + 0x0020U)
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/* Recieve data register */
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#define I2C3_ICRXD (I2C3_BASE + 0x0024U)
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/* Transmit data register */
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#define I2C3_ICTXD (I2C3_BASE + 0x0024U)
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/* Clock control register 2 */
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#define I2C3_ICCCR2 (I2C3_BASE + 0x0028U)
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/* I2C ch? base address */
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#define I2C5_BASE (BASE_I2C5_ADDR) /* Physical address:0xE66E0000, Logical address:0xFDCE0000 */
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/* Slave control register */
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#define I2C5_ICSCR (I2C5_BASE + 0x0000U)
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/* Master control register */
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#define I2C5_ICMCR (I2C5_BASE + 0x0004U)
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/* Slave status register */
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#define I2C5_ICSSR (I2C5_BASE + 0x0008U)
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/* Master status register */
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#define I2C5_ICMSR (I2C5_BASE + 0x000CU)
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/* Slave interrupt enable register */
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#define I2C5_ICSIER (I2C5_BASE + 0x0010U)
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/* Master interrupt enable register */
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#define I2C5_ICMIER (I2C5_BASE + 0x0014U)
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/* Clock control register */
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#define I2C5_ICCCR (I2C5_BASE + 0x0018U)
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/* Slave address register */
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#define I2C5_ICSAR (I2C5_BASE + 0x001CU)
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/* Master address register */
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#define I2C5_ICMAR (I2C5_BASE + 0x0020U)
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/* Recieve data register */
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#define I2C5_ICRXD (I2C5_BASE + 0x0024U)
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/* Transmit data register */
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#define I2C5_ICTXD (I2C5_BASE + 0x0024U)
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/* Clock control register 2 */
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#define I2C5_ICCCR2 (I2C5_BASE + 0x0028U)
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/* SCL mask Control register */
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#define I2C5_ICMPR (I2C5_BASE + 0x002CU)
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/* SCL high Control register */
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#define I2C5_ICHPR (I2C5_BASE + 0x0030U)
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/* SCL low Control register */
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#define I2C5_ICLPR (I2C5_BASE + 0x0034U)
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/* First bit setup cycle register */
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#define I2C5_ICFBSCR (I2C5_BASE + 0x0038U)
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#endif /* I2C_REGISTER_H__ */
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