add

Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt

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+
+(Priority1)<29><> Multicore SPI support for lower CPU usage(REKR_MOBIS-270)
+	<09><> Case1- Workaround(Short term solution)
+			Pham is currently modifying the source code within the customer's environment
+
+	<09><> Case2 - MCAL Multicore TYPE 4(Long term solution) 
+			Support for Multi-core Type 4 is feasible; however, we need additional time to ensure a quality implementation.
+
+			Reference URL"2.5.6.4 MCAL Multi-Core Module Type IV"
+			https://www.autosar.org/fileadmin/standards/R19-11/CP/AUTOSAR_EXP_BSWDistributionGuide.pdf
+
+(Priority1)<29><> I2C communication reset requirement: explanation the I2C patch to customer(REKR_MOBIS-943)
+	<09><> Binh to provide a technical explanation to the customer.
+	<09><> MCAL Version Verification
+		v19.1.0  -> we will check custemer's use ver.
+		v19.3.0 -> we will check custemer's use ver.
+		v19.4.0 -> The customer is planning to update to this version. Renesas will issue a patch based on this version.(Target Delivery Date: May 22th)
+
+(Priority1)<29><> I2C communication reset requirement: Reset requirement discussion(REKR_MOBIS-995/957)
+	The customer tested after removing the Reset function(Reset I2C with SRCR and SRSTCLR), 
+	but they reported that I2C Stuck occurred. (Note: This is verbal feedback; no formal logs are available yet.)
+	In today's meeting, Binh advised the customer that removing the Reset API is not recommended.
+
+	The customer's  is that directly controlling H/W registers from the BSW (rather than using an  API) is not an ideal implementation.
+
+	<09><> Requests to the H/W Team
+	Customer Requirement: 
+	Please provide a detailed technical explanation of why the Reset(Reset I2C with SRCR and SRSTCLR) is mandatory for I2C communication. 
+	We need clear reasoning to justify this to the customer.
+
+	<09><> Requests to the MCAL Team
+	Customer Requirement: The customer is requesting to have the I2C Reset integrated within the MCAL CDD Iic.
+	If we proceed with this integration, what would be the expected delivery schedule?
+
+<EFBFBD><EFBFBD> AutoSAR architecture review
+	Meeting with the customer is scheduled for Tuesday, May 12th in the afternoon.
+
+<EFBFBD><EFBFBD> Let's review the source code together to debug this issue.
+	 <20><> CDD EMM notification(callback: REKR_MOBIS-1000)
+	 <20><> IRQ model sample code(REKR_MOBIS-965)
+
+<EFBFBD><EFBFBD> We need to verify the actual behavior of the CDD module
+	CRC: Verification is needed.
+	EMM: Verification is needed.
+	IPMMU: The customer will not use this feature as it conflicts with the existing configurations on the QNX side.
+	RFSO: Verification is needed.
+	THS: Verification is needed. 1<><31> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, but 4<><34> <20><><EFBFBD><EFBFBD> Notification<6F><6E> EMM<4D><4D><EFBFBD><EFBFBD> <20>ö<EFBFBD><C3B6><EFBFBD>.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD> AP<41><50><EFBFBD><EFBFBD> 4<><34> <20><><EFBFBD>밡<EFBFBD><EBB0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>)
+	ICCOM: The customer has completed the verification.
+	IIC: The customer has completed the verification.

Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt

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+           P1       P2
+OEM      6/1      9/15
+Mobis   5/15     6/30
+Code Freeze
+
+Tony. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ CPM Fully Type2 <20><>û
+1<EFBFBD><EFBFBD> 7<><37><EFBFBD><EFBFBD>
+
+Autosar SC1 : DDR Only <20><><EFBFBD><EFBFBD>
+Autosar SC3 : SRAM <20>Ϻ<EFBFBD> + DDR <20><><EFBFBD><EFBFBD>
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>غ<EFBFBD><D8BA><EFBFBD>Ȳ
+1. MCAL 19.4.0 => Tony <20><><EFBFBD><EFBFBD> <20>Ϸ<EFBFBD>.
+2. Autosar SC3
+
+*SPI <20><><EFBFBD><EFBFBD>¡ Test 
+Mobis - Autosar SC3 + MCAL 19.1.0 + SPI Multi-Core Patch : <20>ݿ<EFBFBD><DDBF><EFBFBD> Start
+Renesas - Autosar SC1 + P1 Environment + SPI Multi-Core Patch : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 16:00 Start
+
+<EFBFBD>ʿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
+*<2A><><EFBFBD><EFBFBD> <20><>ġ<EFBFBD><C4A1> MCAL 19.4.0 Base<73><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD>Ѵ<EFBFBD>.
+1. SPI Multi-Core(Like Type2) Patch <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
+2. I2C Stuck <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
+3. I2C Reset API 1th <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> MCAL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
+4. I2C <20><> <20>⺻ Build <20><> <20><> <20>ְ<EFBFBD> RTE_xx <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(Binh<6E><68> MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>)
+5. MCU Module PLL <20><>ȸ <20><><EFBFBD><EFBFBD>, Jira-487 <20><>ġ<EFBFBD><C4A1> <20>ʿ<EFBFBD>.
+
+*ECM/EMM/RFSO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>̵尡 <20>ʿ<EFBFBD>.
+*MTCI I2C Reset API <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʴ´<CAB4>.
+*SPI Multi-Core Patch <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+
+<EFBFBD>ڵ帮<EFBFBD><EFBFBD>X