diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/Mobis빌드시사용모듈.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/Mobis빌드시사용모듈.txt new file mode 100644 index 00000000..9d9e907b --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/Mobis빌드시사용모듈.txt @@ -0,0 +1,13 @@ +»ç¿ë ¸ðµâ +MCU +IIC +WDG -> »ç¿ë ¾ÈÇÏ´Â µí +ICCOM +SPI +PORT +GPT +DIO + + + +19.4.0 SPI°¡ µ¿ÀÛÇÏ´Ù°¡ ³ëƼ°¡ ¿Ã¶ó¿ÀÁö ¾Ê´Â Çö»óÀÌ ÀÖ´Ù. diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt new file mode 100644 index 00000000..848954dc --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt @@ -0,0 +1,68 @@ +void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data) +{ + uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF); + uint8 targetAddr = (uint8) (regAdd & 0xFF); + uint8 txBuf[3]; /* [Address, Data, CRC] */ + uint8 crcInput[4]; /* Maximum 4 bytes for Read-back CRC */ + uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress; + + /* 1. Page Switching Logic with CRC8 */ + if (g_pmic_current_page[slaveIdx] != targetPage) + { + uint8 pgRxBuf[2]; + + txBuf[0] = 0x00; /* Page Selector Register */ + txBuf[1] = targetPage; /* This is 0x01 */ + + crcInput[0] = (slaveAddr << 1) | 0x00U; + crcInput[1] = txBuf[0]; + crcInput[2] = txBuf[1]; + txBuf[2] = crc8(crcInput, 3); + + /* [Spec] Page Write - 1st */ + IIC_Reset(); + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + /* [Spec] Page Write - 2nd */ + IIC_Reset(); + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + /* [Spec] Page Read-back Verification */ + IIC_Reset(); + CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + crcInput[0] = (slaveAddr << 1) | 0x00U; + crcInput[1] = 0x00; + crcInput[2] = (slaveAddr << 1) | 0x01U; + crcInput[3] = pgRxBuf[0]; + + if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage)) + { + g_pmic_current_page[slaveIdx] = targetPage; + } + else + { + g_pmic_current_page[slaveIdx] = 0xFF; + return; + } + } + + /* 2. Actual Data Write with CRC8 */ + /* RE-INITIALIZE txBuf and crcInput with correct values (targetAddr=0x07, data=0x84) */ + txBuf[0] = targetAddr; /* 0x07 */ + txBuf[1] = data; /* 0x84 - ÀÎÀÚ·Î ¹ÞÀº µ¥ÀÌÅÍ ¸í½ÃÀû ´ëÀÔ */ + + /* Calculate CRC specifically for this write operation */ + crcInput[0] = (slaveAddr << 1) | 0x00U; + crcInput[1] = txBuf[0]; /* 0x07 */ + crcInput[2] = txBuf[1]; /* 0x84 */ + txBuf[2] = crc8(crcInput, 3); + + IIC_Reset(); + /* Expecting Packet: SlaveID + 0x07 + 0x84 + CRC */ + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); +} \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_old.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_old.txt new file mode 100644 index 00000000..00041055 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_old.txt @@ -0,0 +1,70 @@ +void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data) +{ + uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF); + uint8 targetAddr = (uint8)(regAdd & 0xFF); + uint8 txBuf[3]; /* [Address, Data, CRC] */ + uint8 crcInput[4]; /* Maximum 4 bytes for Read-back CRC */ + uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress; + + /* 1. Page Switching Logic with CRC8 */ + if (g_pmic_current_page[slaveIdx] != targetPage) + { + uint8 pgRxBuf[2]; /* [Data, CRC] */ + + /* Prepare Page Change Packet: Reg 0x00, Target Page */ + txBuf[0] = 0x00; /* Page Selector Register */ + txBuf[1] = targetPage; + + /* CRC for Write: SlaveAddr(W) + RegAddr + Data */ + crcInput[0] = (slaveAddr << 1) | 0x00U; + crcInput[1] = txBuf[0]; + crcInput[2] = txBuf[1]; + txBuf[2] = crc8(crcInput, 3); + + /* [Spec] 1st Page Write with CRC */ + IIC_Reset(); + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + /* [Spec] 2nd Page Write with CRC */ + IIC_Reset(); + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + /* [Spec] Page Read-back Verification with CRC */ + IIC_Reset(); + /* Use WriteRead (Repeated Start) to read Reg 0x00 */ + CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); + + /* [Modified] Verify Read-back CRC: SlaveAddr(W) + RegAddr + SlaveAddr(R) + Received Data */ + crcInput[0] = (slaveAddr << 1) | 0x00U; /* Slave(W) */ + crcInput[1] = 0x00; /* Register Address (Page Selector) */ + crcInput[2] = (slaveAddr << 1) | 0x01U; /* Slave(R) */ + crcInput[3] = pgRxBuf[0]; /* Received Page Value */ + + if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage)) + { + g_pmic_current_page[slaveIdx] = targetPage; + } + else + { + g_pmic_current_page[slaveIdx] = 0xFF; /* Switch failed or CRC error */ + return; + } + } + + /* 2. Actual Data Write with CRC8 */ + txBuf[0] = targetAddr; + txBuf[1] = data; + + /* CRC for Write: SlaveAddr(W) + RegAddr + Data */ + crcInput[0] = (slaveAddr << 1) | 0x00U; + crcInput[1] = txBuf[0]; + crcInput[2] = txBuf[1]; + txBuf[2] = crc8(crcInput, 3); + + IIC_Reset(); + CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]); + I2C_Communication_Complete(); +} \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt new file mode 100644 index 00000000..1fd275d6 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt @@ -0,0 +1,49 @@ + +(Priority1)¡á Multicore SPI support for lower CPU usage(REKR_MOBIS-270) + ¡Ý Case1- Workaround(Short term solution) + Pham is currently modifying the source code within the customer's environment + + ¡Ý Case2 - MCAL Multicore TYPE 4(Long term solution) + Support for Multi-core Type 4 is feasible; however, we need additional time to ensure a quality implementation. + + Reference URL"2.5.6.4 MCAL Multi-Core Module Type IV" + https://www.autosar.org/fileadmin/standards/R19-11/CP/AUTOSAR_EXP_BSWDistributionGuide.pdf + +(Priority1)¡á I2C communication reset requirement: explanation the I2C patch to customer(REKR_MOBIS-943) + ¡Ý Binh to provide a technical explanation to the customer. + ¡Ý MCAL Version Verification + v19.1.0 -> we will check custemer's use ver. + v19.3.0 -> we will check custemer's use ver. + v19.4.0 -> The customer is planning to update to this version. Renesas will issue a patch based on this version.(Target Delivery Date: May 22th) + +(Priority1)¡á I2C communication reset requirement: Reset requirement discussion(REKR_MOBIS-995/957) + The customer tested after removing the Reset function(Reset I2C with SRCR and SRSTCLR), + but they reported that I2C Stuck occurred. (Note: This is verbal feedback; no formal logs are available yet.) + In today's meeting, Binh advised the customer that removing the Reset API is not recommended. + + The customer's is that directly controlling H/W registers from the BSW (rather than using an API) is not an ideal implementation. + + ¡Ý Requests to the H/W Team + Customer Requirement: + Please provide a detailed technical explanation of why the Reset(Reset I2C with SRCR and SRSTCLR) is mandatory for I2C communication. + We need clear reasoning to justify this to the customer. + + ¡Ý Requests to the MCAL Team + Customer Requirement: The customer is requesting to have the I2C Reset integrated within the MCAL CDD Iic. + If we proceed with this integration, what would be the expected delivery schedule? + +¡á AutoSAR architecture review + Meeting with the customer is scheduled for Tuesday, May 12th in the afternoon. + +¡á Let's review the source code together to debug this issue. + ¡Ý CDD EMM notification(callback: REKR_MOBIS-1000) + ¡Ý IRQ model sample code(REKR_MOBIS-965) + +¡á We need to verify the actual behavior of the CDD module + CRC: Verification is needed. + EMM: Verification is needed. + IPMMU: The customer will not use this feature as it conflicts with the existing configurations on the QNX side. + RFSO: Verification is needed. + THS: Verification is needed. 1°³ ¼¾¼­ ¼³Á¤, but 4°³ ¼¾¼­ NotificationÀÌ EMMÀ¸·Î ¿Ã¶ó¿È.(Â÷µ¿ÈÆ Ã¥ÀÓ´Ô AP¿¡¼­ 4°³ »ç¿ë°¡´ÉÇÑÁö È®ÀÎ) + ICCOM: The customer has completed the verification. + IIC: The customer has completed the verification. diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt new file mode 100644 index 00000000..ec9c075b --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt @@ -0,0 +1,32 @@ + P1 P2 +OEM 6/1 9/15 +Mobis 5/15 6/30 +Code Freeze + +Tony. ¸®Äù½ºÆ® CPM Fully Type2 ¿äû +1¸í 7°³¿ù + +Autosar SC1 : DDR Only »ç¿ë +Autosar SC3 : SRAM ÀϺΠ+ DDR »ç¿ë + +°í°´ Áغñ»óȲ +1. MCAL 19.4.0 => Tony Àü´Þ ¿Ï·á. +2. Autosar SC3 + +*SPI ¿¡ÀÌ¡ Test +Mobis - Autosar SC3 + MCAL 19.1.0 + SPI Multi-Core Patch : ±Ý¿äÀÏ Start +Renesas - Autosar SC1 + P1 Environment + SPI Multi-Core Patch : ¸ñ¿äÀÏ 16:00 Start + +ÇÊ¿ä»çÇ× +*¸ðµç ÆÐÄ¡´Â MCAL 19.4.0 Base¿¡¼­ ¹ßÇàµÇ¾î¾ßÇÑ´Ù. +1. SPI Multi-Core(Like Type2) Patch Áغñ(¾Æ¸¶ Pham) +2. I2C Stuck ÆÐÄ¡ Áغñ(¾Æ¸¶ Pham) +3. I2C Reset API 1th ÆÐÄ¡ Áغñ(¾Æ¸¶ MCAL °³¹ßÆÀ) +4. I2C °¡ ±âº» Build µÉ ¼ö ÀÖ°Ô RTE_xx »èÁ¦ ¹× ¼öÁ¤(BinhÀÌ MCAL ÆÀ°ú ÇùÀÇ Áß) +5. MCU Module PLL ¿ìȸ ¼³Á¤, Jira-487 ÆÐÄ¡°¡ ÇÊ¿ä. + +*ECM/EMM/RFSO ±¸Çö¹æ¹ý °¡À̵尡 ÇÊ¿ä. +*MTCI I2C Reset API µ¿ÀÛÀÌ µÇÁö ¾Ê´Â´Ù. +*SPI Multi-Core Patch ÈÄ ÆÄÇü ÃøÁ¤ + +Äڵ帮ºäX diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx new file mode 100644 index 00000000..c9da1320 Binary files /dev/null and b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx differ diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx new file mode 100644 index 00000000..82d54e61 Binary files /dev/null and b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx differ diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260526_GPIO_SET.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260526_GPIO_SET.txt new file mode 100644 index 00000000..02b2ee31 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260526_GPIO_SET.txt @@ -0,0 +1,31 @@ +¹Ú¼ºÁØ Ã¥ÀÓ´Ô Test +8Â÷ º¸µå PMIC IRQ GP4_16 ÀÎÅÍ·´Æ® Test +8Â÷ º¸µå SCL3 GP8_6 ÀÎÅÍ·´Æ® Test + +Interrupt Mask Clear +Register MSKCLRn R/W H¡¯0000 0000 H¡¯19C 32 + + +For some unknown reason, testing on GP1_20 showed that GP0_6 was being controlled instead. +Consequently, Mobis is planning to change the assignment once again from GP1_20 to GP4_16. + +Will there be any issues if Mobis uses GP4_16 to receive the PMIC Interrupt? + +Interrupt ID +>619 PortGroup0 0x028B GPIO0_port_group0.ch0 +> + 32 +> = 651 + +>623 PortGroup1 0x028F GPIO0_port_group1.ch0 +> + 32 +> = 655 + +>635 PortGroup4 0x029B GPIO2_port_group0.ch0 +> + 32 +> = 667 + +>651 PortGroup8 0x02AB GPIO3_port_group0.ch0 +> + 32 +> = 683 + +PER.Set.simple ASD:0xE605019C %Long 0x40 \ No newline at end of file diff --git a/Datasheet/PMIC/PMIC_Memory_Map_수정중.xlsx b/Datasheet/PMIC/PMIC_Memory_Map_수정중.xlsx new file mode 100644 index 00000000..8a221a89 Binary files /dev/null and b/Datasheet/PMIC/PMIC_Memory_Map_수정중.xlsx differ