add

2026-06-15 15:51:05 +09:00
parent eef0056485
commit f4b5cfc54a
9 changed files with 263 additions and 0 deletions
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/Mobis빌드시사용모듈.txt
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/Mobis빌드시사용모듈.txt
@@ -0,0 +1,13 @@
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+MCU
+IIC
+WDG -> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϴ<EFBFBD> <20><>
+ICCOM
+SPI
+PORT
+GPT
+DIO
+
+
+
+19.4.0 SPI<50><49> <20><><EFBFBD><EFBFBD><EFBFBD>ϴٰ<CFB4> <20><>Ƽ<EFBFBD><C6BC> <20>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD> <20>ʴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ִ<EFBFBD>.
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt
@@ -0,0 +1,68 @@
+void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8) (regAdd & 0xFF);
+    uint8 txBuf[3];      /* [Address, Data, CRC] */
+    uint8 crcInput[4];   /* Maximum 4 bytes for Read-back CRC */
+    uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress;
+
+    /* 1. Page Switching Logic with CRC8 */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        uint8 pgRxBuf[2]; 
+        
+        txBuf[0] = 0x00;        /* Page Selector Register */
+        txBuf[1] = targetPage;  /* This is 0x01 */
+        
+        crcInput[0] = (slaveAddr << 1) | 0x00U;
+        crcInput[1] = txBuf[0];
+        crcInput[2] = txBuf[1];
+        txBuf[2] = crc8(crcInput, 3);
+
+        /* [Spec] Page Write - 1st */
+        IIC_Reset();
+        CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        /* [Spec] Page Write - 2nd */
+        IIC_Reset();
+        CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        /* [Spec] Page Read-back Verification */
+        IIC_Reset();
+        CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        crcInput[0] = (slaveAddr << 1) | 0x00U;
+        crcInput[1] = 0x00;
+        crcInput[2] = (slaveAddr << 1) | 0x01U;
+        crcInput[3] = pgRxBuf[0];
+        
+        if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage))
+        {
+            g_pmic_current_page[slaveIdx] = targetPage;
+        }
+        else
+        {
+            g_pmic_current_page[slaveIdx] = 0xFF; 
+            return;
+        }
+    }
+
+    /* 2. Actual Data Write with CRC8 */
+    /* RE-INITIALIZE txBuf and crcInput with correct values (targetAddr=0x07, data=0x84) */
+    txBuf[0] = targetAddr;      /* 0x07 */
+    txBuf[1] = data;            /* 0x84 - <20><><EFBFBD>ڷ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> */
+    
+    /* Calculate CRC specifically for this write operation */
+    crcInput[0] = (slaveAddr << 1) | 0x00U;
+    crcInput[1] = txBuf[0];     /* 0x07 */
+    crcInput[2] = txBuf[1];     /* 0x84 */
+    txBuf[2] = crc8(crcInput, 3);
+
+    IIC_Reset();
+    /* Expecting Packet: SlaveID + 0x07 + 0x84 + CRC */
+    CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+    I2C_Communication_Complete();
+}
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_old.txt
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_old.txt
@@ -0,0 +1,70 @@
+void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8)(regAdd & 0xFF);
+    uint8 txBuf[3];      /* [Address, Data, CRC] */
+    uint8 crcInput[4];   /* Maximum 4 bytes for Read-back CRC */
+    uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress;
+
+    /* 1. Page Switching Logic with CRC8 */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        uint8 pgRxBuf[2]; /* [Data, CRC] */
+        
+        /* Prepare Page Change Packet: Reg 0x00, Target Page */
+        txBuf[0] = 0x00;        /* Page Selector Register */
+        txBuf[1] = targetPage;
+        
+        /* CRC for Write: SlaveAddr(W) + RegAddr + Data */
+        crcInput[0] = (slaveAddr << 1) | 0x00U;
+        crcInput[1] = txBuf[0];
+        crcInput[2] = txBuf[1];
+        txBuf[2] = crc8(crcInput, 3);
+
+        /* [Spec] 1st Page Write with CRC */
+        IIC_Reset();
+        CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        /* [Spec] 2nd Page Write with CRC */
+        IIC_Reset();
+        CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        /* [Spec] Page Read-back Verification with CRC */
+        IIC_Reset();
+        /* Use WriteRead (Repeated Start) to read Reg 0x00 */
+        CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+        I2C_Communication_Complete();
+
+        /* [Modified] Verify Read-back CRC: SlaveAddr(W) + RegAddr + SlaveAddr(R) + Received Data */
+        crcInput[0] = (slaveAddr << 1) | 0x00U; /* Slave(W) */
+        crcInput[1] = 0x00;                     /* Register Address (Page Selector) */
+        crcInput[2] = (slaveAddr << 1) | 0x01U; /* Slave(R) */
+        crcInput[3] = pgRxBuf[0];               /* Received Page Value */
+        
+        if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage))
+        {
+            g_pmic_current_page[slaveIdx] = targetPage;
+        }
+        else
+        {
+            g_pmic_current_page[slaveIdx] = 0xFF; /* Switch failed or CRC error */
+            return;
+        }
+    }
+
+    /* 2. Actual Data Write with CRC8 */
+    txBuf[0] = targetAddr;
+    txBuf[1] = data;
+    
+    /* CRC for Write: SlaveAddr(W) + RegAddr + Data */
+    crcInput[0] = (slaveAddr << 1) | 0x00U;
+    crcInput[1] = txBuf[0];
+    crcInput[2] = txBuf[1];
+    txBuf[2] = crc8(crcInput, 3);
+
+    IIC_Reset();
+    CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+    I2C_Communication_Complete();
+}
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt
@@ -0,0 +1,49 @@
+
+(Priority1)<29><> Multicore SPI support for lower CPU usage(REKR_MOBIS-270)
+	<09><> Case1- Workaround(Short term solution)
+			Pham is currently modifying the source code within the customer's environment
+
+	<09><> Case2 - MCAL Multicore TYPE 4(Long term solution) 
+			Support for Multi-core Type 4 is feasible; however, we need additional time to ensure a quality implementation.
+
+			Reference URL"2.5.6.4 MCAL Multi-Core Module Type IV"
+			https://www.autosar.org/fileadmin/standards/R19-11/CP/AUTOSAR_EXP_BSWDistributionGuide.pdf
+
+(Priority1)<29><> I2C communication reset requirement: explanation the I2C patch to customer(REKR_MOBIS-943)
+	<09><> Binh to provide a technical explanation to the customer.
+	<09><> MCAL Version Verification
+		v19.1.0  -> we will check custemer's use ver.
+		v19.3.0 -> we will check custemer's use ver.
+		v19.4.0 -> The customer is planning to update to this version. Renesas will issue a patch based on this version.(Target Delivery Date: May 22th)
+
+(Priority1)<29><> I2C communication reset requirement: Reset requirement discussion(REKR_MOBIS-995/957)
+	The customer tested after removing the Reset function(Reset I2C with SRCR and SRSTCLR), 
+	but they reported that I2C Stuck occurred. (Note: This is verbal feedback; no formal logs are available yet.)
+	In today's meeting, Binh advised the customer that removing the Reset API is not recommended.
+
+	The customer's  is that directly controlling H/W registers from the BSW (rather than using an  API) is not an ideal implementation.
+
+	<09><> Requests to the H/W Team
+	Customer Requirement: 
+	Please provide a detailed technical explanation of why the Reset(Reset I2C with SRCR and SRSTCLR) is mandatory for I2C communication. 
+	We need clear reasoning to justify this to the customer.
+
+	<09><> Requests to the MCAL Team
+	Customer Requirement: The customer is requesting to have the I2C Reset integrated within the MCAL CDD Iic.
+	If we proceed with this integration, what would be the expected delivery schedule?
+
+<EFBFBD><EFBFBD> AutoSAR architecture review
+	Meeting with the customer is scheduled for Tuesday, May 12th in the afternoon.
+
+<EFBFBD><EFBFBD> Let's review the source code together to debug this issue.
+	 <20><> CDD EMM notification(callback: REKR_MOBIS-1000)
+	 <20><> IRQ model sample code(REKR_MOBIS-965)
+
+<EFBFBD><EFBFBD> We need to verify the actual behavior of the CDD module
+	CRC: Verification is needed.
+	EMM: Verification is needed.
+	IPMMU: The customer will not use this feature as it conflicts with the existing configurations on the QNX side.
+	RFSO: Verification is needed.
+	THS: Verification is needed. 1<><31> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, but 4<><34> <20><><EFBFBD><EFBFBD> Notification<6F><6E> EMM<4D><4D><EFBFBD><EFBFBD> <20>ö<EFBFBD><C3B6><EFBFBD>.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD> AP<41><50><EFBFBD><EFBFBD> 4<><34> <20><><EFBFBD>밡<EFBFBD><EBB0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>)
+	ICCOM: The customer has completed the verification.
+	IIC: The customer has completed the verification.
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt
@@ -0,0 +1,32 @@
+           P1       P2
+OEM      6/1      9/15
+Mobis   5/15     6/30
+Code Freeze
+
+Tony. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ CPM Fully Type2 <20><>û
+1<EFBFBD><EFBFBD> 7<><37><EFBFBD><EFBFBD>
+
+Autosar SC1 : DDR Only <20><><EFBFBD><EFBFBD>
+Autosar SC3 : SRAM <20>Ϻ<EFBFBD> + DDR <20><><EFBFBD><EFBFBD>
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>غ<EFBFBD><D8BA><EFBFBD>Ȳ
+1. MCAL 19.4.0 => Tony <20><><EFBFBD><EFBFBD> <20>Ϸ<EFBFBD>.
+2. Autosar SC3
+
+*SPI <20><><EFBFBD><EFBFBD>¡ Test 
+Mobis - Autosar SC3 + MCAL 19.1.0 + SPI Multi-Core Patch : <20>ݿ<EFBFBD><DDBF><EFBFBD> Start
+Renesas - Autosar SC1 + P1 Environment + SPI Multi-Core Patch : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 16:00 Start
+
+<EFBFBD>ʿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
+*<2A><><EFBFBD><EFBFBD> <20><>ġ<EFBFBD><C4A1> MCAL 19.4.0 Base<73><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD>Ѵ<EFBFBD>.
+1. SPI Multi-Core(Like Type2) Patch <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
+2. I2C Stuck <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
+3. I2C Reset API 1th <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> MCAL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
+4. I2C <20><> <20>⺻ Build <20><> <20><> <20>ְ<EFBFBD> RTE_xx <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(Binh<6E><68> MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>)
+5. MCU Module PLL <20><>ȸ <20><><EFBFBD><EFBFBD>, Jira-487 <20><>ġ<EFBFBD><C4A1> <20>ʿ<EFBFBD>.
+
+*ECM/EMM/RFSO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>̵尡 <20>ʿ<EFBFBD>.
+*MTCI I2C Reset API <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʴ´<CAB4>.
+*SPI Multi-Core Patch <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+
+<EFBFBD>ڵ帮<EFBFBD><EFBFBD>X
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx
--- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External
@@ -0,0 +1,31 @@
+<EFBFBD>ڼ<EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD> Test 
+8<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> PMIC IRQ GP4_16 <20><><EFBFBD>ͷ<EFBFBD>Ʈ Test
+8<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> SCL3 GP8_6 <20><><EFBFBD>ͷ<EFBFBD>Ʈ Test
+
+Interrupt Mask Clear
+Register MSKCLRn R/W H<><48>0000 0000 H<><48>19C 32 
+
+
+For some unknown reason, testing on GP1_20 showed that GP0_6 was being controlled instead. 
+Consequently, Mobis is planning to change the assignment once again from GP1_20 to GP4_16.
+
+Will there be any issues if Mobis uses GP4_16 to receive the PMIC Interrupt?
+
+Interrupt ID
+>619	 PortGroup0	0x028B	GPIO0_port_group0.ch0
+> + 32
+> = 651
+
+>623	 PortGroup1	0x028F	GPIO0_port_group1.ch0
+> + 32
+> = 655
+
+>635	 PortGroup4	0x029B	GPIO2_port_group0.ch0
+> + 32
+> = 667
+
+>651 	PortGroup8	0x02AB	GPIO3_port_group0.ch0
+> + 32
+> = 683
+
+PER.Set.simple ASD:0xE605019C %Long 0x40