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IOC, BSS
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MPU <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE><EFBFBD><EFBFBD> <20>ʿ<EFBFBD>
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DBSC5 -> <20><>Ʈ<EFBFBD>ѷ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> DDR<44><52> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>־<EFBFBD>?
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<EFBFBD>̰<EFBFBD> QoS <20><><EFBFBD><EFBFBD><EFBFBD>̾<EFBFBD>?
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1. DDR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> <20><><EFBFBD><EFBFBD> <20>帳<EFBFBD>ϴ<EFBFBD>.
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2. <20>ϱ<EFBFBD> A3CR0, A3CR1, A3CR2 <20><> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>帳<EFBFBD>ϴ<EFBFBD>.
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3. <20>߰<EFBFBD><DFB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> RCORE ROM/RAM<41><4D> <20>ٸ<EFBFBD><D9B8><EFBFBD><EFBFBD><EFBFBD> <20><>ġ<EFBFBD>Ͽ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>ִٸ<D6B4> <20><><EFBFBD><EFBFBD> <20><>Ź<EFBFBD>帳<EFBFBD>ϴ<EFBFBD>.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ұ<EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>̳ʸ<CCB3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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PCU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ڷ<EFBFBD><DAB7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD>.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><EEB6BB> üũ<C3BC>ؾ<EFBFBD><D8BE>ϴ<EFBFBD><CFB4><EFBFBD> <20>ٴ°<D9B4> <20>Ϻ<EFBFBD><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><EEB6B2>?
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IPL <20><><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>.
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2<EFBFBD><EFBFBD>
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DBSC5 & AXI-Bus(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ) <20>Ѵ<EFBFBD>.
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IPL<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
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TCM -> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>?
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<EFBFBD>ٸ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD><D7BE>ְ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD>.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> IOC,
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<EFBFBD><EFBFBD><EFBFBD>鷯.
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RTVRAM 0 - IPL<50><4C><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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RTVRAM 1 - <20><><EFBFBD><EFBFBD> IOC, BSS <20><> <20>Ű<EFBFBD> <20>ôµ<C3B4>. <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> ȿ<><C8BF><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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SYSRAM - E630000 -> <20><><EFBFBD> <20>־ Test
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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TCM <20><><EFBFBD><EFBFBD>
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MPU<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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TCM
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SRAM. =>
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DDR.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>, ->
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CRO.
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ddr <20>ű<EFBFBD><C5B1><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>
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QOx <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ÿ<EFBFBD><C5B8>.
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DBSC5.
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Cat. MPU.
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4.2.2.
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CR52<EFBFBD><EFBFBD> Write <20><><EFBFBD><EFBFBD>, 1<><31>
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1. DDR <20>ִ<EFBFBD> <20>̹<EFBFBD><CCB9><EFBFBD><EFBFBD><EFBFBD> <20>Ϻθ<CFBA> SRAM, TCM<43><4D><EFBFBD><EFBFBD> <20>ű<EFBFBD><C5B1><EFBFBD> <20>۾<EFBFBD> <20>ʿ<EFBFBD>(AI HKL)
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- TCM enable <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD><EFBFBD>.
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2. <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> QoS <20><><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> CR-Core <20><><EFBFBD><EFBFBD> Up<55><70> <20>ɼ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> <20><><EFBFBD><EFBFBD>(AI <20><>Ÿ<EFBFBD><C5B8>)
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3. DBSC5 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>̻<EFBFBD><CCBB><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> CR-Core <20><><EFBFBD><EFBFBD> Up<55><70> <20>ɼ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> <20><><EFBFBD><EFBFBD>(AI <20><>Ÿ<EFBFBD><C5B8>)
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- DBSC5 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD> HKL<4B><4C><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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4. Scat <20><><EFBFBD>ϰ<EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20>̻<EFBFBD><CCBB><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(Woody&HKL)
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5. Core Write Buffer(WBCTLR)<29><> Enable <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE>.
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- TR32<33><32> Ȯ<><C8AE><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> disable<6C><65> <20>Ǿ<EFBFBD> <20>־<EFBFBD> Enable<6C>ؼ<EFBFBD> ȿ<><C8BF> Ȯ<><C8AE>
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@@ -0,0 +1,451 @@
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DBSC5 (External Bus Controller for SDRAM)
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DBSC5_0
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DB0SYSCONF0 00000001 Reserved_11 000000 Reserved_8 0
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Reserved_3 00 pch 1
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DB0SYSCONF1A 00000000 Reserved_2 00000000 freqratioa ?
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DB0SYSCONF2A 00000241 Reserved_10 000000 dfickm 1: LPDDR5
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chpos 08 sli_schmda 1: 16bit x 2ch
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DB0MEMKINDA 0000000C Reserved_4 00000000 ddcga 0C
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DB0MEMCONF00A 10220A01 dens00a 0: 2^n type Reserved_29 0
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awrw00a 10 Reserved_22 0
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awbg00a 2: 4 Bankgroups Reserved_19 0
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awbk00a 2: 4 banks Reserved_12 00
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awcl00a 0A Reserved_2 00
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dw00a 1: 16 bits
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DB0MEMCONF01A 00000000 dens01a 0: 2^n type Reserved_29 0
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awrw01a 00 Reserved_22 0
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awbg01a 0: 0 Bankgroup Reserved_19 0
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awbk01a ? Reserved_12 00
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awcl01a 00 Reserved_2 00
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dw01a ?
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DB0MEMCONF10A 10220A01 dens10a 0: 2^n type Reserved_29 0
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awrw10a 10 Reserved_22 0
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awbg10a 2: 4 Bankgroups Reserved_19 0
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awbk10a 2: 4 banks Reserved_12 00
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awcl10a 0A Reserved_2 00
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dw10a 1: 16 bits
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DB0MEMCONF11A 00000000 dens11a 0: 2^n type Reserved_29 0
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awrw11a 00 Reserved_22 0
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awbg11a 0: 0 Bankgroup Reserved_19 0
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awbk11a ? Reserved_12 00
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awcl11a 00 Reserved_2 00
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dw11a ?
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DB0SYSCNT0A 00000000 Reserved_16 0000 reglocka 0000
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DB0FCPRSCTRL00A 00000000 Reserved_1 00000000 fcscachedis 0: enable
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DB0ACEN 00000001 Reserved_1 00000000 accen 1: Enables access to the SDRAM
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DB0BLA 00000002 Reserved_2 00000000 bla 2: Fixed to 16
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DB0BUS0CNF1 00010000 Reserved_17 0000 bgadm 1: Comatible Mode
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Reserved_14 0 Reserved_8 00
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bkadp 00 bkadm 0: The whole logical address space is regarded as..
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DB0CAM0CNF1 00048218 Reserved_24 00 wbkwait 04
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swpinpri3 08 swpinpri2 02
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swpinpri1 01 swpinpri1f 08
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DB0CAM0CNF2 000001C4 Reserved_10 000000 fillunit 1: 128 bytes
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fcdirtymax 0C fcdirtymin 04
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DB0CAM0CNF3 00000003 Reserved_8 000000 rdfull 03
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DB0CAM0CTRL0 00000000 Reserved_1 00000000 camflush 0: No flush
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DB0CAM0STAT0 00000001 Reserved_1 00000000 camempty0 1: Data is empty in cache 0
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DB0SCHCNT0 000F0037 Reserved_26 00 scqosckps 0: No scaler apply
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Reserved_20 00 scqtzen 0F
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Reserved_6 0000 scszen 1: enable
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scbaen 1: enable Reserved_3 0
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scpgen 1: enable scrwen 1: enable
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scqosen 1: enable
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DB0SCHCNT1 00000000 Reserved_16 0000 Reserved_8 00
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schch1 00 schch0 00
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DB0SCHSZ0 00000001 Reserved_8 000000 szth 01
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DB0SCHRW0 F7311111 rdstptol3 0F rdstptol2 07
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rdstptol1 03 rdstptol0 01
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wrstptol3 01 wrstptol2 01
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wrstptol1 01 wrstptol0 01
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DB0SCHRW1 0000007C Reserved_24 00 Reserved_8 0000
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sctrfcab 7C
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DB0SCHTR0 09070401 scdt3 09 scdt2 07
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scdt1 04 scdt0 01
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DB0SCHFCTST0 180A1C07 scactact 18 scrdact 0A
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scwract 1C scpreact 07
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DB0SCHFCTST1 0A0C070C scrdwr 0A scwrrd 0C
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scactrdwr 07 scasyncofs 0C
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DB0SCHFCTST2 111F1FFF wrperi3 01 wrperi2 01
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wrperi1 01 wrperi0 0F
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rdperi3 01 rdperi2 0F
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rdperi1 0F rdperi0 0F
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DB0SCHQOS00 0000FFFF Reserved_16 0000 qos0ini FFFF
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DB0SCHQOS01 00000480 Reserved_16 0000 qos0th0 0480
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DB0SCHQOS02 00000300 Reserved_16 0000 qos0th1 0300
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DB0SCHQOS03 00000180 Reserved_16 0000 qos0th2 0180
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DB0SCHQOS40 00000400 Reserved_16 0000 qos4ini 0400
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DB0SCHQOS41 00000300 Reserved_16 0000 qos4th0 0300
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DB0SCHQOS42 00000200 Reserved_16 0000 qos4th1 0200
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DB0SCHQOS43 00000100 Reserved_16 0000 qos4th2 0100
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DB0SCHQOS90 00000300 Reserved_16 0000 qos9ini 0300
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DB0SCHQOS91 00000240 Reserved_16 0000 qos9th0 0240
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DB0SCHQOS92 00000180 Reserved_16 0000 qos9th1 0180
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DB0SCHQOS93 000000C0 Reserved_16 0000 qos9th2 00C0
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DB0SCHQOS120 00000040 Reserved_16 0000 qos12ini 0040
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DB0SCHQOS121 00000030 Reserved_16 0000 qos12th0 0030
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DB0SCHQOS122 00000020 Reserved_16 0000 qos12th1 0020
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DB0SCHQOS123 00000010 Reserved_16 0000 qos12th2 0010
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DB0SCHQOS130 00000300 Reserved_16 0000 qos13ini 0300
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DB0SCHQOS131 00000240 Reserved_16 0000 qos13th0 0240
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DB0SCHQOS132 00000180 Reserved_16 0000 qos13th1 0180
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DB0SCHQOS133 000000C0 Reserved_16 0000 qos13th2 00C0
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DB0SCHQOS140 00000200 Reserved_16 0000 qos14ini 0200
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DB0SCHQOS141 00000180 Reserved_16 0000 qos14th0 0180
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DB0SCHQOS142 00000100 Reserved_16 0000 qos14th1 0100
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DB0SCHQOS143 00000080 Reserved_16 0000 qos14th2 0080
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DB0SCHQOS150 00000100 Reserved_16 0000 qos15ini 0100
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DB0SCHQOS151 000000C0 Reserved_16 0000 qos15th0 00C0
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DB0SCHQOS152 00000080 Reserved_16 0000 qos15th1 0080
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DB0SCHQOS153 00000040 Reserved_16 0000 qos15th2 0040
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DB0FSINTXXX00A 00000000 intexdclaxa 0: no interrupt intexdclsra 0: no interrupt
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Reserved_11 000000 intodasbda 0: no interrupt
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intodasrda 0: no interrupt intodasbxa 0: no interrupt
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intodasrxa 0: no interrupt intodaswxa 0: no interrupt
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intodasawa 0: no interrupt intodasara 0: no interrupt
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Reserved_3 0 intdxaswxa 0: no interrupt
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intdxasawa 0: no interrupt intdxasara 0: no interrupt
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DB0FSINTXXX01A 00000000 Reserved_23 0000 Reserved_16 00
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Reserved_7 0000 intnomem0a 0: no interrupt
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intedbccr0a 0: no interrupt Reserved_4 0
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intdxamawx0a 0: no interrupt intdxamaw0a 0: no interrupt
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intdxamar0a 0: no interrupt intepdvaxi0a 0: no interrupt
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DB0FSINTXXX02A 00000000 intcmbcsr0a 00 intcdbcsr0a 00
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intcmbcrr0a 00 intcdbcrr0a 00
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DB0FSINTXXX03A 00000000 intcdbcdr0a 00000000
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DB0FSINTXXX04A 00000000 intcmbcdr0a 00000000
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DB0FSINTXXX08A 00000000 Reserved_19 0000 Reserved_16 0
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Reserved_3 0000 intexbcdr0a 0: no interrupt
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intexbcsr0a 0: no interrupt intexbcrr0a 0: no interrupt
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DB0FSINTXXX09A 00000000 Reserved_26 00 Reserved_24 0
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Reserved_18 00 Reserved_16 0
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Reserved_10 00 intoddvard1a 0: no interrupt
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intdxdvard1a 0: no interrupt Reserved_2 00
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intoddvard0a 0: no interrupt intdxdvard0a 0: no interrupt
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DB0FSINTXXX10A 00000000 Reserved_16 0000 intxxasynsba 0000
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DB0FSINTCLR00A 00000000 Reserved_1 00000000 icldclsa ?
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DB0FSINTENB00A C00007F7 ienexdclaxa 1: Interrupt enable ienexdclsra 1: Interrupt enable
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Reserved_11 000000 ienodasbda 1: Interrupt enable
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ienodasrda 1: Interrupt enable ienodasbxa 1: Interrupt enable
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ienodasrxa 1: Interrupt enable ienodaswxa 1: Interrupt enable
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ienodasawa 1: Interrupt enable ienodasara 1: Interrupt enable
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Reserved_3 0 iendxaswxa 1: Interrupt enable
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iendxasawa 1: Interrupt enable iendxasara 1: Interrupt enable
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DB0FSINTENB01A 0000000E Reserved_23 0000 Reserved_16 00
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Reserved_7 0000 iennomem0a 0: Interrupt disable
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ienedbccr0a 0: Interrupt disable Reserved_4 0
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iendxamawx0a 1: Interrupt enable iendxamaw0a 1: Interrupt enable
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iendxamar0a 1: Interrupt enable ienepdvaxi0a 0: Interrupt disable
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DB0FSINTENB02A FFFFFFFF iencmbcsr0a FF iencdbcsr0a FF
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iencmbcrr0a FF iencdbcrr0a FF
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DB0FSINTENB03A 00000000 iencdbcdr0a 00000000
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DB0FSINTENB04A 00000000 iencmbcdr0a 00000000
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DB0FSINTENB08A 00000000 Reserved_19 0000 Reserved_16 0
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Reserved_3 0000 ienexbcdr0a 0: Interrupt disable
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ienexbcsr0a 0: Interrupt disable ienexbcrr0a 0: Interrupt disable
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DB0FSINTENB09A 00000000 Reserved_26 00 Reserved_24 0
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Reserved_18 00 Reserved_16 0
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Reserved_10 00 ienoddvard1a 0: Interrupt disable
|
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iendxdvard1a 0: Interrupt disable Reserved_2 00
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ienoddvard0a 0: Interrupt disable iendxdvard0a 0: Interrupt disable
|
||||
DB0FSINTENB10A 00000000 Reserved_16 0000 ienxxasynsba 0000
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DB0FSINJECT00A 00000000 ijtexdclaxa 0: uninjection mode ijtexdclsra 0: uninjection mode
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Reserved_11 000000 ijtodasbda 0: uninjection mode
|
||||
ijtodasrda 0: uninjection mode ijtodasbxa 0: uninjection mode
|
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ijtodasrxa 0: uninjection mode ijtodaswxa 0: uninjection mode
|
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ijtodasawa 0: uninjection mode ijtodasara 0: uninjection mode
|
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Reserved_3 0 ijtdxaswxa 0: uninjection mode
|
||||
ijtdxasawa 0: uninjection mode ijtdxasara 0: uninjection mode
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DB0FSINJECT01A 00000000 Reserved_23 0000 Reserved_16 00
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Reserved_7 0000 ijtnomem0a 0: uninjection mode
|
||||
ijtedbccr0a 0: uninjection mode Reserved_4 0
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||||
ijtdxamawx0a 0: uninjection mode ijtdxamaw0a 0: uninjection mode
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ijtdxamar0a 0: uninjection mode ijtepdvaxi0a 0: uninjection mode
|
||||
DB0FSINJECT02A 00000000 Reserved_25 00 ijtcmbcsr0a 0: uninjection mode
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||||
Reserved_17 00 ijtcdbcsr0a 0: uninjection mode
|
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Reserved_9 00 ijtcmbcrr0a 0: uninjection mode
|
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Reserved_1 00 ijtcdbcrr0a 0: uninjection mode
|
||||
DB0FSINJECT03A 00000000 Reserved_1 00000000 ijtcdbcdr0a 0: uninjection mode
|
||||
DB0FSINJECT04A 00000000 Reserved_1 00000000 ijtcmbcdr0a 0: uninjection mode
|
||||
DB0FSINJECT05A 00000000 Reserved_25 00 Reserved_24 0
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Reserved_17 00 Reserved_16 0
|
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Reserved_9 00 Reserved_8 0
|
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Reserved_1 00 Reserved_0 0
|
||||
DB0FSINJECT06A 00000000 Reserved_1 00000000 Reserved_0 0
|
||||
DB0FSINJECT07A 00000000 Reserved_1 00000000 Reserved_0 0
|
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DB0FSINJECT09A 00000000 Reserved_26 00 Reserved_24 0
|
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Reserved_18 00 Reserved_16 0
|
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Reserved_10 00 ijtoddvard1a 0: uninjection mode
|
||||
ijtdxdvard1a 0: uninjection mode Reserved_2 00
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||||
ijtoddvard0a 0: uninjection mode ijtdxdvard0a 0: uninjection mode
|
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DB0FSINJECT10A 00000000 Reserved_16 0000 ijtxxasynsba 0000
|
||||
DB0FSINTCNT0A 00000000 Reserved_24 00 cntdxaswxa 00
|
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cntdxasawa 00 cntdxasara 00
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DB0FSINTCNT1A 00000000 cntcxfcprd0a 00 cntdxamawx0a 00
|
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cntdxamaw0a 00 cntdxamar0a 00
|
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DB0FSINTCNT3A 00000000 cntcmbcsr0a 00 cntcdbcsr0a 00
|
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cntcmbcrr0a 00 cntcdbcrr0a 00
|
||||
DB0FSINTCNT04A 00000000 Reserved_16 0000 cntcmbcdr0a 00
|
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cntcdbcdr0a 00
|
||||
DB0FSINTCNT06A 00000000 Reserved_16 0000 Reserved_0 0000
|
||||
DB0FSCONFAXI0 00000000 Reserved_14 000000 Reserved_12 0
|
||||
Reserved_10 0 drameccen01 0: disable DRAM ECC protection
|
||||
drameccen00 0: disable DRAM ECC protection Reserved_5 0
|
||||
srameccdis 0: enable SysRAM ECC protection Reserved_1 0
|
||||
errcrctdis 0: enable error correction
|
||||
DB0FSECCIJTCHK 00003FFA Reserved_14 000000 eccijtchk 3FFA
|
||||
DB0FSECCIJTERRL 00000000 eccijterrl 00000000
|
||||
DB0FSECCIJTERRM 00000000 eccijterrm 00000000
|
||||
DB0FSECCIJTERRH 00000000 Reserved_14 000000 eccijterrh 0000
|
||||
DB0FSECCIJTADRL0 00000000 eccijtadrl0 00000000
|
||||
DB0FSECCIJTADRH0 00000000 Reserved_8 000000 eccijtadrh0 00
|
||||
DB0FSECCIJTDATL0 00000000 eccijtdatl0 00000000
|
||||
DB0FSECCIJTDATH0 00000000 eccijtdath0 00000000
|
||||
DB0FSDRAMECCAREA00 00000000 drameccarea00 00000000
|
||||
DB0FSDRAMECCAREA01 00000000 drameccarea01 00000000
|
||||
DB0FSCTRLAXI0 00000000 Reserved_1 00000000 postenaxi 0
|
||||
DB0FSCTRLBCAM0A 00000000 Reserved_1 00000000 bcijtreq 0
|
||||
DB0FSCTRLBCAM1A 00000000 Reserved_1 00000000 bcijtaddr 0
|
||||
DB0FSMNDEA0LA 00000000 mndea0la 00000000
|
||||
DB0FSMNDEA0HA 00000000 Reserved_8 000000 mndea0ha 00
|
||||
DB0FSMNDESID0A 00000000 Reserved_8 000000 mndesid0a 00
|
||||
DB0FSMNEDCSID0A 00000000 Reserved_24 00 mnedcsidwx0a 00
|
||||
mnedcsidaw0a 00 mnedcsidar0a 00
|
||||
DB0FSCTRL00A 00000000 Reserved_1 00000000 srainidis 0: Enable
|
||||
DB0FSCTRL01A 00000000 Reserved_2 00000000 Reserved_1 0
|
||||
ddrinistart0 0: Not trigger
|
||||
DB0FSCONF00A 00000000 Reserved_2 00000000 ddrinirank0 0
|
||||
DB0FSCONF01A 00000000 ddriniareas0 00000000
|
||||
DB0FSCONF02A 00000000 ddriniareae0 00000000
|
||||
DB0FSCONF03A 00000000 Reserved_2 00000000 Reserved_0 0
|
||||
DB0FSSTAT00A 00000001 Reserved_2 00000000 Reserved_1 0
|
||||
srainiend0 1
|
||||
DB0FSSTAT01A 00000000 Reserved_2 00000000 Reserved_1 0
|
||||
ddriniend0 0
|
||||
DB0FSSTAT02A 00000001 Reserved_2 00000000 Reserved_1 0
|
||||
bceccempty0 1
|
||||
DB0FCPRSFS00A 00000000 Reserved_10 000000 fserr_force 0
|
||||
Reserved_4 00 fserr_inj 00
|
||||
DB0FCPRSFS01A 00000000 Reserved_4 00000000 fserr_sta 00
|
||||
DB0FCPRSFS02A 00000000 Reserved_4 00000000 fserr_sta_clr 00
|
||||
DB0FCPRSFS03A 00000000 fstrd 00000000
|
||||
DB0FCPRSFS04A 00000000 Reserved_2 00000000 fstrd_clr 0
|
||||
DB0FCPRSFS05A 00000000 fstdcd 00000000
|
||||
DB0FCPRSFS06A 00000000 Reserved_2 00000000 fstdcd_clr 0
|
||||
|
||||
DBSC5_1
|
||||
DB0SYSCONF1 00020000 Reserved_18 0000 ddrckr ?
|
||||
Reserved_2 0000 freqratio 0: Frequency ratio of DBSC5 clock to memory clock =
|
||||
DB0SYSCONF2 00000001 Reserved_3 00000000 sli_schmdd 1: 16bit x 2ch
|
||||
DB0PHYCONF0 00000001 Reserved_9 000000 Reserved_8 0
|
||||
Reserved_2 00 phytype 1: DFI
|
||||
DB0MEMKIND 0000000C Reserved_4 00000000 ddcg 0C
|
||||
DB0MEMCONF00 10220A01 dens00 0: 2^n type Reserved_29 0
|
||||
awrw00 10 Reserved_22 0
|
||||
awbg00 2: 4 Bankgroups Reserved_19 0
|
||||
awbk00 2: 4 banks Reserved_12 00
|
||||
awcl00 0A Reserved_2 00
|
||||
dw00 1: 16 bits
|
||||
DB0MEMCONF01 00000000 dens01 0: 2^n type Reserved_29 0
|
||||
awrw01 00 Reserved_22 0
|
||||
awbg01 0: 0 Bankgroup Reserved_19 0
|
||||
awbk01 ? Reserved_12 00
|
||||
awcl01 00 Reserved_2 00
|
||||
dw01 ?
|
||||
DB0MEMCONF10 10220A01 dens10 0: 2^n type Reserved_29 0
|
||||
awrw10 10 Reserved_22 0
|
||||
awbg10 2: 4 Bankgroups Reserved_19 0
|
||||
awbk10 2: 4 banks Reserved_12 00
|
||||
awcl10 0A Reserved_2 00
|
||||
dw10 1: 16 bits
|
||||
DB0MEMCONF11 00000000 dens11 0: 2^n type Reserved_29 0
|
||||
awrw11 00 Reserved_22 0
|
||||
awbg11 0: 0 Bankgroup Reserved_19 0
|
||||
awbk11 ? Reserved_12 00
|
||||
awcl11 00 Reserved_2 00
|
||||
dw11 ?
|
||||
DB0SYSCNT0 00000000 Reserved_16 0000 reglock 0000
|
||||
DB0RFEN 00000001 Reserved_17 0000 Reserved_16 0
|
||||
Reserved_1 0000 arfen 1: Starts the auto-refresh function
|
||||
DB0CMD 00000000 opc 00 ch 00
|
||||
Reserved_19 0 rank 0: Rank 0
|
||||
arg 0000
|
||||
DB0WAIT 00000000 Reserved_1 00000000 busy 0: The command specified by using the DBCMD..
|
||||
DB0TR0 0000000E Reserved_8 000000 cl 0E
|
||||
DB0TR1 00000007 Reserved_8 000000 cwl 07
|
||||
DB0TR2 00000000 Reserved_8 000000 al 00
|
||||
DB0TR3 0000000B Reserved_8 000000 trcd 0B
|
||||
DB0TR4 000D000B Reserved_24 00 trpa 0D
|
||||
Reserved_8 00 trp 0B
|
||||
DB0TR5 00000025 Reserved_8 000000 trc 25
|
||||
DB0TR6 0000001A Reserved_8 000000 tras 1A
|
||||
DB0TR7 00020002 Reserved_24 00 trrd_s 02
|
||||
Reserved_8 00 trrd 02
|
||||
DB0TR8 0000000B Reserved_8 000000 tfaw 0B
|
||||
DB0TR9 00000003 Reserved_8 000000 trdpr 03
|
||||
DB0TR10 00000015 Reserved_8 000000 twr 15
|
||||
DB0TR11 00000010 Reserved_8 000000 trdwr 10
|
||||
DB0TR12 000D0013 Reserved_24 00 twrrd_s 0D
|
||||
Reserved_8 00 twrrd 13
|
||||
DB0TR14 02050005 Reserved_24 02 tckehdll 05
|
||||
Reserved_8 00 tckeh 05
|
||||
DB0TR15 02090009 tespd 02 tckesr 09
|
||||
Reserved_8 00 tckel 09
|
||||
DB0TR16 2C6C1D20 dqienltncy 2C dql 6C
|
||||
dqenltncy 1D wdql 20
|
||||
DB0TR17 04060000 tmodrd 04 tmod 06
|
||||
Reserved_0 0000
|
||||
DB0TR18 00000000 Reserved_27 00 rodtl 0: BL/2 cycles
|
||||
Reserved_19 00 rodta 0: Simultaneous with the read command
|
||||
Reserved_11 00 wodtl 0: BL/2 cycles
|
||||
Reserved_3 00 wodta 0: Simultaneous with the write command
|
||||
DB0TR20 00AD00AD txsdll 00AD txs 00AD
|
||||
DB0TR21 00020004 Reserved_24 00 tccd_s 02
|
||||
Reserved_8 00 tccd 04
|
||||
DB0TR22 03840012 tzqcal 0384 Reserved_8 00
|
||||
tzqlat 12
|
||||
DB0TR23 00000000 Reserved_2 00000000 rrspc 0: No limitation
|
||||
DB0TR24 0C380C1A rdcsgap 0C rdcslat 38
|
||||
wrcsgap 0C wrcslat 1A
|
||||
DB0TR25 00000000 Reserved_24 00 Reserved_16 00
|
||||
Reserved_8 00 Reserved_0 00
|
||||
DB0TR27 00000007 tpdn 00000007
|
||||
DB0TR28 0001D4C0 txsrdsm 0001D4C0
|
||||
DB0TR29 0001BD50 tdsmxp 0001BD50
|
||||
DB0TR30 00000003 Reserved_8 000000 tcmdpd 03
|
||||
DB0TR31 00000011 Reserved_8 000000 twck2dqomax 01
|
||||
twck2dqimax 01
|
||||
DB0TR32 0C0C0F1B twckpresta 0C twckenlf 0C
|
||||
twckenw 0F twckenr 1B
|
||||
DB0TR33 00004B04 Reserved_16 0000 twckdis 4B
|
||||
Reserved_4 00 twcktgl 04
|
||||
DB0TR34 00000104 Reserved_10 000000 twckpst 1
|
||||
Reserved_3 00 twcksus 4
|
||||
DB0TR35 000C0013 Reserved_24 00 twr2wckoff 0C
|
||||
Reserved_8 00 trd2wckoff 13
|
||||
DB0TR36 00020303 Reserved_20 0000 twsfswrx 02
|
||||
Reserved_12 00 twsoffwrx 03
|
||||
Reserved_4 00 twssuswrx 03
|
||||
DB0TR37 00000018 Reserved_16 0000 tosco 0018
|
||||
DB0BL 00000002 Reserved_2 00000000 bl 2: Fixed to 16
|
||||
DB0RFCNF1 00080480 refpmax 0008 refint 0480
|
||||
DB0RFCNF2 00010000 Reserved_20 0000 refpmin 01
|
||||
Reserved_2 0000 refints 0: Average interval is REFINT
|
||||
DB0CALCNF 01000010 Reserved_25 00 calen 1: SDRAM calibration is enabled
|
||||
Reserved_17 00 Reserved_16 0
|
||||
calint 0010
|
||||
DB0RNK2 000000CC Reserved_16 0000 Reserved_8 00
|
||||
rkrr1 0C rkrr0 0C
|
||||
DB0RNK3 00000066 Reserved_16 0000 Reserved_8 00
|
||||
rkrw1 06 rkrw0 06
|
||||
DB0RNK4 00000066 Reserved_16 0000 Reserved_8 00
|
||||
rkwr1 06 rkwr0 06
|
||||
DB0RNK5 000000EE Reserved_16 0000 Reserved_8 00
|
||||
rkww1 0E rkww0 0E
|
||||
DB0WRX0 00000000 Reserved_2 00000000 wxfe0 0: disable
|
||||
wxs0 0: data to be written is..
|
||||
DB0WRX1 00000000 Reserved_2 00000000 wxfe1 0: disable
|
||||
wxs1 0: data to be written is..
|
||||
DB0DCLPCNT 00000000 Reserved_2 00000000 rdcfen 0: disable
|
||||
wdcfen 0: disable
|
||||
DB0BSWAP E4E4E4E4 bswap E4E4E4E4
|
||||
DB0DBICNT 00000003 Reserved_2 00000000 dbirden 1: Read DBI function is enabled
|
||||
dbiwren 1: Write DBI function is enabled
|
||||
DB0DFIPMSTRCNF 00000011 Reserved_6 00000000 wtmode 1
|
||||
Reserved_1 0 pmstren 1
|
||||
DB0DFIPMSTRSTAT0 00000003 Reserved_8 000000 Reserved_0 03
|
||||
DB0DFIPMSTRSTAT1 0000000A Reserved_4 00000000 pmstrreq1 1
|
||||
pmstrack1 0 pmstrreq0 1
|
||||
pmstrack0 0
|
||||
DB0DFILPCNF1 00000000 Reserved_8 000000 lpresp 00
|
||||
DB0DFICUPDCNF 504C0001 cupdreqmax 50 cupdreqmin 4C
|
||||
Reserved_1 0000 cupden 1: Enable
|
||||
DB0RFMC0 00000000 Reserved_14 000000 Reserved_12 0
|
||||
Reserved_10 0 Reserved_8 0
|
||||
Reserved_6 0 rfmsb01 0
|
||||
Reserved_2 0 rfmsb00 0
|
||||
DB0RFMC1 00000000 Reserved_14 000000 Reserved_12 0
|
||||
Reserved_10 0 Reserved_8 0
|
||||
Reserved_6 0 rfmsb11 0
|
||||
Reserved_2 0 rfmsb10 0
|
||||
DB0WCKCNT 00000000 Reserved_3 00000000 cntwckwr 0: toggle dfi_wck_wr_p* according to read or write
|
||||
cntwcken 0
|
||||
DB0DFISTAT0 00000001 Reserved_1 00000000 dfiinitcompl0 1
|
||||
DB0DFICNT0 00000020 Reserved_29 0 dfifrequency0 00
|
||||
dfibytedis0 00 Reserved_14 0
|
||||
dfifreqfsp0 0 dficlkdis0 00
|
||||
Reserved_6 0 dfifreqratio0 ?
|
||||
Reserved_1 0 dfiinitstart0 0
|
||||
DB0PDCNT02 00000000 Reserved_16 0000 freqchgack0 0000
|
||||
DB0PDCNT03 00000000 Reserved_16 0000 dllrstn0 0000
|
||||
DB0PDLK0 00000000 plock0 00000000
|
||||
DB0PDRGA0 00000838 Reserved_16 0000 pra0 0838
|
||||
DB0PDRGD0 00008080 prd0 00008080
|
||||
DB0PDRGM0 00000000 Reserved_4 00000000 prm0 00
|
||||
DB0PDSTAT00 00000200 cntstat00 00000200
|
||||
DB0DFISTAT1 00000001 Reserved_1 00000000 dfiinitcompl1 1
|
||||
DB0DFICNT1 00000020 Reserved_29 0 dfifrequency1 00
|
||||
dfibytedis1 00 Reserved_14 0
|
||||
dfifreqfsp1 0 dficlkdis1 00
|
||||
Reserved_6 0 dfifreqratio1 ?
|
||||
Reserved_1 0 dfiinitstart1 0
|
||||
DB0PDCNT12 00000000 Reserved_16 0000 freqchgack1 0000
|
||||
DB0PDCNT13 00000000 Reserved_16 0000 dllrstn1 0000
|
||||
DB0PDLK1 00000000 plock1 00000000
|
||||
DB0PDRGA1 00000838 Reserved_16 0000 pra1 0838
|
||||
DB0PDRGD1 00008080 prd1 00008080
|
||||
DB0PDRGM1 00000000 Reserved_4 00000000 prm1 00
|
||||
DB0PDSTAT10 00000200 cntstat10 00000200
|
||||
DB0MRRDR0 00000002 Reserved_16 0000 mrrdr01 00
|
||||
mrrdr00 02
|
||||
DB0MRRDR1 00000002 Reserved_16 0000 mrrdr11 00
|
||||
mrrdr10 02
|
||||
DB0WCK2DQMD 00000000 wck2dqmd 00000000
|
||||
DB0WCK2DQOSCTHH00 FFFFFFFF wck2dqoscthh01 FFFF wck2dqoscthh00 FFFF
|
||||
DB0WCK2DQOSCTHH10 FFFFFFFF wck2dqoscthh11 FFFF wck2dqoscthh10 FFFF
|
||||
DB0WCK2DQOSCTHL00 00000000 wck2dqoscthl01 0000 wck2dqoscthl00 0000
|
||||
DB0WCK2DQOSCTHL10 00000000 wck2dqoscthl11 0000 wck2dqoscthl10 0000
|
||||
DB0TSTCONF1 00000000 Reserved_1 00000000 lowfreqmd 0: Normal
|
||||
DB0FSINTXXX00D 00000000 Reserved_7 00000000 intodaswxd 0: no interupt
|
||||
intodasawd 0: no interupt intodasard 0: no interupt
|
||||
Reserved_3 0 intdxaswxd 0: no interupt
|
||||
intdxasawd 0: no interupt intdxasard 0: no interupt
|
||||
DB0FSINTXXX01D 00000000 intexdcld1d 0: no interupt Reserved_30 0
|
||||
Reserved_26 00 intoddvawr1d 0: no interupt
|
||||
intoddvacq1d 0: no interupt intdxdvawr1d 0: no interupt
|
||||
intdxdvacq1d 0: no interupt intoddvphy1d 0: no interupt
|
||||
intoddvdbs1d 0: no interupt intdxdvphy1d 0: no interupt
|
||||
intdxdvdbs1d 0: no interupt intepdvphy1d 0: no interupt
|
||||
intepdvdbs1d 0: no interupt intexdcld0d 0: no interupt
|
||||
Reserved_14 0 Reserved_10 00
|
||||
intoddvawr0d 0: no interupt intoddvacq0d 0: no interupt
|
||||
intdxdvawr0d 0: no interupt intdxdvacq0d 0: no interupt
|
||||
intoddvphy0d 0: no interupt intoddvdbs0d 0: no interupt
|
||||
intdxdvphy0d 0: no interupt intdxdvdbs0d 0: no interupt
|
||||
intepdvphy0d 0: no interupt intepdvdbs0d 0: no interupt
|
||||
DB0FSINTXXX03D 00000000 Reserved_16 0000 intxxasynsbd 0000
|
||||
DB0FSINTCLR00D 00000000 Reserved_1 00000000 icldclsd ?
|
||||
DB0FSINTENB00D 00000077 Reserved_7 00000000 ienodaswxd 1: Interrupt enable
|
||||
ienodasawd 1: Interrupt enable ienodasard 1: Interrupt enable
|
||||
Reserved_3 0 iendxaswxd 1: Interrupt enable
|
||||
iendxasawd 1: Interrupt enable iendxasard 1: Interrupt enable
|
||||
DB0FSINTENB03D 00000000 Reserved_16 0000 ienxxasynsbd 0000
|
||||
DB0FSINJECT00D 00000000 Reserved_7 00000000 ijtodaswxd 0: uninjection mode
|
||||
ijtodasawd 0: uninjection mode ijtodasard 0: uninjection mode
|
||||
Reserved_3 0 ijtdxaswxd 0: uninjection mode
|
||||
ijtdxasawd 0: uninjection mode ijtdxasard 0: uninjection mode
|
||||
DB0FSINJECT03D 00000000 Reserved_16 0000 ijtxxasynsbd 0000
|
||||
DB0FSINTCNT00D 00000000 Reserved_24 00 cntdxaswxd 00
|
||||
cntdxasawd 00 cntdxasard 00
|
||||
DB0FSINTCNT01D 00000000 cntdxdvawr0d 00 cntdxdvacq0d 00
|
||||
cntdxdvphy0d 00 cntdxdvdbs0d 00
|
||||
DB0FSINTCNT02D 00000000 Reserved_8 000000 Reserved_0 00
|
||||
DB0FSINTCNT03D 00000000 cntdxdvawr1d 00 cntdxdvacq1d 00
|
||||
cntdxdvphy1d 00 cntdxdvdbs1d 00
|
||||
DB0FSINTCNT04D 00000000 Reserved_8 000000 Reserved_0 00
|
||||
DB0FSINTCNT06D 00000000 Reserved_8 000000 Reserved_0 00
|
||||
DB0FSINTCNT08D 00000000 Reserved_8 000000 Reserved_0 00
|
||||
DB0FSCONFDBS0 00000000 Reserved_1 00000000 Reserved_0 0
|
||||
DB0FSCTRLDBS0 00000000 Reserved_1 00000000 Reserved_0 0
|
||||
@@ -0,0 +1,303 @@
|
||||
/* TOOLDIAG List of possible tool diagnostics
|
||||
*
|
||||
* TOOLDIAG-1) Possible diagnostic: RemovedUnusedSection
|
||||
* Pattern <pattern> only matches removed unused sections.
|
||||
*
|
||||
* Reason: Not all regions need to contain data variables.
|
||||
*
|
||||
* TOOLDIAG-2) Possible diagnostic: UnusedSection
|
||||
* No section matches pattern <pattern>.
|
||||
*
|
||||
* Reason: Config specific auto-generated sections which sometimes are empty.
|
||||
*/
|
||||
|
||||
/* Possible diagnostic TOOLDIAG-1 <*> */
|
||||
/* Possible diagnostic TOOLDIAG-2 <*> */
|
||||
|
||||
#define exctable_addr 0x61000000
|
||||
#define exctable_size 0x00001000
|
||||
#define reset_addr 0x61001000
|
||||
#define reset_size 0x00000200
|
||||
#define RAM_start_addr 0x61440000
|
||||
#define RAM_size 0x01000000
|
||||
#define ROM_start_addr 0x61001200
|
||||
#define ROM_size 0x00300000
|
||||
|
||||
#define SRAM_LOAD_REGION_addr 0x61301200
|
||||
#define SRAM_LOAD_REGION_size 0x00040000
|
||||
|
||||
#define GPIO_start_addr 0xe6061800
|
||||
#define GPIO_end_addr 0xe6061a00
|
||||
|
||||
#define rom_sect_addr exctable_addr
|
||||
#define rom_addr ROM_start_addr
|
||||
#define rom_size ROM_size
|
||||
|
||||
;#define rom_data_addr RAM_start_addr
|
||||
;#define rom_data_size RAM_size
|
||||
;#define ram_addr ImageLimit(ROM_DATA_END)
|
||||
;#define ram_size ((RAM_start_addr + RAM_size) - ram_addr)
|
||||
|
||||
|
||||
;#define cx_ram_size (RAM_size/4)
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define cx_ram_size 0x00100000 /* 1MB per core */
|
||||
/*==========================================================================*/
|
||||
|
||||
#define ram_C0_START 0x61440000 /* 0x61440000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C0_addr 0x61440000 /* 0x61440000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C0_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
#define ram_C1_START 0x61540000 /* 0x61540000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C1_addr 0x61540000 /* 0x61540000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C1_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
#define ram_C2_START 0x61640000 /* 0x61640000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C2_addr 0x61640000 /* 0x61640000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C2_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 shared memory between cores*/
|
||||
#define ram_SHARED_addr 0x61740000 /* = 0x61740000 */
|
||||
#define ram_SHARED_size 0x00000100 /* Increased for T1 trace buffers (20KB) */
|
||||
/*==========================================================================*/
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 shared memory between cores*/
|
||||
#define ram_T1_addr 0x61740100 /* = 0x61740100 */
|
||||
#define ram_T1_size 0x00004F00 /* Increased for T1 trace buffers (20KB) */
|
||||
/*==========================================================================*/
|
||||
|
||||
/* IOC readable region */
|
||||
#define BOARD_C0_RAM_BEG 0x61440000
|
||||
#define BOARD_C0_URAM_END (ram_C0_addr + cx_ram_size)
|
||||
|
||||
#define BOARD_C1_RAM_BEG 0x61540000
|
||||
#define BOARD_C1_URAM_END (ram_C1_addr + cx_ram_size)
|
||||
|
||||
#define BOARD_C2_RAM_BEG 0x61640000
|
||||
#define BOARD_C2_URAM_END (ram_C2_addr + cx_ram_size)
|
||||
|
||||
/* Non-cacheable IOC buffer DATA region : DDR */
|
||||
#define ram_IOC_NONCACHE_addr 0x61745000 /* 0x61745000 */
|
||||
#define ram_IOC_NONCACHE_size 0x00050000 /* 320KB for IOC data */
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: RT-VRAM1 COMPATIBLE MODE SRAM */
|
||||
/* Stack region : RT-VRAM1 SRAM */
|
||||
#define SRAM_TEXT_REGION_addr 0xE2000000
|
||||
#define SRAM_TEXT_REGION_size 0x00040000 /* 1MB for STACK TEXT */
|
||||
|
||||
#define SRAM_IOC_REGION_addr 0xE2040000
|
||||
#define SRAM_IOC_REGION_size 0x00050000 /* 1MB for STACK IOC */
|
||||
|
||||
#define SRAM_STACK_REGION_addr 0xE2090000
|
||||
#define SRAM_STACK_REGION_size 0x00070000 /* 1MB for STACK STACK */
|
||||
|
||||
|
||||
;#define ram_STACK_REGION_addr 0xE2000000
|
||||
;#define ram_STACK_REGION_size 0x000FFFFF /* 640KB for STACK */
|
||||
|
||||
/* Non-cacheable IOC buffer BSS region : RT-VRAM1 SRAM */
|
||||
;#define ram_IOC_NONCACHE_BSS_addr 0xE20A0000
|
||||
;#define ram_IOC_NONCACHE_BSS_size 0x00050000 /* 320KB for IOC bss */
|
||||
|
||||
/*==========================================================================*/
|
||||
;#define C0_ATCM_LOAD_REGION_ADDR 0x61002000
|
||||
;#define C0_ATCM_LOAD_REGION_SIZE 0x00004000
|
||||
|
||||
|
||||
;#define CORE_ATCM_SIZE 0x00004000
|
||||
;#define CORE_BTCM_SIZE 0x00004000
|
||||
;#define CORE_CTCM_SIZE 0x00004000
|
||||
|
||||
;#define C0_ATCM_REGION_ADDR 0xE4000000
|
||||
;#define C0_BTCM_REGION_ADDR 0xE4100000
|
||||
;#define C0_CTCM_REGION_ADDR 0xE4200000
|
||||
|
||||
|
||||
/*=================================================*/
|
||||
/* definition of global HW specific symbols */
|
||||
GLOBAL_HW_SPECIFIC_SYMBOLS 0
|
||||
{
|
||||
; MK: core local GIC IO registers
|
||||
MK_RSA_MK_Io0 0xf0000000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io0 0xf0200000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU1 memory-mapped device registers
|
||||
MK_RSA_MK_Io1 0xe6fc0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io1 0xe6fc1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU2 memory-mapped device registers
|
||||
MK_RSA_MK_Io2 0xe6fd0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io2 0xe6fd1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU3 memory-mapped device registers
|
||||
MK_RSA_MK_Io3 0xe6fe0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io3 0xe6fe1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU4 memory-mapped device registers
|
||||
MK_RSA_MK_Io4 0xffc00000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io4 0xffc10000 EMPTY 0 { }
|
||||
|
||||
; MK: MFIS multifunctional interface
|
||||
MK_RSA_MK_Io5 0xe6269400 EMPTY 0 { }
|
||||
MK_RLA_MK_Io5 0xe626a500 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU0 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo0 0xe61e0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo0 0xe61f0000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU1 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo1 0xe6fc0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo1 0xe6fc1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU2 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo2 0xe6fd0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo2 0xe6fd1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU3 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo3 0xe6fe0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo3 0xe6fe1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU4 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo4 0xffc00000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo4 0xffc10000 EMPTY 0 { }
|
||||
}
|
||||
|
||||
/*==========================================================================*/
|
||||
/* CUSTOM: R52 shared memory between cores*/
|
||||
ram_SHARED ram_SHARED_addr ram_SHARED_size
|
||||
{
|
||||
mk_shared_sync +0 ALIGN 256 FIXED
|
||||
{
|
||||
*(.mk_shared_sync)
|
||||
*(.mk_shared_sync.*)
|
||||
}
|
||||
}
|
||||
/*==========================================================================*/
|
||||
/*==========================================================================*/
|
||||
/* CUSTOM: R52 shared memory between cores*/
|
||||
ram_T1 ram_T1_addr ram_T1_size
|
||||
{
|
||||
T1 +0 ALIGN 256 FIXED
|
||||
{
|
||||
*(.T1_bss*)
|
||||
*(.T1_clear*)
|
||||
*(.T1_traceBuffer*)
|
||||
}
|
||||
}
|
||||
/*==========================================================================*/
|
||||
|
||||
/*==========================================================================*/
|
||||
/* Non-cacheable IOC buffer region */
|
||||
ram_IOC_NONCACHE ram_IOC_NONCACHE_addr ram_IOC_NONCACHE_size
|
||||
{
|
||||
IOC_NONCACHE_DATA_BUFFERS + 0 FIXED
|
||||
{
|
||||
/* IOC channel data buffers */
|
||||
Ioc_data_app_ch*.o(.data)
|
||||
Ioc_data_app_ch*.o(.data.*)
|
||||
Ioc_data_app_ch*.o(.zdata)
|
||||
Ioc_data_app_ch*.o(.zdata.*)
|
||||
Ioc_data_app_ch*.o(.sdata)
|
||||
Ioc_data_app_ch*.o(.sdata.*)
|
||||
Ioc_data_app_ch*.o(.rodata)
|
||||
Ioc_data_app_ch*.o(.rodata.*)
|
||||
|
||||
/ IOC configuration data /
|
||||
Ioc_configuration.o(.rodata)
|
||||
Ioc_configuration.o(.rodata.*)
|
||||
Ioc_srcconfiguration.o(.rodata)
|
||||
Ioc_srcconfiguration.o(.rodata.*)
|
||||
Ioc_mk_configuration.o(.rodata)
|
||||
Ioc_mk_configuration.o(.rodata.*)
|
||||
}
|
||||
}
|
||||
|
||||
SRAM_IOC_NONCACHE SRAM_IOC_REGION_addr SRAM_IOC_REGION_size
|
||||
{
|
||||
IOC_NONCACHE_START +0 ALIGN 256 EMPTY 0 { }
|
||||
IOC_NONCACHE_BSS_BUFFERS +0 ALIGN 256 UNINIT
|
||||
{
|
||||
Mk_ARM_configuration.o(.bss.MK_ARMTmuSpinlock)
|
||||
Mk_ARM_configuration.o(.bss.MK_armSpinlock)
|
||||
Dcm.o(.bss.Dcm_*)
|
||||
Dcm_*.o(.bss.Dcm_*)
|
||||
CanTp_*.o(.bss.CanTp_*)
|
||||
/* IOC channel data buffers */
|
||||
Ioc_data_app_ch*.o(.bss)
|
||||
Ioc_data_app_ch*.o(.bss.*)
|
||||
Ioc_data_app_ch*.o(.zbss)
|
||||
Ioc_data_app_ch*.o(.zbss.*)
|
||||
Ioc_data_app_ch*.o(.sbss)
|
||||
Ioc_data_app_ch*.o(.sbss.*)
|
||||
|
||||
/* IOC readable regions for all applications and cores */
|
||||
*(.bss.IOC_RSA_READABLE_*)
|
||||
*(.bss.IOC_RLA_READABLE_*)
|
||||
*(IOC_RSA_READABLE_*.bss)
|
||||
*(IOC_RLA_READABLE_*.bss)
|
||||
|
||||
/* Spinlock tables - must be non-cacheable and shareable for multicore */
|
||||
Mk_c0_configuration.o(.bss.MK_c0_lockTable)
|
||||
Mk_c1_configuration.o(.bss.MK_c1_lockTable)
|
||||
Mk_c2_configuration.o(.bss.MK_c2_lockTable)
|
||||
}
|
||||
IOC_NONCACHE_END +0 EMPTY 0 { }
|
||||
}
|
||||
|
||||
SRAM_LOAD_REGION SRAM_LOAD_REGION_addr SRAM_LOAD_REGION_size
|
||||
{
|
||||
SRAM_LOAD_REGION_START +0 ALIGN 256 EMPTY 0 { }
|
||||
SRAM_TEXT_REGION SRAM_TEXT_REGION_addr ALIGN 256
|
||||
{
|
||||
Rte_OsApplication_0.o(.text)
|
||||
Rte_OsApplication_0.o(.text.*)
|
||||
*(.text.IOC*)
|
||||
*(.text.Ioc*)
|
||||
CtComASILD_RX_MsgUpdates_Auto.o(.text)
|
||||
CtComASILD_RX_MsgUpdates_Auto.o(.text.*)
|
||||
CtComASILD_TX_MsgUpdates_Auto.o(.text)
|
||||
CtComASILD_TX_MsgUpdates_Auto.o(.text.*)
|
||||
CDD_Iccom0_A2R.o(.text)
|
||||
CDD_Iccom0_A2R.o(.text.*)
|
||||
CDD_Iccom0_R2A.o(.text)
|
||||
CDD_Iccom0_R2A.o(.text.*)
|
||||
CDD_Iccom1_A2R.o(.text)
|
||||
CDD_Iccom1_A2R.o(.text.*)
|
||||
CDD_Iccom1_R2A.o(.text)
|
||||
CDD_Iccom1_R2A.o(.text.*)
|
||||
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR0_CAT2_ISR)
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR1_CAT2_ISR)
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR2_CAT2_ISR)
|
||||
|
||||
}
|
||||
SRAM_LOAD_REGION_END +0 EMPTY 0 { }
|
||||
}
|
||||
|
||||
|
||||
/* CORE0 hot text copied from ROM to ATCM */
|
||||
;C0_ATCM_LOAD_REGION C0_ATCM_LOAD_REGION_ADDR C0_ATCM_LOAD_REGION_SIZE
|
||||
;{
|
||||
; C0_ATCM_START +0 ALIGN 256 EMPTY 0 { }
|
||||
; C0_ATCM_REGION C0_ATCM_REGION_ADDR ALIGN 256
|
||||
; {
|
||||
;
|
||||
; }
|
||||
; C0_ATCM_END +0 EMPTY 0 { }
|
||||
;}
|
||||
|
||||
|
||||
/*==========================================================================*/
|
||||
@@ -0,0 +1,303 @@
|
||||
/* TOOLDIAG List of possible tool diagnostics
|
||||
*
|
||||
* TOOLDIAG-1) Possible diagnostic: RemovedUnusedSection
|
||||
* Pattern <pattern> only matches removed unused sections.
|
||||
*
|
||||
* Reason: Not all regions need to contain data variables.
|
||||
*
|
||||
* TOOLDIAG-2) Possible diagnostic: UnusedSection
|
||||
* No section matches pattern <pattern>.
|
||||
*
|
||||
* Reason: Config specific auto-generated sections which sometimes are empty.
|
||||
*/
|
||||
|
||||
/* Possible diagnostic TOOLDIAG-1 <*> */
|
||||
/* Possible diagnostic TOOLDIAG-2 <*> */
|
||||
|
||||
#define exctable_addr 0x61000000
|
||||
#define exctable_size 0x00001000
|
||||
#define reset_addr 0x61001000
|
||||
#define reset_size 0x00000200
|
||||
#define RAM_start_addr 0x61440000
|
||||
#define RAM_size 0x01000000
|
||||
#define ROM_start_addr 0x61001200
|
||||
#define ROM_size 0x00300000
|
||||
|
||||
#define SRAM_LOAD_REGION_addr 0x61301200
|
||||
#define SRAM_LOAD_REGION_size 0x00040000
|
||||
|
||||
#define GPIO_start_addr 0xe6061800
|
||||
#define GPIO_end_addr 0xe6061a00
|
||||
|
||||
#define rom_sect_addr exctable_addr
|
||||
#define rom_addr ROM_start_addr
|
||||
#define rom_size ROM_size
|
||||
|
||||
;#define rom_data_addr RAM_start_addr
|
||||
;#define rom_data_size RAM_size
|
||||
;#define ram_addr ImageLimit(ROM_DATA_END)
|
||||
;#define ram_size ((RAM_start_addr + RAM_size) - ram_addr)
|
||||
|
||||
|
||||
;#define cx_ram_size (RAM_size/4)
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define cx_ram_size 0x00100000 /* 1MB per core */
|
||||
/*==========================================================================*/
|
||||
|
||||
#define ram_C0_START 0x61440000 /* 0x61440000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C0_addr 0x61440000 /* 0x61440000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C0_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
#define ram_C1_START 0x61540000 /* 0x61540000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C1_addr 0x61540000 /* 0x61540000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C1_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
#define ram_C2_START 0x61640000 /* 0x61640000 */
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 core ram size*/
|
||||
#define ram_C2_addr 0x61640000 /* 0x61640000 */
|
||||
/*==========================================================================*/
|
||||
#define ram_C2_size cx_ram_size /* 0x00100000 (1MB) */
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 shared memory between cores*/
|
||||
#define ram_SHARED_addr 0x61740000 /* = 0x61740000 */
|
||||
#define ram_SHARED_size 0x00000100 /* Increased for T1 trace buffers (20KB) */
|
||||
/*==========================================================================*/
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: R52 shared memory between cores*/
|
||||
#define ram_T1_addr 0x61740100 /* = 0x61740100 */
|
||||
#define ram_T1_size 0x00004F00 /* Increased for T1 trace buffers (20KB) */
|
||||
/*==========================================================================*/
|
||||
|
||||
/* IOC readable region */
|
||||
#define BOARD_C0_RAM_BEG 0x61440000
|
||||
#define BOARD_C0_URAM_END (ram_C0_addr + cx_ram_size)
|
||||
|
||||
#define BOARD_C1_RAM_BEG 0x61540000
|
||||
#define BOARD_C1_URAM_END (ram_C1_addr + cx_ram_size)
|
||||
|
||||
#define BOARD_C2_RAM_BEG 0x61640000
|
||||
#define BOARD_C2_URAM_END (ram_C2_addr + cx_ram_size)
|
||||
|
||||
/* Non-cacheable IOC buffer DATA region : DDR */
|
||||
#define ram_IOC_NONCACHE_addr 0x61745000 /* 0x61745000 */
|
||||
#define ram_IOC_NONCACHE_size 0x00050000 /* 320KB for IOC data */
|
||||
|
||||
/*==========================================================================*/
|
||||
/*CUSTOM: RT-VRAM1 COMPATIBLE MODE SRAM */
|
||||
/* Stack region : RT-VRAM1 SRAM */
|
||||
#define SRAM_TEXT_REGION_addr 0xE2000000
|
||||
#define SRAM_TEXT_REGION_size 0x00040000 /* 1MB for STACK TEXT */
|
||||
|
||||
#define SRAM_IOC_REGION_addr 0xE2040000
|
||||
#define SRAM_IOC_REGION_size 0x00050000 /* 1MB for STACK IOC */
|
||||
|
||||
#define SRAM_STACK_REGION_addr 0xE2090000
|
||||
#define SRAM_STACK_REGION_size 0x00070000 /* 1MB for STACK STACK */
|
||||
|
||||
|
||||
;#define ram_STACK_REGION_addr 0xE2000000
|
||||
;#define ram_STACK_REGION_size 0x000FFFFF /* 640KB for STACK */
|
||||
|
||||
/* Non-cacheable IOC buffer BSS region : RT-VRAM1 SRAM */
|
||||
;#define ram_IOC_NONCACHE_BSS_addr 0xE20A0000
|
||||
;#define ram_IOC_NONCACHE_BSS_size 0x00050000 /* 320KB for IOC bss */
|
||||
|
||||
/*==========================================================================*/
|
||||
;#define C0_ATCM_LOAD_REGION_ADDR 0x61002000
|
||||
;#define C0_ATCM_LOAD_REGION_SIZE 0x00004000
|
||||
|
||||
|
||||
;#define CORE_ATCM_SIZE 0x00004000
|
||||
;#define CORE_BTCM_SIZE 0x00004000
|
||||
;#define CORE_CTCM_SIZE 0x00004000
|
||||
|
||||
;#define C0_ATCM_REGION_ADDR 0xE4000000
|
||||
;#define C0_BTCM_REGION_ADDR 0xE4100000
|
||||
;#define C0_CTCM_REGION_ADDR 0xE4200000
|
||||
|
||||
|
||||
/*=================================================*/
|
||||
/* definition of global HW specific symbols */
|
||||
GLOBAL_HW_SPECIFIC_SYMBOLS 0
|
||||
{
|
||||
; MK: core local GIC IO registers
|
||||
MK_RSA_MK_Io0 0xf0000000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io0 0xf0200000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU1 memory-mapped device registers
|
||||
MK_RSA_MK_Io1 0xe6fc0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io1 0xe6fc1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU2 memory-mapped device registers
|
||||
MK_RSA_MK_Io2 0xe6fd0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io2 0xe6fd1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU3 memory-mapped device registers
|
||||
MK_RSA_MK_Io3 0xe6fe0000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io3 0xe6fe1000 EMPTY 0 { }
|
||||
|
||||
; MK: TMU4 memory-mapped device registers
|
||||
MK_RSA_MK_Io4 0xffc00000 EMPTY 0 { }
|
||||
MK_RLA_MK_Io4 0xffc10000 EMPTY 0 { }
|
||||
|
||||
; MK: MFIS multifunctional interface
|
||||
MK_RSA_MK_Io5 0xe6269400 EMPTY 0 { }
|
||||
MK_RLA_MK_Io5 0xe626a500 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU0 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo0 0xe61e0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo0 0xe61f0000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU1 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo1 0xe6fc0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo1 0xe6fc1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU2 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo2 0xe6fd0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo2 0xe6fd1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU3 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo3 0xe6fe0000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo3 0xe6fe1000 EMPTY 0 { }
|
||||
|
||||
; counter subsystem: TMU4 memory-mapped device registers
|
||||
MK_RSA_MK_OsIo4 0xffc00000 EMPTY 0 { }
|
||||
MK_RLA_MK_OsIo4 0xffc10000 EMPTY 0 { }
|
||||
}
|
||||
|
||||
/*==========================================================================*/
|
||||
/* CUSTOM: R52 shared memory between cores*/
|
||||
ram_SHARED ram_SHARED_addr ram_SHARED_size
|
||||
{
|
||||
mk_shared_sync +0 ALIGN 256 FIXED
|
||||
{
|
||||
*(.mk_shared_sync)
|
||||
*(.mk_shared_sync.*)
|
||||
}
|
||||
}
|
||||
/*==========================================================================*/
|
||||
/*==========================================================================*/
|
||||
/* CUSTOM: R52 shared memory between cores*/
|
||||
ram_T1 ram_T1_addr ram_T1_size
|
||||
{
|
||||
T1 +0 ALIGN 256 FIXED
|
||||
{
|
||||
*(.T1_bss*)
|
||||
*(.T1_clear*)
|
||||
*(.T1_traceBuffer*)
|
||||
}
|
||||
}
|
||||
/*==========================================================================*/
|
||||
|
||||
/*==========================================================================*/
|
||||
/* Non-cacheable IOC buffer region */
|
||||
ram_IOC_NONCACHE ram_IOC_NONCACHE_addr ram_IOC_NONCACHE_size
|
||||
{
|
||||
IOC_NONCACHE_DATA_BUFFERS + 0 FIXED
|
||||
{
|
||||
/* IOC channel data buffers */
|
||||
Ioc_data_app_ch*.o(.data)
|
||||
Ioc_data_app_ch*.o(.data.*)
|
||||
Ioc_data_app_ch*.o(.zdata)
|
||||
Ioc_data_app_ch*.o(.zdata.*)
|
||||
Ioc_data_app_ch*.o(.sdata)
|
||||
Ioc_data_app_ch*.o(.sdata.*)
|
||||
Ioc_data_app_ch*.o(.rodata)
|
||||
Ioc_data_app_ch*.o(.rodata.*)
|
||||
|
||||
/ IOC configuration data /
|
||||
Ioc_configuration.o(.rodata)
|
||||
Ioc_configuration.o(.rodata.*)
|
||||
Ioc_srcconfiguration.o(.rodata)
|
||||
Ioc_srcconfiguration.o(.rodata.*)
|
||||
Ioc_mk_configuration.o(.rodata)
|
||||
Ioc_mk_configuration.o(.rodata.*)
|
||||
}
|
||||
}
|
||||
|
||||
SRAM_IOC_NONCACHE SRAM_IOC_REGION_addr SRAM_IOC_REGION_size
|
||||
{
|
||||
IOC_NONCACHE_START +0 ALIGN 256 EMPTY 0 { }
|
||||
IOC_NONCACHE_BSS_BUFFERS +0 ALIGN 256 UNINIT
|
||||
{
|
||||
Mk_ARM_configuration.o(.bss.MK_ARMTmuSpinlock)
|
||||
Mk_ARM_configuration.o(.bss.MK_armSpinlock)
|
||||
Dcm.o(.bss.Dcm_*)
|
||||
Dcm_*.o(.bss.Dcm_*)
|
||||
CanTp_*.o(.bss.CanTp_*)
|
||||
/* IOC channel data buffers */
|
||||
Ioc_data_app_ch*.o(.bss)
|
||||
Ioc_data_app_ch*.o(.bss.*)
|
||||
Ioc_data_app_ch*.o(.zbss)
|
||||
Ioc_data_app_ch*.o(.zbss.*)
|
||||
Ioc_data_app_ch*.o(.sbss)
|
||||
Ioc_data_app_ch*.o(.sbss.*)
|
||||
|
||||
/* IOC readable regions for all applications and cores */
|
||||
*(.bss.IOC_RSA_READABLE_*)
|
||||
*(.bss.IOC_RLA_READABLE_*)
|
||||
*(IOC_RSA_READABLE_*.bss)
|
||||
*(IOC_RLA_READABLE_*.bss)
|
||||
|
||||
/* Spinlock tables - must be non-cacheable and shareable for multicore */
|
||||
Mk_c0_configuration.o(.bss.MK_c0_lockTable)
|
||||
Mk_c1_configuration.o(.bss.MK_c1_lockTable)
|
||||
Mk_c2_configuration.o(.bss.MK_c2_lockTable)
|
||||
}
|
||||
IOC_NONCACHE_END +0 EMPTY 0 { }
|
||||
}
|
||||
|
||||
SRAM_LOAD_REGION SRAM_LOAD_REGION_addr SRAM_LOAD_REGION_size
|
||||
{
|
||||
SRAM_LOAD_REGION_START +0 ALIGN 256 EMPTY 0 { }
|
||||
SRAM_TEXT_REGION SRAM_TEXT_REGION_addr ALIGN 256
|
||||
{
|
||||
Rte_OsApplication_0.o(.text)
|
||||
Rte_OsApplication_0.o(.text.*)
|
||||
*(.text.IOC*)
|
||||
*(.text.Ioc*)
|
||||
CtComASILD_RX_MsgUpdates_Auto.o(.text)
|
||||
CtComASILD_RX_MsgUpdates_Auto.o(.text.*)
|
||||
CtComASILD_TX_MsgUpdates_Auto.o(.text)
|
||||
CtComASILD_TX_MsgUpdates_Auto.o(.text.*)
|
||||
CDD_Iccom0_A2R.o(.text)
|
||||
CDD_Iccom0_A2R.o(.text.*)
|
||||
CDD_Iccom0_R2A.o(.text)
|
||||
CDD_Iccom0_R2A.o(.text.*)
|
||||
CDD_Iccom1_A2R.o(.text)
|
||||
CDD_Iccom1_A2R.o(.text.*)
|
||||
CDD_Iccom1_R2A.o(.text)
|
||||
CDD_Iccom1_R2A.o(.text.*)
|
||||
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR0_CAT2_ISR)
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR1_CAT2_ISR)
|
||||
CDD_Iccom_MFIS_Irq.o(.text.OS_ISR_MFIS_xIICR2_CAT2_ISR)
|
||||
|
||||
}
|
||||
SRAM_LOAD_REGION_END +0 EMPTY 0 { }
|
||||
}
|
||||
|
||||
|
||||
/* CORE0 hot text copied from ROM to ATCM */
|
||||
;C0_ATCM_LOAD_REGION C0_ATCM_LOAD_REGION_ADDR C0_ATCM_LOAD_REGION_SIZE
|
||||
;{
|
||||
; C0_ATCM_START +0 ALIGN 256 EMPTY 0 { }
|
||||
; C0_ATCM_REGION C0_ATCM_REGION_ADDR ALIGN 256
|
||||
; {
|
||||
;
|
||||
; }
|
||||
; C0_ATCM_END +0 EMPTY 0 { }
|
||||
;}
|
||||
|
||||
|
||||
/*==========================================================================*/
|
||||
@@ -0,0 +1,48 @@
|
||||
ARM Cortex-R52(ARMv8-R PMSA) ȯ<>濡<EFBFBD><E6BFA1> MPU<50><55> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> ǥ<><C7A5> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ǹ<EFBFBD> <20><><EFBFBD>̵<EFBFBD><CCB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>帳<EFBFBD>ϴ<EFBFBD>. <20>ռ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߰<EFBFBD><DFB0>ߴ<EFBFBD> ġ<><C4A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD> <20><><EFBFBD><EFBFBD> <20>ٽ<EFBFBD> <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD> ¤<><C2A4><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
|
||||
??? MPU <20><><EFBFBD><EFBFBD> ǥ<><C7A5> <20><><EFBFBD><EFBFBD> (Configuration Sequence)
|
||||
1<EFBFBD>ܰ<EFBFBD>: MPU <20><> ij<><C4B3> <20><>Ȱ<EFBFBD><C8B0>ȭ (<28>ʱ<EFBFBD>ȭ <20>غ<EFBFBD>)
|
||||
<EFBFBD>ý<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><> <20><><EFBFBD><EFBFBD> MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ý<EFBFBD><C3BD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʵ<EFBFBD><CAB5><EFBFBD> MPU<50><55> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<><C4B3>(L1/L2)<29><> <20>ݵ<EFBFBD><DDB5><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD>ý<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SCTLR)<29><><EFBFBD><EFBFBD> MPU Enable <20><>Ʈ(M)<29><> Cache <20><>Ʈ(C, I)<29><> 0<><30><EFBFBD><EFBFBD> Ŭ<><C5AC><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
2<EFBFBD>ܰ<EFBFBD>: <20>Ӽ<EFBFBD> <20>ȷ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> (MAIR0, MAIR1 <20><><EFBFBD><EFBFBD>)
|
||||
MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 8<><38><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20>Ӽ<EFBFBD>(ij<><C4B3> <20><>å, Device/Normal <20><><EFBFBD><EFBFBD>)<29><> <20≯<EFBFBD> <20><><EFBFBD><EFBFBD>ó<EFBFBD><C3B3> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD>ʼ<EFBFBD> <20><><EFBFBD><EFBFBD>: MAIR0 (Index 0~3)<29>Ӹ<EFBFBD> <20>ƴ϶<C6B4>, MAIR1 (Index 4~7)<29><> <20>ݵ<EFBFBD><DDB5><EFBFBD> <20>Բ<EFBFBD> <20>ʱ<EFBFBD>ȭ<EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>. <20>ʱ<EFBFBD>ȭ<EFBFBD><C8AD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Index<65><78> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϸ<EFBFBD> <20><><EFBFBD><EFBFBD> <20>Ұ<EFBFBD><D2B0><EFBFBD> Data Abort<72><74> <20><EFBFBD><DFBB>մϴ<D5B4>.
|
||||
|
||||
3<EFBFBD>ܰ<EFBFBD>: <20><><EFBFBD><EFBFBD><D7B6><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Ȱ<><C8B0>ȭ (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>̳<EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
Ư<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>, Ư<><C6AF> <20><><EFBFBD><EFBFBD>(Privileged)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>⺻ <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>. (SCTLR.BR <20><>Ʈ <20><><EFBFBD><EFBFBD>)
|
||||
|
||||
4<EFBFBD>ܰ<EFBFBD>: <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(Region) <20><><EFBFBD><EFBFBD> (PRSELR ?? PRBAR ?? PRLAR)
|
||||
<EFBFBD><EFBFBD>ij<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(.scat)<29><> <20><><EFBFBD>ǵ<EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20>ʰ<EFBFBD> 1:1<><31> <20><>Ī<EFBFBD>Ͽ<EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>輱<EFBFBD><E8BCB1> <20>߽<EFBFBD><DFBD>ϴ<EFBFBD>.
|
||||
|
||||
PRSELR (Region Selection): <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ȣ(0~N)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
PRBAR (Base Address Register): <20>ش<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ּҿ<D6BC> **<2A><><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD>(AP, SH, XN)**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
PRLAR (Limit Address Register): <20>ش<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>ּҿ<D6BC> **MAIR <20>ε<EFBFBD><CEB5><EFBFBD>(AttrIndx)**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȱ<><C8B0>ȭ(EN=1)<29>մϴ<D5B4>.
|
||||
|
||||
5<EFBFBD>ܰ<EFBFBD>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ȭ <20><> MPU/ij<><C4B3> Ȱ<><C8B0>ȭ
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ϸ<EFBFBD><CFB7>Ǹ<EFBFBD> <20>ݵ<EFBFBD><DDB5><EFBFBD> DSB(Data Synchronization Barrier)<29><> ISB(Instruction Synchronization Barrier) <20><><EFBFBD>ɾ <20><><EFBFBD><EFBFBD><EFBFBD>Ͽ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ü<EFBFBD><C3BC> <20>ݿ<EFBFBD><DDBF>ǵ<EFBFBD><C7B5><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> SCTLR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϳ<EFBFBD><CDBF><EFBFBD> MPU<50><55> ij<>ø<EFBFBD> <20>ٽ<EFBFBD> Ȱ<><C8B0>ȭ(Enable)<29>մϴ<D5B4>.
|
||||
|
||||
?? FAE <20>ǹ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>̵<EFBFBD> (üũ<C3BC><C5A9><EFBFBD><EFBFBD>Ʈ)
|
||||
<EFBFBD>ռ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ó<EFBFBD><C3B3>, <20>ڵ<EFBFBD> <20><><EFBFBD>䳪 <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> 4<><34><EFBFBD><EFBFBD> <20><>Ģ<EFBFBD><C4A2> <20>ݵ<EFBFBD><DDB5><EFBFBD> Ȯ<><C8AE><EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>.
|
||||
|
||||
1. "<22><>ij<EFBFBD><C4B3> <20><><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD>)<29><> MPU(<28>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD>)<29><> 1:1 <20><>ġ"
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DFBB>ϴ<EFBFBD> <20><>Ÿ<EFBFBD><C5B8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>. <20><>Ŀ <20><>ũ<EFBFBD><C5A9>Ʈ(.scat)<29><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EEB8AE> <20><><EFBFBD>۰<EFBFBD> <20><> <20>ּҰ<D6BC> MPU<50><55> PRBAR / PRLAR <20><><EFBFBD>輱<EFBFBD><E8BCB1> 1<><31><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ġ<EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>. <20><><EFBFBD><EFBFBD><EFBFBD>̳<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20>߰<EFBFBD><DFB0><EFBFBD> <20><><EFBFBD>ļ<EFBFBD> <20>ɰ<EFBFBD><C9B0><EFBFBD><EFBFBD><EFBFBD> <20>ʾҴ<CABE><D2B4><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͻʽÿ<CABD>.
|
||||
|
||||
2. "<22>ֺ<EFBFBD><D6BA><EFBFBD>ġ(IO) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<><C4B3> <20>Ӽ<EFBFBD> Ȯ<><C8AE>"
|
||||
GIC(<28><><EFBFBD>ͷ<EFBFBD>Ʈ), TMU(Ÿ<≯<EFBFBD>), <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(SPI, I2C) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><>ġ<EFBFBD><C4A1> <20><><EFBFBD>ε<EFBFBD> <20>ּ<EFBFBD> <20>뿪<EFBFBD><EBBFAA> <20>ݵ<EFBFBD><DDB5><EFBFBD> Device Memory (ij<><C4B3> <20><>) <20>Ӽ<EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD> <20>Ҵ<EFBFBD><D2B4>ؾ<EFBFBD> <20>մϴ<D5B4>. <20>̰<EFBFBD><CCB0><EFBFBD> Write-Back/Write-Through <20><><EFBFBD><EFBFBD> <20>Ϲ<EFBFBD> <20><EFBFBD><DEB8><EFBFBD> ij<><C4B3> <20>Ӽ<EFBFBD><D3BC><EFBFBD> <20>ɸ<EFBFBD><C9B8><EFBFBD> <20>ﰢ<EFBFBD><EFB0A2><EFBFBD><EFBFBD> AXI <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ÿ<>Ӿƿ<D3BE><C6BF><EFBFBD> <20><EFBFBD><DFBB>մϴ<D5B4>.
|
||||
|
||||
3. "<22>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(IOC) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<><C4B3> <20>ϰ<EFBFBD><CFB0><EFBFBD>"
|
||||
<EFBFBD><EFBFBD>Ƽ<EFBFBD>ھ<EFBFBD> ȯ<>濡<EFBFBD><E6BFA1> <20>ھ<EFBFBD><DABE><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ɶ<EFBFBD><C9B6><EFBFBD> <20>ɰų<C9B0> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ְ<EFBFBD><D6B0><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(DDR <20>Ǵ<EFBFBD> RT-VRAM<41><4D> BSS <20><><EFBFBD><EFBFBD> <20><>) <20><><EFBFBD><EFBFBD> <20>ݵ<EFBFBD><DDB5><EFBFBD> Non-cacheable <20>Ǵ<EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> Snoop<6F><70> <20>Ϻ<EFBFBD><CFBA><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD> <20>Ӽ<EFBFBD><D3BC><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD> <20>մϴ<D5B4>.
|
||||
|
||||
4. "Execute-never (XN) <20><>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>и<EFBFBD>"
|
||||
|
||||
XN = 0 (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>): ROM, Bootloader, <20>ڵ<EFBFBD>(.text) <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ӵϴ<D3B4>.
|
||||
|
||||
XN = 1 (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>): Stack, Heap, Data(.bss), IO Peripheral <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 100%<25><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ݾƾ<DDBE> <20>մϴ<D5B4>. <20>̴<EFBFBD> <20>߸<EFBFBD><DFB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ý<EFBFBD><C3BD><EFBFBD> <20><><EFBFBD>ָ<EFBFBD> <20>ʱ Instruction Abort<72><74> <20><><EFBFBD>Ƴ<EFBFBD><C6B3><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʼ<EFBFBD> <20><><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
@@ -0,0 +1,366 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0x6174501B // PRBAR7 - IOC DATA
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0x61794FC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE200001B // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE209FFC3 // PRLAR8 - SRAM STACK end : 0xE209FFFF
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE20A001B // PRBAR9 - SRAM IOC NONCACHE BSS start: 0xE20A0000
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20EFFC7 // PRLAR9 - SRAM IOC NONCACHE BSS end: 0xE2885000 (256KB)
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR r0, =0xE4000003 // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE62FFFC9 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE2100003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE3FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,375 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0xE2000002 // PRBAR7 - SRAM TEXT
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0xE203FFC3 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE204001B // PRBAR8 - SRAM IOC
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE208FFC3 // PRLAR8
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE209001B // PRBAR9 - SRAM STACK
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20FFFC3 // PRLAR9
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR r0, =0x6174501B // PRBAR10 - IOC DDR
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0x61794FC7 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE2100003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE3FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
|
||||
LDR r0, =21 //Select Region 21
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE4000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE62FFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,375 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0xE2000002 // PRBAR7 - SRAM TEXT
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0xE203FFC3 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE204001B // PRBAR8 - SRAM IOC
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE208FFC3 // PRLAR8
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE209001B // PRBAR9 - SRAM STACK
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20FFFC3 // PRLAR9
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR r0, =0x6174501B // PRBAR10 - IOC DDR
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0x61794FC7 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE2100003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE3FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
|
||||
LDR r0, =21 //Select Region 21
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE4000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE62FFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,481 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x00AA04FF
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
Index,<EFBFBD><EFBFBD>õ <EFBFBD><EFBFBD>,<EFBFBD>Ӽ<EFBFBD> (Memory Type), <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>뵵 (Example)
|
||||
0, 0x44, Normal Non-Cacheable, "DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD>" (Normal Non-Cacheable)
|
||||
1, 0xFF, Normal Write-Back, "<22>Ϲ<EFBFBD> <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD> Flash/RAM)" (Normal Write-Back, Read/Write-Allocate)
|
||||
2, 0xEE, Normal Write-Back, "<22>߿<EFBFBD> <20>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD>(Stack), TCM <20><><EFBFBD><EFBFBD>" Read-Allocate, No Write-Allocate (<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<EFBFBD><EFBFBD> <EFBFBD>Ҵ<EFBFBD>, <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD>Ҵ<EFBFBD>)
|
||||
3, 0x44, Normal Non-Cacheable, "DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD>" (Normal Non-Cacheable)
|
||||
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =0xFFAA4404
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
LDR r0, =0x44444400
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
Index,<EFBFBD><EFBFBD>õ <EFBFBD><EFBFBD>,<EFBFBD>Ӽ<EFBFBD> (Memory Type), <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>뵵 (Example)
|
||||
0, 0x04, Device-nGnRE, "<22><><EFBFBD><EFBFBD> <20>ֺ<EFBFBD> <20><>ġ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (I2C, SPI, CAN <20><>)" ij<EFBFBD><EFBFBD> X / <EFBFBD><EFBFBD><EFBFBD><EFBFBD> O / <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>,"<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ֺ<EFBFBD> <EFBFBD><EFBFBD>ġ <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (I2C, SPI, CAN <EFBFBD><EFBFBD>)
|
||||
1, 0x44, Normal Non-Cacheable, "DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD>, IOC"(Normal Non-Cacheable) ij<EFBFBD>ø<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ġ<EFBFBD><EFBFBD> <EFBFBD>ʰ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>,"DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> (IOC)"
|
||||
2, 0xAA, Normal Write-Through, "<22>߿<EFBFBD> <20>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD>(Stack), TCM <20><><EFBFBD><EFBFBD>"RA, No-WA: <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> ij<EFBFBD><EFBFBD> <EFBFBD>Ҵ<EFBFBD>, <EFBFBD><EFBFBD> <EFBFBD><EFBFBD> ij<EFBFBD>ÿ<EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>","<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<EFBFBD><EFBFBD><EFBFBD><EFBFBD>, TCM, <EFBFBD>߿<EFBFBD> <EFBFBD>Ķ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)"
|
||||
3, 0xFF, Normal Write-Back, "<22>Ϲ<EFBFBD> <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD> Flash/RAM)"(Normal Write-Back, Read/Write-Allocate)
|
||||
4, 0x00, Device-nGnRnE, "<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Device <20><><EFBFBD><EFBFBD> (<28>ʿ<EFBFBD><CABF><EFBFBD>), <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, CPU<50><55> ó<><C3B3><EFBFBD><EFBFBD> <20><><EFBFBD>ٸ<EFBFBD>"
|
||||
5~7, 0x44,Normal Non-Cacheable, "<22><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> ij<><C4B3> <20>̻<EFBFBD><CCBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)"(Normal Non-Cacheable)
|
||||
|
||||
0x04,Device-nGnRE,ij<EFBFBD><EFBFBD> X / <EFBFBD><EFBFBD><EFBFBD><EFBFBD> O / <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>,"<22><><EFBFBD><EFBFBD> <20>ֺ<EFBFBD> <20><>ġ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (I2C, SPI, CAN <20><>)"
|
||||
0x44,Normal Non-Cacheable,ij<EFBFBD>ø<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ġ<EFBFBD><EFBFBD> <EFBFBD>ʰ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>,"DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> (IOC)"
|
||||
0xAA,Normal Write-Through,"RA, No-WA: <20><><EFBFBD><EFBFBD> <20><> ij<><C4B3> <20>Ҵ<EFBFBD>, <20><> <20><> ij<>ÿ<EFBFBD> <20><DEB8> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>","<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD>, TCM, <20>߿<EFBFBD> <20>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>)"
|
||||
0xEE,Normal Write-Back,"RA, No-WA: <20><><EFBFBD><EFBFBD> <20><> ij<><C4B3> <20>Ҵ<EFBFBD>, <20><> <20><> <20><DEB8> <20>ٷ<EFBFBD> <20><><EFBFBD><EFBFBD> (ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)","<22><><EFBFBD>뷮 <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><>ȸ<EFBFBD><C8B8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ۼ<EFBFBD><DBBC><EFBFBD> <20><><EFBFBD><EFBFBD>"
|
||||
0xFF,Normal Write-Back,"RA, WA: <20>а<EFBFBD> <20><> <20><> <20><><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȱ<><C8B0> (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)","<22>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD> <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD>, <20>Ϲ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (Flash/DDR)"
|
||||
0x00,Device-nGnRnE,<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<EFBFBD><EFBFBD><EFBFBD><EFBFBD>/ij<EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>),"<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20>ſ<EFBFBD> <20>ΰ<EFBFBD><CEB0><EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><>Ʈ<EFBFBD>ѷ<EFBFBD>"
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
|
||||
Region0,DDR Memory Image ROM (0x6100_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ, <EFBFBD>̺<EFBFBD><EFBFBD>浵 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8,
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5 4
|
||||
Region1,System Register (0x0000_0000),Index 1 (0xFF)
|
||||
0x0000_0000<EFBFBD><EFBFBD> <EFBFBD>Ϲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ý<EFBFBD><EFBFBD><EFBFBD>, Master port 0 (Peripheral)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ, <EFBFBD>̺<EFBFBD><EFBFBD>浵 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
Region 2 = RPC Memory Space (0x0800_0000), Index 0 (0x44)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 0, <EFBFBD><EFBFBD> Index 0
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index0 <EFBFBD><EFBFBD>õ, <EFBFBD>̺<EFBFBD><EFBFBD>浵 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
Region3,Reserved (0x0C00_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
Region4,DDR Memory (0x4000_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
Region5,DDR Memory (0x4030_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
Region6,DDR Memory Image RAM 0x6144_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
|
||||
LDR r0, =0x6174501B // PRBAR7 - IOC DATA
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0x61794FC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
Region7,IOC DATA (0x6174_5000),Index 3 (0x44),
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 11, <EFBFBD><EFBFBD> Index 3,
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index1 <EFBFBD><EFBFBD>õ, <EFBFBD>̺<EFBFBD><EFBFBD>浵 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
LDR r0, =0xE200001B // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE209FFC3 // PRLAR8 - SRAM STACK end : 0xE209FFFF
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
Region8,SRAM Stack (0xE200_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 01, <EFBFBD><EFBFBD> Index 1,
|
||||
<EFBFBD><EFBFBD>TCM <EFBFBD>̵<EFBFBD> Ȥ<EFBFBD><EFBFBD> Index 2<EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ʿ<EFBFBD>
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =0xE20A001B // PRBAR9 - SRAM IOC NONCACHE BSS start: 0xE20A0000
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20EFFC7 // PRLAR9 - SRAM IOC NONCACHE BSS end: 0xE2885000 (256KB)
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
Region9,IOC BSS (0xE20A_0000),Index 3 (0x44)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 11, Index 3,
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index1 <EFBFBD><EFBFBD>õ
|
||||
|
||||
|
||||
|
||||
LDR r0, =0xE4000003 // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE62FFFC9 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
<EFBFBD><EFBFBD>Region10,Core0 TCM (0xE400_0000),Index 4 ???
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 100, <EFBFBD><EFBFBD> Index 4
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
Region11,System RAM (1MB) (0xE630_0000),Index 1 (0xFF),
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
Region12, Reserved Peripheral (0xE640_0000),Index 4 ???
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 100, <EFBFBD><EFBFBD> Index 4 ??
|
||||
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
Region13, BootROM (0xEB10_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
Region14,BootROM(0xEB12_8000),Index 4 ??
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 100, <EFBFBD><EFBFBD> Index 4 ??
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
Region15,RT-VRAM0 Mirroring area (0xEB20_0000),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
Region16,Reserved (0xEB40_0000~ 0xFFFFFFFF),Index 4 ??
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 100, <EFBFBD><EFBFBD> Index 4 ??
|
||||
0xEB40_0000 ~ 0xFFFFFFFF<EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index 4, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
Region17,DDR Memory (0x6174_0100 ~ 0x6174_4FC0),Index 4 ??
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 100, <EFBFBD><EFBFBD> Index 4 ??
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
Region18,DDR Memory (0x6300_0000 ~ 0xBFFF_FFFF),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
Region19,Reserved (0xC000_0000 ~ 0xE1FF_FFFF),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
<EFBFBD><EFBFBD> RT-VRAM0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD> <EFBFBD>ǵ<EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ʿ<EFBFBD>.
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE2100003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE3FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
Region20,RT-VRAM1 (0xE210_0000 ~ 0xE3FF_FFFF),Index 1 (0xFF)
|
||||
<EFBFBD><EFBFBD>Ʈ [3:1]<EFBFBD><EFBFBD> 1, <EFBFBD><EFBFBD> Index 1
|
||||
Woody <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> Index2 <EFBFBD><EFBFBD>õ
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,422 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* ===========================================================
|
||||
* Woody <EFBFBD><EFBFBD>õ MPU <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (MAIR <EFBFBD><EFBFBD> Region 0-20)
|
||||
*
|
||||
* Index,<EFBFBD><EFBFBD>õ <EFBFBD><EFBFBD>,<EFBFBD>Ӽ<EFBFBD> (Memory Type), <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>뵵 (Example)
|
||||
* 0, 0x04, Device-nGnRE, "<22><><EFBFBD><EFBFBD> <20>ֺ<EFBFBD> <20><>ġ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (I2C, SPI, CAN <20><>)"
|
||||
* 1, 0x44, Normal Non-Cacheable, "DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD>"
|
||||
* 2, 0xAA, Normal Write-Through, "<22>߿<EFBFBD> <20>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD>(Stack), TCM <20><><EFBFBD><EFBFBD>"
|
||||
* 3, 0xFF, Normal Write-Back, "<22>Ϲ<EFBFBD> <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD> Flash/RAM)"
|
||||
* 4, 0x00, Device-nGnRnE, "<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Device <20><><EFBFBD><EFBFBD> (<28>ʿ<EFBFBD><CABF><EFBFBD>), <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, CPU<50><55> ó<><C3B3><EFBFBD><EFBFBD> <20><><EFBFBD>ٸ<EFBFBD>"
|
||||
* 5~7, 0x44,Normal Non-Cacheable, "<22><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> ij<><C4B3> <20>̻<EFBFBD><CCBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)"
|
||||
* =========================================================== */
|
||||
|
||||
/* 1. MAIR <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<EFBFBD>Ӽ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>) */
|
||||
|
||||
/* MAIR0: Index 3(Normal WB), 2(Normal WT), 1(Normal NC), 0(Device-nGnRE) */
|
||||
LDR r0, =0xFFAA4404
|
||||
MCR p15, 0, r0, c10, c2, 0 /* Write MAIR0 */
|
||||
|
||||
/* MAIR1: Index 7~5(Normal NC <EFBFBD><EFBFBD><EFBFBD><EFBFBD>), 4(Device-nGnRnE) */
|
||||
LDR r0, =0x44444400
|
||||
MCR p15, 0, r0, c10, c2, 1 /* Write MAIR1 */
|
||||
|
||||
/* 2. Region 0 ~ 15 <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (Direct Access) */
|
||||
|
||||
/* Region 0: DDR ROM - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x61000004 /* Base: 0x6100_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c8, 0 /* PRBAR0 */
|
||||
|
||||
LDR r0, =0x6143FFC3 /* Limit: 0x6143_FFFF, Enable, Non-shareable */
|
||||
MCR p15, 0, r0, c6, c8, 1 /* PRLAR0 */
|
||||
|
||||
/* Region 1: System Register - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x00000004 /* Base: 0x0000_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c8, 4 /* PRBAR1 */
|
||||
LDR r0, =0x07FFFFC3 /* Limit: 0x07FF_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c8, 5 /* PRLAR1 */
|
||||
|
||||
/* Region 2: RPC Flash - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x08000004 /* Base: 0x0800_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c9, 0 /* PRBAR2 */
|
||||
LDR r0, =0x0BFFFFC3 /* Limit: 0x0BFF_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c9, 1 /* PRLAR2 */
|
||||
|
||||
/* Region 3: Reserved - Index 3 (WB) */
|
||||
LDR r0, =0x0C000006 /* Base: 0x0C00_0000, Attr: Index 3 */
|
||||
MCR p15, 0, r0, c6, c9, 4 /* PRBAR3 */
|
||||
LDR r0, =0x3FFFFFC3 /* Limit: 0x3FFF_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c9, 5 /* PRLAR3 */
|
||||
|
||||
/* Region 4: DDR Memory - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x40000004 /* Base: 0x4000_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c10, 0 /* PRBAR4 */
|
||||
LDR r0, =0x402FFFC3 /* Limit: 0x402F_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c10, 1 /* PRLAR4 */
|
||||
|
||||
/* Region 5: DDR Memory - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x40300004 /* Base: 0x4030_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c10, 4 /* PRBAR5 */
|
||||
LDR r0, =0x60FFFFC3 /* Limit: 0x60FF_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c10, 5 /* PRLAR5 */
|
||||
|
||||
/* Region 6: DDR Image RAM - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x61440004 /* Base: 0x6144_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c11, 0 /* PRBAR6 */
|
||||
LDR r0, =0x617400C3 /* Limit: 0x6174_0000, Enable */
|
||||
MCR p15, 0, r0, c6, c11, 1 /* PRLAR6 */
|
||||
|
||||
/* <EFBFBD><EFBFBD> Region 7: IOC DATA (<EFBFBD>ٽ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ؼ<EFBFBD>) - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0x61745004 /* Base: 0x6174_5000, Attr: Index 2 (Normal WT) */
|
||||
MCR p15, 0, r0, c6, c11, 4 /* PRBAR7 */
|
||||
LDR r0, =0x61794FC3 /* Limit: 0x6179_4FC0, Enable */
|
||||
MCR p15, 0, r0, c6, c11, 5 /* PRLAR7 */
|
||||
|
||||
/* <EFBFBD><EFBFBD> Region 8: SRAM STACK (<EFBFBD>ٽ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ؼ<EFBFBD>) - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0xE2000004 /* Base: 0xE200_0000, Attr: Index 2 (Normal WT) */
|
||||
MCR p15, 0, r0, c6, c12, 0 /* PRBAR8 */
|
||||
LDR r0, =0xE209FFC3 /* Limit: 0xE209_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c12, 1 /* PRLAR8 */
|
||||
|
||||
/* <EFBFBD><EFBFBD> Region 9: IOC BSS (<EFBFBD>ٽ<EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ؼ<EFBFBD>) - Woody <EFBFBD><EFBFBD>õ Index 2 <EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
LDR r0, =0xE20A0004 /* Base: 0xE20A_0000, Attr: Index 2 (Normal WT) */
|
||||
MCR p15, 0, r0, c6, c12, 4 /* PRBAR9 */
|
||||
LDR r0, =0xE20EFFC3 /* Limit: 0xE20E_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c12, 5 /* PRLAR9 */
|
||||
|
||||
/* Region 10: Core0 TCM - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0xE4000004 /* Base: 0xE400_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c13, 0 /* PRBAR10 */
|
||||
LDR r0, =0xE62FFFC9 /* Limit: 0xE62F_FFFF, Enable, AttrIndex[3:1]=100(Idx 4) */
|
||||
MCR p15, 0, r0, c6, c13, 1 /* PRLAR10 */
|
||||
|
||||
/* Region 11: System RAM(1MB) - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0xE6300004 /* Base: 0xE630_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c13, 4 /* PRBAR11 */
|
||||
LDR r0, =0xE63FFFC3 /* Limit: 0xE63F_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c13, 5 /* PRLAR11 */
|
||||
|
||||
/* Region 12: Reserved Peripheral - Index 3 (WB) */
|
||||
LDR r0, =0xE6400006 /* Base: 0xE640_0000, Attr: Index 3 */
|
||||
MCR p15, 0, r0, c6, c14, 0 /* PRBAR12 */
|
||||
LDR r0, =0xEB0FFFC9 /* Limit: 0xEB0F_FFFF, Enable, Idx 4 */
|
||||
MCR p15, 0, r0, c6, c14, 1 /* PRLAR12 */
|
||||
|
||||
/* Region 13: BootROM - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0xEB100004 /* Base: 0xEB10_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c14, 4 /* PRBAR13 */
|
||||
LDR r0, =0xEB127FC3 /* Limit: 0xEB12_7FC0, Enable */
|
||||
MCR p15, 0, r0, c6, c14, 5 /* PRLAR13 */
|
||||
|
||||
/* Region 14: BootROM - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
LDR r0, =0xEB128004 /* Base: 0xEB12_8000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c15, 0 /* PRBAR14 */
|
||||
LDR r0, =0xEB1FFFC9 /* Limit: 0xEB1F_FFFF, Enable, Idx 4 */
|
||||
MCR p15, 0, r0, c6, c15, 1 /* PRLAR14 */
|
||||
|
||||
/* Region 15: RT-VRAM0 Mirror - Index 3 (WB) */
|
||||
LDR r0, =0xEB200006 /* Base: 0xEB20_0000, Attr: Index 3 */
|
||||
MCR p15, 0, r0, c6, c15, 4 /* PRBAR15 */
|
||||
LDR r0, =0xEB3FFFC3 /* Limit: 0xEB3F_FFFF, Enable */
|
||||
MCR p15, 0, r0, c6, c15, 5 /* PRLAR15 */
|
||||
|
||||
/* 3. Region 16 ~ 20 <EFBFBD><EFBFBD><EFBFBD><EFBFBD> (Indirect Access via PRSELR) */
|
||||
|
||||
/* Region 16: Reserved Catch-all - Index 3 (WB) */
|
||||
MOV r0, #16
|
||||
MCR p15, 0, r0, c6, c2, 1 /* PRSELR = 16 */
|
||||
LDR r0, =0xEB400006 /* Base: 0xEB40_0000, Attr: Index 3 */
|
||||
MCR p15, 0, r0, c6, c3, 0 /* PRBAR */
|
||||
LDR r0, =0xFFFFFFC9 /* Limit: 0xFFFF_FFFF, Idx 4 */
|
||||
MCR p15, 0, r0, c6, c3, 1 /* PRLAR */
|
||||
|
||||
/* Region 17: DDR Memory - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
MOV r0, #17
|
||||
MCR p15, 0, r0, c6, c2, 1 /* PRSELR = 17 */
|
||||
LDR r0, =0x61740104 /* Base: 0x6174_0100, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c3, 0 /* PRBAR */
|
||||
LDR r0, =0x61744FC9 /* Limit: 0x6174_4FC0, Idx 4 */
|
||||
MCR p15, 0, r0, c6, c3, 1 /* PRLAR */
|
||||
|
||||
/* Region 18: DDR Memory - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
MOV r0, #18
|
||||
MCR p15, 0, r0, c6, c2, 1 /* PRSELR = 18 */
|
||||
LDR r0, =0x63000004 /* Base: 0x6300_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c3, 0 /* PRBAR */
|
||||
LDR r0, =0xBFFFFFC3 /* Limit: 0xBFFF_FFFF, Idx 1 */
|
||||
MCR p15, 0, r0, c6, c3, 1 /* PRLAR */
|
||||
|
||||
/* Region 19: Reserved - Index 3 (WB) */
|
||||
MOV r0, #19
|
||||
MCR p15, 0, r0, c6, c2, 1 /* PRSELR = 19 */
|
||||
LDR r0, =0xC0000006 /* Base: 0xC000_0000, Attr: Index 3 */
|
||||
MCR p15, 0, r0, c6, c3, 0 /* PRBAR */
|
||||
LDR r0, =0xE1FFFFC3 /* Limit: 0xE1FF_FFFF, Idx 1 */
|
||||
MCR p15, 0, r0, c6, c3, 1 /* PRLAR */
|
||||
|
||||
/* Region 20: RT-VRAM1 - Woody <EFBFBD><EFBFBD>õ Index 2 (WT) */
|
||||
MOV r0, #20
|
||||
MCR p15, 0, r0, c6, c2, 1 /* PRSELR = 20 */
|
||||
LDR r0, =0xE2100004 /* Base: 0xE210_0000, Attr: Index 2 */
|
||||
MCR p15, 0, r0, c6, c3, 0 /* PRBAR */
|
||||
LDR r0, =0xE3FFFFC3 /* Limit: 0xE3FF_FFFF, Idx 1 */
|
||||
MCR p15, 0, r0, c6, c3, 1 /* PRLAR */
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,369 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x00AA04FF
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0x6174501B // PRBAR7 - IOC DATA
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0x61794FC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR? ? ?r0, =0xE200001B? // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
? MCR? ? ?p15, 0, r0, c6, c12, 0
|
||||
? LDR? ? ?r0, =0xE209FFCD? // PRLAR8 - SRAM STACK end : 0xE209FFFF (Index 6, 0xAA)
|
||||
? MCR? ? ?p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE20A001B // PRBAR9 - SRAM IOC NONCACHE BSS start: 0xE20A0000
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20EFFC7 // PRLAR9 - SRAM IOC NONCACHE BSS end: 0xE2885000 (256KB)
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR? ? ?r0, =0xE4000003? // PRBAR10
|
||||
? ?MCR? ? ?p15, 0, r0, c6, c13, 0
|
||||
? ?LDR? ? ?r0, =0xE62FFFCD? // PRLAR10 - TCM (Index 6, 0xAA)
|
||||
? ?MCR? ? ?p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR? ? ?r0, =0xE6400003? // PRBAR12
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c14, 0
|
||||
? ? LDR? ? ?r0, =0xEB0FFFCF? // PRLAR12 - Reserved (Index 7, 0x00)
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR? ? ?p15, 0, r0, c6, c2, 1? // PRSELR
|
||||
LDR? ? ?r0, =0xE2100003? ? ? ? // PRBAR
|
||||
MCR? ? ?p15, 0, r0, c6, c3, 0? // PRBAR
|
||||
LDR? ? ?r0, =0xE3FFFFCD? ? ? ? // PRLAR (Index 6, 0xAA)
|
||||
MCR? ? ?p15, 0, r0, c6, c3, 1? // PRLAR
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,369 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x00AA04FF
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0x6174501B // PRBAR7 - IOC DATA
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0x61794FC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE200001B // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE209FFCD // PRLAR8 - SRAM STACK end : 0xE209FFFF (Index 6, 0xAA)
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE20A001B // PRBAR9 - SRAM IOC NONCACHE BSS start: 0xE20A0000
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20EFFC7 // PRLAR9 - SRAM IOC NONCACHE BSS end: 0xE2885000 (256KB)
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR r0, =0xE4000003 // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE62FFFCD // PRLAR10 - TCM (Index 6, 0xAA)
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFCF // PRLAR12 - Reserved (Index 7, 0x00)
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 // PRSELR
|
||||
LDR r0, =0xE2100003 // PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 // PRBAR
|
||||
LDR r0, =0xE3FFFFCD // PRLAR (Index 6, 0xAA)
|
||||
MCR p15, 0, r0, c6, c3, 1 // PRLAR
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
@@ -0,0 +1,369 @@
|
||||
/* MK_ARM_entry.asm
|
||||
*
|
||||
* Contains an example implementation of a reset vector to be used with the
|
||||
* microkernel.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
/* DCG Deviations:
|
||||
*
|
||||
* DCG-1) Deviated Rule: [OS_ASM_STRUCT_020]
|
||||
* This file contains 2 return instructions. Expected: 1
|
||||
*
|
||||
* Reason:
|
||||
* This file contains a local function, which DCG allows.
|
||||
*/
|
||||
/* Deviation DCG-1 <*> */
|
||||
|
||||
/* must be first */
|
||||
#include <private/Mk_asm.h> /* Must be first! */
|
||||
#include <private/ARM/Mk_ARM_core.h>
|
||||
#include <private/ARM/Mk_ARM_thread.h>
|
||||
#include <private/ARM/Mk_ARM_enablevfp.h>
|
||||
#include <Mk_qmboard.h>
|
||||
|
||||
#ifndef MK_HAS_ECC_RAM
|
||||
#define MK_HAS_ECC_RAM 0
|
||||
#endif
|
||||
|
||||
MK_SECTION_TEXT
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_global MK_QM_Entry
|
||||
MK_global Start
|
||||
MK_extern MK_Entry2
|
||||
MK_extern MK_kernelStackTop
|
||||
MK_extern MK_BoardEarlyInit
|
||||
MK_extern MK_hwMasterCoreIndex
|
||||
#if MK_HAS_ECC_RAM
|
||||
MK_extern MK_InitEccRam
|
||||
#endif
|
||||
|
||||
/* Constant pool */
|
||||
MK_LABEL(MK_kernelStackTopAddr)
|
||||
MK_word MK_kernelStackTop
|
||||
|
||||
/* Example entry function */
|
||||
MK_FUNC(MK_QM_Entry)
|
||||
MK_LABEL(MK_QM_Entry)
|
||||
MK_LABEL(Start)
|
||||
/* switch to SVC and disable interrupts */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
/* enable the VFP */
|
||||
bl MK_QM_EnableVfp
|
||||
|
||||
/* initialize registers */
|
||||
bl MK_QM_InitRegisters
|
||||
|
||||
#if MK_HAS_ECC_RAM
|
||||
/* intialize ECC RAM */
|
||||
bl MK_InitEccRam
|
||||
#endif
|
||||
/* setup stack for startup */
|
||||
#if MK_MAXCORES > 1
|
||||
MK_QM_GET_CORE_ID r0, r1
|
||||
ldr r3, MK_kernelStackTopAddr
|
||||
ldr sp, [r3, r0, lsl #2]
|
||||
mov r1, #0
|
||||
cmp r1, r13
|
||||
beq MK_CoreDisabled
|
||||
#else
|
||||
ldr sp, MK_kernelStackTopAddr
|
||||
ldr sp, [sp]
|
||||
#endif
|
||||
|
||||
/* call board specific early initialization */
|
||||
bl MK_BoardEarlyInit
|
||||
|
||||
/* start the microkernel */
|
||||
b MK_Entry2
|
||||
MK_FUNC_END(MK_QM_Entry)
|
||||
|
||||
/* MK_QM_EnableVfp
|
||||
*
|
||||
* Enable the VFPV16 Co-processor.
|
||||
*/
|
||||
MK_FUNC(MK_QM_EnableVfp)
|
||||
MK_LABEL(MK_QM_EnableVfp)
|
||||
mrc p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, MK_imm(#, 0), r0, c1, c0, MK_imm(#, 2)
|
||||
mov r0, #0x40000000
|
||||
vmsr FPEXC, r0
|
||||
bx lr
|
||||
MK_FUNC_END(MK_QM_EnableVfp)
|
||||
|
||||
/* MK_QM_InitRegisters
|
||||
*
|
||||
* Initialize all registers with constant values. This way, the registers of
|
||||
* both cores will have identical values, and a lockstep error cannot result
|
||||
* from different (random) initial values for a register.
|
||||
*
|
||||
* NOTE:
|
||||
* - This function expects that on entry CPU mode is SVC with interrupts disabled.
|
||||
*
|
||||
* r13 -> sp
|
||||
* r14 -> lr
|
||||
*/
|
||||
MK_FUNC(MK_QM_InitRegisters)
|
||||
MK_LABEL(MK_QM_InitRegisters)
|
||||
/* initialize general purpose registers */
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
mov r2, r0
|
||||
mov r3, r0
|
||||
mov r4, r0
|
||||
mov r5, r0
|
||||
mov r6, r0
|
||||
mov r7, r0
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
|
||||
/* initialize spsr_svc */
|
||||
mov sp, r0
|
||||
/* lr is already initialized with the return address! */
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { r8_fiq - lr_fiq, spsr_fiq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_FIQ)
|
||||
mov r8, r0
|
||||
mov r9, r0
|
||||
mov r10, r0
|
||||
mov r11, r0
|
||||
mov r12, r0
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_irq, lr_irq, spsr_irq } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_IRQ)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_abt, lr_abt, spsr_abt } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_ABT)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_und, lr_und, spsr_und } */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_UND)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
msr spsr_cxsf, r0
|
||||
|
||||
/* initialize banked registers { sp_sys, lr_sys } */
|
||||
/* System mode has same registers available as User mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SYS)
|
||||
mov sp, r0
|
||||
mov lr, r0
|
||||
|
||||
/* Switch back to SVC mode */
|
||||
msr cpsr_cxsf, #(MK_THRPSW_COMMON | MK_THRPSW_IFIQ_DISABLED | MK_THRPSW_MODE_SVC)
|
||||
|
||||
LDR r0, =0x44EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0x00AA04FF
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1
|
||||
|
||||
LDR r0, =0x61000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x6143FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0x60FFFFC3 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0x61440003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0x617400C3 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0x6174501B // PRBAR7 - IOC DATA
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0x61794FC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE200001B // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE209FFCD // PRLAR8 - SRAM STACK end : 0xE209FFFF (Index 6, 0xAA)
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE20A001B // PRBAR9 - SRAM IOC NONCACHE BSS start: 0xE20A0000
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20EFFC7 // PRLAR9 - SRAM IOC NONCACHE BSS end: 0xE2885000 (256KB)
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
LDR r0, =0xE4000003 // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE62FFFCD // PRLAR10 - TCM (Index 6, 0xAA)
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
|
||||
LDR r0, =0xE6300002 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xE63FFFC3 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFCF // PRLAR12 - Reserved (Index 7, 0x00)
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
|
||||
LDR r0, =0xEB100002 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB127FC3 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB128003 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB200002 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
LDR r0, =16 //Select Region 16
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xEB400003
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 16)
|
||||
LDR r0, =0xFFFFFFC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 16)
|
||||
|
||||
LDR r0, =17 //Select Region 17 T1 RAM
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x61740103 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR (Region 17)
|
||||
LDR r0, =0x61744FC9 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR (Region 17)
|
||||
|
||||
LDR r0, =18 //Select Region 18
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0x63000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xBFFFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =19 //Select Region 19
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xC0000003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE1FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 // PRSELR
|
||||
LDR r0, =0xE2100003 // PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 // PRBAR
|
||||
LDR r0, =0xE3FFFFCD // PRLAR (Index 6, 0xAA)
|
||||
MCR 5p15, 0, r0, c6, c3, 1 // PRLAR
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 /* Read CPACR */
|
||||
ORR r0, r0, #(0xF << 20) /* Enable full access for VFP/NEON (bits 20-23) */
|
||||
MCR p15, 0, r0, c1, c0, 2 /* Write back to CPACR */
|
||||
|
||||
/* initialize vFPU registers */
|
||||
vmov d0, r1, r1
|
||||
vmov d1, r1, r1
|
||||
vmov d2, r1, r1
|
||||
vmov d3, r1, r1
|
||||
vmov d4, r1, r1
|
||||
vmov d5, r1, r1
|
||||
vmov d6, r1, r1
|
||||
vmov d7, r1, r1
|
||||
vmov d8, r1, r1
|
||||
vmov d9, r1, r1
|
||||
vmov d10, r1, r1
|
||||
vmov d11, r1, r1
|
||||
vmov d12, r1, r1
|
||||
vmov d13, r1, r1
|
||||
vmov d14, r1, r1
|
||||
vmov d15, r1, r1
|
||||
|
||||
#if MK_FPU_NREGS > 16
|
||||
/* Initialize D16-D31, if available */
|
||||
vmrs r0, MVFR0
|
||||
and r0, r0, #MK_VFP_MVFR0_SIMDREG_MASK /* Extract SIMDReg field */
|
||||
cmp r0, #MK_FPU_VFP3D32
|
||||
bne MK_QM_VfpInitRegistersDone
|
||||
|
||||
/* Hand assemble these vmov instructions to support multi-core systems with
|
||||
* heterogeneous FPUs.
|
||||
*/
|
||||
MK_VMOV_D16X_R1_R1(16)
|
||||
MK_VMOV_D16X_R1_R1(17)
|
||||
MK_VMOV_D16X_R1_R1(18)
|
||||
MK_VMOV_D16X_R1_R1(19)
|
||||
MK_VMOV_D16X_R1_R1(20)
|
||||
MK_VMOV_D16X_R1_R1(21)
|
||||
MK_VMOV_D16X_R1_R1(22)
|
||||
MK_VMOV_D16X_R1_R1(23)
|
||||
MK_VMOV_D16X_R1_R1(24)
|
||||
MK_VMOV_D16X_R1_R1(25)
|
||||
MK_VMOV_D16X_R1_R1(26)
|
||||
MK_VMOV_D16X_R1_R1(27)
|
||||
MK_VMOV_D16X_R1_R1(28)
|
||||
MK_VMOV_D16X_R1_R1(29)
|
||||
MK_VMOV_D16X_R1_R1(30)
|
||||
MK_VMOV_D16X_R1_R1(31)
|
||||
#endif
|
||||
|
||||
MK_LABEL(MK_QM_VfpInitRegistersDone)
|
||||
|
||||
/* initialize call buffer. Save LR first! */
|
||||
mov r0, lr
|
||||
|
||||
bl MK_QM_InitRegisters_l1
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l1, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l1)
|
||||
bl MK_QM_InitRegisters_l2
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l2, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l2)
|
||||
bl MK_QM_InitRegisters_l3
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l3, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l3)
|
||||
bl MK_QM_InitRegisters_l4
|
||||
MK_LBL_TYPE(MK_QM_InitRegisters_l4, object)
|
||||
MK_LABEL(MK_QM_InitRegisters_l4)
|
||||
|
||||
mov lr, r0
|
||||
bx lr
|
||||
|
||||
MK_FUNC_END(MK_QM_InitRegisters)
|
||||
|
||||
MK_FUNC(MK_CoreDisabled)
|
||||
MK_LABEL(MK_CoreDisabled)
|
||||
bl MK_CoreDisabledLoop
|
||||
MK_LBL_TYPE(MK_CoreDisabledLoop, object)
|
||||
MK_LABEL(MK_CoreDisabledLoop)
|
||||
wfe
|
||||
b MK_CoreDisabledLoop
|
||||
MK_FUNC_END(MK_CoreDisabled)
|
||||
|
||||
MK_ASM_END
|
||||
|
||||
/* Editor settings; DO NOT DELETE
|
||||
* vi:set ts=4:
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,60 @@
|
||||
1. TRACE32<33><32><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD>)
|
||||
Cortex-R52 <20>ھ<EFBFBD><DABE><EFBFBD> ij<><C4B3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ý<EFBFBD><C3BD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> **SCTLR(System Control Register)**<2A><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
TRACE32 <20><><EFBFBD>ɾ<EFBFBD> â<><C3A2> **register.view /system**<2A><> <20>Է<EFBFBD><D4B7>ϰų<CFB0>, <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB4><EFBFBD><EFBFBD><EFBFBD> CPU -> System Register<65><72> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
SCTLR (<28>Ǵ<EFBFBD> SCTLR_EL1) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ã<><C3A3><EFBFBD>ϴ<EFBFBD>.
|
||||
**<2A><>Ʈ 2 (C bit)**<2A><> Ȯ<><C8AE><EFBFBD>մϴ<D5B4>.
|
||||
C=1: D-Cache Ȱ<><C8B0>ȭ (Enabled)
|
||||
C=0: D-Cache <20><>Ȱ<EFBFBD><C8B0>ȭ (Disabled)
|
||||
<EFBFBD>߰<EFBFBD><EFBFBD><EFBFBD> **<2A><>Ʈ 12 (I bit)**<2A><> 1<><31><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>Ͽ<EFBFBD> Instruction Cache<68><65> <20><><EFBFBD><EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ø<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
2. MPU (Memory Protection Unit) <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>
|
||||
SCTLR<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ð<EFBFBD> <20><><EFBFBD><EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD>, <20>ش<EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD>(RT-VRAM <20><>)<29><> MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> **"Non-cacheable"**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ð<EFBFBD> <20>۵<EFBFBD><DBB5><EFBFBD><EFBFBD><EFBFBD> <20>ʽ<EFBFBD><CABD>ϴ<EFBFBD>.
|
||||
TRACE32<EFBFBD><EFBFBD><EFBFBD><EFBFBD> mmu.list.vtt (<28>Ǵ<EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ʈ â)<29><> <20><><EFBFBD><EFBFBD> RT-VRAM <20>ּ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD><D3BC><EFBFBD> Ȯ<><C8AE><EFBFBD>մϴ<D5B4>.
|
||||
<EFBFBD>ش<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Normal <20><> <20>ƴ<EFBFBD> Device <20>Ǵ<EFBFBD> **Strongly-ordered**<2A><> <20>Ǿ<EFBFBD> <20>ְų<D6B0>, **Inner/Outer Non-cacheable**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>ִٸ<D6B4> ij<><C4B3> ȿ<><C8BF><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD><D3B5><EFBFBD> <20>ް<EFBFBD><DEB0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
3. <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD> <20>ڵ<EFBFBD>(<28>⵿ <20>ڵ<EFBFBD>) Ȯ<><C8AE>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ռ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͻ<EFBFBD> SoC FuSa <20><><EFBFBD><EFBFBD> <20>ڵ峪 <20>⵿ <20><><EFBFBD><EFBFBD>(Startup code) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20>Ѵ<EFBFBD> <20>κ<EFBFBD><CEBA><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD> <20><><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD> Ů<>ϴ<EFBFBD>.
|
||||
asm <20><><EFBFBD><EFBFBD><EFBFBD>̳<EFBFBD> hw_setup.c <20><><EFBFBD><EFBFBD> <20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD> MCR p15, 0, r0, c1, c0, 0 (SCTLR <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20>ڵ尡 <20>ִ<EFBFBD><D6B4><EFBFBD>, <20><EFBFBD> <20><>Ʈ 2<><32> 1<><31> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE> <20><><EFBFBD><EFBFBD>Ʈ (CR52 <20><><EFBFBD><EFBFBD> <20>̽<EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
1. L1 Data Cache Ȱ<><C8B0>ȭ <20><><EFBFBD><EFBFBD> (SCTLR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
|
||||
<EFBFBD><EFBFBD><EFBFBD>翡<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>κ<EFBFBD><CEBA>Դϴ<D4B4>. ij<>ð<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD><D3B5><EFBFBD> 10<31><30> <20>̻<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϴ<EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: TRACE32<33><32><EFBFBD><EFBFBD> Register.view /System <20><><EFBFBD><EFBFBD>
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: SCTLR_EL1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> **Bit 2 (C bit)**<2A><> **1(Enable)**<2A><><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
<EFBFBD>ǹ<EFBFBD>: 0<≯<EFBFBD> CPU<50><55> <20><DEB8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
2. MPU (Memory Protection Unit) <20><><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
SCTLR<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20>, Ư<><C6AF> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD>(RT-VRAM <20><>)<29><> "ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>"<22><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: TRACE32<33><32><EFBFBD><EFBFBD> MMU.List.VTT (<28>Ǵ<EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20><>) Ȯ<><C8AE>
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: RT-VRAM <20>ּ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Attribute<74><65> **"Normal / Inner-cacheable / Outer-cacheable"**<2A><> <20>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE>.
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȣ: <20><><EFBFBD><EFBFBD> **"Device"**<2A><> "Strongly-ordered", <20>Ǵ<EFBFBD> **"Non-cacheable"**<2A><> <20>Ǿ<EFBFBD> <20>ִٸ<D6B4> <20>ӵ<EFBFBD><D3B5><EFBFBD> <20>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
3. RT-VRAM Ȯ<><C8AE>/<2F><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD> <20><> Wait State <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͻ<EFBFBD> Ȯ<><C8AE> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>. <20><EFBFBD><DEB8><EFBFBD> <20><>ü<EFBFBD><C3BC> '<27><><EFBFBD><EFBFBD> <20>ð<EFBFBD>' <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: SoC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Bus Bridge <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ǵ<EFBFBD> LBSC(Local Bus State Controller) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: <20><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD> <20><> Wait Cycle<6C><65> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> Ŭ<><C5AC>(BCLK) <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ֺ<EFBFBD><D6BA><EFBFBD> <20>ùٸ<C3B9><D9B8><EFBFBD> Ȯ<><C8AE>.
|
||||
4. Tightly Coupled Memory (TCM) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
CR52 <20>ھ<EFBFBD><DABE><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD> ATCM/BTCM<43><4D> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: <20><>Ŀ <20><>ũ<EFBFBD><C5A9>Ʈ(.ld) <20>Ǵ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(.map) Ȯ<><C8AE>.
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> memcpy <20>Լ<EFBFBD><D4BC><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ϲ<EFBFBD> RAM<41><4D> <20>ƴ<EFBFBD> TCM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ġ<EFBFBD>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE>. (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʼ<EFBFBD><CABC>Դϴ<D4B4>.)
|
||||
5. <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD>ҽ<EFBFBD> <20><>Ƽ<EFBFBD>Ŵ<EFBFBD> (Resource Partitioning)
|
||||
A<EFBFBD>ھ<EFBFBD><EFBFBD><EFBFBD> R<>ھ <20><><EFBFBD>ÿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD><CFB7><EFBFBD> <20>ο<EFBFBD><CEBF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: QoS(Quality of Service) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: R<>ھ<EFBFBD>(CR52)<29><> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20>켱<EFBFBD><ECBCB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> A<>ھ <20>з<EFBFBD> <20><><EFBFBD><EFBFBD> <20>ð<EFBFBD><C3B0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
1. Cache <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>Ʈ: CR52<35><32> **L1 Instruction Cache(32KB)**<2A><> **L1 Data Cache(32KB)**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>: SCTLR_EL1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||||
<EFBFBD>ٽ<EFBFBD>: Ư<><C6AF> 100KB <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ű<EFBFBD><C5B1>ٸ<EFBFBD> D-Cache(<28><>Ʈ 2)<29><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD><D3B5><EFBFBD> ó<><C3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
2. TCM <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>뵵
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>Ʈ: CR52<35><32><EFBFBD><EFBFBD> ATCM, BTCM, CTCM<43><4D> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20>ð<EFBFBD>(Latency) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
Ȯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>: TCMTR (TCM Type Register) <20><> IMP_ATCM_REGIONR <20><>.
|
||||
üũ: 100KB <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Shared RAM<41><4D><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ּҰ<D6BC> <20>Ϲ<EFBFBD> System RAM<41><4D><EFBFBD><EFBFBD> <20>ƴϸ<C6B4> TCM<43><4D><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>. TCM<43><4D><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20><> <20>ξ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
3. MPU <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD> <20>߿<EFBFBD>)
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>Ʈ: <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20>Ŵ<EFBFBD><C5B4><EFBFBD> <20><>Section 13. Memory Protection Unit<69><74> <20><><EFBFBD><EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>: MAIR_EL1 (Memory Attribute Indirection Register).
|
||||
üũ: <20><> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD><D3BC><EFBFBD> Normal<61><6C><EFBFBD><EFBFBD> Device<63><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>մϴ<D5B4>. <20><><EFBFBD><EFBFBD> RT-VRAM<41>̳<EFBFBD> System RAM<41><4D> Device <20>Ӽ<EFBFBD><D3BC><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ִٸ<D6B4>, CPU<50><55> <20≯<EFBFBD> <20>ֺ<EFBFBD><D6BA><EFBFBD>ġ<EFBFBD><C4A1> <20>ν<EFBFBD><CEBD>ؼ<EFBFBD> ij<><C4B3><EFBFBD><EFBFBD> <20>ƿ<EFBFBD> <20><> <20>մϴ<D5B4>.
|
||||
4. System RAM / RT-VRAM <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>뵵
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>Ʈ: V4M<34><4D><EFBFBD><EFBFBD> **System RAM(<28>л<EFBFBD> <20><>ġ)**<2A><> **RT-VRAM(Real-Time <20><><EFBFBD><EFBFBD>)**<2A><> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
Ȯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>: <20><><EFBFBD><EFBFBD> <20><>Ű<EFBFBD><C5B0>ó <20><><EFBFBD>̾<EFBFBD><CCBE><EFBFBD>.
|
||||
üũ: CR52<35><32> System RAM<41><4D> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>긮<EFBFBD><EAB8AE><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD>ľ<EFBFBD> <20><> <20><> <20>־<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>. <20>ݸ<EFBFBD> RT-VRAM<41><4D> CR52<35><32> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>پ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>. (<28><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD> <20><> <20>ӵ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>⼭ <20><EFBFBD><DFBB><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> Ů<>ϴ<EFBFBD>.)
|
||||
5. DDR <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>뵵
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>Ʈ: DDR<44><52> <20>뷮<EFBFBD><EBB7AE> ũ<><C5A9><EFBFBD><EFBFBD> CR52 <20><><EFBFBD>忡<EFBFBD><E5BFA1><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><EFBFBD><DEB8><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
üũ: Ȥ<><C8A4> 100KB <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20>߰<EFBFBD> <20><><EFBFBD>ο<EFBFBD> DDR<44><52> <20><><EFBFBD><EFBFBD> <20>ְų<D6B0>, <20><><EFBFBD><EFBFBD>/<2F><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DDR<44><52> <20><><EFBFBD><EFBFBD> <20>ִٸ<D6B4> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ް<EFBFBD><DEB0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
1. L1 Data Cache Ȱ<><C8B0>ȭ <20><><EFBFBD><EFBFBD> (SCTLR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
|
||||
<EFBFBD><EFBFBD><EFBFBD>翡<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>κ<EFBFBD><CEBA>Դϴ<D4B4>. ij<>ð<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD><D3B5><EFBFBD> 10<31><30> <20>̻<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϴ<EFBFBD>.
|
||||
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: TRACE32<33><32><EFBFBD><EFBFBD> Register.view /System <20><><EFBFBD><EFBFBD>
|
||||
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: SCTLR_EL1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> **Bit 2 (C bit)**<2A><> **1(Enable)**<2A><><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
<EFBFBD>ǹ<EFBFBD>: 0<≯<EFBFBD> CPU<50><55> <20><DEB8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
2. MPU (Memory Protection Unit) <20><><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
SCTLR<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20>, Ư<><C6AF> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD>(RT-VRAM <20><>)<29><> "ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>"<22><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: TRACE32<33><32><EFBFBD><EFBFBD> MMU.List.VTT (<28>Ǵ<EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20><>) Ȯ<><C8AE>
|
||||
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: RT-VRAM <20>ּ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Attribute<74><65> **"Normal / Inner-cacheable / Outer-cacheable"**<2A><> <20>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȣ: <20><><EFBFBD><EFBFBD> **"Device"**<2A><> "Strongly-ordered", <20>Ǵ<EFBFBD> **"Non-cacheable"**<2A><> <20>Ǿ<EFBFBD> <20>ִٸ<D6B4> <20>ӵ<EFBFBD><D3B5><EFBFBD> <20>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
|
||||
|
||||
3. RT-VRAM Ȯ<><C8AE>/<2F><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD> <20><> Wait State <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͻ<EFBFBD> Ȯ<><C8AE> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>. <20><EFBFBD><DEB8><EFBFBD> <20><>ü<EFBFBD><C3BC> '<27><><EFBFBD><EFBFBD> <20>ð<EFBFBD>' <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: SoC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Bus Bridge <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ǵ<EFBFBD> LBSC(Local Bus State Controller) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: <20><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD> <20><> Wait Cycle<6C><65> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> Ŭ<><C5AC>(BCLK) <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ֺ<EFBFBD><D6BA><EFBFBD> <20>ùٸ<C3B9><D9B8><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
4. Tightly Coupled Memory (TCM) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
CR52 <20>ھ<EFBFBD><DABE><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD> ATCM/BTCM<43><4D> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: <20><>Ŀ <20><>ũ<EFBFBD><C5A9>Ʈ(.ld) <20>Ǵ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(.map) Ȯ<><C8AE>.
|
||||
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> memcpy <20>Լ<EFBFBD><D4BC><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ϲ<EFBFBD> RAM<41><4D> <20>ƴ<EFBFBD> TCM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ġ<EFBFBD>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE>. (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʼ<EFBFBD><CABC>Դϴ<D4B4>.)
|
||||
|
||||
5. <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD>ҽ<EFBFBD> <20><>Ƽ<EFBFBD>Ŵ<EFBFBD> (Resource Partitioning)
|
||||
A<EFBFBD>ھ<EFBFBD><EFBFBD><EFBFBD> R<>ھ <20><><EFBFBD>ÿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD><CFB7><EFBFBD> <20>ο<EFBFBD><CEBF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
|
||||
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: QoS(Quality of Service) <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
üũ <20><><EFBFBD><EFBFBD>Ʈ: R<>ھ<EFBFBD>(CR52)<29><> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20>켱<EFBFBD><ECBCB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> A<>ھ <20>з<EFBFBD> <20><><EFBFBD><EFBFBD> <20>ð<EFBFBD><C3B0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>.
|
||||
|
||||
?? <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>̵<EFBFBD>
|
||||
<EFBFBD><EFBFBD> å<>Ӵ<EFBFBD><D3B4>̳<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>̷<EFBFBD><CCB7><EFBFBD> <20><>û<EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>.
|
||||
|
||||
"<22><><EFBFBD><EFBFBD> <20><><EFBFBD>̵忡 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֿ<EFBFBD><D6BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CR52 ij<><C4B3> <20><>Ȱ<EFBFBD><C8B0>ȭ<EFBFBD><C8AD> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20>ǽɵ˴ϴ<CBB4>. <20><>Ȯ<EFBFBD><C8AE> <20>м<EFBFBD><D0BC><EFBFBD> <20><><EFBFBD><EFBFBD> <20>Ʒ<EFBFBD> 3<><33><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(Dump)<29><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ֽʽÿ<CABD>."
|
||||
|
||||
SCTLR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> (TRACE32 ĸó)
|
||||
|
||||
MPU <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ʈ (<28><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Attribute <20><><EFBFBD><EFBFBD>)
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>Ŀ <20><>ũ<EFBFBD><C5A9>Ʈ(.ld) <20><> <20><EFBFBD><DEB8><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>Ѹ<EFBFBD><D1B8><EFBFBD>:
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֵ<EFBFBD><D6B5><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> "Ȯ<><C8AE><EFBFBD>غþ<D8BA>?" <20><> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ì<><C3AC><EFBFBD>ž<EFBFBD> <20>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD> Ÿ<><C5B8> <20>̴ϴ<CCB4>. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>Ƴ<DEBE><C6B3><EFBFBD> "<22>ʳװ<CAB3> ij<>ø<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>" Ȥ<><C8A4> **"MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߸<EFBFBD><DFB8>߳<EFBFBD>"**<2A><><EFBFBD><EFBFBD> <20>ٷ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٷ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD> SCTLR <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB6><EFBFBD> <20>ϼ<EFBFBD><CFBC><EFBFBD>! ?? <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD>ϰڽ<CFB0><DABD>ϴ<EFBFBD>. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ʽÿ<CABD>!
|
||||
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Load Diff
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Load Diff
@@ -0,0 +1,53 @@
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(HKL)<29><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Scatter <20><><EFBFBD>ϰ<EFBFBD> MPU <20><><EFBFBD><EFBFBD> <20>ڵ<EFBFBD>(Mk_ARM_entry.asm)<29><> <20><><EFBFBD><EFBFBD> <20>м<EFBFBD><D0BC>߽<EFBFBD><DFBD>ϴ<EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>帮<EFBFBD><E5B8AE>, <20>ý<EFBFBD><C3BD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ۿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> '<27><><EFBFBD><EFBFBD> <20>̽<EFBFBD>'<27><> MPU <20>ڵ忡<DAB5><E5BFA1> <20>߰ߵǾ<DFB5><C7BE><EFBFBD><EFBFBD>ϴ<EFBFBD>. <20><><EFBFBD><EFBFBD>(Hideki)<29><> "ij<><C4B3> Ȯ<><C8AE><EFBFBD>غó<D8BA>"<22><> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20>־<EFBFBD><D6BE><EFBFBD>.
|
||||
|
||||
<EFBFBD>м<EFBFBD><EFBFBD><EFBFBD> 5<><35><EFBFBD><EFBFBD> <20>ٽ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>帳<EFBFBD>ϴ<EFBFBD>. <20>Ϻ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> <20>ٷ<EFBFBD> <20>ǵ<EFBFBD><C7B5><EFBFBD> <20>Ͻø<CFBD> <20>˴ϴ<CBB4>.
|
||||
|
||||
1. [ġ<><C4A1><EFBFBD><EFBFBD>] DDR RAM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 'Non-cacheable'<27><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Scatter <20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> RAM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU<50><55> <20>Ӽ<EFBFBD><D3BC><EFBFBD> <20><>ġ<EFBFBD><C4A1><EFBFBD><EFBFBD> <20>ʽ<EFBFBD><CABD>ϴ<EFBFBD>.
|
||||
|
||||
|
||||
Scatter <20><><EFBFBD><EFBFBD> <20><>Ȳ: <20><><EFBFBD><EFBFBD> RAM(ram_C0/C1/C2)<29><> 0x6144_0000 <20>뿪<EFBFBD><EBBFAA> <20><>ġ<EFBFBD>Ǿ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
MPU <20><><EFBFBD><EFBFBD> <20><>Ȳ (asm <20><><EFBFBD><EFBFBD>): Region 6<><36><EFBFBD><EFBFBD> <20><> <20>ּ<EFBFBD> <20>뿪(0x6144_0003)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>ϴµ<CFB4>, <20>Ӽ<EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD> 3<><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: MAIR0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> **3<><33> <20>Ӽ<EFBFBD><D3BC><EFBFBD> 0x44**<2A><> <20>Ǿ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>. ARMv8-R <20><>Ű<EFBFBD><C5B0>ó<EFBFBD><C3B3><EFBFBD><EFBFBD> 0x44<34><34> Normal Non-cacheable (ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><> <20><>)<29><> <20>ǹ<EFBFBD><C7B9>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TRACE32<33><32><EFBFBD><EFBFBD> SCTLR<4C><52> ij<>ø<EFBFBD> <20>, MPU<50><55><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> "ij<><C4B3> <20><><EFBFBD><EFBFBD>"<22><> <20><><EFBFBD>ƹ<EFBFBD><C6B9>ȱ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DDR <20><><EFBFBD><EFBFBD> <20>ӵ<EFBFBD><D3B5><EFBFBD> ó<><C3B3><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Դϴ<D4B4>.
|
||||
|
||||
2. SRAM Stack <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ij<>ð<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>(Stack)<29><> CPU<50><55> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD>, <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϰ<EFBFBD> <20>ɰ<EFBFBD><C9B0>ϰ<EFBFBD> <20><><EFBFBD>õǾ<C3B5> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: Region 8<><38>(SRAM Stack, 0xE200_0000) <20><><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD> **3<><33>(0x44)**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> SRAM<41><4D> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Ƴ<EFBFBD><C6B3><EFBFBD><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><>õ <20><><EFBFBD><EFBFBD> push/pop <20><><EFBFBD>۸<EFBFBD><DBB8><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ð<EFBFBD>(Wait State)<29><> <20><EFBFBD><DFBB>ϰ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
3. MAIR0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (32<33><32>Ʈ vs 64<36><34>Ʈ)
|
||||
<EFBFBD>ڵ忡<EFBFBD><EFBFBD> MAIR0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> 0x44EEFF44<34><34><EFBFBD><EFBFBD> 32<33><32>Ʈ <20><><EFBFBD><EFBFBD> <20>ְ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ARMv8-R<><52><EFBFBD><EFBFBD> MAIR0<52><30> 64<36><34>Ʈ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>. <20><><EFBFBD><EFBFBD> <20>ڵ<EFBFBD><DAB5><EFBFBD> <20><><EFBFBD><EFBFBD> 32<33><32>Ʈ(<28>ε<EFBFBD><CEB5><EFBFBD> 4~7<><37>)<29><> 0<><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ΰ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: Region 7<><37>(IOC Data)<29><> Region 9<><39>(IOC BSS)<29><> <20>ε<EFBFBD><CEB5><EFBFBD> 7<><37> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD> <20><> <20><>, <20><><EFBFBD>ǵ<EFBFBD><C7B5><EFBFBD> <20><><EFBFBD><EFBFBD> 0x00 <20>Ӽ<EFBFBD>(Strongly-ordered/Device)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ǿ<EFBFBD> <20>ý<EFBFBD><C3BD><EFBFBD><EFBFBD><EFBFBD> <20>ſ<EFBFBD> <20>Ҿ<EFBFBD><D2BE><EFBFBD><EFBFBD>ϰų<CFB0> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
|
||||
|
||||
4. Scatter <20><><EFBFBD>ϰ<EFBFBD> MPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ġ
|
||||
|
||||
DDR ROM: Scatter <20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD><EFBFBD><EFBFBD> ROM<4F><4D> 0x6100_1200<30><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, MPU Region 0<><30><EFBFBD><EFBFBD> 0x6100_0000<30><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>. (<28>̰<EFBFBD> ū <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ƴϳ<C6B4> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF>մϴ<D5B4>.)
|
||||
|
||||
|
||||
IOC DATA <20><><EFBFBD><EFBFBD>: Scatter<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0x6174_5000<30><30><EFBFBD><EFBFBD> 320KB<4B><42> <20><><EFBFBD>Ҵµ<D2B4>, MPU Region 7<><37><EFBFBD><EFBFBD> <20≯<EFBFBD> Non-cacheable(0x1B -> Attr Index 3<><33> <20><><EFBFBD><EFBFBD>)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>. <20><><EFBFBD>뷮 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
|
||||
|
||||
5. Write Buffer (WBCTLR) Ȱ<><C8B0>ȭ <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TRACE32<33><32> Ȯ<><C8AE><EFBFBD>Ͻ<EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> asm <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD> WBCTLR<4C>̳<EFBFBD> Write Buffer<65><72> Ȱ<><C8B0>ȭ<EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ԵǾ<D4B5> <20><><EFBFBD><EFBFBD> <20>ʽ<EFBFBD><CABD>ϴ<EFBFBD>.
|
||||
|
||||
[Woody <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>̵<EFBFBD> (HKL <20><><EFBFBD><EFBFBD>)]
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> å<>ӴԲ<D3B4> <20>Ʒ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>û<EFBFBD>Ͻʽÿ<CABD>.
|
||||
|
||||
MAIR0 <20><><EFBFBD><EFBFBD>: 0x44EEFF44 <20><><EFBFBD><EFBFBD>, ij<><C4B3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> 0xFF <20>Ӽ<EFBFBD><D3BC><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 64<36><34>Ʈ <20><>ü <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>. (<28><>: 0x44444444FFEEEEFF)
|
||||
|
||||
MPU Region 6, 8 <20>Ӽ<EFBFBD> <20><><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD> RAM<41><4D> Stack <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ӽ<EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD> 2<><32>(0xEE) <20>Ǵ<EFBFBD> **1<><31>(0xFF)**<2A><> <20><><EFBFBD><EFBFBD> Cacheable <20>Ӽ<EFBFBD><D3BC><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>.
|
||||
|
||||
Startup Code <20><><EFBFBD><EFBFBD>: Mk_QM_InitRegisters <20><>ƾ <20><><EFBFBD>Ŀ<EFBFBD> WBCTLR Ȱ<><C8B0>ȭ <20>ڵ带 <20><><EFBFBD><EFBFBD><EFBFBD>Ͽ<EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> Write Buffer<65><72> <20><> <20><>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, **"ij<>ô<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU<50><55> ij<>ø<EFBFBD> <20><><EFBFBD><EFBFBD> <20>־<EFBFBD><D6BE><EFBFBD>"**<2A><> <20><> <20>̹<EFBFBD> <20>м<EFBFBD><D0BC><EFBFBD> <20>ٽ<EFBFBD><D9BD>Դϴ<D4B4>. <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ø<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>絵 <20>ٷ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ۿ<EFBFBD> <20><><EFBFBD><EFBFBD> <20>̴ϴ<CCB4>. ?? <20>߰<EFBFBD><DFB0><EFBFBD> <20>ּ<EFBFBD> <20>뿪 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF>Ͻø<CFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ּ<EFBFBD><D6BC><EFBFBD>!
|
||||
Reference in New Issue
Block a user