update
This commit is contained in:
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,19 @@
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ȯ<><C8AF>
|
||||
Core0(<28><><EFBFBD>뷮 <20><><EFBFBD><EFBFBD> 100%): TMU x3(Task), CAN,
|
||||
Core1: Driver <20><><EFBFBD><EFBFBD>.
|
||||
Core2: SPI x 2, GPT,
|
||||
|
||||
* <20>̱<EFBFBD><CCB1>ھ<EFBFBD> ȯ<>濡<EFBFBD><E6BFA1> Test <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.(<28><><EFBFBD><EFBFBD> <20><>Ȳ<EFBFBD><C8B2><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ƽ<EFBFBD>ھ<DABE><EEB8B8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ƴ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>)
|
||||
EB <20><><EFBFBD><EFBFBD><EFBFBD>ҽ<EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ, <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD><EFBFBD>ϴµ<CFB4>,
|
||||
|
||||
Driver <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ư<EFBFBD><C6B0><EFBFBD>?
|
||||
Core0<EFBFBD><EFBFBD> <20>ƹ<EFBFBD> <20>͵<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>¿<EFBFBD><C2BF><EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD> <20><> 100% <20><><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD>?(HKL Ȯ<><C8AE>)
|
||||
|
||||
TC397, CET<45><54> 700us
|
||||
|
||||
AI
|
||||
TX: 20 Messages (32-byte payload) @ 10ms Cycle
|
||||
* RX: 150 Messages (32-byte payload) @ 10ms Incoming Cycle (Processed at 5ms Task Rate)
|
||||
TX<EFBFBD><EFBFBD> 20<32><30> <20><><EFBFBD><EFBFBD>, RX<52><58> 9<><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>µ<EFBFBD>, 10<31><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͱ<EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
|
||||
Driver<EFBFBD><EFBFBD><EFBFBD><EFBFBD> Time<6D><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE>.
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,10 +1,10 @@
|
||||
---- MasterMesg Matches (9 in 1 files) ----
|
||||
App_CDD_IIC_Common_Sample.c (sample_application\src) line 95 : volatile IicMessageType MasterMesg;
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : MasterMesg = IIC_NOTICE_IDLE;
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : MasterMesg = IIC_NOTICE_IDLE;
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : MasterMesg = IIC_NOTICE_IDLE;
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
|
||||
main in App_CDD_IIC_Common_Sample.c (sample_application\src) : MasterMesg = IIC_NOTICE_IDLE;
|
||||
IicAppNotice in App_CDD_IIC_Common_Sample.c (sample_application\src) : MasterMesg = NoticeInfo->Message;
|
||||
---- I2c3 Matches (0 in 0 files) ----
|
||||
---- I2c3 Search Errors Encountered (7) ----
|
||||
The following 7 files could not be processed:
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.siproj : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_sym : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xab : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xad : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xm : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xsb : File could not be opened.
|
||||
C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xsd : File could not be opened.
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,39 @@
|
||||
Jira 2863
|
||||
|
||||
|
||||
IPL <20><><EFBFBD><EFBFBD>Ʈ <20>ڵ<EFBFBD>
|
||||
IPL <20><><EFBFBD><EFBFBD> <20>ڵ<EFBFBD>
|
||||
IPL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD>ġ <20><><EFBFBD>̵<EFBFBD><CCB5><EFBFBD>? GHS<48><53> <20><><EFBFBD>罺 <20><><EFBFBD>̵尡 <20><><EFBFBD><EFBFBD>. <20><><EFBFBD>̼<EFBFBD><CCBC><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD>.
|
||||
|
||||
IPL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ڵ尡 <20><><EFBFBD><EFBFBD>.
|
||||
<EFBFBD>ñ<EFBFBD><EFBFBD><EFBFBD> <20><>ġ, GHS <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ġ
|
||||
IPL<EFBFBD><EFBFBD> HKL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD><D3B4><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>忡<EFBFBD><E5BFA1> F/W <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>(IPL. Autosar, Uboot)
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴµ<CFB4> I2C <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB>ϴ°<CFB4>?
|
||||
Chip <20><><EFBFBD><EFBFBD> WDG, I2C <20><>Ŷ<EFBFBD><C5B6> <20><><EFBFBD><EFBFBD>?
|
||||
|
||||
|
||||
case1 CR<43>ھ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>. -> I2C<32><43><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
|
||||
|
||||
|
||||
|
||||
case2 (HKL <20>ó<EFBFBD><C3B3><EFBFBD><EFBFBD><EFBFBD>.)
|
||||
CR<EFBFBD><EFBFBD><EFBFBD><EFBFBD> PMIC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 10ms <20><><EFBFBD><EFBFBD><CDB9><EFBFBD> <20><><EFBFBD><EFBFBD> <20>д´<D0B4>.
|
||||
|
||||
QNX<EFBFBD><EFBFBD><EFBFBD><EFBFBD> OTA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߰<EFBFBD><DFB0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB>Ѵ<EFBFBD>. -> IPL<50><4C> <20><><EFBFBD><EFBFBD> <20>ʱ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ȴ<EFBFBD>.
|
||||
QNX <20><><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ִ°<D6B4>?
|
||||
HKL PMIC I2C
|
||||
<EFBFBD><EFBFBD>HKL <20>̹<EFBFBD><CCB9><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ٽ<EFBFBD> <20>־ Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ʿ<EFBFBD>.
|
||||
|
||||
Case2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB>ϰ<EFBFBD> IPL <20><><EFBFBD>ý<EFBFBD>, I2C <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB><EFBFBD>.
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,300 @@
|
||||
/* MK_ARM_reset.asm
|
||||
*
|
||||
* This file contains the early initialization function for the RCARV4MCR52.
|
||||
* This functionality should be executed before the microkernel is started
|
||||
* in the first place.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety
|
||||
* standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
#include <private/Mk_asm.h>
|
||||
#include <private/ARM/Mk_ARM_mpu_v8r_memoryprotection.h>
|
||||
#include "Mk_board.h"
|
||||
#include "Mk_qmboard.h"
|
||||
|
||||
MK_global boardResetStart
|
||||
MK_extern MK_QM_Entry
|
||||
|
||||
/* Macros for setting up the MPU and the caches.
|
||||
*/
|
||||
/* Base and limit addresses for peripheral region. */
|
||||
#define MK_QM_DEV_BASE 0xe4000000
|
||||
#define MK_QM_DEV_LIMIT 0xffffffff
|
||||
|
||||
|
||||
#define MK_QM_MAIR_ATTR(a,i) ((a) << ((i) * 8))
|
||||
|
||||
#define MK_QM_MAIR0_ATTR0 MK_ARM_MPU_MAIR_ATT_DEV | MK_ARM_MPU_MAIR_ATT_DEV_NGNRNE
|
||||
#define MK_QM_MAIR0_ATTR MK_QM_MAIR_ATTR(MK_QM_MAIR0_ATTR0,0)
|
||||
|
||||
/* Boot address of CR core */
|
||||
#define CR_START_ADDRESS 0xE2100000UL
|
||||
#define MPU_AREA0_BASE_ADDRESS 0xE2100000UL
|
||||
/* (BASE + 0x1FFFFF) & ~(0x3F) */
|
||||
#define MPU_AREA0_LIMIT_ADDRESS 0xFFFFFFC0UL
|
||||
|
||||
#define RW_Access 0b01
|
||||
#define Non_Shareable 0b00
|
||||
#define ENable 0b1
|
||||
#define AttrIndx1 0b001
|
||||
|
||||
MK_SECTION_EXCTABLE
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_ALIGN_EXCTABLE
|
||||
/* Exception table for HYP mode */
|
||||
MK_LABEL(MK_StartupExceptionTableHyp)
|
||||
ldr pc, MK_QM_ResetAddr
|
||||
MK_LABEL(MK_QM_HypUndef)
|
||||
b MK_QM_HypUndef
|
||||
MK_LABEL(MK_QM_HypSvc)
|
||||
b MK_QM_HypSvc
|
||||
MK_LABEL(MK_QM_HypPrefetchAbort)
|
||||
b MK_QM_HypPrefetchAbort
|
||||
MK_LABEL(MK_QM_HypDataAbort)
|
||||
b MK_QM_HypDataAbort
|
||||
MK_LABEL(MK_QM_HypTrap)
|
||||
b MK_QM_HypTrap
|
||||
MK_LABEL(MK_QM_HypIrq)
|
||||
b MK_QM_HypIrq
|
||||
MK_LABEL(MK_QM_HypFiq)
|
||||
b MK_QM_HypFiq
|
||||
|
||||
MK_LABEL(MK_QM_ResetAddr)
|
||||
MK_word boardResetStart
|
||||
|
||||
MK_SECTION_RESET
|
||||
MK_CODE_ARM
|
||||
|
||||
MK_FUNC(boardResetStart)
|
||||
MK_LABEL(boardResetStart)
|
||||
//ldr r0, =MK_QM_ResetArmMode
|
||||
//bx r0
|
||||
b MK_QM_ResetArmMode
|
||||
MK_FUNC_END(boardResetStart)
|
||||
|
||||
|
||||
/* Arm mode entry point after reset. Cortex-R52 boots up in Hyp mode (EL2). See r52 trm, sec 7.3 */
|
||||
MK_FUNC(MK_QM_ResetArmMode)
|
||||
MK_LABEL(MK_QM_ResetArmMode)
|
||||
|
||||
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
mov r4, #0
|
||||
mov r5, #0
|
||||
mov r6, #0
|
||||
mov r7, #0
|
||||
mov r8, #0
|
||||
mov r9, #0
|
||||
mov r10, #0
|
||||
mov r11, #0
|
||||
mov r12, #0
|
||||
mov lr, #0
|
||||
|
||||
/* Disable all regions */
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
mov r2, #24
|
||||
|
||||
MK_LABEL(loop)
|
||||
mcr p15, #0, r0, c6, c2, #1
|
||||
mcr p15, #0, r1, c6, c3, #1
|
||||
add r0, r0, #1
|
||||
cmp r0, r2
|
||||
bne loop
|
||||
|
||||
/* Setup TCM base addresses. */
|
||||
MK_QM_GET_CORE_ID r0, r1 /* Load CoreID into r0; r1 will be clobbered. */
|
||||
|
||||
ldr r1, =MK_QM_ATcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 0 /* Set A-TCM base. */
|
||||
|
||||
ldr r1, =MK_QM_BTcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 1 /* Set B-TCM base. */
|
||||
|
||||
ldr r1, =MK_QM_CTcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 2 /* Set C-TCM base. */
|
||||
|
||||
LDR r0, =0x00EEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
/* 0x00000000 - 0x3FFFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
|
||||
LDR r0, =0x00000002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
|
||||
/* DDR 0x40000000 - 0xBFFFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
|
||||
LDR r0, =0x40000002 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0xBFFFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
|
||||
/* Reserved 0xC0000000 - 0xDFFFFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
|
||||
LDR r0, =0xC0000003 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xDFFFFFC7 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
|
||||
/* RT-VRAM 0xE0000000 - 0xE3FFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
|
||||
LDR r0, =0xE0000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0xE3FFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
|
||||
/* TCM 0xE4000000 - 0xE4BFFFFF, Index0, Non-Share, Read/Write, Execute, Non-Cacheable */
|
||||
LDR r0, =0xE4000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0xE4BFFFC1 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
|
||||
/* Reserved 0xE4C00000 - 0xE62FFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
|
||||
LDR r0, =0xE4C00003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0xE62FFFC7 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
|
||||
/* System RAM 0xE6300000 - 0xE63FFFFF, Index1, Inner Shareable, Read/Write, Execute-Never, Non-Cacheable */
|
||||
LDR r0, =0xE630001B // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0xE63FFFC1 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
|
||||
/* Reserved 0xE6400000 - 0xEB0FFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
|
||||
LDR r0, =0xE6400003 // PRBAR7
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0xEB0FFFC7 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
|
||||
/* BootROM & RT-VRAM0 0xEB100000 - 0xEB2FFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
|
||||
LDR r0, =0xEB100002 // PRBAR8
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xEB2FFFC3 // PRLAR8
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
|
||||
/* Reserved 0xEB300000 - 0xFFFFFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
|
||||
LDR r0, =0xEB300003 // PRBAR9
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xFFFFFFC7 // PRLAR9
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
|
||||
/* Enable MPU */
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
|
||||
MK_QM_GET_CORE_ID r0, r1 /* Load CoreID into r0; r1 will be clobbered. */
|
||||
|
||||
mov r4, r0 /* Preserve CoreID for TCM selection. */
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* ATCM base = 0xE4000000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE400
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop
|
||||
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* BTCM base = 0xE4100000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE410
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop_2)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop_2
|
||||
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* CTCM base = 0xE4200000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE420
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop_3)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop_3
|
||||
|
||||
ldr r0, =MK_StartupExceptionTableHyp
|
||||
mcr p15,4,r0,c12,c0,0 /* Set Hypervisor table in HVBAR */
|
||||
|
||||
/* Set up the Peripheral Port Region Register (IMP_PERIPHPREGIONR)
|
||||
Enable peripheral port at EL1 and EL0 */
|
||||
mrc p15, 0, r0, c15, c0, 0
|
||||
orr r0, 1
|
||||
mcr p15, 0, r0, c15, c0, 0
|
||||
|
||||
/* Setup TCM base addresses. */
|
||||
|
||||
/* Enable TCM regions in MPU before enabling it. */
|
||||
/* Enable TCM regions in MPU before enabling it. */
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0 /* Load SCTLR */
|
||||
bic r0, r0, #0x1 << 30 /* Clear TE bit (Exceptions taken in A32 state) */
|
||||
mcr p15, 0, r0, c1, c0, 0 /* Store SCTLR */
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1 << 5 /* Clear Thumb bit */
|
||||
orr r0, r0, #0x1 << 6 /* Set mask bit F. Disable FIQ. */
|
||||
orr r0, r0, #0x1 << 7 /* Set mask bit I. Disable IRQ. */
|
||||
orr r0, r0, #0x1 << 8 /* Set mask bit A. Disable async-aborts. */
|
||||
msr cpsr, r0 /* Setup mask bits A, F, I and Thumb bit */
|
||||
msr SPSR_cxsf, r0 /* Will stay set after ERET */
|
||||
|
||||
|
||||
ldr r0, =MK_QM_ResetStartEl1 /* Prepare to switch to EL1 */
|
||||
msr ELR_hyp, r0 /* Write r0 into ELR_hyp */
|
||||
mrs r0, SPSR_hyp /* Read SPSR_hyp into r0 */
|
||||
ldr r1, =0xffffffc0
|
||||
and r0, r0, r1 /* r0 = r0 & FFFF FFC0. Clear SPSR_hyp bits [5:0] -> Execution state bit + Mode bits. */
|
||||
ldr r1, =0x13
|
||||
orr r0, r0, r1 /* r0 = r0 | 0x13. Set bits b010011 -> Set mode to SVC and A32 */
|
||||
|
||||
msr SPSR_hyp, r0 /* Write r0 into SPSR_hyp */
|
||||
eret
|
||||
|
||||
|
||||
MK_LABEL(MK_QM_ResetStartEl1)
|
||||
b MK_QM_Entry
|
||||
MK_FUNC_END(MK_QM_ResetArmMode)
|
||||
|
||||
|
||||
/* Entry vector for cores that are disabled in current configuration. */
|
||||
MK_LABEL(MK_QM_CoreIdle)
|
||||
/* We do a pseudo "bl" so the debugger will show this core as disabled in the stack frame. */
|
||||
bl MK_QM_CoreIdleLoop
|
||||
MK_LABEL(MK_QM_CoreIdleLoop)
|
||||
wfe /* save power */
|
||||
b MK_QM_CoreIdleLoop
|
||||
|
||||
@@ -0,0 +1,339 @@
|
||||
/* MK_ARM_reset.asm
|
||||
*
|
||||
* This file contains the early initialization function for the RCARV4MCR52.
|
||||
* This functionality should be executed before the microkernel is started
|
||||
* in the first place.
|
||||
*
|
||||
* Warning: This file has not been developed in accordance with a safety
|
||||
* standard (no ASIL)!
|
||||
*
|
||||
* (c) Elektrobit Automotive GmbH
|
||||
*/
|
||||
|
||||
#include <private/Mk_asm.h>
|
||||
#include <private/ARM/Mk_ARM_mpu_v8r_memoryprotection.h>
|
||||
#include "Mk_board.h"
|
||||
#include "Mk_qmboard.h"
|
||||
|
||||
MK_global boardResetStart
|
||||
MK_extern MK_QM_Entry
|
||||
|
||||
/* Macros for setting up the MPU and the caches.
|
||||
*/
|
||||
/* Base and limit addresses for peripheral region. */
|
||||
#define MK_QM_DEV_BASE 0xe4000000
|
||||
#define MK_QM_DEV_LIMIT 0xffffffff
|
||||
|
||||
|
||||
#define MK_QM_MAIR_ATTR(a,i) ((a) << ((i) * 8))
|
||||
|
||||
#define MK_QM_MAIR0_ATTR0 MK_ARM_MPU_MAIR_ATT_DEV | MK_ARM_MPU_MAIR_ATT_DEV_NGNRNE
|
||||
#define MK_QM_MAIR0_ATTR MK_QM_MAIR_ATTR(MK_QM_MAIR0_ATTR0,0)
|
||||
|
||||
/* Boot address of CR core */
|
||||
#define CR_START_ADDRESS 0xE2100000UL
|
||||
#define MPU_AREA0_BASE_ADDRESS 0xE2100000UL
|
||||
/* (BASE + 0x1FFFFF) & ~(0x3F) */
|
||||
#define MPU_AREA0_LIMIT_ADDRESS 0xFFFFFFC0UL
|
||||
|
||||
#define RW_Access 0b01
|
||||
#define Non_Shareable 0b00
|
||||
#define ENable 0b1
|
||||
#define AttrIndx1 0b001
|
||||
|
||||
MK_SECTION_EXCTABLE
|
||||
MK_CODE_COMMON
|
||||
MK_ALIGN_CODE_ARM
|
||||
|
||||
MK_ALIGN_EXCTABLE
|
||||
/* Exception table for HYP mode */
|
||||
MK_LABEL(MK_StartupExceptionTableHyp)
|
||||
ldr pc, MK_QM_ResetAddr
|
||||
MK_LABEL(MK_QM_HypUndef)
|
||||
b MK_QM_HypUndef
|
||||
MK_LABEL(MK_QM_HypSvc)
|
||||
b MK_QM_HypSvc
|
||||
MK_LABEL(MK_QM_HypPrefetchAbort)
|
||||
b MK_QM_HypPrefetchAbort
|
||||
MK_LABEL(MK_QM_HypDataAbort)
|
||||
b MK_QM_HypDataAbort
|
||||
MK_LABEL(MK_QM_HypTrap)
|
||||
b MK_QM_HypTrap
|
||||
MK_LABEL(MK_QM_HypIrq)
|
||||
b MK_QM_HypIrq
|
||||
MK_LABEL(MK_QM_HypFiq)
|
||||
b MK_QM_HypFiq
|
||||
|
||||
MK_LABEL(MK_QM_ResetAddr)
|
||||
MK_word boardResetStart
|
||||
|
||||
MK_SECTION_RESET
|
||||
MK_CODE_ARM
|
||||
|
||||
MK_FUNC(boardResetStart)
|
||||
MK_LABEL(boardResetStart)
|
||||
//ldr r0, =MK_QM_ResetArmMode
|
||||
//bx r0
|
||||
b MK_QM_ResetArmMode
|
||||
MK_FUNC_END(boardResetStart)
|
||||
|
||||
|
||||
/* Arm mode entry point after reset. Cortex-R52 boots up in Hyp mode (EL2). See r52 trm, sec 7.3 */
|
||||
MK_FUNC(MK_QM_ResetArmMode)
|
||||
MK_LABEL(MK_QM_ResetArmMode)
|
||||
|
||||
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
mov r4, #0
|
||||
mov r5, #0
|
||||
mov r6, #0
|
||||
mov r7, #0
|
||||
mov r8, #0
|
||||
mov r9, #0
|
||||
mov r10, #0
|
||||
mov r11, #0
|
||||
mov r12, #0
|
||||
mov lr, #0
|
||||
|
||||
/* Disable all regions */
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
mov r2, #24
|
||||
|
||||
MK_LABEL(loop)
|
||||
mcr p15, #0, r0, c6, c2, #1
|
||||
mcr p15, #0, r1, c6, c3, #1
|
||||
add r0, r0, #1
|
||||
cmp r0, r2
|
||||
bne loop
|
||||
|
||||
/* Setup TCM base addresses. */
|
||||
MK_QM_GET_CORE_ID r0, r1 /* Load CoreID into r0; r1 will be clobbered. */
|
||||
|
||||
ldr r1, =MK_QM_ATcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 0 /* Set A-TCM base. */
|
||||
|
||||
ldr r1, =MK_QM_BTcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 1 /* Set B-TCM base. */
|
||||
|
||||
ldr r1, =MK_QM_CTcmBase
|
||||
ldr r1, [r1, r0, LSL #2]
|
||||
orr r1, r1, #0x3
|
||||
mcr p15, 0, r1, c9, c1, 2 /* Set C-TCM base. */
|
||||
|
||||
/* Attribute index 1, normal, cache */
|
||||
mov r0, #0xFF00
|
||||
mcr p15, #0, r0, c10, c2, #0
|
||||
/* Select Region 0 via PRSELR */
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c2, #1
|
||||
|
||||
/* BASE - PRBAR[31:6] */
|
||||
ldr r0, =MPU_AREA0_BASE_ADDRESS
|
||||
/* PRBAR[4:3] SH=b'00 - Normal memory, Non-shareable,
|
||||
PRBAR[2:1] AP=b'01 - Read/Write Allocation
|
||||
PRBAR[0] XN=b'0 - Instruction permitted */
|
||||
ldr r1, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
orr r0, r0, r1
|
||||
/* Set XN, AP, SH, BASE */
|
||||
mcr p15, #0, r0, c6, c3, #0
|
||||
|
||||
|
||||
|
||||
/* BASE - PRLAR[31:6] */
|
||||
LDR r0, =0xDDEEFF44
|
||||
MCR p15, 0, r0, c10, c2, 0 // MAIR0
|
||||
|
||||
LDR r0, =0xE2100002 // PRBAR0
|
||||
MCR p15, 0, r0, c6, c8, 0
|
||||
LDR r0, =0xE2A3FFC3 // PRLAR0
|
||||
MCR p15, 0, r0, c6, c8, 1
|
||||
LDR r0, =0x2 // PRBAR1
|
||||
MCR p15, 0, r0, c6, c8, 4
|
||||
LDR r0, =0x7FFFFC3 // PRLAR1
|
||||
MCR p15, 0, r0, c6, c8, 5
|
||||
LDR r0, =0x8000002 // PRBAR2
|
||||
MCR p15, 0, r0, c6, c9, 0
|
||||
LDR r0, =0xBFFFFC1 // PRLAR2
|
||||
MCR p15, 0, r0, c6, c9, 1
|
||||
LDR r0, =0xC000002 // PRBAR3
|
||||
MCR p15, 0, r0, c6, c9, 4
|
||||
LDR r0, =0x3FFFFFC3 // PRLAR3
|
||||
MCR p15, 0, r0, c6, c9, 5
|
||||
LDR r0, =0x40000002 // PRBAR4
|
||||
MCR p15, 0, r0, c6, c10, 0
|
||||
LDR r0, =0x402FFFC3 // PRLAR4
|
||||
MCR p15, 0, r0, c6, c10, 1
|
||||
LDR r0, =0x40300003 // PRBAR5
|
||||
MCR p15, 0, r0, c6, c10, 4
|
||||
LDR r0, =0xBFFFFFC9 // PRLAR5
|
||||
MCR p15, 0, r0, c6, c10, 5
|
||||
LDR r0, =0xC0000003 // PRBAR6
|
||||
MCR p15, 0, r0, c6, c11, 0
|
||||
LDR r0, =0xDFFFFFC9 // PRLAR6
|
||||
MCR p15, 0, r0, c6, c11, 1
|
||||
LDR r0, =0xE2A4001B // PRBAR7
|
||||
MCR p15, 0, r0, c6, c11, 4
|
||||
LDR r0, =0xE2FFFFC1 // PRLAR7
|
||||
MCR p15, 0, r0, c6, c11, 5
|
||||
LDR r0, =0xE4C00002 // PRBAR8
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE62FFFC9 // PRLAR8
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
LDR r0, =0xE20E001B // PRBAR9
|
||||
MCR p15, 0, r0, c6, c12, 4
|
||||
LDR r0, =0xE20FFFC3 // PRLAR9
|
||||
MCR p15, 0, r0, c6, c12, 5
|
||||
LDR r0, =0xE630001B // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE63FFFC3 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
LDR r0, =0xE6400003 // PRBAR11
|
||||
MCR p15, 0, r0, c6, c13, 4
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR11
|
||||
MCR p15, 0, r0, c6, c13, 5
|
||||
LDR r0, =0xEB100002 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB127FC3 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
LDR r0, =0xEB128003 // PRBAR13
|
||||
MCR p15, 0, r0, c6, c14, 4
|
||||
LDR r0, =0xEB1FFFC9 // PRLAR13
|
||||
MCR p15, 0, r0, c6, c14, 5
|
||||
LDR r0, =0xEB200002 // PRBAR14
|
||||
MCR p15, 0, r0, c6, c15, 0
|
||||
LDR r0, =0xEB3FFFC3 // PRLAR14
|
||||
MCR p15, 0, r0, c6, c15, 1
|
||||
LDR r0, =0xEB400003 // PRBAR15
|
||||
MCR p15, 0, r0, c6, c15, 4
|
||||
LDR r0, =0xFFFFFFC9 // PRLAR15
|
||||
MCR p15, 0, r0, c6, c15, 5
|
||||
|
||||
MOV r1, #16
|
||||
MCR p15, 0, r1, c6, c2, 1 // PRSELR = 16
|
||||
LDR r0, =0xE3000002 // PRBAR16
|
||||
MCR p15, 0, r0, c6, c3, 0
|
||||
LDR r0, =0xE3FFFFC9 // PRLAR16
|
||||
MCR p15, 0, r0, c6, c3, 1
|
||||
|
||||
MOV r1, #17
|
||||
MCR p15, 0, r1, c6, c2, 1 // PRSELR = 17
|
||||
LDR r0, =0xE4000003 // PRBAR17: SH=0b00(Non-Shareable), AP=R/W, XN
|
||||
MCR p15, 0, r0, c6, c3, 0
|
||||
LDR r0, =0xE4BFFFC1 // PRLAR17: Attr0(0x44), Non-Cacheable (TCM region)
|
||||
MCR p15, 0, r0, c6, c3, 1
|
||||
|
||||
/* Enable MPU */
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #1
|
||||
dsb
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
isb
|
||||
|
||||
MK_QM_GET_CORE_ID r0, r1 /* Load CoreID into r0; r1 will be clobbered. */
|
||||
|
||||
mov r4, r0 /* Preserve CoreID for TCM selection. */
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* ATCM base = 0xE4000000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE400
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop
|
||||
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* BTCM base = 0xE4100000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE410
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop_2)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop_2
|
||||
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
|
||||
/* CTCM base = 0xE4200000 + (core_id << 22) */
|
||||
movw r0, #0x0000
|
||||
movt r0, #0xE420
|
||||
mov r1, r4, LSL #22
|
||||
add r0, r0, r1
|
||||
add r1, r0, #0x4000
|
||||
|
||||
MK_LABEL(MK_QM_ClearAtcmLoop_3)
|
||||
strd r2, r3, [r0], #8 /* 8-byte stores also initialize ECC syndrome. */
|
||||
cmp r0, r1
|
||||
bne MK_QM_ClearAtcmLoop_3
|
||||
|
||||
ldr r0, =MK_StartupExceptionTableHyp
|
||||
mcr p15,4,r0,c12,c0,0 /* Set Hypervisor table in HVBAR */
|
||||
|
||||
/* Set up the Peripheral Port Region Register (IMP_PERIPHPREGIONR)
|
||||
Enable peripheral port at EL1 and EL0 */
|
||||
mrc p15, 0, r0, c15, c0, 0
|
||||
orr r0, 1
|
||||
mcr p15, 0, r0, c15, c0, 0
|
||||
|
||||
/* Setup TCM base addresses. */
|
||||
|
||||
/* Enable TCM regions in MPU before enabling it. */
|
||||
/* Enable TCM regions in MPU before enabling it. */
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0 /* Load SCTLR */
|
||||
bic r0, r0, #0x1 << 30 /* Clear TE bit (Exceptions taken in A32 state) */
|
||||
mcr p15, 0, r0, c1, c0, 0 /* Store SCTLR */
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1 << 5 /* Clear Thumb bit */
|
||||
orr r0, r0, #0x1 << 6 /* Set mask bit F. Disable FIQ. */
|
||||
orr r0, r0, #0x1 << 7 /* Set mask bit I. Disable IRQ. */
|
||||
orr r0, r0, #0x1 << 8 /* Set mask bit A. Disable async-aborts. */
|
||||
msr cpsr, r0 /* Setup mask bits A, F, I and Thumb bit */
|
||||
msr SPSR_cxsf, r0 /* Will stay set after ERET */
|
||||
|
||||
|
||||
ldr r0, =MK_QM_ResetStartEl1 /* Prepare to switch to EL1 */
|
||||
msr ELR_hyp, r0 /* Write r0 into ELR_hyp */
|
||||
mrs r0, SPSR_hyp /* Read SPSR_hyp into r0 */
|
||||
ldr r1, =0xffffffc0
|
||||
and r0, r0, r1 /* r0 = r0 & FFFF FFC0. Clear SPSR_hyp bits [5:0] -> Execution state bit + Mode bits. */
|
||||
ldr r1, =0x13
|
||||
orr r0, r0, r1 /* r0 = r0 | 0x13. Set bits b010011 -> Set mode to SVC and A32 */
|
||||
|
||||
msr SPSR_hyp, r0 /* Write r0 into SPSR_hyp */
|
||||
eret
|
||||
|
||||
|
||||
MK_LABEL(MK_QM_ResetStartEl1)
|
||||
b MK_QM_Entry
|
||||
MK_FUNC_END(MK_QM_ResetArmMode)
|
||||
|
||||
|
||||
/* Entry vector for cores that are disabled in current configuration. */
|
||||
MK_LABEL(MK_QM_CoreIdle)
|
||||
/* We do a pseudo "bl" so the debugger will show this core as disabled in the stack frame. */
|
||||
bl MK_QM_CoreIdleLoop
|
||||
MK_LABEL(MK_QM_CoreIdleLoop)
|
||||
wfe /* save power */
|
||||
b MK_QM_CoreIdleLoop
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
<EFBFBD>ý<EFBFBD><EFBFBD><EFBFBD> <20>ٿ<EFBFBD>
|
||||
<EFBFBD>ӵ<EFBFBD> <20>輱.
|
||||
|
||||
1<EFBFBD><EFBFBD> 8õ <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CPU<50><55> memcopy, DDR to RT-VRAM1(Ȯ<><C8AE> <20><><EFBFBD><EFBFBD>) or system 1.3m<EFBFBD><EFBFBD> <20>ɸ<EFBFBD> <20>̰<EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>°<EFBFBD>?
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,55 @@
|
||||
https://onefieldjira.renesas.com/browse/SOC-3502
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SMA <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ü<><C3BC><EFBFBD>߽<EFBFBD><DFBD>ϱ<EFBFBD>?
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(<28><>: <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>)<29><> <20><EFBFBD><EEB6BB> <20>˴ϱ<CBB4>?
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>û<EFBFBD><C3BB> <20><><EFBFBD><EFBFBD> MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϱ<D4B4>?
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ٰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ߴµ<DFB4>, <20>ش<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI <20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD> <20>ڵ忡<DAB5><E5BFA1> <20><EFBFBD><DFBB>ϴ<EFBFBD><CFB4><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ֽʽÿ<CABD>. <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB>ϴ<EFBFBD> <20><>ġ<EFBFBD><C4A1> SPI API/<2F>ڵ忡 <20><><EFBFBD><EFBFBD> <20>ڼ<EFBFBD><DABC><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֽñ<D6BD> <20>ٶ<EFBFBD><D9B6>ϴ<EFBFBD>.
|
||||
|
||||
|
||||
1.<2E><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE>-Ȯ<><C8AE><EFBFBD><EFBFBD>
|
||||
|
||||
2. ȸ<>ε<EFBFBD> Ȯ<><C8AE> - Ȯ<><C8AE><EFBFBD><EFBFBD>
|
||||
Core0
|
||||
Core1 - ADC, MSIOF1
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŷ 1<><31> + ch <20><>Ŷ 4<><34>, ä<>δ<EFBFBD> 1<><31><EFBFBD><EFBFBD> RX <20><><EFBFBD><EFBFBD>,
|
||||
<EFBFBD>ѹ<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ŷ 5<><35>(<28><><EFBFBD><EFBFBD>,1<><31>,~4<><34>) <20><><EFBFBD><EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> -> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>۸<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<EFBFBD>ͼ<EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD> -> <20>ܺ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>۸<EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
10ms Task<73><6B><EFBFBD><EFBFBD> <20><><EFBFBD>ư<EFBFBD>
|
||||
|
||||
Core2 - USS, MSIOF5
|
||||
min200<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ũ<EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
<EFBFBD>ͽ<EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
|
||||
3. <20>ٺ<EFBFBD>ġ <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE> -Ȯ<><C8AE><EFBFBD><EFBFBD>.
|
||||
*SpiSupportConcurrentAsyncTransmit
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EVB<56><42> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
|
||||
|
||||
4. Binh <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ǻ<EFBFBD><C7BB><EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><DFBB><EFBFBD><EFBFBD><EFBFBD> <20><>,
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Spi_GulActiveHWUnits<74><73> <20><><EFBFBD><EFBFBD> -> 0
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD> SPI Hw Unit<69><74> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ֽʽÿ<CABD>.(arxml)?
|
||||
|
||||
AI
|
||||
<EFBFBD><EFBFBD><EFBFBD>ɶ<EFBFBD>
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
|
||||
<EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>Ʈ
|
||||
|
||||
AI.
|
||||
arxml<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>
|
||||
0.<2E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, Ȯ<><C8AE> <20>ؼ<EFBFBD> <20>ֱ<EFBFBD> ->
|
||||
1. <20><><EFBFBD>ͳ<EFBFBD> -> <20>ͽ<EFBFBD><CDBD>ͳ<EFBFBD>.
|
||||
2. <20><><EFBFBD>ɶ<EFBFBD> <20><><EFBFBD><EFBFBD> - not, all(O), cat2
|
||||
Not ->
|
||||
Cate2
|
||||
3. <20><><EFBFBD><EFBFBD>
|
||||
ȭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>8<EFBFBD><38>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Ƽ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>.
|
||||
|
||||
<EFBFBD><EFBFBD>ũ<EFBFBD><EFBFBD>Ʈ,
|
||||
<EFBFBD><EFBFBD>ī<EFBFBD>̺<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٽ<EFBFBD>.
|
||||
|
||||
*MISO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 104<30><34><EFBFBD><EFBFBD>ũ<EFBFBD>η<EFBFBD> HI<48><49> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.(<28><><EFBFBD><EFBFBD>) <20><><EFBFBD>̽<EFBFBD> <20>̻<EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,64 @@
|
||||
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Ʒ<EFBFBD><C6B7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ϸ<EFBFBD> <20>ǰ<EFBFBD><C7B0><EFBFBD>?
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>8 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> index1(0xFF, Normal Write-Back, Read/Write-Allocate)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>־<EFBFBD>, index6(0xAA, Normal Write-Through)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>10<EFBFBD><EFBFBD> TCM<43><4D> index4(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, 0x00<30><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>־<EFBFBD>, index6(0xAA, Normal Write-Through)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD>.
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>14&16&17<31><37><EFBFBD><EFBFBD> index4 (0xFF, Normal Write-Back, Read/Write-Allocate) <20><><EFBFBD><EFBFBD>
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>20<EFBFBD><EFBFBD> RT-VRAM1<4D><31> index1(0xFF, Normal Write-Back, Read/Write-Allocate)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>־<EFBFBD>, index6(0xAA, Normal Write-Through)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>12<EFBFBD><EFBFBD> Reserved<65><64> index4(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, 0x00<30><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>־<EFBFBD>, index7(0x00, Device-nGnRnE)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
|
||||
LDR r0, =0x00AA04FF
|
||||
MCR p15, 0, r0, c10, c2, 1 // MAIR1 <20><><EFBFBD><EFBFBD>
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>8 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =0xE200001B // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
MCR p15, 0, r0, c6, c12, 0
|
||||
LDR r0, =0xE209FFC3 // PRLAR8 - SRAM STACK end : 0xE209FFFF
|
||||
MCR p15, 0, r0, c6, c12, 1
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR? ? ?r0, =0xE200001B? // PRBAR8 - SRAM STACK start : 0xE2000000
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c12, 0
|
||||
? ? LDR? ? ?r0, =0xE209FFCD? // PRLAR8 - SRAM STACK end : 0xE209FFFF (Index 6 <20><><EFBFBD><EFBFBD>, 0xAA)
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c12, 1
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>10 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =0xE4000003 // PRBAR10
|
||||
MCR p15, 0, r0, c6, c13, 0
|
||||
LDR r0, =0xE62FFFC9 // PRLAR10
|
||||
MCR p15, 0, r0, c6, c13, 1
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR? ? ?r0, =0xE4000003? // PRBAR10
|
||||
? ?MCR? ? ?p15, 0, r0, c6, c13, 0
|
||||
? ?LDR? ? ?r0, =0xE62FFFCD? // PRLAR10 - TCM (Index 6 <20><><EFBFBD><EFBFBD>), 0xAA)
|
||||
? ?MCR? ? ?p15, 0, r0, c6, c13, 1
|
||||
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>12 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =0xE6400003 // PRBAR12
|
||||
MCR p15, 0, r0, c6, c14, 0
|
||||
LDR r0, =0xEB0FFFC9 // PRLAR12
|
||||
MCR p15, 0, r0, c6, c14, 1
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR? ? ?r0, =0xE6400003? // PRBAR12
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c14, 0
|
||||
? ? LDR? ? ?r0, =0xEB0FFFCF? // PRLAR12 - Reserved Peripheral end (Index 7 <20><><EFBFBD><EFBFBD>)
|
||||
? ? MCR? ? ?p15, 0, r0, c6, c14, 1
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>20 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR p15, 0, r0, c6, c2, 1 //PRSELR
|
||||
LDR r0, =0xE2100003 //PRBAR
|
||||
MCR p15, 0, r0, c6, c3, 0 //PRBAR
|
||||
LDR r0, =0xE3FFFFC3 //PRLAR
|
||||
MCR p15, 0, r0, c6, c3, 1 //PRLAR
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LDR r0, =20 //Select Region 20
|
||||
MCR? ? ?p15, 0, r0, c6, c2, 1? // PRSELR
|
||||
LDR? ? ?r0, =0xE2100003? ? ? ? // PRBAR (<28><><EFBFBD><EFBFBD> <20>ּ<EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
MCR? ? ?p15, 0, r0, c6, c3, 0? // PRBAR
|
||||
LDR? ? ?r0, =0xE3FFFFCD? ? ? ? // PRLAR (<28><><EFBFBD>ڸ<EFBFBD> C3 -> CD <20><><EFBFBD><EFBFBD>, Index 6 <20><><EFBFBD><EFBFBD>)
|
||||
MCR? ? ?p15, 0, r0, c6, c3, 1? // PRLAR
|
||||
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
A. Device Memory (<28>ֺ<EFBFBD><D6BA><EFBFBD>ġ <20><><EFBFBD>ٿ<EFBFBD> - ij<><C4B3> <20><><EFBFBD><EFBFBD> <20>Ұ<EFBFBD>)
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD> I/O<><4F> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ÿ<>̹<EFBFBD><CCB9><EFBFBD> <20><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϰ<EFBFBD> <20><>ų<EFBFBD><C5B3> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
0x00 (Device-nGnRnE): <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. <20><><EFBFBD>۸<EFBFBD> <20>Ұ<EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>. (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
0x04 (Device-nGnRE): <20>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD> <20>ֺ<EFBFBD><D6BA><EFBFBD>ġ<EFBFBD><C4A1>. (Early Acknowledgement <20><><EFBFBD><EFBFBD>)
|
||||
0x08 (Device-nGRE): <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ġ <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
|
||||
0x0C (Device-GRE): <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ġ <20><><EFBFBD><EFBFBD>)
|
||||
|
||||
B. Normal Memory (<28>Ϲ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>ڵ<EFBFBD><DAB5><EFBFBD> - ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
<EFBFBD><EFBFBD> <20>а<EFBFBD> <20><> <20><> ij<><C4B3>(Cache)<29><> <20><EFBFBD><EEB6BB> Ȱ<><C8B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, **ij<><C4B3> <20>̽<EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><EFBFBD><EEB6BB> <20>Ҵ<EFBFBD><D2B4><EFBFBD><EFBFBD><EFBFBD>(Allocate)**<2A><> <20><><EFBFBD><EFBFBD><EFBFBD>մϴ<D5B4>.
|
||||
ij<EFBFBD><EFBFBD> <20><>å: Non-Cacheable(<28>̻<EFBFBD><CCBB><EFBFBD>), Write-Through(<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>), Write-Back(ij<>ÿ<EFBFBD><C3BF><EFBFBD> <20><><EFBFBD><EFBFBD>)
|
||||
<EFBFBD>Ҵ<EFBFBD> <20><>å: Read-Allocate(<28><><EFBFBD><EFBFBD> <20><> ij<>÷<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>), Write-Allocate(<28><> <20><> ij<>÷<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
|
||||
|
||||
Index,Value,<2C>Ӽ<EFBFBD> (Memory Type),<2C><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (ij<><C4B3>/<2F>Ҵ<EFBFBD> <20><>å),<2C><><EFBFBD><EFBFBD> <20>뵵 (Example)
|
||||
1,0x04,Device-nGnRE,ij<><C4B3> X / <20><><EFBFBD><EFBFBD> O / <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>,"<22><><EFBFBD><EFBFBD> <20>ֺ<EFBFBD> <20><>ġ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (I2C, SPI, CAN <20><>)"
|
||||
2,0x44,Normal Non-Cacheable,ij<>ø<EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ġ<EFBFBD><C4A1> <20>ʰ<EFBFBD> <20><EFBFBD><DEB8><EFBFBD> <20><><EFBFBD><EFBFBD>,"DMA <20><><EFBFBD><EFBFBD>, <20><>Ƽ<EFBFBD>ھ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD> <20><EFBFBD><DEB8><EFBFBD> (IOC)"
|
||||
3,0xAA,Normal Write-Through,"RA, No-WA: <20><><EFBFBD><EFBFBD> <20><> ij<><C4B3> <20>Ҵ<EFBFBD>, <20><> <20><> ij<>ÿ<EFBFBD> <20><DEB8> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>","<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD>, TCM, <20>߿<EFBFBD> <20>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>)"
|
||||
4,0xEE,Normal Write-Back,"RA, No-WA: <20><><EFBFBD><EFBFBD> <20><> ij<><C4B3> <20>Ҵ<EFBFBD>, <20><> <20><> <20><DEB8> <20>ٷ<EFBFBD> <20><><EFBFBD><EFBFBD> (ij<><C4B3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)","<22><><EFBFBD>뷮 <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><>ȸ<EFBFBD><C8B8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ۼ<EFBFBD><DBBC><EFBFBD> <20><><EFBFBD><EFBFBD>"
|
||||
5,0xFF,Normal Write-Back,"RA, WA: <20>а<EFBFBD> <20><> <20><> <20><><EFBFBD><EFBFBD> ij<>ø<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȱ<><C8B0> (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)","<22>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD> <20>ڵ<EFBFBD> <20><><EFBFBD><EFBFBD>, <20>Ϲ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (Flash/DDR)"
|
||||
6,0x00,Device-nGnRnE,<2C><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>/ij<><C4B3> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>),"<22><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20>ſ<EFBFBD> <20>ΰ<EFBFBD><CEB0><EFBFBD> <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><>Ʈ<EFBFBD>ѷ<EFBFBD>"
|
||||
Binary file not shown.
@@ -0,0 +1,544 @@
|
||||
#*******************************************************************************
|
||||
# DISCLAIMER
|
||||
# This software is supplied by Renesas Electronics Corporation and is only
|
||||
# intended for use with Renesas products. No other uses are authorized. This
|
||||
# software is owned by Renesas Electronics Corporation and is protected under
|
||||
# all applicable laws, including copyright laws.
|
||||
# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
# Renesas reserves the right, without notice, to make changes to this software
|
||||
# and to discontinue the availability of this software. By using this software,
|
||||
# you agree to the additional terms and conditions found by accessing the
|
||||
# following link:
|
||||
# http://www.renesas.com/disclaimer
|
||||
# Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
#******************************************************************************/
|
||||
|
||||
|
||||
|
||||
# ******************************************************************************
|
||||
# * DESCRIPTION : makefile for Loader
|
||||
# ******************************************************************************
|
||||
# ******************************************************************************
|
||||
# * @file Makefile
|
||||
# * - Version : 0.14
|
||||
# * @brief
|
||||
# * .
|
||||
# ******************************************************************************
|
||||
# ******************************************************************************
|
||||
# * History : DD.MM.YYYY Version Description
|
||||
# * : 02.02.2022 0.01 First Release
|
||||
# * : 17.02.2022 0.02 Support AArch32
|
||||
# * : 23.03.2022 0.03 Removed unnecessary functions
|
||||
# * : 09.05.2022 0.04 Used the standard library
|
||||
# * Renamed the image
|
||||
# * Added make option "LSI"
|
||||
# * Removed make option "AArch"
|
||||
# * Changed to make common things common in LSI
|
||||
# * : 17.06.2022 0.05 Support secure boot for S4
|
||||
# * : 02.08.2022 0.06 Support WDT
|
||||
# * : 07.11.2022 0.07 Support DDR initialization/QOS initialization processing
|
||||
# * : 14.12.2022 0.08 Fixed make option "EMMC_TRANS_MODE"
|
||||
# * Support MMU
|
||||
# * : 15.12.2022 0.09 Support RegionID check
|
||||
# * Fixed "LSI" default settings
|
||||
# * : 04.04.2023 0.10 Fixed not used standerd library.
|
||||
# * : 21.08.2023 0.11 Add support for V4M.
|
||||
# * : 04.09.2023 0.12 Add C4 power domain setting.
|
||||
# * : 19.12.2024 0.13 Add build option "RTOS_LOAD_NUM"
|
||||
# * Add build option "ECM_ERROR_ENABLE"
|
||||
# * and "ECMERRTGTR_INTC".
|
||||
# * : 26.05.2025 0.14 Add build option "OPTEE_LOAD_ENABLE"
|
||||
# * : 02.09.2025 0.15 Add build option "ECC_DRAM_RANK" for ECC_ENABLE=1
|
||||
# ******************************************************************************
|
||||
|
||||
###################################################
|
||||
# makefile
|
||||
###################################################
|
||||
|
||||
define add_define
|
||||
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
|
||||
endef
|
||||
|
||||
INCLUDE_DIR = -Iinclude
|
||||
|
||||
OUTDIR := build
|
||||
|
||||
# LSI setting common define
|
||||
RCAR_S4:=0
|
||||
RCAR_V4H:=1
|
||||
RCAR_V4M:=2
|
||||
NORMAL:=0
|
||||
SECURE:=1
|
||||
HS400:=0
|
||||
HS200:=1
|
||||
HIGH_SPEED:=2
|
||||
NO_HIGH_SPEED:=3
|
||||
$(eval $(call add_define,RCAR_S4))
|
||||
$(eval $(call add_define,RCAR_V4H))
|
||||
$(eval $(call add_define,RCAR_V4M))
|
||||
$(eval $(call add_define,NORMAL))
|
||||
$(eval $(call add_define,SECURE))
|
||||
$(eval $(call add_define,HS400))
|
||||
$(eval $(call add_define,HS200))
|
||||
$(eval $(call add_define,HIGH_SPEED))
|
||||
$(eval $(call add_define,NO_HIGH_SPEED))
|
||||
|
||||
#/* Select LSI("S4" or "V4H" or "V4M")***********************
|
||||
ifeq ("$(LSI)", "")
|
||||
LSI = S4
|
||||
endif
|
||||
|
||||
ifeq (${LSI},S4)
|
||||
RCAR_LSI:=${RCAR_S4}
|
||||
#output file name
|
||||
FILE_NAME = ca55_loader
|
||||
else ifeq (${LSI},V4H)
|
||||
RCAR_LSI:=${RCAR_V4H}
|
||||
#output file name
|
||||
FILE_NAME = cr52_loader
|
||||
else ifeq (${LSI},V4M)
|
||||
RCAR_LSI:=${RCAR_V4M}
|
||||
#output file name
|
||||
FILE_NAME = cr52_loader
|
||||
else
|
||||
$(error "Error: ${LSI} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LSI))
|
||||
|
||||
ifndef BOOT_MODE
|
||||
BOOT_MODE:=${NORMAL}
|
||||
else
|
||||
ifeq (${BOOT_MODE},NORMAL)
|
||||
BOOT_MODE:=${NORMAL}
|
||||
else ifeq (${BOOT_MODE},SECURE)
|
||||
BOOT_MODE:=${SECURE}
|
||||
ifeq (${LSI},S4)
|
||||
$(eval $(call add_define,TARGET_CORTEX_A))
|
||||
$(eval $(call add_define,TARGET_DEVICE_S4X))
|
||||
$(eval $(call add_define,AARCH64))
|
||||
else ifeq (${LSI},V4H)
|
||||
$(eval $(call add_define,TARGET_DEVICE_V4H))
|
||||
else ifeq (${LSI},V4M)
|
||||
$(eval $(call add_define,TARGET_DEVICE_V4M))
|
||||
endif
|
||||
else
|
||||
$(error "Error: ${BOOT_MODE} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,BOOT_MODE))
|
||||
endif
|
||||
|
||||
ifndef EMMC_TRANS_MODE
|
||||
EMMC_TRANS_MODE:=${HS400}
|
||||
else
|
||||
ifeq (${EMMC_TRANS_MODE},HS400)
|
||||
EMMC_TRANS_MODE:=${HS400}
|
||||
else ifeq (${EMMC_TRANS_MODE},HS200)
|
||||
EMMC_TRANS_MODE:=${HS200}
|
||||
else ifeq (${EMMC_TRANS_MODE},HIGH_SPEED)
|
||||
EMMC_TRANS_MODE:=${HIGH_SPEED}
|
||||
else ifeq (${EMMC_TRANS_MODE},NO_HIGH_SPEED)
|
||||
EMMC_TRANS_MODE:=${NO_HIGH_SPEED}
|
||||
else
|
||||
$(error "Error: ${EMMC_TRANS_MODE} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,EMMC_TRANS_MODE))
|
||||
endif
|
||||
|
||||
# Process RCAR_DRAM_SPLIT flag (V4H only)
|
||||
ifeq (${LSI},V4H)
|
||||
ifndef RCAR_DRAM_SPLIT
|
||||
RCAR_DRAM_SPLIT := 1
|
||||
$(eval $(call add_define,RCAR_DRAM_SPLIT))
|
||||
else
|
||||
ifeq (${RCAR_DRAM_SPLIT},0)
|
||||
$(eval $(call add_define,RCAR_DRAM_SPLIT))
|
||||
else ifeq (${RCAR_DRAM_SPLIT},1)
|
||||
$(eval $(call add_define,RCAR_DRAM_SPLIT))
|
||||
else
|
||||
$(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.")
|
||||
endif
|
||||
endif
|
||||
else ifeq (${LSI},V4M)
|
||||
ifndef RCAR_DRAM_SPLIT
|
||||
RCAR_DRAM_SPLIT := 0
|
||||
$(eval $(call add_define,RCAR_DRAM_SPLIT))
|
||||
else
|
||||
ifneq (${RCAR_DRAM_SPLIT},0)
|
||||
$(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process RCAR_PERIODIC_WRITE_TRAINING flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef RCAR_PERIODIC_WRITE_TRAINING
|
||||
RCAR_PERIODIC_WRITE_TRAINING := 1
|
||||
$(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
|
||||
else
|
||||
ifeq (${RCAR_PERIODIC_WRITE_TRAINING},0)
|
||||
$(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
|
||||
else ifeq (${RCAR_PERIODIC_WRITE_TRAINING},1)
|
||||
$(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING))
|
||||
else
|
||||
$(error "Error:RCAR_PERIODIC_WRITE_TRAINING=${RCAR_PERIODIC_WRITE_TRAINING} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process RCAR_PERIODIC_READ_TRAINING flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef RCAR_PERIODIC_READ_TRAINING
|
||||
RCAR_PERIODIC_READ_TRAINING := 1
|
||||
$(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
|
||||
else
|
||||
ifeq (${RCAR_PERIODIC_READ_TRAINING},0)
|
||||
$(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
|
||||
else ifeq (${RCAR_PERIODIC_READ_TRAINING},1)
|
||||
$(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING))
|
||||
else
|
||||
$(error "Error:RCAR_PERIODIC_READ_TRAINING=${RCAR_PERIODIC_READ_TRAINING} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process DBSC_REFINTS flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef DBSC_REFINTS
|
||||
DBSC_REFINTS := 0
|
||||
$(eval $(call add_define,DBSC_REFINTS))
|
||||
else
|
||||
ifeq (${DBSC_REFINTS},0)
|
||||
$(eval $(call add_define,DBSC_REFINTS))
|
||||
else ifeq (${DBSC_REFINTS},1)
|
||||
$(eval $(call add_define,DBSC_REFINTS))
|
||||
else
|
||||
$(error "Error:DBSC_REFINTS=${DBSC_REFINTS} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process RTVRAM_EXTEND flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef RTVRAM_EXTEND
|
||||
RTVRAM_EXTEND := 1
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else
|
||||
ifeq (${RTVRAM_EXTEND},0)
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else ifeq (${RTVRAM_EXTEND},1)
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else
|
||||
$(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process RTOS_LOAD_NUM flag
|
||||
# 1:RTOS#0 only 3:RTOS#0,#1,#2
|
||||
ifndef RTOS_LOAD_NUM
|
||||
RTOS_LOAD_NUM := 1
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else
|
||||
ifeq (${RTOS_LOAD_NUM},1)
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else ifeq (${RTOS_LOAD_NUM},3)
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else
|
||||
$(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process OPTEE_LOAD_ENABLE flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef OPTEE_LOAD_ENABLE
|
||||
OPTEE_LOAD_ENABLE := 1
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else
|
||||
ifeq (${OPTEE_LOAD_ENABLE},0)
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else ifeq (${OPTEE_LOAD_ENABLE},1)
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else
|
||||
$(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
OUTPUT_FILE = $(FILE_NAME).elf
|
||||
|
||||
#object file name
|
||||
OBJ_FILE = common/string.o \
|
||||
common/log/log.o \
|
||||
common/log/scif.o \
|
||||
common/timer/generic_timer.o \
|
||||
image_load/image_load.o \
|
||||
ip/ip_control.o \
|
||||
ip/emmc/emmc_boot.o \
|
||||
ip/emmc/emmc_cmd.o \
|
||||
ip/emmc/emmc_init.o \
|
||||
ip/emmc/emmc_interrupt.o \
|
||||
ip/emmc/emmc_mount.o \
|
||||
ip/emmc/emmc_multiboot.o \
|
||||
ip/emmc/emmc_read.o \
|
||||
ip/emmc/emmc_utility.o \
|
||||
loader/stack.o \
|
||||
loader/loader_main.o \
|
||||
ip/interrupt.o
|
||||
|
||||
ifeq (${BOOT_MODE},SECURE)
|
||||
OBJ_FILE += secure/secure_boot.o \
|
||||
secure/src/comm_drv/icum_d_comm_pe.o \
|
||||
secure/src/icumif_lib/r_icumif.o \
|
||||
secure/shared/src/mem_info_def.o \
|
||||
secure/user_api/user_icumif_api.o
|
||||
|
||||
INCLUDE_DIR += -Isecure/src/comm_drv -Isecure/src/icumif_lib -Isecure/icumif -Isecure/include -Isecure/user_api -Isecure/shared/src
|
||||
|
||||
endif
|
||||
|
||||
ifeq (${LSI},S4)
|
||||
OBJ_FILE += \
|
||||
loader/loader_s4.o \
|
||||
ip/swdt/swdt.o \
|
||||
loader/loader_mmu_table.o \
|
||||
loader/loader_exceptions.o
|
||||
#linker script name
|
||||
MEMORY_DEF = loader/loader_s4.ld
|
||||
else ifeq (${LSI},V4H)
|
||||
OBJ_FILE += \
|
||||
cpu_on/cpu_on.o \
|
||||
ip/qos/qos.o \
|
||||
cnf_tbl/cnf_tbl_v4h.o \
|
||||
ip/rtvram/rtvram.o \
|
||||
loader/loader_v4h.o \
|
||||
loader/loader_main_common.o \
|
||||
protect/region_id/region_id.o \
|
||||
cnf_tbl/rgidcnf_tbl_v4h.o \
|
||||
ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \
|
||||
ip/ddr/v4h/lpddr5/ecm_enable_v4h.o
|
||||
#linker script name
|
||||
MEMORY_DEF = loader/loader_v4h.ld
|
||||
|
||||
INCLUDE_DIR += -Iip/ddr
|
||||
else ifeq (${LSI},V4M)
|
||||
OBJ_FILE += \
|
||||
cpu_on/cpu_on.o \
|
||||
ip/qos/qos.o \
|
||||
cnf_tbl/cnf_tbl_v4m.o \
|
||||
ip/rtvram/rtvram.o \
|
||||
loader/loader_v4m.o \
|
||||
loader/loader_main_common.o \
|
||||
protect/region_id/region_id.o \
|
||||
cnf_tbl/rgidcnf_tbl_v4m.o \
|
||||
ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \
|
||||
ip/ddr/v4m/lpddr5/ecm_enable_v4m.o
|
||||
#linker script name
|
||||
MEMORY_DEF = loader/loader_v4m.ld
|
||||
|
||||
INCLUDE_DIR += -Iip/ddr
|
||||
|
||||
endif
|
||||
|
||||
###################################################
|
||||
# Process access protection flag
|
||||
# 0:Disable 1:Enable
|
||||
ifndef ACC_PROT_ENABLE
|
||||
ACC_PROT_ENABLE := 0
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else
|
||||
ifeq (${ACC_PROT_ENABLE},0)
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else ifeq (${ACC_PROT_ENABLE},1)
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else
|
||||
$(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Debug build
|
||||
DEBUG:=0
|
||||
|
||||
# Process DEBUG flag
|
||||
$(eval $(call assert_boolean,DEBUG))
|
||||
$(eval $(call add_define,DEBUG))
|
||||
ifeq (${DEBUG},0)
|
||||
$(eval $(call add_define,NDEBUG))
|
||||
else
|
||||
CFLAGS += -g
|
||||
ASFLAGS += -g -Wa,--gdwarf-2
|
||||
endif
|
||||
|
||||
# Process LOG_LEVEL
|
||||
ifndef LOG_LEVEL
|
||||
LOG_LEVEL := 2
|
||||
endif
|
||||
$(eval $(call add_define,LOG_LEVEL))
|
||||
|
||||
# Process ECC_ENABLE
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef ECC_ENABLE
|
||||
ECC_ENABLE:= 0
|
||||
$(eval $(call add_define,ECC_ENABLE))
|
||||
else
|
||||
ifeq (${ECC_ENABLE},0)
|
||||
$(eval $(call add_define,ECC_ENABLE))
|
||||
else ifeq (${ECC_ENABLE},1)
|
||||
$(eval $(call add_define,ECC_ENABLE))
|
||||
else
|
||||
$(error "Error: ECC_ENABLE=${ECC_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process ECM_ERROR_ENABLE flag
|
||||
ifndef ECM_ERROR_ENABLE
|
||||
ECM_ERROR_ENABLE := 1
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else
|
||||
ifeq (${ECM_ERROR_ENABLE},0)
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else ifeq (${ECM_ERROR_ENABLE},1)
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else
|
||||
$(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process ECC_DRAM_RANK flag
|
||||
# 1:1RANK 2:2RANK
|
||||
ifndef ECC_DRAM_RANK
|
||||
ECC_DRAM_RANK := 1
|
||||
$(eval $(call add_define,ECC_DRAM_RANK))
|
||||
else
|
||||
ifeq (${ECC_DRAM_RANK},1)
|
||||
$(eval $(call add_define,ECC_DRAM_RANK))
|
||||
else ifeq (${ECC_DRAM_RANK},2)
|
||||
$(eval $(call add_define,ECC_DRAM_RANK))
|
||||
else
|
||||
$(error "Error:ECC_DRAM_RANK=${ECC_DRAM_RANK} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process ECMERRTGTR_INTC flag
|
||||
ifndef ECMERRTGTR_INTC
|
||||
ECMERRTGTR_INTC := 1
|
||||
$(eval $(call add_define,ECMERRTGTR_INTC))
|
||||
else
|
||||
ifeq (${ECMERRTGTR_INTC},0)
|
||||
$(eval $(call add_define,ECMERRTGTR_INTC))
|
||||
else ifeq (${ECMERRTGTR_INTC},1)
|
||||
$(eval $(call add_define,ECMERRTGTR_INTC))
|
||||
else
|
||||
$(error "Error:ECMERRTGTR_INTC=${ECMERRTGTR_INTC} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
include ip/ddr/ddr.mk
|
||||
endif
|
||||
|
||||
# Process DBSC HUNGUP WA
|
||||
ifndef WA_OTLINT5579
|
||||
WA_OTLINT5579:= 1
|
||||
endif
|
||||
$(eval $(call add_define,WA_OTLINT5579))
|
||||
|
||||
# Private Option for QoS and DBSC
|
||||
RCAR_PERIODIC_TRAINING_SEPARATE_MODE:= 0
|
||||
$(eval $(call add_define,RCAR_PERIODIC_TRAINING_SEPARATE_MODE))
|
||||
|
||||
###################################################
|
||||
|
||||
OUTDIR_REL := $(OUTDIR)/release
|
||||
OUTDIR_OBJ := $(OUTDIR)/obj
|
||||
|
||||
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
CPP = ${CROSS_COMPILE}cpp
|
||||
AS = ${CROSS_COMPILE}gcc
|
||||
AR = ${CROSS_COMPILE}ar
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
OC = ${CROSS_COMPILE}objcopy
|
||||
OD = ${CROSS_COMPILE}objdump
|
||||
|
||||
ifeq (${LSI},S4)
|
||||
ASFLAGS += -march=armv8.2-a
|
||||
CFLAGS += -march=armv8.2-a \
|
||||
-O0
|
||||
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ASFLAGS += -march=armv8-r
|
||||
CFLAGS += -march=armv8-r \
|
||||
-O2
|
||||
endif
|
||||
|
||||
ASFLAGS += -ffreestanding -Wa,--fatal-warnings \
|
||||
-Wmissing-include-dirs \
|
||||
-c -D__ASSEMBLY \
|
||||
$(INCLUDE_DIR) $(DEFINES)
|
||||
|
||||
CFLAGS += -ffreestanding -Wall \
|
||||
-Wmissing-include-dirs \
|
||||
-std=c99 -c \
|
||||
$(INCLUDE_DIR) $(DEFINES)
|
||||
|
||||
LDFLAGS = --fatal-warnings -O1 -nostdlib
|
||||
|
||||
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
|
||||
|
||||
LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc
|
||||
LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc
|
||||
|
||||
###################################################
|
||||
.SUFFIXES : .s .c .o
|
||||
|
||||
###################################################
|
||||
# command
|
||||
|
||||
.PHONY: all
|
||||
all: $(OUTPUT_FILE)
|
||||
|
||||
###################################################
|
||||
# Linker
|
||||
###################################################
|
||||
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
|
||||
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \
|
||||
$(CC) $(CFLAGS) -xc - -o $(OUTDIR_OBJ)/build_message.o
|
||||
|
||||
-mkdir "$(OUTDIR_REL)"
|
||||
|
||||
$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
|
||||
-T $(MEMORY_DEF) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
|
||||
$(LDFLAGS) \
|
||||
-Map $(OUTDIR_REL)/$(FILE_NAME).map \
|
||||
$(LIBS)
|
||||
|
||||
$(OC) -O srec --srec-forceS3 $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).srec
|
||||
$(OC) -O binary $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).bin
|
||||
$(OD) -dx $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
|
||||
|
||||
###################################################
|
||||
# Compile
|
||||
###################################################
|
||||
|
||||
$(OUTDIR_OBJ)/%.o:%.c
|
||||
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
|
||||
@$(CC) $(CFLAGS) -o $@ -c $<
|
||||
|
||||
$(OUTDIR_OBJ)/%.o:%.S
|
||||
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
|
||||
@$(AS) $(ASFLAGS) -o $@ -c $<
|
||||
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -rf $(OUTDIR)
|
||||
@@ -0,0 +1 @@
|
||||
-dx build/release/ca55_loader.elf
|
||||
Binary file not shown.
@@ -0,0 +1,323 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file cnf_tbl.c
|
||||
* - Version : 0.04
|
||||
* @brief Configuration table for V4H.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 28.07.2021 0.01 First Release
|
||||
* : 23.05.2022 0.02 Integration of S4 and V4H
|
||||
* Renamed from conf_tbl.c to cnf_tbl_v4h.c.
|
||||
* : 22.05.2023 0.03 Update the qos config table for response to past
|
||||
* follow back.
|
||||
* : 08.06.2023 0.04 Update the qos config table for ISP and VSPX.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <cpg_register.h>
|
||||
#endif
|
||||
#include <cnf_tbl.h>
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=".qosbw_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qoswt_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qosbw_tbl[] = {
|
||||
[0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL},
|
||||
[11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[22] = {0x000C04100000FFFFULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[24] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[28] = {0x000C04100000FFFFULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[31] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[42] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL},
|
||||
[43] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL},
|
||||
[44] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[45] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[46] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[47] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[54] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[56] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[58] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[60] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[61] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[78] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[79] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL},
|
||||
[86] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[87] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[88] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[89] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[90] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[95] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[99] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[104] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[105] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[106] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[107] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[108] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[109] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[110] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[111] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[112] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[113] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[115] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[117] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL}
|
||||
};
|
||||
|
||||
|
||||
/* Now go back to default rules */
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=default
|
||||
|
||||
#pragma ghs section rodata=".qoswt_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qosbw_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qoswt_tbl[] = {
|
||||
[0] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[1] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[2] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[3] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[4] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[5] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[6] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[7] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[8] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[9] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[10] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[11] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[12] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[13] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[14] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[15] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[16] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[17] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[18] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[19] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[20] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[21] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[22] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL},
|
||||
[24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL},
|
||||
[25] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[27] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[28] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04050000C001ULL, 0x0000000000000000ULL},
|
||||
[30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL},
|
||||
[31] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[32] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[33] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[34] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[35] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[36] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[37] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[38] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[39] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[40] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[41] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[42] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[43] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[44] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[45] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[46] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[47] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[48] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[49] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[50] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[51] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[52] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[53] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[54] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[55] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[56] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[57] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[58] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[59] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[60] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[61] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[62] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[63] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[64] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[65] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[66] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[67] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[68] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[69] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[70] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[71] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[72] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[73] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[74] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[75] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[76] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[77] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[78] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[79] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[80] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[81] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x0000000000000000ULL},
|
||||
[83] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[84] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[85] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[86] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[87] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[88] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[89] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[90] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[91] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[92] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[93] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[94] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[95] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[96] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[97] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[98] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[99] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[100] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[101] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[102] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[103] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[104] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[105] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[106] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[107] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[108] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[109] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[110] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[111] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[112] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[113] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[114] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[115] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[116] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[117] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[118] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[119] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[120] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[121] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[122] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[123] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[124] = {0x0000000000000000ULL, 0x0000000000000000ULL}
|
||||
};
|
||||
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
/* Now go back to default rules */
|
||||
#pragma ghs section rodata=default
|
||||
#endif
|
||||
@@ -0,0 +1,318 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file cnf_tbl_v4m.c
|
||||
* - Version : 0.01
|
||||
* @brief Configuration table for V4M.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.08.2023 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <cpg_register.h>
|
||||
#endif
|
||||
#include <cnf_tbl.h>
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=".qosbw_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qoswt_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qosbw_tbl[] = {
|
||||
[0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[2] = {0x001430170000FFFFULL, 0x00100030004FFC01ULL}, /*CR52 Core0 W*/
|
||||
[3] = {0x001430170000FFFFULL, 0x00200030004FFC01ULL}, /*CR52 Core1 W*/
|
||||
[4] = {0x001430170000FFFFULL, 0x00100030004FFC01ULL}, /*CR52 Core2 W*/
|
||||
[5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[7] = {0x001430170000FFFFULL, 0x00100030004FFC01ULL}, /*CR52 Core0 R*/
|
||||
[8] = {0x001430170000FFFFULL, 0x00100030004FFC01ULL}, /*CR52 Core1 R*/
|
||||
[9] = {0x001430170000FFFFULL, 0x00200030004FFC01ULL}, /*CR52 Core2 R*/
|
||||
[10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL},
|
||||
[11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[22] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[24] = {0x0000000000000000ULL, 0x00100030004FFC01ULL},
|
||||
[25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[28] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[31] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[42] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[43] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[44] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[45] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[46] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[47] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[54] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[56] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[58] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[60] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[61] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[78] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[79] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL},
|
||||
[86] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[87] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[88] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[89] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[90] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[95] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[99] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[104] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[105] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[106] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[107] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[108] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[109] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[110] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[111] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[112] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[113] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[115] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[117] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL}
|
||||
};
|
||||
|
||||
|
||||
/* Now go back to default rules */
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=default
|
||||
|
||||
#pragma ghs section rodata=".qoswt_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qosbw_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qoswt_tbl[] = {
|
||||
[0] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[1] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[2] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[3] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[4] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[5] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[6] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[7] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[8] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[9] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[10] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[11] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[12] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[13] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[14] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[15] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[16] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[17] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[18] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[19] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[20] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[21] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[22] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL},
|
||||
[24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL},
|
||||
[25] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[27] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[28] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04050000C001ULL, 0x0000000000000000ULL},
|
||||
[30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL},
|
||||
[31] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[32] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[33] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[34] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[35] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[36] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[37] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[38] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[39] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[40] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[41] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[42] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[43] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[44] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[45] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[46] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[47] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[48] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[49] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[50] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[51] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[52] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[53] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[54] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[55] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[56] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[57] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[58] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[59] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[60] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[61] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[62] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[63] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[64] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[65] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[66] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[67] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[68] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[69] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[70] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[71] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[72] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[73] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[74] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[75] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[76] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[77] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[78] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[79] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[80] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[81] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x0000000000000000ULL},
|
||||
[83] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[84] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[85] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[86] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[87] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[88] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[89] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[90] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[91] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[92] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[93] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[94] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[95] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[96] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[97] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[98] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[99] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[100] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[101] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[102] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[103] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[104] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[105] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[106] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[107] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[108] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[109] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[110] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[111] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[112] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[113] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[114] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[115] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[116] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[117] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[118] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[119] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[120] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[121] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[122] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[123] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[124] = {0x0000000000000000ULL, 0x0000000000000000ULL}
|
||||
};
|
||||
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
/* Now go back to default rules */
|
||||
#pragma ghs section rodata=default
|
||||
#endif
|
||||
@@ -0,0 +1,318 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file cnf_tbl_v4m.c
|
||||
* - Version : 0.01
|
||||
* @brief Configuration table for V4M.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.08.2023 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <cpg_register.h>
|
||||
#endif
|
||||
#include <cnf_tbl.h>
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=".qosbw_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qoswt_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qosbw_tbl[] = {
|
||||
[0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL},
|
||||
[11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL},
|
||||
[16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[22] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[24] = {0x0000000000000000ULL, 0x00100030004FFC01ULL},
|
||||
[25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[28] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[31] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[42] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[43] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[44] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[45] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[46] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[47] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[54] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[56] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[58] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[60] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[61] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[78] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[79] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL},
|
||||
[85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL},
|
||||
[86] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[87] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[88] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[89] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[90] = {0x001004080000FFFFULL, 0x0000000000000000ULL},
|
||||
[91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL},
|
||||
[93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[95] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[99] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[104] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[105] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[106] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[107] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[108] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[109] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[110] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[111] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[112] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[113] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[115] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[117] = {0x000000000000FFFFULL, 0x0000000000000000ULL},
|
||||
[118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL},
|
||||
[122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL},
|
||||
[124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL}
|
||||
};
|
||||
|
||||
|
||||
/* Now go back to default rules */
|
||||
#if defined(__RH850G3K__)
|
||||
#pragma ghs section rodata=default
|
||||
|
||||
#pragma ghs section rodata=".qoswt_tbl"
|
||||
#else
|
||||
__attribute__ ((section(".qosbw_tbl")))
|
||||
#endif
|
||||
const QOS_SETTING_TABLE g_qoswt_tbl[] = {
|
||||
[0] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[1] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[2] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[3] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[4] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[5] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[6] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[7] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[8] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[9] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[10] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[11] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[12] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[13] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[14] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[15] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[16] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[17] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[18] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[19] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[20] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[21] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[22] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL},
|
||||
[24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL},
|
||||
[25] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[26] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[27] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[28] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[29] = {0x000C04050000C001ULL, 0x0000000000000000ULL},
|
||||
[30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL},
|
||||
[31] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[32] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[33] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[34] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[35] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[36] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[37] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[38] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[39] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[40] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[41] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[42] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[43] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[44] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[45] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[46] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[47] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[48] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[49] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[50] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[51] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[52] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[53] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[54] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[55] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[56] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[57] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[58] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[59] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[60] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[61] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[62] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[63] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[64] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[65] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[66] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[67] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[68] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[69] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[70] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[71] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[72] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[73] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[74] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[75] = {0x001424870000C001ULL, 0x0000000000000000ULL},
|
||||
[76] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[77] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[78] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[79] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[80] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[81] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[82] = {0x001424870000FFFFULL, 0x0000000000000000ULL},
|
||||
[83] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[84] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[85] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[86] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[87] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[88] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[89] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[90] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[91] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[92] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[93] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[94] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[95] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[96] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[97] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[98] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[99] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[100] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[101] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[102] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[103] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[104] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[105] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[106] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[107] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[108] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[109] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[110] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[111] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[112] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[113] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[114] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[115] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[116] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[117] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[118] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[119] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[120] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[121] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[122] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[123] = {0x0000000000000000ULL, 0x0000000000000000ULL},
|
||||
[124] = {0x0000000000000000ULL, 0x0000000000000000ULL}
|
||||
};
|
||||
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
/* Now go back to default rules */
|
||||
#pragma ghs section rodata=default
|
||||
#endif
|
||||
@@ -0,0 +1,226 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file rgidcnf_tbl_v4h.c
|
||||
* - Version : 0.09
|
||||
* @brief Configuration table for V4H.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 16.12.2022 0.01 First Release
|
||||
* : 23.01.2023 0.02 Added RAM protection table.
|
||||
* Update Region ID settings.
|
||||
* : 07.02.2024 0.03 Update System RAM protection setting Area0.
|
||||
* : 30.08.2024 0.04 Updated Region ID and RAM protection setting
|
||||
* for QNX.
|
||||
* : 05.12.2024 0.05 Update RAM protection settings for ICCOM
|
||||
* memory area (SDRAM Area5).
|
||||
* Update Region ID settings for VSPD and VSPX.
|
||||
* Update Region ID settings for IPMMU.
|
||||
* Update RAM protection setting.
|
||||
* : 16.12.2024 0.06 Updated Region ID setting.
|
||||
* Updated Region ID setting and RAM protection
|
||||
* setting for booting CR52 3 cores.
|
||||
* Added IMP Region ID table.
|
||||
* Added IPMMU Region ID table.
|
||||
* : 26.05.2025 0.07 Updated RAM protection settings for
|
||||
* protection area.
|
||||
* : 28.07.2025 0.08 Updated Region ID setting.
|
||||
* : 03.09.2025 0.09 Removed Region ID setting table.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <cpg_register.h>
|
||||
#endif
|
||||
#include <cnf_tbl.h>
|
||||
#include <image_load.h>
|
||||
#include "ram_protection.h"
|
||||
|
||||
/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */
|
||||
const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* address READ Write */
|
||||
[RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */
|
||||
/* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */
|
||||
[RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */
|
||||
[2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */
|
||||
const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* address READ Write */
|
||||
[RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */
|
||||
/* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */
|
||||
[RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */
|
||||
[RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */
|
||||
[3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */
|
||||
const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* access Secure */
|
||||
/* address R | W R|W */
|
||||
[SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */
|
||||
/*
|
||||
* Change the access permission from 0xFFCCFFCC to 0xFFCCFFCD
|
||||
* if user want to enable protection of System Ram Area0.
|
||||
*/
|
||||
/* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */
|
||||
[SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */
|
||||
[2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */
|
||||
[3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */
|
||||
const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = {
|
||||
/* access secure */
|
||||
/* address R | W R|W */
|
||||
[RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */
|
||||
/* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */
|
||||
[CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */
|
||||
/* This secure setting is added by sdram_protection() in loader_main function. */
|
||||
[SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF
|
||||
* Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF
|
||||
* R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
[SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */
|
||||
[SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */
|
||||
[CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */
|
||||
[CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */
|
||||
[CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */
|
||||
[RESERVERD_AREA] = {DRAM_ADDR_AREA12,{0xFFFFFFFFU, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF */
|
||||
[CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFF9FFF9U, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */
|
||||
[14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
#else
|
||||
[SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */
|
||||
[SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */
|
||||
[SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */
|
||||
[SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */
|
||||
[CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */
|
||||
[CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */
|
||||
[CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */
|
||||
[RESERVERD_AREA] = {DRAM_ADDR_AREA15,{0xFFFFFFFFU, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF */
|
||||
[CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA16,{0xFFF9FFF9U, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */
|
||||
#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
[17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
@@ -0,0 +1,230 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file rgidcnf_tbl_v4m.c
|
||||
* - Version : 0.11
|
||||
* @brief Configuration table for V4M.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.08.2023 0.01 First Release
|
||||
* : 15.09.2023 0.02 Update setting table according to
|
||||
* HWUM Rev.0.50.
|
||||
* : 10.10.2023 0.03 Removed unimplemented registers.
|
||||
* : 23.01.2024 0.04 Added RAM protection table.
|
||||
* Update Region ID settings.
|
||||
* : 07.02.2024 0.05 Update System RAM protection setting Area0.
|
||||
* : 11.10.2024 0.06 Updated Region ID and RAM protection setting
|
||||
* for QNX.
|
||||
* : 05.12.2024 0.07 Update RAM protection settings for ICCOM
|
||||
* memory area (SDRAM Area5).
|
||||
* Update Region ID settings for VSPD and VSPX.
|
||||
* Update Region ID settings for IPMMU.
|
||||
* Update RAM protection setting.
|
||||
* : 16.12.2024 0.08 Updated Region ID setting.
|
||||
* Updated Region ID setting and RAM protection
|
||||
* setting for booting CR52 3 cores.
|
||||
* Update Region ID settings for ISP ch1.
|
||||
* Update Region ID settings for PCI1.
|
||||
* Added IPMMU Region ID table.
|
||||
* : 26.05.2025 0.09 Updated RAM protection settings for
|
||||
* protection area.
|
||||
* : 28.07.2025 0.10 Updated Region ID setting.
|
||||
* : 03.09.2025 0.11 Removed Region ID setting table.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <cpg_register.h>
|
||||
#endif
|
||||
#include <cnf_tbl.h>
|
||||
#include <image_load.h>
|
||||
#include "ram_protection.h"
|
||||
|
||||
/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */
|
||||
const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* address READ Write */
|
||||
[RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */
|
||||
/* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */
|
||||
[RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */
|
||||
[2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */
|
||||
const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* address READ Write */
|
||||
[RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */
|
||||
/* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */
|
||||
[RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */
|
||||
[RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */
|
||||
[3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */
|
||||
const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = {
|
||||
/* access Secure */
|
||||
/* address R | W R|W */
|
||||
[SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */
|
||||
/*
|
||||
* Change the access permission from 0xFFD8FFD8 to 0xFFD8FFD9
|
||||
* if user want to enable protection of System Ram Area0.
|
||||
*/
|
||||
/* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */
|
||||
[SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */
|
||||
[2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */
|
||||
[3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */
|
||||
const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = {
|
||||
/* access secure */
|
||||
/* address R | W R|W */
|
||||
[RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */
|
||||
/* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */
|
||||
[CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */
|
||||
/* This secure setting is added by sdram_protection() in loader_main function. */
|
||||
[SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF
|
||||
* Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF
|
||||
* R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
[SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */
|
||||
[SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */
|
||||
[CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */
|
||||
[CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */
|
||||
[CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */
|
||||
[CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA12,{0xFFF9FFF9U, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */
|
||||
[RESERVERD_AREA] = {DRAM_ADDR_AREA13,{0xFFFFFFFFU, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF */
|
||||
[14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
#else
|
||||
[SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */
|
||||
[SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */
|
||||
[SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */
|
||||
[SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */
|
||||
[ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */
|
||||
[CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */
|
||||
[CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */
|
||||
[CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */
|
||||
[CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */
|
||||
[CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA15,{0xFFF9FFF9U, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */
|
||||
[RESERVERD_AREA] = {DRAM_ADDR_AREA16,{0xFFFFFFFFU, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF */
|
||||
#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
[17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
[63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}},
|
||||
};
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : log
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file log.c
|
||||
* - Version : 0.04
|
||||
* @brief Access protection setting driver.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 03.07.2020 0.01 First Release
|
||||
* : 16.06.2022 0.02 Change log output
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 04.04.2023 0.04 Removed sprintf.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "stdarg.h"
|
||||
#include "stdint.h"
|
||||
#include "log.h"
|
||||
#include "scif.h"
|
||||
|
||||
#define NULL_CHAR '\0'
|
||||
|
||||
/***********************************************************
|
||||
* log_printf
|
||||
***********************************************************/
|
||||
|
||||
static uint32_t uint32_print(uint32_t num)
|
||||
{
|
||||
uint8_t num_buf[10];
|
||||
uint32_t count = 0U;
|
||||
uint32_t i = 0U;
|
||||
uint32_t rem;
|
||||
uint32_t unum = num;
|
||||
|
||||
while (1) {
|
||||
rem = unum % 10U;
|
||||
num_buf[i] = (uint8_t)('0' + rem);
|
||||
|
||||
i++;
|
||||
unum = unum / 10U;
|
||||
if (unum < 1U) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (i != 0U) {
|
||||
i--;
|
||||
(void)console_putc(num_buf[i]);
|
||||
count++;
|
||||
};
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t int32_print(int32_t num)
|
||||
{
|
||||
uint32_t unum;
|
||||
uint32_t count = 0U;
|
||||
|
||||
if (num < 0) {
|
||||
(void)console_putc((uint8_t)'-');
|
||||
count = 1U;
|
||||
unum = (uint32_t)-num;
|
||||
} else {
|
||||
unum = (uint32_t)num;
|
||||
}
|
||||
|
||||
count += uint32_print(unum);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t uint32_hex_print(uint32_t num)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t count = 0U;
|
||||
uint8_t c;
|
||||
|
||||
for (i = 0U; i < 8U; i++) {
|
||||
/* 0-F */
|
||||
c = (uint8_t)((num >> ((7U - i) * 4U)) & 0x0FU);
|
||||
if (c >= 0x0AU) {
|
||||
/* A-F */
|
||||
c += (uint8_t)('a' - 0x0AU);
|
||||
} else {
|
||||
/* 0-9 */
|
||||
c += (uint8_t)'0';
|
||||
}
|
||||
(void)console_putc(c);
|
||||
count++;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t str_print(const char *str)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
|
||||
while (*str != NULL_CHAR) {
|
||||
(void)console_putc((uint8_t)*str);
|
||||
str++;
|
||||
count++;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
void log_printf(const char *fmt, ...)
|
||||
{
|
||||
va_list args;
|
||||
int32_t num;
|
||||
uint32_t unum;
|
||||
char *str;
|
||||
uint32_t count = 0U;
|
||||
|
||||
va_start(args, fmt);
|
||||
while (*fmt != NULL_CHAR) {
|
||||
if (*fmt == '%') {
|
||||
fmt++;
|
||||
switch (*fmt) {
|
||||
case 'i':
|
||||
/* No break */
|
||||
case 'd':
|
||||
num = va_arg(args, int32_t);
|
||||
count += int32_print(num);
|
||||
break;
|
||||
case 's':
|
||||
str = va_arg(args, char *);
|
||||
count += str_print(str);
|
||||
break;
|
||||
case 'x':
|
||||
unum = va_arg(args, uint32_t);
|
||||
count += uint32_hex_print(unum);
|
||||
break;
|
||||
case 'u':
|
||||
unum = va_arg(args, uint32_t);
|
||||
count += uint32_print(unum);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
(void)console_putc((uint8_t)*fmt);
|
||||
count++;
|
||||
}
|
||||
fmt++;
|
||||
}
|
||||
va_end(args);
|
||||
}
|
||||
@@ -0,0 +1,163 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : SCIF driver
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file scif.c
|
||||
* - Version : 0.07
|
||||
* @brief 1. Initial setting of SCIF.
|
||||
* 2. Initial setting of HSCIF.
|
||||
* 3. Log output function.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 28.07.2021 0.01 First Release
|
||||
* : 03.09.2021 0.02 Modify the timing of MODEMR judgement.
|
||||
* : 15.10.2021 0.03 Modify register access to read modify write.
|
||||
* : 03.12.2021 0.04 Fix incorrect configuration process.
|
||||
* : 06.01.2022 0.05 Static analysis support
|
||||
* : 16.06.2022 0.06 Change line feed code
|
||||
* : 31.10.2022 0.07 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <types.h>
|
||||
#include <scif.h>
|
||||
#include <mem_io.h>
|
||||
#include <rst_register.h>
|
||||
|
||||
/* Define */
|
||||
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
|
||||
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
|
||||
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
|
||||
|
||||
|
||||
static void (*rcar_putc)(uint8_t outchar);
|
||||
|
||||
static void scif_console_init(uint32_t modemr);
|
||||
static void scif_console_putc(uint8_t outchar);
|
||||
static void hscif_console_putc(uint8_t outchar);
|
||||
|
||||
|
||||
static void scif_console_init(uint32_t modemr)
|
||||
{
|
||||
switch(modemr)
|
||||
{
|
||||
case MODEMR_HSCIF_DLMODE_3000000:
|
||||
{
|
||||
/* Set the pointer to a function that outputs one character. */
|
||||
rcar_putc = hscif_console_putc;
|
||||
break;
|
||||
}
|
||||
case MODEMR_HSCIF_DLMODE_1843200:
|
||||
{
|
||||
/* Set the pointer to a function that outputs one character. */
|
||||
rcar_putc = hscif_console_putc;
|
||||
break;
|
||||
}
|
||||
case MODEMR_HSCIF_DLMODE_921600:
|
||||
{
|
||||
/* Set the pointer to a function that outputs one character. */
|
||||
rcar_putc = hscif_console_putc;
|
||||
break;
|
||||
}
|
||||
case MODEMR_SCIF_DLMODE:
|
||||
default:
|
||||
{
|
||||
/* Set the pointer to a function that outputs one character. */
|
||||
rcar_putc = scif_console_putc;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* End of function scif_console_init(void) */
|
||||
|
||||
void scif_init(void)
|
||||
{
|
||||
uint32_t modemr;
|
||||
|
||||
modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U);
|
||||
modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
|
||||
|
||||
scif_console_init(modemr);
|
||||
}
|
||||
/* End of function scif_init(void) */
|
||||
|
||||
void console_putc(uint8_t outchar)
|
||||
{
|
||||
if (outchar == 0x0A) /* \n */
|
||||
{
|
||||
rcar_putc( 0x0D ); /* \r */
|
||||
}
|
||||
rcar_putc(outchar);
|
||||
}
|
||||
/* End of function console_putc(void) */
|
||||
|
||||
|
||||
static void scif_console_putc(uint8_t outchar)
|
||||
{
|
||||
uint16_t reg;
|
||||
|
||||
/* Check that transfer of SCIF0 is completed */
|
||||
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */
|
||||
reg = mem_read16(SCIF_SCFSR);
|
||||
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
|
||||
mem_write16(SCIF_SCFSR, reg);
|
||||
|
||||
/* Check that transfer of SCIF0 is completed */
|
||||
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
|
||||
{
|
||||
;
|
||||
}
|
||||
}
|
||||
/* End of function scif_console_putc(uint8_t outchar) */
|
||||
|
||||
static void hscif_console_putc(uint8_t outchar)
|
||||
{
|
||||
uint16_t reg;
|
||||
|
||||
/* Check that transfer of SCIF0 is completed */
|
||||
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */
|
||||
reg = mem_read16(HSCIF_HSFSR);
|
||||
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
|
||||
mem_write16(HSCIF_HSFSR, reg);
|
||||
|
||||
/* Check that transfer of SCIF0 is completed */
|
||||
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
|
||||
{
|
||||
;
|
||||
}
|
||||
}
|
||||
/* End of function hscif_console_putc(uint8_t outchar) */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Standard library
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file string.c
|
||||
* - Version : 0.01
|
||||
* @brief standard library.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 04.04.2023 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
|
||||
void *memcpy(void *dst, const void *src, size_t len)
|
||||
{
|
||||
uint8_t *p1 = (uint8_t *)dst;
|
||||
const uint8_t *p2 = (const uint8_t *)src;
|
||||
while(len > 0U)
|
||||
{
|
||||
*(p1++) = *(p2++);
|
||||
len--;
|
||||
}
|
||||
return dst;
|
||||
}
|
||||
/* End of function memcpy( void* dst, const void* src, size_t n ) */
|
||||
|
||||
void *memset(void *dst, int val, size_t len)
|
||||
{
|
||||
uint8_t *p = (uint8_t *)dst;
|
||||
const uint8_t uc = (uint8_t)val;
|
||||
|
||||
while (len > 0U)
|
||||
{
|
||||
*p++ = uc;
|
||||
len--;
|
||||
}
|
||||
return (dst);
|
||||
}
|
||||
/* End of function memset(void *dst, int val, size_t len) */
|
||||
@@ -0,0 +1,177 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : generic timer
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file generic_timer.c
|
||||
* - Version : 0.08
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 19.01.2022 0.01 First Release
|
||||
* : 17.02.2022 0.02 Support AArch32
|
||||
* : 09.05.2022 0.03 Supports argument check of micro_wait()
|
||||
* Moved the definition of the define value
|
||||
* Removed __ARM_ARCH_8R__ and __ARM_ARCH_8A__
|
||||
* Change macro to inline function
|
||||
* Added initial settings
|
||||
* Remove unnecessary casts
|
||||
* Change the value of RCAR_CNTC_EXTAL
|
||||
* : 16.06.2022 0.04 Change the value of RCAR_CNTC_EXTAL
|
||||
* : 16.06.2022 0.05 Change log output
|
||||
* : 31.10.2022 0.06 License notation change.
|
||||
* : 04.04.2023 0.07 Removed stdio.h.
|
||||
* : 21.08.2023 0.08 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <mem_io.h>
|
||||
#include <timer.h>
|
||||
#include <log.h>
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define RCAR_CNTC_EXTAL (16666666U) /* 16.666666MHz */
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define RCAR_CNTC_EXTAL (16666600U) /* 16.666600MHz */
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#define CNTFID_OFF (0x0020U)
|
||||
#define CNTCR_OFF (0x0000U)
|
||||
#define CNTCR_EN ((1U) << 0U)
|
||||
#define RCAR_CNTC_BASE (0xE6080000U)
|
||||
#define RCAR_CONV_MICROSEC (1000000U)
|
||||
#define RCAR_MAX_WAITTIME (10000000U)
|
||||
#define RCAR_MIN_WAITTIME (0U)
|
||||
|
||||
#ifdef __aarch64__
|
||||
static inline uint64_t get_cntfrq(void)
|
||||
{
|
||||
uint64_t freq;
|
||||
__asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq));
|
||||
|
||||
return(freq);
|
||||
}
|
||||
|
||||
static inline void set_cntfrq(uint64_t reg_cntfid)
|
||||
{
|
||||
__asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid));
|
||||
}
|
||||
|
||||
static inline uint64_t get_cntpct(void)
|
||||
{
|
||||
uint64_t base_count;
|
||||
__asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count));
|
||||
|
||||
return(base_count);
|
||||
}
|
||||
|
||||
#elif __arm__
|
||||
static inline uint32_t get_cntfrq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
__asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
return(freq);
|
||||
}
|
||||
|
||||
static inline void set_cntfrq(uint32_t reg_cntfid)
|
||||
{
|
||||
__asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid));
|
||||
}
|
||||
|
||||
static inline uint64_t get_cntpct(void)
|
||||
{
|
||||
uint64_t base_count;
|
||||
__asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count));
|
||||
|
||||
return(base_count);
|
||||
}
|
||||
#endif /* __aarch64__ */
|
||||
|
||||
void generic_timer_init(void)
|
||||
{
|
||||
/* Update memory mapped and register based freqency */
|
||||
/* AArch64:cntfrq_el0 */
|
||||
/* AArch32:cntfrq */
|
||||
set_cntfrq(RCAR_CNTC_EXTAL);
|
||||
|
||||
mem_write32(RCAR_CNTC_BASE + CNTFID_OFF, RCAR_CNTC_EXTAL);
|
||||
|
||||
/* Enable counter */
|
||||
mem_bitset32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_EN);
|
||||
}
|
||||
/* End of function generic_timer_init(void) */
|
||||
|
||||
void micro_wait(uint64_t micro_sec)
|
||||
{
|
||||
uint64_t base_count = 0U;
|
||||
uint64_t get_count = 0U;
|
||||
uint64_t wait_time = 0U;
|
||||
#ifdef __aarch64__
|
||||
uint64_t freq = 0U;
|
||||
#elif __arm__
|
||||
uint32_t freq = 0U;
|
||||
#endif /* __aarch64__ */
|
||||
|
||||
|
||||
if((micro_sec > RCAR_MIN_WAITTIME) && (micro_sec <= RCAR_MAX_WAITTIME))
|
||||
{
|
||||
/* AArch64:cntfrq_el0 */
|
||||
/* AArch32:cntfrq */
|
||||
freq = get_cntfrq();
|
||||
/* AArch64:cntpct_el0 */
|
||||
/* AArch32:cntpct */
|
||||
base_count = get_cntpct();
|
||||
|
||||
micro_sec *= freq;
|
||||
while (micro_sec > wait_time)
|
||||
{
|
||||
/* cntpct */
|
||||
get_count = get_cntpct();
|
||||
|
||||
/* INT30-C Pre confirmation */
|
||||
if (get_count < base_count)
|
||||
{
|
||||
ERROR("micro_wait(Timer value error!!).\n");
|
||||
panic;
|
||||
}
|
||||
else
|
||||
{
|
||||
wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("micro_wait(wait time)\n");
|
||||
ERROR("wait time = 0x%x\n", (unsigned int)micro_sec);
|
||||
panic;
|
||||
}
|
||||
|
||||
}
|
||||
/* End of function micro_wait(uint64_t micro_sec) */
|
||||
|
||||
@@ -0,0 +1,391 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Power management driver
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file cpu_on.c
|
||||
* - Version : 0.12
|
||||
* @brief 1. Boot process of ARM CPU core.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 17.02.2022 0.01 First Release
|
||||
* : 25.02.2022 0.02 Changed to boot Cortex-R on Core 0.
|
||||
* : 23.03.2022 0.03 Removed unnecessary header file inclusions
|
||||
* : 09.05.2022 0.04 Removed unnecessary processing
|
||||
* Removed unnecessary cast
|
||||
* : 31.10.2022 0.05 License notation change.
|
||||
* : 21.08.2023 0.06 Add support for V4M.
|
||||
* : 16.11.2023 0.07 Changed not to execute ASPREG setting
|
||||
* in case of V4M.
|
||||
* : 10.09.2024 0.08 Updated Region ID and RAM protection setting
|
||||
* for QNX.
|
||||
* : 11.10.2024 0.09 Updated Region ID and RAM protection setting
|
||||
* for QNX for V4M.
|
||||
* : 09.12.2024 0.10 Updated OTP_MEM_OTPMONITOR60 register to
|
||||
* OTP_MEM_OTPMONITOR17 register for V4M.
|
||||
* And Improve the adj_ca_variant_freq function.
|
||||
* : 19.12.2024 0.11 Add support for booting CR52 core2.
|
||||
* : 18.03.2025 0.12 Add INTC initialization process.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <mem_io.h>
|
||||
#include <cpu_on.h>
|
||||
#include <rst_register.h>
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#include "access_protection.h"
|
||||
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
||||
|
||||
/* ARM */
|
||||
#define CA_CORE0_WUP_REQ (0x00000001U)
|
||||
#define CA_CORE0_VLD_RVBARP (0x00000001U)
|
||||
#define CR_BTMD_RBAR (0x00000000U)
|
||||
#define CR_VLD_BARP (0x00000001U << 0U)
|
||||
#define CR_BAREN_VALID (0x00000001U << 4U)
|
||||
#define CRRST (0x00000000U)
|
||||
|
||||
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U)
|
||||
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U)
|
||||
#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U)
|
||||
#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U)
|
||||
|
||||
/* APMU */
|
||||
#define APMU_BASE (BASE_APMU_ADDR)
|
||||
#define CORTEX_R_CORE (0U) /* Target is Cortex R52 core0 */
|
||||
#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register0 */
|
||||
#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Reset Control Register0 */
|
||||
#define CORTEX_R_CORE2 (2U) /* Target is Cortex R52 core2 */
|
||||
#define APMU_CRRSTCTRL2 (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register2 */
|
||||
#define APMU_CRBARP2 (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x033CU) /* Cortex-R Reset Control Register2 */
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
//EMPTY
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
|
||||
#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */
|
||||
#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */
|
||||
#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */
|
||||
|
||||
#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */
|
||||
|
||||
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U))
|
||||
#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U)
|
||||
#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U)
|
||||
|
||||
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0)
|
||||
|
||||
// #if (RCAR_LSI == RCAR_V4H)
|
||||
// #define V4H_5_NI_CA (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
|
||||
// #define V4H_3_NI_CA (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
// #elif (RCAR_LSI == RCAR_V4M)
|
||||
// #define V4M_5_NI_CA (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
// #define V4M_3_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
// #define V4M_2_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
// #endif /* RCAR_LSI == RCAR_V4H */
|
||||
|
||||
#define CPG_PLL2CR0_KICK_BIT (0x80000000U)
|
||||
#define CPG_PLLECR_PLL2ST_BIT (0x00000200U)
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4M)
|
||||
#define CPG_BASE (BASE_CPG_ADDR)
|
||||
#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U)
|
||||
#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU)
|
||||
#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U)
|
||||
#define CPG_SRSTCLR5_VAL (0x80000000U)
|
||||
#define CPG_SRSTCLR11_VAL (0x00080000U)
|
||||
#define CPG_MSTPCR5_VAL (0x80000000U)
|
||||
#endif /* RCAR_LSI == RCAR_V4M */
|
||||
|
||||
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
|
||||
#if (RCAR_LSI == RCAR_V4M)
|
||||
static void intc_init(void);
|
||||
#endif /* RCAR_LSI == RCAR_V4M */
|
||||
|
||||
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
|
||||
{
|
||||
if(RCAR_PWR_TARGET_CR == target)
|
||||
{
|
||||
/* CR52 core0 Boot address set */
|
||||
mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP));
|
||||
mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
|
||||
|
||||
/* CR52 core2 Boot address set */
|
||||
mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP));
|
||||
mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
|
||||
}
|
||||
// #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
else if(RCAR_PWR_TARGET_CR2 == target)
|
||||
{
|
||||
/* CR52 core2 Boot address set */
|
||||
mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP));
|
||||
mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
|
||||
}
|
||||
// #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
else
|
||||
{
|
||||
/* CA Boot address set */
|
||||
mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
||||
mem_write32(APMU_RVBARPHC0, 0x00000020U); /* CA boot address 0x20_XXXXXXXX */
|
||||
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
|
||||
mem_write32(APMU_RVBARPHC0, 0x00000000U);
|
||||
#endif
|
||||
#else
|
||||
mem_write32(APMU_RVBARPHC0, 0x00000000U);
|
||||
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
||||
}
|
||||
}
|
||||
/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
|
||||
|
||||
void arm_cpu_on(uint32_t target, uint32_t boot_addr)
|
||||
{
|
||||
uint32_t res_data;
|
||||
|
||||
if(RCAR_PWR_TARGET_CR == target)
|
||||
{
|
||||
/* CR Boot address set. */
|
||||
arm_cpu_set_address(target, boot_addr);
|
||||
|
||||
/* CR reset. */
|
||||
mem_write32(APMU_CRRSTCTRL, CRRST);
|
||||
|
||||
/* CR CORE 2 */
|
||||
/* CR Boot address set. */
|
||||
arm_cpu_set_address(target, boot_addr);
|
||||
|
||||
/* CR reset. */
|
||||
mem_write32(APMU_CRRSTCTRL2, CRRST);
|
||||
}
|
||||
// #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
else if(RCAR_PWR_TARGET_CR2 == target)
|
||||
{
|
||||
/* CR Boot address set. */
|
||||
arm_cpu_set_address(target, boot_addr);
|
||||
|
||||
/* CR reset. */
|
||||
mem_write32(APMU_CRRSTCTRL2, CRRST);
|
||||
}
|
||||
// #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
else
|
||||
{
|
||||
#if (RCAR_LSI == RCAR_V4M)
|
||||
/* For the initial setting flow of INTC, see Section 15.4.5 in
|
||||
* "R-Car Series, V4M Series User's Manual".
|
||||
*/
|
||||
/* INTC initialize */
|
||||
intc_init();
|
||||
#endif /* RCAR_LSI == RCAR_V4M */
|
||||
|
||||
/* CA Boot address set. */
|
||||
arm_cpu_set_address(target, boot_addr);
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
/*
|
||||
* In case of V4M, doesn't execute following process at Cx 2nd IPL.
|
||||
* Because following register setting is needed to execute before C4 power on.
|
||||
*/
|
||||
/* AP-System core initialize */
|
||||
res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U));
|
||||
res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
|
||||
mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data);
|
||||
|
||||
res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
|
||||
res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
|
||||
mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
|
||||
/* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */
|
||||
res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
|
||||
res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
|
||||
mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
|
||||
#endif /* RCAR_LSI == RCAR_V4H */
|
||||
/* CA core0 wake up sequence. */
|
||||
mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ);
|
||||
/* Wait until CA core0 wake up sequence finished. */
|
||||
do
|
||||
{
|
||||
res_data = mem_read32(APMU_PWRCTRLC0);
|
||||
}while(CA_CORE0_WUP_REQ & res_data);
|
||||
}
|
||||
}
|
||||
/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
|
||||
|
||||
void adj_ca_variant_freq(void)
|
||||
{
|
||||
|
||||
/* adding support for xtal 20MHz and 33 1/3 MHz
|
||||
* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0)
|
||||
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
|
||||
* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1)
|
||||
*/
|
||||
uint32_t md = (mem_read32(RST_MODEMR0) >> 13) & 0x3U;
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
uint32_t V4H_5_NI_CA;
|
||||
uint32_t V4H_3_NI_CA;
|
||||
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U :
|
||||
V4H_5_NI_CA = (0x53U); /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
|
||||
V4H_3_NI_CA = (0x5FU); /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
break;
|
||||
case 0x1U :
|
||||
V4H_5_NI_CA = (0x45U); /* 1400[MHz] = 60/3[MHz] x (0x45 + 0x1) */
|
||||
V4H_3_NI_CA = (0x4FU); /* 1600[MHz] = 60/3[MHz] x (0x4F + 0x1) */
|
||||
break; /* 60 / 3 = 20.00MHz */
|
||||
case 0x3U :
|
||||
V4H_5_NI_CA = (0x53U); /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
|
||||
V4H_3_NI_CA = (0x5FU); /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
break; /* 50 / 3 = 16.6666MHz */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
|
||||
uint32_t V4M_5_NI_CA;
|
||||
uint32_t V4M_3_NI_CA;
|
||||
uint32_t V4M_2_NI_CA;
|
||||
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U :
|
||||
V4M_5_NI_CA = (0x5FU); /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
V4M_3_NI_CA = (0x6FU); /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
V4M_2_NI_CA = (0x6FU); /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
break;
|
||||
case 0x1U :
|
||||
V4M_5_NI_CA = (0x4FU); /* 3200/4[MHz] = 60/3[MHz] x (0x4F + 0x1) */
|
||||
/*Note: 930MHz - target is 933MHz*/
|
||||
V4M_3_NI_CA = (0x5CU); /* 3720/4[MHz] = 60/3[MHz] x (0x5C + 0x1) */
|
||||
V4M_2_NI_CA = (0x5CU); /* 3720/4[MHz] = 60/3[MHz] x (0x5C + 0x1) */
|
||||
break; /* 60 / 3 = 20.00MHz */
|
||||
case 0x3U :
|
||||
V4M_5_NI_CA = (0x5FU); /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
|
||||
V4M_3_NI_CA = (0x6FU); /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
V4M_2_NI_CA = (0x6FU); /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
|
||||
break; /* 50 / 3 = 16.6666MHz */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
# endif /* RCAR_LSI == RCAR_V4H */
|
||||
|
||||
uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
|
||||
uint32_t pll2_freq = mem_read32(CPG_PLL2CR0);
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
/* Set the CPU frequency division ratio according to the type of variant. */
|
||||
switch (product)
|
||||
{
|
||||
case VARIANT_V4H_7:
|
||||
/* Default value, do nothing */;
|
||||
break;
|
||||
case VARIANT_V4H_5:
|
||||
pll2_freq = (pll2_freq & ~(0xFFU << 20U));
|
||||
pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U));
|
||||
break;
|
||||
case VARIANT_V4H_3:
|
||||
pll2_freq = (pll2_freq & ~(0xFFU << 20U));
|
||||
pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U));
|
||||
break;
|
||||
default:
|
||||
; /* Do nothing */
|
||||
break;
|
||||
}
|
||||
|
||||
if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
|
||||
{
|
||||
/* Write Division value to FRQCRC0 register */
|
||||
mem_write32(CPG_CPGWPR, ~(pll2_freq));
|
||||
mem_write32(CPG_PLL2CR0, pll2_freq);
|
||||
|
||||
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
|
||||
mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
|
||||
|
||||
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
|
||||
{
|
||||
;
|
||||
}
|
||||
}
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
/* Set the CPU frequency division ratio according to the type of variant. */
|
||||
switch (product)
|
||||
{
|
||||
case VARIANT_V4M_7:
|
||||
/* Default value, do nothing */;
|
||||
break;
|
||||
case VARIANT_V4M_5:
|
||||
pll2_freq = (pll2_freq & ~(0xFFU << 20U));
|
||||
pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U));
|
||||
break;
|
||||
case VARIANT_V4M_3:
|
||||
pll2_freq = (pll2_freq & ~(0xFFU << 20U));
|
||||
pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U));
|
||||
break;
|
||||
case VARIANT_V4M_2:
|
||||
pll2_freq = (pll2_freq & ~(0xFFU << 20U));
|
||||
pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U));
|
||||
break;
|
||||
default:
|
||||
; /* Do nothing */
|
||||
break;
|
||||
}
|
||||
|
||||
if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
|
||||
{
|
||||
/* Write Division value to FRQCRC0 register */
|
||||
mem_write32(CPG_CPGWPR, ~(pll2_freq));
|
||||
mem_write32(CPG_PLL2CR0, pll2_freq);
|
||||
|
||||
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
|
||||
mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
|
||||
|
||||
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
|
||||
{
|
||||
;
|
||||
}
|
||||
}
|
||||
#endif /* RCAR_LSI == RCAR_V4H */
|
||||
}
|
||||
/* End of function adj_cpu_variant_freq(void) */
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4M)
|
||||
static void intc_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL));
|
||||
mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL);
|
||||
|
||||
mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL));
|
||||
mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL);
|
||||
|
||||
mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL));
|
||||
reg = mem_read32(CPG_MSTPCR5);
|
||||
reg |= CPG_MSTPCR5_VAL;
|
||||
mem_write32(CPG_MSTPCR5, reg);
|
||||
}
|
||||
/* End of function intc_init(void) */
|
||||
#endif /* RCAR_LSI == RCAR_V4M */
|
||||
@@ -0,0 +1,735 @@
|
||||
#/*******************************************************************************
|
||||
# * DISCLAIMER
|
||||
# * This software is supplied by Renesas Electronics Corporation and is only
|
||||
# * intended for use with Renesas products. No other uses are authorized. This
|
||||
# * software is owned by Renesas Electronics Corporation and is protected under
|
||||
# * all applicable laws, including copyright laws.
|
||||
# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
# * Renesas reserves the right, without notice, to make changes to this software
|
||||
# * and to discontinue the availability of this software. By using this software,
|
||||
# * you agree to the additional terms and conditions found by accessing the
|
||||
# * following link:
|
||||
# * http://www.renesas.com/disclaimer
|
||||
# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
|
||||
# *******************************************************************************/
|
||||
#
|
||||
# *******************************************************************************
|
||||
# * DESCRIPTION : makefile for Loader
|
||||
# ******************************************************************************
|
||||
|
||||
define add_define
|
||||
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
|
||||
endef
|
||||
|
||||
INCLUDE_DIR = -Iinclude \
|
||||
-Iip/ddr
|
||||
|
||||
OUTDIR := build
|
||||
|
||||
# LSI setting common define
|
||||
RCAR_S4 := 0
|
||||
RCAR_V4H := 1
|
||||
RCAR_V4M := 2
|
||||
$(eval $(call add_define,RCAR_S4))
|
||||
$(eval $(call add_define,RCAR_V4H))
|
||||
$(eval $(call add_define,RCAR_V4M))
|
||||
ifneq ("$(FORCE_115200)", "")
|
||||
$(eval $(call add_define,FORCE_115200))
|
||||
endif
|
||||
|
||||
#/* Select LSI("S4" or "V4H" or "V4M" )********************************
|
||||
ifeq ("$(LSI)", "")
|
||||
LSI = S4
|
||||
endif
|
||||
|
||||
ifeq (${LSI},S4)
|
||||
RCAR_LSI:=${RCAR_S4}
|
||||
DIR_NAME_SA9 = s4
|
||||
OBJ_FILE += loader/loader_main_s4.o \
|
||||
cnf_tbl/cnf_tbl_s4.o \
|
||||
ip/qos/qos.o \
|
||||
ip/rtvram/rtvram.o \
|
||||
ip/ddr/s4/lpddr4x/ecc_enable_s4.o
|
||||
INCLUDE_DIR += -Imcu
|
||||
include ip/ddr/ddr.mk
|
||||
else ifeq (${LSI},V4H)
|
||||
RCAR_LSI:=${RCAR_V4H}
|
||||
DIR_NAME_SA9 = v4h
|
||||
OBJ_FILE += loader/loader_main_v4h.o \
|
||||
ip/fcpr/fcpr.o \
|
||||
ip/i2c/i2c5.o \
|
||||
ip/i2c/pmic.o \
|
||||
ip/i2c/pmic_wdt.o \
|
||||
cnf_tbl/cnf_tbl_v4h.o \
|
||||
common/crc32.o \
|
||||
image_load/android_ab.o \
|
||||
ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \
|
||||
ip/ddr/v4h/lpddr5/ecm_enable_v4h.o
|
||||
else ifeq (${LSI},V4M)
|
||||
RCAR_LSI:=${RCAR_V4M}
|
||||
DIR_NAME_SA9 = v4m
|
||||
OBJ_FILE += loader/loader_main_v4m.o \
|
||||
ip/fcpr/fcpr.o \
|
||||
cnf_tbl/cnf_tbl_v4m.o \
|
||||
ip/sysc/sysc.o \
|
||||
ip/avs/avs.o \
|
||||
ip/i2c/i2c.o \
|
||||
ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \
|
||||
ip/ddr/v4m/lpddr5/ecm_enable_v4m.o
|
||||
else
|
||||
$(error "Error: ${LSI} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LSI))
|
||||
|
||||
# timing measurement
|
||||
ifeq ("$(MEASURE_TIME)", "")
|
||||
MEASURE_TIME = 0
|
||||
else
|
||||
$(eval $(call add_define,MEASURE_TIME))
|
||||
# Set log level to Error, so we dont waste time with unnecessary prints
|
||||
LOG_LEVEL := 1
|
||||
OBJ_FILE += common/scmt_checkpoint.o \
|
||||
common/timer/scmt.o
|
||||
endif
|
||||
ifeq ("$(MEASURE_TIME_NOPRINT)", "")
|
||||
MEASURE_TIME_NOPRINT = 0
|
||||
else
|
||||
$(eval $(call add_define,MEASURE_TIME_NOPRINT))
|
||||
endif
|
||||
|
||||
###################################################
|
||||
|
||||
#output file name
|
||||
FILE_NAME = icumx_loader
|
||||
FILE_NAME_SA0 = bootparam_sa0
|
||||
FILE_NAME_SA9 = cert_header_sa9
|
||||
FILE_NAME_TFMV_TBL = tfmv_ver_tbl
|
||||
FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl
|
||||
|
||||
OUTPUT_FILE = $(FILE_NAME).elf
|
||||
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
|
||||
OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf
|
||||
OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf
|
||||
OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf
|
||||
|
||||
#object file name
|
||||
OBJ_FILE += cpu_on/cpu_on.o \
|
||||
common/log/log.o \
|
||||
common/log/scif.o \
|
||||
common/timer/micro_wait.o \
|
||||
image_load/image_load.o \
|
||||
intc/intc.o \
|
||||
intc/vecttbl.o \
|
||||
intc/vect_set.o \
|
||||
ip/ip_control.o \
|
||||
ip/cpg/cpg.o \
|
||||
ip/emmc/emmc_boot.o \
|
||||
ip/wdt/wdt.o \
|
||||
loader/loader.o \
|
||||
loader/loader_main_common.o \
|
||||
protect/ram_protection.o \
|
||||
protect/region_id.o \
|
||||
protect/stack_protect.o \
|
||||
remap/remap.o \
|
||||
rom_api/rom_api.o
|
||||
|
||||
OBJ_FILE_SA0 = tools/dummy_create/sa0.o
|
||||
OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o
|
||||
OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o
|
||||
OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o
|
||||
|
||||
#linker script name
|
||||
ifeq (${LSI},V4M)
|
||||
MEMORY_DEF = loader/icumx_loader_v4m.ld
|
||||
else
|
||||
MEMORY_DEF = loader/icumx_loader.ld
|
||||
endif
|
||||
|
||||
MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld
|
||||
MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld
|
||||
MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld
|
||||
MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld
|
||||
|
||||
###################################################
|
||||
|
||||
# Debug build
|
||||
DEBUG:=0
|
||||
|
||||
# Process DEBUG flag
|
||||
$(eval $(call assert_boolean,DEBUG))
|
||||
$(eval $(call add_define,DEBUG))
|
||||
ifeq (${DEBUG},0)
|
||||
$(eval $(call add_define,NDEBUG))
|
||||
CFLAGS += -Onone
|
||||
else
|
||||
ASFLAGS += -G -dwarf2
|
||||
CFLAGS += -G -dwarf2 -Odebug
|
||||
endif
|
||||
|
||||
# booting performance check
|
||||
ifneq ("$(WDT_RESET)", "")
|
||||
$(eval $(call add_define,WDT_RESET))
|
||||
endif
|
||||
|
||||
# Process STRICT_AB_BOOTING flag
|
||||
ifneq ("$(STRICT_AB_BOOT)", "")
|
||||
$(eval $(call add_define,STRICT_AB_BOOTING))
|
||||
endif
|
||||
|
||||
# booting performance check
|
||||
ifneq ("$(BOOT_GPIO)", "")
|
||||
$(eval $(call add_define,BOOT_GPIO_CHECK))
|
||||
endif
|
||||
OBJ_FILE += ip/gpio/gpio.o
|
||||
|
||||
# MISRA Option
|
||||
#------ MISRA ------
|
||||
ifndef MISRA
|
||||
MISRA := MANDATORY
|
||||
endif
|
||||
ifeq ("$(MISRA)", "DISABLE")
|
||||
MISRA_OPTION = DISABLE
|
||||
else ifeq ("$(MISRA)", "FULL")
|
||||
MISRA_OPTION = FULL
|
||||
else ifeq ("$(MISRA)", "MANDATORY")
|
||||
MISRA_OPTION = MANDATORY
|
||||
else ifeq ("$(MISRA)", "REQUIRED")
|
||||
MISRA_OPTION = REQUIRED
|
||||
endif
|
||||
CFLAGS_MISRA_FULL = \
|
||||
--misra_adv=warn \
|
||||
--misra_req=warn \
|
||||
--misra_mand=warn \
|
||||
--no_misra_runtime \
|
||||
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
|
||||
CFLAGS_MISRA_REQUIRED = \
|
||||
--misra_adv=silent \
|
||||
--misra_req=warn \
|
||||
--misra_mand=warn \
|
||||
--no_misra_runtime \
|
||||
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
|
||||
CFLAGS_MISRA_MANDATORY = \
|
||||
--misra_adv=silent \
|
||||
--misra_req=silent \
|
||||
--misra_mand=warn \
|
||||
--no_misra_runtime \
|
||||
--misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
|
||||
# MISRA 2012 Rule 3.1 is confirmed with static analysis
|
||||
ifeq ("$(MISRA_OPTION)", "FULL")
|
||||
CFLAGS += $(CFLAGS_MISRA_FULL)
|
||||
else ifeq ("$(MISRA)", "REQUIRED")
|
||||
CFLAGS += $(CFLAGS_MISRA_REQUIRED)
|
||||
else ifeq ("$(MISRA)", "MANDATORY")
|
||||
CFLAGS += $(CFLAGS_MISRA_MANDATORY)
|
||||
endif
|
||||
|
||||
# Process LOG_LEVEL
|
||||
ifndef LOG_LEVEL
|
||||
LOG_LEVEL := 1
|
||||
endif
|
||||
$(eval $(call add_define,LOG_LEVEL))
|
||||
ifeq (${LOG_LEVEL},0)
|
||||
LDFLAGS += -nostdlib
|
||||
endif
|
||||
|
||||
# Process SET_FCPR_PARAM flag
|
||||
# 0:Disable, 1:Enable (Support V4H / V4M Linux OS)
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef SET_FCPR_PARAM
|
||||
SET_FCPR_PARAM := 0
|
||||
$(eval $(call add_define,SET_FCPR_PARAM))
|
||||
else
|
||||
ifeq (${SET_FCPR_PARAM},0)
|
||||
$(eval $(call add_define,SET_FCPR_PARAM))
|
||||
else ifeq (${SET_FCPR_PARAM},1)
|
||||
$(eval $(call add_define,SET_FCPR_PARAM))
|
||||
else
|
||||
$(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.")
|
||||
endif
|
||||
endif
|
||||
else
|
||||
SET_FCPR_PARAM := 0
|
||||
$(eval $(call add_define,SET_FCPR_PARAM))
|
||||
endif
|
||||
|
||||
# Process BOOT_MCU flag (S4 only)
|
||||
# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH
|
||||
ifeq (${LSI},S4)
|
||||
ifndef BOOT_MCU
|
||||
BOOT_MCU :=3
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
else
|
||||
ifeq (${BOOT_MCU},0)
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
else ifeq (${BOOT_MCU},1)
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
else ifeq (${BOOT_MCU},2)
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
else ifeq (${BOOT_MCU},3)
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
else
|
||||
$(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.")
|
||||
endif
|
||||
endif
|
||||
else
|
||||
BOOT_MCU :=0
|
||||
$(eval $(call add_define,BOOT_MCU))
|
||||
endif
|
||||
|
||||
ifneq (${BOOT_MCU},0)
|
||||
OBJ_FILE += mcu/cpu_on_for_mcu.o \
|
||||
mcu/sdmac.o \
|
||||
mcu/loader_main_mcu.o \
|
||||
mcu/image_load_for_mcu.o \
|
||||
mcu/codesram_ecc.o
|
||||
endif
|
||||
|
||||
# Process RTVRAM_EXTEND flag
|
||||
ifeq (${LSI},S4)
|
||||
ifndef RTVRAM_EXTEND
|
||||
RTVRAM_EXTEND := 1
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else
|
||||
ifeq (${RTVRAM_EXTEND},0)
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else ifeq (${RTVRAM_EXTEND},1)
|
||||
$(eval $(call add_define,RTVRAM_EXTEND))
|
||||
else
|
||||
$(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process QSPI_DDR_MODE flag
|
||||
# 0:SDR, 1:DDR
|
||||
ifndef QSPI_DDR_MODE
|
||||
QSPI_DDR_MODE := 0
|
||||
$(eval $(call add_define,QSPI_DDR_MODE))
|
||||
else
|
||||
ifeq (${QSPI_DDR_MODE},0)
|
||||
$(eval $(call add_define,QSPI_DDR_MODE))
|
||||
else ifeq (${QSPI_DDR_MODE},1)
|
||||
$(eval $(call add_define,QSPI_DDR_MODE))
|
||||
else
|
||||
$(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# RCAR_QSPI_DDR_DUMMY_CYCLE
|
||||
ifndef RCAR_QSPI_DDR_DUMMY_CYCLE
|
||||
RCAR_QSPI_DDR_DUMMY_CYCLE := 9
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE))
|
||||
|
||||
# Process RCAR_SA9_TYPE flag
|
||||
# 0:Flash, 1:eMMC
|
||||
ifeq (${LSI},S4)
|
||||
ifndef RCAR_SA9_TYPE
|
||||
RCAR_SA9_TYPE := 0
|
||||
$(eval $(call add_define,RCAR_SA9_TYPE))
|
||||
else
|
||||
ifeq (${RCAR_SA9_TYPE},0)
|
||||
$(eval $(call add_define,RCAR_SA9_TYPE))
|
||||
else ifeq (${RCAR_SA9_TYPE},1)
|
||||
$(eval $(call add_define,RCAR_SA9_TYPE))
|
||||
else
|
||||
$(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
RCAR_SA9_TYPE := 0
|
||||
$(eval $(call add_define,RCAR_SA9_TYPE))
|
||||
endif
|
||||
|
||||
|
||||
ifeq (${RCAR_SA9_TYPE},1)
|
||||
OBJ_FILE += image_load/image_load_emmc.o \
|
||||
ip/emmc/emmc_cmd.o \
|
||||
ip/emmc/emmc_init.o \
|
||||
ip/emmc/emmc_interrupt.o \
|
||||
ip/emmc/emmc_mount.o \
|
||||
ip/emmc/emmc_multiboot.o \
|
||||
ip/emmc/emmc_read.o \
|
||||
ip/emmc/emmc_utility.o
|
||||
else ifeq (${RCAR_SA9_TYPE},0)
|
||||
OBJ_FILE += image_load/image_load_flash.o \
|
||||
ip/dma/dma.o \
|
||||
ip/rpc/rpc.o \
|
||||
ip/rpc/qspi_xdr_mode.o \
|
||||
ip/rpc/dma2.o \
|
||||
ip/rpc/rpcqspidrv.o \
|
||||
ip/rpc/spiflash2drv.o \
|
||||
ip/mfis/mfis.o
|
||||
endif
|
||||
|
||||
# Process CA_LOAD_TYPE flag
|
||||
# 0:CA Loader 1:BL31 (or Secure Monitor)
|
||||
ifeq (${LSI},S4)
|
||||
ifndef CA_LOAD_TYPE
|
||||
CA_LOAD_TYPE := 0
|
||||
$(eval $(call add_define,CA_LOAD_TYPE))
|
||||
else
|
||||
ifeq (${CA_LOAD_TYPE},0)
|
||||
$(eval $(call add_define,CA_LOAD_TYPE))
|
||||
else ifeq (${CA_LOAD_TYPE},1)
|
||||
$(eval $(call add_define,CA_LOAD_TYPE))
|
||||
else
|
||||
$(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
CA_LOAD_TYPE := 0
|
||||
$(eval $(call add_define,CA_LOAD_TYPE))
|
||||
endif
|
||||
|
||||
ifeq (${RCAR_SA9_TYPE},1)
|
||||
ifeq (${CA_LOAD_TYPE},0)
|
||||
$(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process MCU_SECURE_BOOT flag (S4 only)
|
||||
ifndef MCU_SECURE_BOOT
|
||||
MCU_SECURE_BOOT := 0
|
||||
$(eval $(call add_define,MCU_SECURE_BOOT))
|
||||
else
|
||||
ifeq (${MCU_SECURE_BOOT},0)
|
||||
$(eval $(call add_define,MCU_SECURE_BOOT))
|
||||
else ifeq (${MCU_SECURE_BOOT},1)
|
||||
ifeq (${BOOT_MCU},0)
|
||||
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.")
|
||||
else
|
||||
$(eval $(call add_define,MCU_SECURE_BOOT))
|
||||
endif
|
||||
else
|
||||
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process SW_VERSION_CHECK flag
|
||||
# 0:Disable 1:Enable
|
||||
ifndef SW_VERSION_CHECK
|
||||
SW_VERSION_CHECK := 0
|
||||
$(eval $(call add_define,SW_VERSION_CHECK))
|
||||
else
|
||||
ifeq (${SW_VERSION_CHECK},0)
|
||||
$(eval $(call add_define,SW_VERSION_CHECK))
|
||||
else ifeq (${SW_VERSION_CHECK},1)
|
||||
$(eval $(call add_define,SW_VERSION_CHECK))
|
||||
else
|
||||
$(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process access protection flag
|
||||
# 0:Disable 1:Enable
|
||||
ifndef ACC_PROT_ENABLE
|
||||
ACC_PROT_ENABLE := 0
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else
|
||||
ifeq (${ACC_PROT_ENABLE},0)
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else ifeq (${ACC_PROT_ENABLE},1)
|
||||
$(eval $(call add_define,ACC_PROT_ENABLE))
|
||||
else
|
||||
$(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq (${MCU_SECURE_BOOT},1)
|
||||
include mcu_secureboot/mcu_secureboot.mk
|
||||
endif
|
||||
|
||||
# Process ADD_HOTPLUG_MAGIC flag
|
||||
ifndef ADD_HOTPLUG_MAGIC
|
||||
ADD_HOTPLUG_MAGIC := 0
|
||||
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
|
||||
else
|
||||
ifeq (${ADD_HOTPLUG_MAGIC},0)
|
||||
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
|
||||
else ifeq (${ADD_HOTPLUG_MAGIC},1)
|
||||
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
|
||||
else
|
||||
$(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process STACK_PROTECT flag
|
||||
ifndef STACK_PROTECT
|
||||
STACK_PROTECT := 0
|
||||
$(eval $(call add_define,STACK_PROTECT))
|
||||
else
|
||||
ifeq (${STACK_PROTECT},0)
|
||||
$(eval $(call add_define,STACK_PROTECT))
|
||||
else ifeq (${STACK_PROTECT},1)
|
||||
$(eval $(call add_define,STACK_PROTECT))
|
||||
CFLAGS += -stack_protector
|
||||
else
|
||||
$(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process RTOS_LOAD_NUM flag
|
||||
# 1:RTOS#0 only 3:RTOS#0,#1,#2
|
||||
ifndef RTOS_LOAD_NUM
|
||||
RTOS_LOAD_NUM := 1
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else
|
||||
ifeq (${RTOS_LOAD_NUM},1)
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else ifeq (${RTOS_LOAD_NUM},3)
|
||||
$(eval $(call add_define,RTOS_LOAD_NUM))
|
||||
else
|
||||
$(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process OPTEE_LOAD_ENABLE flag
|
||||
ifeq ($(filter ${LSI},V4H V4M),${LSI})
|
||||
ifndef OPTEE_LOAD_ENABLE
|
||||
OPTEE_LOAD_ENABLE := 1
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else
|
||||
ifeq (${OPTEE_LOAD_ENABLE},0)
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else ifeq (${OPTEE_LOAD_ENABLE},1)
|
||||
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
|
||||
else
|
||||
$(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process BL2_LOAD_ENABLE flag
|
||||
ifeq (${LSI},V4H)
|
||||
ifndef BL2_LOAD_ENABLE
|
||||
BL2_LOAD_ENABLE := 1
|
||||
$(eval $(call add_define,BL2_LOAD_ENABLE))
|
||||
else
|
||||
ifeq (${BL2_LOAD_ENABLE},0)
|
||||
$(eval $(call add_define,BL2_LOAD_ENABLE))
|
||||
else ifeq (${BL2_LOAD_ENABLE},1)
|
||||
$(eval $(call add_define,BL2_LOAD_ENABLE))
|
||||
else
|
||||
$(error "Error:BL2_LOAD_ENABLE=${BL2_LOAD_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process QNX_OS_LOAD_ENABLE flag
|
||||
ifeq (${LSI},V4H)
|
||||
ifndef QNX_OS_LOAD_ENABLE
|
||||
QNX_OS_LOAD_ENABLE := 1
|
||||
$(eval $(call add_define,QNX_OS_LOAD_ENABLE))
|
||||
else
|
||||
ifeq (${QNX_OS_LOAD_ENABLE},0)
|
||||
$(eval $(call add_define,QNX_OS_LOAD_ENABLE))
|
||||
else ifeq (${QNX_OS_LOAD_ENABLE},1)
|
||||
$(eval $(call add_define,QNX_OS_LOAD_ENABLE))
|
||||
else
|
||||
$(error "Error:QNX_OS_LOAD_ENABLE=${QNX_OS_LOAD_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
###################################################
|
||||
# pass SecureMonitor parametor
|
||||
###################################################
|
||||
# Process SET_CA_PARAM flag
|
||||
ifeq (${LSI},S4)
|
||||
ifndef SET_CA_PARAM
|
||||
SET_CA_PARAM := 1
|
||||
$(eval $(call add_define,SET_CA_PARAM))
|
||||
else
|
||||
ifeq (${SET_CA_PARAM},0)
|
||||
$(eval $(call add_define,SET_CA_PARAM))
|
||||
else ifeq (${SET_CA_PARAM},1)
|
||||
$(eval $(call add_define,SET_CA_PARAM))
|
||||
else
|
||||
$(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.")
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process ECM_ENABLE
|
||||
ifndef ECM_ENABLE
|
||||
ECM_ENABLE:= 0
|
||||
$(eval $(call add_define,ECM_ENABLE))
|
||||
else
|
||||
ifeq (${ECM_ENABLE},0)
|
||||
$(eval $(call add_define,ECM_ENABLE))
|
||||
else ifeq (${ECM_ENABLE},1)
|
||||
$(eval $(call add_define,ECM_ENABLE))
|
||||
else
|
||||
$(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process ECM_ERROR_ENABLE flag
|
||||
ifndef ECM_ERROR_ENABLE
|
||||
ECM_ERROR_ENABLE := 1
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else
|
||||
ifeq (${ECM_ERROR_ENABLE},0)
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else ifeq (${ECM_ERROR_ENABLE},1)
|
||||
$(eval $(call add_define,ECM_ERROR_ENABLE))
|
||||
else
|
||||
$(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
# Process SAN_ENABLE
|
||||
ifndef SAN_ENABLE
|
||||
SAN_ENABLE:= 0
|
||||
$(eval $(call add_define,SAN_ENABLE))
|
||||
else
|
||||
ifeq (${SAN_ENABLE},0)
|
||||
$(eval $(call add_define,SAN_ENABLE))
|
||||
else ifeq (${SAN_ENABLE},1)
|
||||
$(eval $(call add_define,SAN_ENABLE))
|
||||
OBJ_FILE += \
|
||||
ip/san/v4h.o \
|
||||
ip/wdt/rwdt.o
|
||||
else
|
||||
$(error "Error: SAN_ENABLE=${SAN_ENABLE} is not supported.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process DBSC HUNGUP WA
|
||||
ifndef WA_OTLINT5579
|
||||
WA_OTLINT5579:= 1
|
||||
endif
|
||||
$(eval $(call add_define,WA_OTLINT5579))
|
||||
|
||||
###################################################
|
||||
|
||||
OUTDIR_REL := $(OUTDIR)/release
|
||||
OUTDIR_OBJ := $(OUTDIR)/obj
|
||||
|
||||
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
|
||||
|
||||
CC = cxrh850
|
||||
AS = cxrh850
|
||||
LD = cxrh850
|
||||
OC = gsrec
|
||||
OD = gdump
|
||||
|
||||
ASFLAGS += -asm="-preprocess_assembly_files" \
|
||||
-asm="-nostartfiles" \
|
||||
-D__ASSEMBLY \
|
||||
$(INCLUDE_DIR) $(DEFINES)
|
||||
|
||||
CFLAGS += -nostartfiles \
|
||||
-c99 \
|
||||
$(INCLUDE_DIR) $(DEFINES) \
|
||||
--ghstd=last \
|
||||
-Wundef \
|
||||
--diag_error=193 \
|
||||
--prototype_errors
|
||||
# --ghstd=last : Enable Green Hills Standard Mode
|
||||
# -Wundef : Output warning if there are any undefined symbols
|
||||
# --diag_error=193 : Error if zero is applied to undefined symbol
|
||||
# --prototype_errors : Error if there are no any prototype declaration
|
||||
|
||||
ifeq (${LOG_LEVEL},0)
|
||||
# There are no any additional options
|
||||
else
|
||||
CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant
|
||||
endif
|
||||
|
||||
LDFLAGS += -nostartfiles -Mu
|
||||
|
||||
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
|
||||
|
||||
###################################################
|
||||
.SUFFIXES : .s .c .o
|
||||
|
||||
###################################################
|
||||
# command
|
||||
|
||||
.PHONY: all
|
||||
all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL)
|
||||
|
||||
###################################################
|
||||
# Linker
|
||||
###################################################
|
||||
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
|
||||
@echo const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); > $(OUTDIR_OBJ)/build_message.c
|
||||
$(V)$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
|
||||
|
||||
$(V)$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
|
||||
-T $(MEMORY_DEF) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
|
||||
$(LDFLAGS) \
|
||||
-map=$(OUTDIR_REL)/$(FILE_NAME).map
|
||||
|
||||
$(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
|
||||
$(V)$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
|
||||
$(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
|
||||
|
||||
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
|
||||
$(V)$(LD) $(OBJ_FILE_SA0) \
|
||||
-T $(MEMORY_DEF_SA0) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \
|
||||
-map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \
|
||||
-nostdlib
|
||||
|
||||
$(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec
|
||||
$(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin)
|
||||
|
||||
$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9)
|
||||
$(V)$(LD) $(OBJ_FILE_SA9) \
|
||||
-T $(MEMORY_DEF_SA9) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \
|
||||
-map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \
|
||||
-nostdlib
|
||||
|
||||
$(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec
|
||||
$(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin)
|
||||
|
||||
$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL)
|
||||
$(V)$(LD) $(OBJ_FILE_TFMV_TBL) \
|
||||
-T $(MEMORY_DEF_TFMV_TBL) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \
|
||||
-map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \
|
||||
-nostdlib
|
||||
|
||||
$(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin)
|
||||
|
||||
$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL)
|
||||
$(V)$(LD) $(OBJ_FILE_NTFMV_TBL) \
|
||||
-T $(MEMORY_DEF_NTFMV_TBL) \
|
||||
-o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \
|
||||
-map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \
|
||||
-nostdlib
|
||||
|
||||
$(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin)
|
||||
|
||||
###################################################
|
||||
# Compile
|
||||
###################################################
|
||||
|
||||
$(OUTDIR_OBJ)/%.o:%.c
|
||||
$(V)$(CC) $(CFLAGS) -o $@ -c $<
|
||||
|
||||
$(OUTDIR_OBJ)/%.o:%.S
|
||||
$(V)$(AS) $(ASFLAGS) -o $@ -c $<
|
||||
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -rf $(OUTDIR)
|
||||
@@ -0,0 +1,12 @@
|
||||
# 1. <20><><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
export PATH="$PATH:/cygdrive/c/ghs/comp_202015"
|
||||
|
||||
# 2. <20><><EFBFBD><EFBFBD> <20>ɼ<EFBFBD> <20><><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٿ<EFBFBD><D9BF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> \ <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>մϴ<D5B4>)
|
||||
_build_param="ECM_ENABLE=1 ECM_ERROR_ENABLE=1 ECC_ENABLE=1 \
|
||||
SW_VERSION_CHECK=1 \
|
||||
OPTEE_LOAD_ENABLE=1 \
|
||||
BL2_LOAD_ENABLE=1 \
|
||||
QNX_OS_LOAD_ENABLE=1 \
|
||||
STACK_PROTECT=1 \
|
||||
FORCE_115200=1 \
|
||||
SAN_ENABLE=1"
|
||||
@@ -0,0 +1,478 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Image load function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file image_load.c
|
||||
* - Version : 0.11
|
||||
* @brief Access protection setting driver.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 29.11.2021 0.01 First Release
|
||||
* : 10.02.2022 0.02 Updated eMMC driver
|
||||
* Removed the comment
|
||||
* Change the line feed code of log output
|
||||
* Change the number of CA programs
|
||||
* : 17.02.2022 0.03 Support AArch32
|
||||
* : 22.03.2022 0.04 Support for GSCE[3.3b]
|
||||
* : 11.05.2022 0.05 Used the standard library
|
||||
* Integrated LOAD_INFO
|
||||
* Changed image_name table
|
||||
* Changed check_load_area
|
||||
* - Change RAM check process
|
||||
* - Change address check process
|
||||
* - Add Image check process
|
||||
* - Processing integration
|
||||
* Changed to processing for each device
|
||||
* Change structure member name
|
||||
* Added function return value judgment
|
||||
* Changed LOGICAL_CONTENT_CERT_ADDR to
|
||||
* get_logic_cont_cert_addr
|
||||
* Changed uint32_t to uintptr_t
|
||||
* Change log output
|
||||
* Add argument of load_init()
|
||||
* Change to error when key information is invalid
|
||||
* Remove unnecessary type conversion
|
||||
* : 11.07.2022 0.06 Change log output
|
||||
* Support secure boot for S4
|
||||
* Change load start processing other than 512byte align
|
||||
* : 02.09.2022 0.07 Added 512byte boundary check
|
||||
* : 31.10.2022 0.08 License notation change.
|
||||
* : 21.08.2023 0.09 Add support for V4M.
|
||||
* : 19.12.2024 0.10 Add support for RTOS#1 and RTOS#2.
|
||||
* : 26.05.2025 0.11 Change key cert address of [CA_OPTIONAL_ID+2].
|
||||
*****************************************************************************/
|
||||
/* indelude */
|
||||
#include <stdint.h>
|
||||
#include <image_load.h>
|
||||
#include <mem_io.h>
|
||||
#include <log.h>
|
||||
|
||||
#include <image_load_emmc.h>
|
||||
#include <emmc_multiboot.h>
|
||||
|
||||
#define KEY_SIZE_FLG_MSK (0x00000003U)
|
||||
#define KEY_SIZE_BIT_SHIFT (21U)
|
||||
#define CERT_INFO_FLG_OFFSET (0x0000000CU)
|
||||
#define KEY_SIZE_4096 (0x00000002U)
|
||||
#define KEY_SIZE_3072 (0x00000001U)
|
||||
#define KEY_SIZE_2048 (0x00000000U)
|
||||
#define WORD_TO_BYTE (4U)
|
||||
#define NOT_OVERLAP_FLAG (0U)
|
||||
#define OVERLAP_FLAG (1U)
|
||||
#define RAM_RANGE_OK (0U)
|
||||
#define RAM_RANGE_NG (1U)
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
|
||||
#define RAM_MAX (4U)
|
||||
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
#define RAM_MAX (5U) /* ++ SRAM in RT-VRAM (0xE2000000 - 0xE200FFFF) */
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
#define ADDRESS_RANGE_512 (512U)
|
||||
|
||||
static void check_load_area(LOAD_INFO* li);
|
||||
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
|
||||
uint32_t *dest_addr);
|
||||
|
||||
void load_image(LOAD_INFO* li)
|
||||
{
|
||||
/* log output of load image for information */
|
||||
load_image_info_print_for_emmc(li);
|
||||
|
||||
/* Check transfer range of image. */
|
||||
check_load_area(li);
|
||||
|
||||
/* Image load start. */
|
||||
load_start(li);
|
||||
}
|
||||
/* End of function load_image(LOAD_INFO* li) */
|
||||
|
||||
void load_init(LOAD_INFO* li, uint32_t num)
|
||||
{
|
||||
uint32_t loop;
|
||||
uintptr_t buf;
|
||||
|
||||
const char *image_name[MAX_PLACED] = {
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
[RTOS_A_ID] = "RTOS A",
|
||||
[RTOS_B_ID] = "RTOS B",
|
||||
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
|
||||
[CA_OPTIONAL_ID] = "CA Program #1 - ATF A",
|
||||
[CA_OPTIONAL_ID + 1] = "CA Program #2 - U-BOOT A",
|
||||
[CA_OPTIONAL_ID + 2] = "CA Program #3 - TEE A",
|
||||
[CA_OPTIONAL_ID + 3] = "CA Program #4 - ATF B",
|
||||
[CA_OPTIONAL_ID + 4] = "CA Program #5 - U-BOOT B",
|
||||
[CA_OPTIONAL_ID + 5] = "CA Program #6 - TEE B",
|
||||
[CA_OPTIONAL_ID + 6] = "CA Program #7",
|
||||
[CA_OPTIONAL_ID + 7] = "CA Program #8",
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
[RTOS1_ID] = "RTOS#1",
|
||||
[RTOS2_ID] = "RTOS#2",
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
};
|
||||
|
||||
const uint32_t key_cert[MAX_PLACED] = {
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
[RTOS_A_ID] = TFMV_KEY_CERT_ADDR,
|
||||
[RTOS_B_ID] = TFMV_KEY_CERT_ADDR,
|
||||
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
|
||||
[CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR,
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
[CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR,
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
[CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR,
|
||||
#endif
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
[CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR,
|
||||
#else
|
||||
[CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR,
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
[CA_OPTIONAL_ID + 3] = TFMV_KEY_CERT_ADDR,
|
||||
[CA_OPTIONAL_ID + 4] = TFMV_KEY_CERT_ADDR,
|
||||
[CA_OPTIONAL_ID + 5] = TFMV_KEY_CERT_ADDR,
|
||||
[CA_OPTIONAL_ID + 6] = TFMV_KEY_CERT_ADDR,
|
||||
[CA_OPTIONAL_ID + 7] = TFMV_KEY_CERT_ADDR,
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
[RTOS1_ID] = TFMV_KEY_CERT_ADDR,
|
||||
[RTOS2_ID] = TFMV_KEY_CERT_ADDR,
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
};
|
||||
|
||||
|
||||
if (num >= 1U && num <= 8U)
|
||||
{
|
||||
/* Set Load info parameter */
|
||||
for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++)
|
||||
{
|
||||
li[loop].name = image_name[loop];
|
||||
li[loop].key_cert_addr = key_cert[loop];
|
||||
li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
|
||||
get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
|
||||
buf = get_src_addr_offset_in_cert(loop);
|
||||
li[loop].src_addr = (SRC_TOP + mem_read32(buf));
|
||||
buf = get_part_num_in_cert(loop);
|
||||
li[loop].part_num = mem_read32(buf);
|
||||
li[loop].load_id = loop;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("load_init(CA program num error).\n");
|
||||
panic;
|
||||
}
|
||||
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
li[RTOS_A_ID].name = image_name[RTOS_A_ID];
|
||||
li[RTOS_A_ID].key_cert_addr = key_cert[RTOS_A_ID];
|
||||
li[RTOS_A_ID].cnt_cert_addr = get_logic_cont_cert_addr(RTOS_A_ID);
|
||||
get_info_from_cert(li[RTOS_A_ID].cnt_cert_addr, &li[RTOS_A_ID].image_size, &li[RTOS_A_ID].boot_addr);
|
||||
buf = get_src_addr_offset_in_cert(RTOS_A_ID);
|
||||
li[RTOS_A_ID].src_addr = (SRC_TOP + mem_read32(buf));
|
||||
buf = get_part_num_in_cert(RTOS_A_ID);
|
||||
li[RTOS_A_ID].part_num = mem_read32(buf);
|
||||
li[RTOS_A_ID].load_id = RTOS_A_ID;
|
||||
|
||||
li[RTOS_B_ID].name = image_name[RTOS_B_ID];
|
||||
li[RTOS_B_ID].key_cert_addr = key_cert[RTOS_B_ID];
|
||||
li[RTOS_B_ID].cnt_cert_addr = get_logic_cont_cert_addr(RTOS_B_ID);
|
||||
get_info_from_cert(li[RTOS_B_ID].cnt_cert_addr, &li[RTOS_B_ID].image_size, &li[RTOS_B_ID].boot_addr);
|
||||
buf = get_src_addr_offset_in_cert(RTOS_B_ID);
|
||||
li[RTOS_B_ID].src_addr = (SRC_TOP + mem_read32(buf));
|
||||
buf = get_part_num_in_cert(RTOS_B_ID);
|
||||
li[RTOS_B_ID].part_num = mem_read32(buf);
|
||||
li[RTOS_B_ID].load_id = RTOS_B_ID;
|
||||
|
||||
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
/* Set Load info parameter for RTOS#1 and RTOS#2 */
|
||||
for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++)
|
||||
{
|
||||
li[loop].name = image_name[loop];
|
||||
li[loop].key_cert_addr = key_cert[loop];
|
||||
li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
|
||||
get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
|
||||
buf = get_src_addr_offset_in_cert(loop);
|
||||
li[loop].src_addr = (SRC_TOP + mem_read32(buf));
|
||||
buf = get_part_num_in_cert(loop);
|
||||
li[loop].part_num = mem_read32(buf);
|
||||
li[loop].load_id = loop;
|
||||
}
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
|
||||
|
||||
}/* End of function load_init(LOAD_INFO* li) */
|
||||
|
||||
|
||||
static void check_load_area(LOAD_INFO* li)
|
||||
{
|
||||
uint32_t src;
|
||||
uint32_t dst;
|
||||
uint32_t len;
|
||||
uint32_t dst_end;
|
||||
uint32_t overlap;
|
||||
uint32_t loop;
|
||||
uint32_t rge_chk_flg;
|
||||
static uint32_t s_num = 1U;
|
||||
|
||||
/* The memory range of destination. */
|
||||
const ADDRESS_RANGE add_list[RAM_MAX] = {
|
||||
[TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END},
|
||||
[TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END},
|
||||
[TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END},
|
||||
[TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END},
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
[TARGET_MEM_SRAM_IN_RTVRAM] = {RTVRAM_SRAM_TOP, RTVRAM_SRAM_END},
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
};
|
||||
|
||||
/* The image range check */
|
||||
const IMAGE_RANGE size_list[CA_IMAGESIZECHK_DEF] = {
|
||||
{ CA_PROGRAM1_ID, CA_PROGRAM1_ADR, CA_PROGRAM1_SIZE},
|
||||
{ CA_PROGRAM2_ID, CA_PROGRAM2_ADR, CA_PROGRAM2_SIZE},
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
|
||||
{ CA_PROGRAM3_ID, CA_PROGRAM3_ADR, CA_PROGRAM3_SIZE},
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
|
||||
};
|
||||
|
||||
static ADDRESS_RANGE s_placed_image[MAX_PLACED] = {
|
||||
[0] = {IPL_TOP, IPL_END}
|
||||
};
|
||||
|
||||
|
||||
src = li->src_addr;
|
||||
dst = li->boot_addr;
|
||||
len = li->image_size;
|
||||
|
||||
/* Check image size */
|
||||
if (len == 0U)
|
||||
{
|
||||
ERROR("image size error\n");
|
||||
panic;
|
||||
}
|
||||
|
||||
/* Check whether source is overflow */
|
||||
/* INT30-C Pre confirmation */
|
||||
if (src > (UINT32_MAX - len))
|
||||
{
|
||||
ERROR("1:overflow is occurred at source\n");
|
||||
ERROR("1:source address = 0x%x image size = 0x%x\n", (unsigned int)src, (unsigned int)len);
|
||||
panic;
|
||||
}
|
||||
|
||||
/* Check whether destination is overflow */
|
||||
/* INT30-C Pre confirmation */
|
||||
if (dst > (UINT32_MAX - len))
|
||||
{
|
||||
ERROR("1:overflow is occurred at destination\n");
|
||||
ERROR("1:destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
|
||||
(unsigned int)len);
|
||||
panic;
|
||||
}
|
||||
else
|
||||
{
|
||||
dst_end = dst + len - 1U;
|
||||
}
|
||||
|
||||
/* Check source address range. */
|
||||
/* No error check is performed because it is detected by the eMMC device */
|
||||
|
||||
/* Check destination address range. */
|
||||
|
||||
/* 512byte boundary check */
|
||||
if (0U != (dst % ADDRESS_RANGE_512))
|
||||
{
|
||||
ERROR("check_load_area (destination address)\n");
|
||||
ERROR("destination address = 0x%x \n", (unsigned int)dst);
|
||||
panic;
|
||||
}
|
||||
|
||||
/* range check */
|
||||
rge_chk_flg = RAM_RANGE_NG;
|
||||
|
||||
for(loop = 0U; loop < RAM_MAX; loop++)
|
||||
{
|
||||
if (add_list[loop].cx_topadd <= dst)
|
||||
{
|
||||
if(dst_end <= add_list[loop].cx_endadd)
|
||||
{
|
||||
rge_chk_flg = RAM_RANGE_OK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(rge_chk_flg != RAM_RANGE_OK)
|
||||
{
|
||||
ERROR("check_load_area (destination address)\n");
|
||||
ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
|
||||
(unsigned int)len);
|
||||
panic;
|
||||
}
|
||||
|
||||
/* Check whether destination is overflow */
|
||||
for (loop = 0U; loop < CA_IMAGESIZECHK_DEF; loop++)
|
||||
{
|
||||
if (li->load_id == size_list[loop].load_id)
|
||||
{
|
||||
if ((size_list[loop].image_adr != 0U) && (dst != size_list[loop].image_adr))
|
||||
{
|
||||
ERROR("check load area.(outside secure area)\n");
|
||||
ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
|
||||
(unsigned int)len);
|
||||
panic;
|
||||
}
|
||||
if ((size_list[loop].image_size != 0U) && (len > size_list[loop].image_size))
|
||||
{
|
||||
ERROR("check load area.(outside secure area)\n");
|
||||
ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst,
|
||||
(unsigned int)len);
|
||||
panic;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check there are no overlaps the image that will be loaded and
|
||||
the images that have already loaded. */
|
||||
overlap = NOT_OVERLAP_FLAG;
|
||||
loop = 0U;
|
||||
do
|
||||
{
|
||||
/* check overlap */
|
||||
if ((dst >= s_placed_image[loop].cx_topadd)
|
||||
&& (dst <= s_placed_image[loop].cx_endadd))
|
||||
{
|
||||
overlap = OVERLAP_FLAG;
|
||||
}
|
||||
else if ((dst_end >= s_placed_image[loop].cx_topadd)
|
||||
&& (dst_end <= s_placed_image[loop].cx_endadd))
|
||||
{
|
||||
overlap = OVERLAP_FLAG;
|
||||
}
|
||||
else if ((dst < s_placed_image[loop].cx_topadd)
|
||||
&& (s_placed_image[loop].cx_endadd < dst_end))
|
||||
{
|
||||
overlap = OVERLAP_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
loop++;
|
||||
}
|
||||
} while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG));
|
||||
|
||||
/* Check the overlap flag.
|
||||
Parameter error if overwrite occurred.
|
||||
Otherwise, add parameters of the image to be loaded into
|
||||
Placed_image. */
|
||||
if (overlap == NOT_OVERLAP_FLAG)
|
||||
{
|
||||
s_placed_image[s_num].cx_topadd = dst;
|
||||
s_placed_image[s_num].cx_endadd = dst_end;
|
||||
s_num++;
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("check load area (overlap)\n");
|
||||
ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, (unsigned int)len);
|
||||
ERROR("overlapped image is [%u]\n", (unsigned int)loop);
|
||||
ERROR("top address = 0x%x end address = 0x%x\n",
|
||||
(unsigned int)s_placed_image[loop].cx_topadd, (unsigned int)s_placed_image[loop].cx_endadd);
|
||||
panic;
|
||||
}
|
||||
}
|
||||
/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */
|
||||
|
||||
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
|
||||
uint32_t *dest_addr)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t certInfo1;
|
||||
uintptr_t pSize;
|
||||
uintptr_t pDestL;
|
||||
|
||||
/* Get key length of content certificate. */
|
||||
val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET);
|
||||
certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK;
|
||||
|
||||
/* Get the transfer address and transfer size from
|
||||
the certificate in accordance with the key length. */
|
||||
if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */
|
||||
{
|
||||
pSize = cert_addr + CERT_INFO_SIZE_OFFSET2;
|
||||
*size = mem_read32(pSize) * WORD_TO_BYTE;
|
||||
pDestL = cert_addr + CERT_INFO_DST_OFFSET2;
|
||||
*dest_addr = mem_read32(pDestL);
|
||||
}
|
||||
else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */
|
||||
{
|
||||
pSize = cert_addr + CERT_INFO_SIZE_OFFSET1;
|
||||
*size = mem_read32(pSize) * WORD_TO_BYTE;
|
||||
pDestL = cert_addr + CERT_INFO_DST_OFFSET1;
|
||||
*dest_addr = mem_read32(pDestL);
|
||||
}
|
||||
else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */
|
||||
{
|
||||
pSize = cert_addr + CERT_INFO_SIZE_OFFSET;
|
||||
*size = mem_read32(pSize) * WORD_TO_BYTE;
|
||||
pDestL = cert_addr + CERT_INFO_DST_OFFSET;
|
||||
*dest_addr = mem_read32(pDestL);
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("get_info_from_cert key size error.\n");
|
||||
panic;
|
||||
}
|
||||
}
|
||||
/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */
|
||||
|
||||
void load_start(LOAD_INFO* li)
|
||||
{
|
||||
uint32_t rtn_val = EMMC_DEV_ERR;
|
||||
uint32_t sector_count;
|
||||
uint32_t fraction;
|
||||
|
||||
/* Converted to number of sectors transferred. */
|
||||
sector_count = li->image_size >> CX_EMMC_SECTOR_SIZE_SHIFT;
|
||||
|
||||
fraction = li->image_size % CX_EMMC_SECTOR_SIZE;
|
||||
/* Add 1 if there is a fraction */
|
||||
if(0U != fraction)
|
||||
{
|
||||
sector_count += 1U;
|
||||
}
|
||||
|
||||
rtn_val = emmc_trans_data(li->part_num, (uintptr_t)(li->src_addr >> CX_EMMC_SECTOR_SIZE_SHIFT),
|
||||
(uintptr_t)li->boot_addr, sector_count);
|
||||
|
||||
if(EMMC_DEV_OK != rtn_val)
|
||||
{
|
||||
ERROR("load_start(emmc_trans_data error).\n");
|
||||
panic;
|
||||
}
|
||||
}
|
||||
/* End of function load_start(LOAD_INFO* li) */
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2022-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Region ID function header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef REGION_ID_H__
|
||||
#define REGION_ID_H__
|
||||
|
||||
#define PROTECTION_DISABLE (0U)
|
||||
#define PROTECTION_ENABLE (1U)
|
||||
|
||||
void rgid_protection_check(void);
|
||||
void ram_protection_check(void);
|
||||
|
||||
#endif /* REGION_ID_H__ */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : AXMM register header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef AXMM_REGISTER_H__
|
||||
#define AXMM_REGISTER_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* System RAM / SDRAM register base address */
|
||||
#define AXMM_BASE (0xE6780000U)
|
||||
|
||||
#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U)
|
||||
#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U)
|
||||
#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U)
|
||||
#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U)
|
||||
#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U)
|
||||
#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U)
|
||||
|
||||
static inline uint32_t get_dptdivcr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_DPTDIVCR + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_dptrgncr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_DPTRGNCR + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_dptseccr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_DPTSECCR + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_sptdivcr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_SPTDIVCR + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_sptrgncr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_SPTRGNCR + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_sptseccr_addr(uint32_t num)
|
||||
{
|
||||
return ((AXMM_SPTSECCR + (num * 4U)));
|
||||
}
|
||||
|
||||
#endif /* AXMM_REGISTER_H__ */
|
||||
@@ -0,0 +1,83 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Configuration table header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef CNF_TBL_H_
|
||||
#define CNF_TBL_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct{
|
||||
uint64_t fix;
|
||||
uint64_t be;
|
||||
} QOS_SETTING_TABLE;
|
||||
|
||||
/* For RAM protection table */
|
||||
typedef struct {
|
||||
uint32_t rw_val;
|
||||
uint32_t sec_val;
|
||||
}RAM_PROTECTION_VALUE_FORMAT;
|
||||
|
||||
typedef struct {
|
||||
uint32_t read_val;
|
||||
uint32_t write_val;
|
||||
}RTRAM_PROTECTION_VALUE_FORMAT;
|
||||
|
||||
typedef struct {
|
||||
uint32_t addr;
|
||||
RTRAM_PROTECTION_VALUE_FORMAT setting_value;
|
||||
}RTRAM_PROTECTION_STRUCTUR;
|
||||
|
||||
typedef struct {
|
||||
uint32_t addr;
|
||||
RAM_PROTECTION_VALUE_FORMAT setting_value;
|
||||
}SYSTEM_RAM_PROTECTION_STRUCTUR;
|
||||
|
||||
typedef struct {
|
||||
uint64_t addr;
|
||||
RAM_PROTECTION_VALUE_FORMAT setting_value;
|
||||
}DRAM_PROTECTION_STRUCTUR;
|
||||
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */
|
||||
#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */
|
||||
|
||||
extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX];
|
||||
extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX];
|
||||
|
||||
/* For RAM protection */
|
||||
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX];
|
||||
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX];
|
||||
extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX];
|
||||
extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX];
|
||||
|
||||
#endif /* CNF_TBL_H_ */
|
||||
@@ -0,0 +1,75 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : cpu on function header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file cpu_on.h
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 17.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
* : 09.12.2024 0.03 Remove OTP_MEM_OTPMONITOR60 register.
|
||||
* : 19.12.2024 0.04 Add definition for booting CR52 core 2.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef CPU_ON_H__
|
||||
#define CPU_ON_H__
|
||||
|
||||
#include "image_load.h"
|
||||
|
||||
#define RCAR_PWR_TARGET_CR (0U)
|
||||
#define RCAR_PWR_TARGET_CR2 (2U)
|
||||
// #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
// #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
#define RCAR_PWR_TARGET_CA (1U)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function & variable prototypes
|
||||
******************************************************************************/
|
||||
void arm_cpu_on(uint32_t target, uint32_t boot_addr);
|
||||
void adj_ca_variant_freq(void);
|
||||
|
||||
#define OTP_MEM_1_BASE (0xE61BF000U)
|
||||
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
|
||||
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
#define VARIANT_V4H_7 (0x00U)
|
||||
#define VARIANT_V4H_5 (0x01U)
|
||||
#define VARIANT_V4H_3 (0x02U)
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
#define VARIANT_V4M_7 (0x00U)
|
||||
#define VARIANT_V4M_5 (0x01U)
|
||||
#define VARIANT_V4M_3 (0x02U)
|
||||
#define VARIANT_V4M_2 (0x04U)
|
||||
#endif /* RCAR_LSI == RCAR_V4H */
|
||||
|
||||
#endif /* CPU_ON_H__ */
|
||||
@@ -0,0 +1,46 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc boot header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_boot.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_BOOT_
|
||||
#define EMMC_BOOT_
|
||||
|
||||
void emmc_initialize( void );
|
||||
|
||||
#endif /* EMMC_BOOT_ */
|
||||
@@ -0,0 +1,68 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc config header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_config.h
|
||||
* - Version : 0.03
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 18.03.2022 0.02 Delete unnecessary define
|
||||
* Delete unnecessary include file
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_CONFIG_H__
|
||||
#define EMMC_CONFIG_H__
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
/* MMC driver config */
|
||||
#define EMMC_RCA (1U) /* RCA */
|
||||
#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
|
||||
#define EMMC_CMD_MAX (60U) /* Don't change. */
|
||||
|
||||
/* etc */
|
||||
#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U)
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
#endif /* #ifndef EMMC_CONFIG_H__ */
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc def header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_def.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_DEF_H__
|
||||
#define EMMC_DEF_H__
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include "emmc_std.h"
|
||||
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
extern st_mmc_base mmc_drv_obj;
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* eMMC driver API */
|
||||
EMMC_ERROR_CODE emmc_init(void);
|
||||
EMMC_ERROR_CODE emmc_terminate(void);
|
||||
EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode);
|
||||
EMMC_ERROR_CODE emmc_mount(void);
|
||||
EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq);
|
||||
EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg);
|
||||
EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id);
|
||||
EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags);
|
||||
uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom);
|
||||
|
||||
|
||||
/* interrupt service */
|
||||
uint32_t emmc_interrupt(void);
|
||||
|
||||
|
||||
/* send command API */
|
||||
EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response);
|
||||
void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg);
|
||||
void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual,
|
||||
uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
|
||||
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg);
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
#endif /* #define EMMC_DEF_H__ */
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc HW Layer header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_hal.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_HAL_H__
|
||||
#define EMMC_HAL_H__
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include <types.h>
|
||||
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
/* Memory card response types */
|
||||
#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU)
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* memory access operation */
|
||||
typedef enum
|
||||
{
|
||||
HAL_MEMCARD_READ = 0U, /**< read */
|
||||
HAL_MEMCARD_WRITE = 1U /**< write */
|
||||
} HAL_MEMCARD_OPERATION;
|
||||
|
||||
/* Type of data width on memorycard bus */
|
||||
typedef enum
|
||||
{
|
||||
HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
|
||||
HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
|
||||
HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
|
||||
} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
|
||||
|
||||
/* mode of data transfer */
|
||||
typedef enum
|
||||
{
|
||||
HAL_MEMCARD_DMA = 0U,
|
||||
HAL_MEMCARD_NOT_DMA = 1U
|
||||
} HAL_MEMCARD_DATA_TRANSFER_MODE;
|
||||
|
||||
|
||||
/* Memory card response types. */
|
||||
typedef enum hal_memcard_response_type
|
||||
{
|
||||
HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
|
||||
HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
|
||||
HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
|
||||
HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
|
||||
HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
|
||||
HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
|
||||
HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
|
||||
HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
|
||||
HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
|
||||
HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
|
||||
} HAL_MEMCARD_RESPONSE_TYPE;
|
||||
|
||||
|
||||
/* Memory card command types. */
|
||||
typedef enum hal_memcard_command_type
|
||||
{
|
||||
HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
|
||||
HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
|
||||
HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
|
||||
HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
|
||||
HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
|
||||
HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
|
||||
} HAL_MEMCARD_COMMAND_TYPE;
|
||||
|
||||
/* Type of memory card */
|
||||
typedef enum hal_memcard_command_card_type
|
||||
{
|
||||
HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
|
||||
HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
|
||||
HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
|
||||
HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
|
||||
} HAL_MEMCARD_COMMAND_CARD_TYPE;
|
||||
|
||||
/* Memory card application command. */
|
||||
typedef enum hal_memcard_command_app_norm
|
||||
{
|
||||
HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
|
||||
HAL_MEMCARD_COMMAND_APP = 0x20000U,
|
||||
HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
|
||||
} HAL_MEMCARD_COMMAND_APP_NORM;
|
||||
|
||||
|
||||
/* Memory card command codes. */
|
||||
typedef enum
|
||||
{
|
||||
/* class 0 and class 1 */
|
||||
CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
|
||||
CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
|
||||
CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
|
||||
CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
|
||||
CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
|
||||
CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
|
||||
CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
|
||||
CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
|
||||
CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
|
||||
CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
|
||||
ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
|
||||
CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
|
||||
CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
|
||||
CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
|
||||
CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
|
||||
CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
|
||||
CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
|
||||
CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
|
||||
CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
|
||||
CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
|
||||
CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */
|
||||
CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
|
||||
ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
|
||||
CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
|
||||
CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
|
||||
|
||||
/* class 2 */
|
||||
CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
|
||||
CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
|
||||
CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
|
||||
CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
|
||||
/* class 3 */
|
||||
CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
|
||||
CMD21 = 21, /* CMD21 */
|
||||
CMD22 = 22, /* CMD22 */
|
||||
ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
|
||||
|
||||
/* class 4 */
|
||||
CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */
|
||||
|
||||
} HAL_MEMCARD_COMMAND;
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
#endif /* EMMC_HAL_H__ */
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc multi boot header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_multiboot.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_MULTIBOOT_H_
|
||||
#define EMMC_MULTIBOOT_H_
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
/* EMMC */
|
||||
#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */
|
||||
#define EMMC_DEV_ERR (0xFFFFFFFFU)
|
||||
#define EMMC_DEV_ERR_HW (0x00000004U)
|
||||
#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U)
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize);
|
||||
/* ******************************** END ************************************ */
|
||||
#endif /* #ifndef EMMC_MULTIBOOT_H_*/
|
||||
@@ -0,0 +1,174 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc register header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_register.h
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 24.10.2022 0.02 SDIF_MODE register to support HS200/400
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_REGISTERS_H__
|
||||
#define EMMC_REGISTERS_H__
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include <rcar_register.h>
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
/* MMC0 channel */
|
||||
#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */
|
||||
|
||||
#define SD_CMD (MMC0_SD_BASE + 0x0000U)
|
||||
#define SD_ARG (MMC0_SD_BASE + 0x0010U)
|
||||
#define SD_STOP (MMC0_SD_BASE + 0x0020U)
|
||||
#define SD_SECCNT (MMC0_SD_BASE + 0x0028U)
|
||||
#define SD_RSP10 (MMC0_SD_BASE + 0x0030U)
|
||||
#define SD_RSP32 (MMC0_SD_BASE + 0x0040U)
|
||||
#define SD_RSP54 (MMC0_SD_BASE + 0x0050U)
|
||||
#define SD_RSP76 (MMC0_SD_BASE + 0x0060U)
|
||||
#define SD_INFO1 (MMC0_SD_BASE + 0x0070U)
|
||||
#define SD_INFO2 (MMC0_SD_BASE + 0x0078U)
|
||||
#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U)
|
||||
#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U)
|
||||
#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U)
|
||||
#define SD_SIZE (MMC0_SD_BASE + 0x0098U)
|
||||
#define SD_OPTION (MMC0_SD_BASE + 0x00A0U)
|
||||
#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U)
|
||||
#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U)
|
||||
#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U)
|
||||
#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U)
|
||||
#define SOFT_RST (MMC0_SD_BASE + 0x0380U)
|
||||
#define HOST_MODE (MMC0_SD_BASE + 0x0390U)
|
||||
#define SDIF_MODE (MMC0_SD_BASE + 0x0398U)
|
||||
#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U)
|
||||
#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U)
|
||||
#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U)
|
||||
#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U)
|
||||
#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U)
|
||||
#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U)
|
||||
#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U)
|
||||
#define SCC_DTCNTL (MMC0_SD_BASE + 0x1000U)
|
||||
#define SCC_TAPSET (MMC0_SD_BASE + 0x1008U)
|
||||
#define SCC_DT2FF (MMC0_SD_BASE + 0x1010U)
|
||||
#define SCC_CKSEL (MMC0_SD_BASE + 0x1018U)
|
||||
#define SCC_SMPCMP (MMC0_SD_BASE + 0x1030U)
|
||||
#define SCC_TMPPORT2 (MMC0_SD_BASE + 0x1038U)
|
||||
|
||||
/* SD_INFO1 Registers */
|
||||
#define SD_INFO1_INFO2 (0x00000004U) /* Access end*/
|
||||
#define SD_INFO1_INFO0 (0x00000001U) /* Response end*/
|
||||
|
||||
/* SD_INFO2 Registers */
|
||||
#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy*/
|
||||
#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable*/
|
||||
#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable*/
|
||||
#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0*/
|
||||
#define SD_INFO2_ALL_ERR (0x0000807FU)
|
||||
#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */
|
||||
|
||||
/* DM_INFO1 Registers */
|
||||
#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */
|
||||
#define DM_CM_INFO_DTRANEND1 (0x00100000U) /* DMAC Channel 1 Transfer End */
|
||||
|
||||
/* DM_INFO2 Registers */
|
||||
#define DM_CM_INFO2_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Error */
|
||||
#define DM_CM_INFO2_DTRANEND1 (0x00020000U) /* DMAC Channel 1 Error */
|
||||
|
||||
/* SOFT_RST */
|
||||
#define SOFT_RST_SDRST (0x00000001U)
|
||||
|
||||
/* SD_CLK_CTRL */
|
||||
#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU)
|
||||
#define SD_CLK_WRITE_MASK (0x000003FFU)
|
||||
|
||||
/* SD_OPTION */
|
||||
#define SD_OPTION_WIDTH (0x00008000U)
|
||||
#define SD_OPTION_WIDTH8 (0x00002000U)
|
||||
#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U)
|
||||
|
||||
|
||||
/* MMC Clock Frequency
|
||||
* 200MHz * 1/x = output clock
|
||||
*/
|
||||
#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */
|
||||
#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode*/
|
||||
#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz*/
|
||||
#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz*/
|
||||
#define MMC_200MHZ (1U) /* 200MHz * 1/1 = 200 MHz HS200/HS400 mode 200Mhz*/
|
||||
|
||||
#define MMC_FREQ_52MHZ (52000000U)
|
||||
#define MMC_FREQ_26MHZ (26000000U)
|
||||
#define MMC_FREQ_20MHZ (20000000U)
|
||||
|
||||
/* MMC Clock DIV */
|
||||
#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */
|
||||
#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
|
||||
|
||||
/* DM_CM_DTRAN_MODE */
|
||||
#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream*/
|
||||
#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream*/
|
||||
#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U)
|
||||
|
||||
/* CC_EXT_MODE */
|
||||
#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */
|
||||
#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */
|
||||
|
||||
/* DM_CM_INFO_MASK */
|
||||
#define DM_CM_INFO_MASK_CLEAR (0xFFEEFEFEU)
|
||||
#define DM_CM_INFO_CH0_ENABLE (0x00010001U)
|
||||
#define DM_CM_INFO_CH1_ENABLE (0x00100001U)
|
||||
|
||||
/* DM_CM_INFO2_MASK */
|
||||
#define DM_CM_INFO2_MASK_CLEAR (0xFFFCFFFEU)
|
||||
#define DM_CM_INFO2_CH0_ENABLE (0x00010001U)
|
||||
#define DM_CM_INFO2_CH1_ENABLE (0x00020001U)
|
||||
|
||||
/* DM_DTRAN_ADDR */
|
||||
#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U)
|
||||
|
||||
/*DM_CM_DTRAN_CTRL */
|
||||
#define DM_CM_DTRAN_CTRL_START (0x00000001U)
|
||||
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
#endif /* EMMC_REGISTERS_H__ */
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
@@ -0,0 +1,312 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc std header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_std.h
|
||||
* - Version : 0.03
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 24.10.2022 0.02 Add supports for HS200/400
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EMMC_STD_H__
|
||||
#define EMMC_STD_H__
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_registers.h"
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
/*CSD register Macros */
|
||||
#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122))
|
||||
#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96))
|
||||
|
||||
/* for sector access */
|
||||
#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
|
||||
#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U)
|
||||
#define EMMC_SECTOR_SIZE (512U)
|
||||
#define EMMC_BLOCK_LENGTH (512U)
|
||||
#define EMMC_BLOCK_LENGTH_DW (128U)
|
||||
|
||||
/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
|
||||
typedef enum
|
||||
{
|
||||
EMMC_ERR = 0U, /**< unknown error */
|
||||
EMMC_SUCCESS , /**< OK */
|
||||
EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */
|
||||
EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */
|
||||
EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */
|
||||
EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */
|
||||
EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */
|
||||
EMMC_ERR_CMD_CRC , /**< command CRC error */
|
||||
EMMC_ERR_DATA_CRC , /**< data CRC error */
|
||||
EMMC_ERR_PARAM , /**< parameter error */
|
||||
EMMC_ERR_RESPONSE , /**< response error */
|
||||
EMMC_ERR_RESPONSE_BUSY , /**< response busy error */
|
||||
EMMC_ERR_TRANSFER , /**< data transfer error */
|
||||
EMMC_ERR_READ_SECTOR , /**< read sector error */
|
||||
EMMC_ERR_WRITE_SECTOR , /**< write sector error */
|
||||
EMMC_ERR_STATE , /**< state error */
|
||||
EMMC_ERR_TIMEOUT , /**< timeout error */
|
||||
EMMC_ERR_ILLEGAL_CARD , /**< illegal card */
|
||||
EMMC_ERR_CARD_BUSY , /**< Busy state */
|
||||
EMMC_ERR_CARD_STATE , /**< card state error */
|
||||
EMMC_ERR_SET_TRACE , /**< trace information error */
|
||||
EMMC_ERR_FROM_TIMER , /**< Timer error */
|
||||
EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */
|
||||
EMMC_ERR_CARD_POWER , /**< card power fail */
|
||||
EMMC_ERR_ERASE_SECTOR , /**< erase sector error */
|
||||
EMMC_ERR_INFO2 , /**< exec cmd error info2 */
|
||||
RCAR_ERR /**< Error judged by R-Car register */
|
||||
|
||||
} EMMC_ERROR_CODE;
|
||||
|
||||
/* Error code judged by R-car register or eMMC return*/
|
||||
#define EMMC_TUNING_FAIL (0U) /* Fail judged by eMMC return*/
|
||||
#define TUNING_SUCCESS (1U) /* Tuning success */
|
||||
#define RCAR_TUNING_FAIL (2U) /* Fail judged by R-car register*/
|
||||
|
||||
/* Response */
|
||||
/** R1 */
|
||||
#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */
|
||||
#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
|
||||
#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */
|
||||
#define EMMC_R1_READY (0x00000100U) /* bit8 */
|
||||
#define EMMC_R1_STATE_SHIFT (9U)
|
||||
|
||||
/** R4 */
|
||||
#define EMMC_R4_STATUS (0x00008000U)
|
||||
|
||||
/** CSD */
|
||||
#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */
|
||||
#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */
|
||||
#define EMMC_TRANSPEED_MULT_SHIFT (3U)
|
||||
|
||||
/** OCR */
|
||||
#define EMMC_HOST_OCR_VALUE (0x40FF8080U)
|
||||
#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */
|
||||
#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */
|
||||
#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U)
|
||||
|
||||
/** EXT_CSD */
|
||||
#define EMMC_EXT_CSD_CARD_TYPE (196U)
|
||||
#define EMMC_EXT_CSD_PARTITION_CONFIG (179U)
|
||||
#define EMMC_EXT_CSD_PWR_CL_DDR_200_360 (253U) /* Power class for 200MHz, DDR at VCC= 3.6V */
|
||||
#define EMMC_EXT_CSD_PWR_CL_200_195 (237U) /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */
|
||||
#define EMMC_EXT_CSD_PWR_CL_26_195 (201U) /* Power class for 26MHz at 1.95V 1 R */
|
||||
#define EMMC_EXT_CSD_PWR_CL_52_195 (200U) /* Power class for 52MHz at 1.95V 1 R */
|
||||
|
||||
#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U)
|
||||
#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U)
|
||||
#define EMMC_EXT_CSD_CARD_TYPE_200MHZ (0x10U)
|
||||
#define EMMC_EXT_CSD_CARD_TYPE_400MHZ (0x40U)
|
||||
|
||||
/** SWITCH (CMD6) argument */
|
||||
#define EXTCSD_ACCESS_BYTE (0x03000000U) /* H'03000000 */
|
||||
|
||||
#define BUS_WIDTH_ADD (183U<<16U) /* H'00b70000 */
|
||||
#define HS_TIMING_ADD (185U<<16U) /* H'00b90000 */
|
||||
#define POW_CLASS_ADD (187U<<16U) /* H'00bb0000 */
|
||||
|
||||
#define BUS_WIDTH_1 (0U<<8U) /* H'00000000 */
|
||||
#define BUS_WIDTH_8 (2U<<8U) /* H'00000200 */
|
||||
#define BUS_WIDTH_8_DDR (6U<<8U) /* H'00000400 */
|
||||
|
||||
#define HS_TIMING_1 (1U<<8U) /* H'00000100 */
|
||||
#define HS_TIMING_HS200 (2U<<8U) /* H'00000200 */
|
||||
#define HS_TIMING_HS400 (3U<<8U) /* H'00000300 */
|
||||
|
||||
#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
|
||||
#define EMMC_SWITCH_HS200 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200) /**< H'03b90200 */
|
||||
#define EMMC_SWITCH_HS400 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400) /**< H'03b90300 */
|
||||
|
||||
#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
|
||||
#define EMMC_SWITCH_BUS_WIDTH_8_DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR) /**< H'03b70600 */
|
||||
|
||||
|
||||
#define EMMC_SWITCH_PARTITION_CONFIG (0x03B30000UL) /**< Partition config = 0x00 */
|
||||
|
||||
/** for st_mmc_base */
|
||||
#define EMMC_MAX_RESPONSE_LENGTH (17U)
|
||||
#define EMMC_MAX_CID_LENGTH (16U)
|
||||
#define EMMC_MAX_CSD_LENGTH (16U)
|
||||
#define EMMC_MAX_EXT_CSD_LENGTH (512U)
|
||||
|
||||
/* speed mode */
|
||||
#define TIMING_HIGH_SPEED_OFF (0U)
|
||||
#define TIMING_HIGH_SPEED (1U)
|
||||
#define TIMING_HS200 (2U)
|
||||
#define TIMING_HS400 (3U)
|
||||
|
||||
/* MMC Clock Frequency */
|
||||
/* 200MHz * 1/x = output clock */
|
||||
#define HS400_50MHZ (8U) /* 400MHz * 1/8 = 50MHz */
|
||||
#define HS400_200MHZ (2U) /* 400MHz * 1/2 = 200MHz */
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* Partition id */
|
||||
typedef enum
|
||||
{
|
||||
PARTITION_ID_USER = 0x0, /**< User Area */
|
||||
PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
|
||||
PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
|
||||
PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
|
||||
PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
|
||||
PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
|
||||
PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
|
||||
PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
|
||||
PARTITION_ID_MASK = 0x7 /**< [2:0] */
|
||||
} EMMC_PARTITION_ID;
|
||||
|
||||
/* card state in R1 response [12:9] */
|
||||
typedef enum
|
||||
{
|
||||
EMMC_R1_STATE_IDLE = 0,
|
||||
EMMC_R1_STATE_READY,
|
||||
EMMC_R1_STATE_IDENT,
|
||||
EMMC_R1_STATE_STBY,
|
||||
EMMC_R1_STATE_TRAN,
|
||||
EMMC_R1_STATE_DATA,
|
||||
EMMC_R1_STATE_RCV,
|
||||
EMMC_R1_STATE_PRG,
|
||||
EMMC_R1_STATE_DIS,
|
||||
EMMC_R1_STATE_BTST,
|
||||
EMMC_R1_STATE_SLEP
|
||||
} EMMC_R1_STATE;
|
||||
|
||||
typedef enum{
|
||||
ESTATE_BEGIN = 0,
|
||||
ESTATE_ISSUE_CMD,
|
||||
ESTATE_NON_RESP_CMD,
|
||||
ESTATE_RCV_RESP,
|
||||
ESTATE_RCV_RESPONSE_BUSY,
|
||||
ESTATE_CHECK_RESPONSE_COMPLETE,
|
||||
ESTATE_DATA_TRANSFER,
|
||||
ESTATE_DATA_TRANSFER_COMPLETE,
|
||||
ESTATE_ACCESS_END,
|
||||
ESTATE_TRANSFER_ERROR,
|
||||
ESTATE_ERROR,
|
||||
ESTATE_END
|
||||
}EMMC_INT_STATE;
|
||||
|
||||
/* eMMC boot driver error information */
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
|
||||
volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
|
||||
volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */
|
||||
volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */
|
||||
volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */
|
||||
volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */
|
||||
} st_error_info;
|
||||
|
||||
|
||||
/* Command information */
|
||||
typedef struct
|
||||
{
|
||||
HAL_MEMCARD_COMMAND cmd; /**< Command information */
|
||||
uint32_t arg; /**< argument */
|
||||
HAL_MEMCARD_OPERATION dir; /**< direction */
|
||||
uint32_t hw; /**< H/W dependence. SD_CMD register value. */
|
||||
} st_command_info;
|
||||
|
||||
|
||||
/* MMC driver base */
|
||||
typedef struct
|
||||
{
|
||||
st_error_info error_info; /**< error information */
|
||||
st_command_info cmd_info; /**< command information */
|
||||
|
||||
/* for data transfer */
|
||||
uint32_t *buff_address_virtual; /**< Dest or Src buff */
|
||||
uint32_t *buff_address_physical; /**< Dest or Src buff */
|
||||
HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */
|
||||
uint32_t trans_size; /**< transfer size for this command */
|
||||
uint32_t remain_size; /**< remain size for this command */
|
||||
uint32_t response_length; /**< response length for this command */
|
||||
|
||||
/* clock */
|
||||
uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
|
||||
uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
|
||||
uint32_t set_freq; /**< Frequency to be set. */
|
||||
|
||||
/* state flag */
|
||||
uint32_t card_power_enable; /**< True : Power ON */
|
||||
uint32_t clock_enable; /**< True : Clock ON */
|
||||
uint32_t initialize; /**< True : initialize complete. */
|
||||
uint32_t mount; /**< True : mount complete. */
|
||||
uint32_t selected; /**< True : selected card. */
|
||||
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */
|
||||
EMMC_R1_STATE current_state; /**< card state */
|
||||
volatile uint32_t during_transfer; /**< True : during transfer */
|
||||
volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
|
||||
volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
|
||||
volatile uint32_t force_terminate; /**< force terminate flag */
|
||||
volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
|
||||
|
||||
/* timeout */
|
||||
uint32_t data_timeout; /**< read and write data timeout.*/
|
||||
|
||||
/* interrupt */
|
||||
volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
|
||||
volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
|
||||
volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
|
||||
volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
|
||||
|
||||
/* response */
|
||||
uint32_t *response; /**< pointer to buffer for executing command. */
|
||||
uint32_t r1_card_status; /**< R1 response data */
|
||||
uint32_t r3_ocr; /**< R3 response data */
|
||||
uint32_t r4_resp; /**< R4 response data */
|
||||
uint32_t r5_resp; /**< R5 response data */
|
||||
|
||||
/* Card registers (4byte align) */
|
||||
uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */
|
||||
uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */
|
||||
uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */
|
||||
uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */
|
||||
|
||||
/* SDHI base address */
|
||||
uintptr_t base_address;
|
||||
} st_mmc_base;
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
#endif /* EMMC_STD_H__ */
|
||||
/* EMMC_STD_H__ */
|
||||
@@ -0,0 +1,417 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : GIC Control Function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file gic.h
|
||||
* - Version : 0.04
|
||||
* @brief Controls GIC-600 registers and interrupts.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.08.2022 0.01 First Release
|
||||
* : 20.09.2022 0.02 Set ChildrenAsleep of GICR_WAKER to 1 and end processing
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 04.04.2023 0.04 Removed stdio.h.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef GIC_H
|
||||
#define GIC_H
|
||||
|
||||
/*******************************************************************************
|
||||
** Include Section **
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
** Version Information **
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
** Global Symbols **
|
||||
*******************************************************************************/
|
||||
/* GIC base */
|
||||
#define GICD_BASE (0xF1000000UL)
|
||||
#define GICR_BASE (GICD_BASE + 0x60000U)
|
||||
|
||||
/* Generic Interrupt Controller Distributor (GICD) */
|
||||
#define GICD_CTLR *((volatile uint32_t *)(GICD_BASE + 0x000U))
|
||||
#define GICD_IGROUPR(n) *((volatile uint32_t *)(GICD_BASE + 0x080U + 4U*(n)))
|
||||
#define GICD_ISENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x100U + 4U*(n)))
|
||||
#define GICD_ICENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x180U + 4U*(n)))
|
||||
#define GICD_ISPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x200U + 4U*(n)))
|
||||
#define GICD_ICPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x280U + 4U*(n)))
|
||||
#define GICD_IPRIORITYR(n) *((volatile uint32_t *)(GICD_BASE + 0x400U + 4U*(n)))
|
||||
#define GICD_ICFGR(n) *((volatile uint32_t *)(GICD_BASE + 0xC00U + 4U*(n)))
|
||||
#define GICD_IGRPMODR(n) *((volatile uint32_t *)(GICD_BASE + 0xD00U + 4U*(n)))
|
||||
#define GICD_IROUTER(n) *((volatile uint64_t *)(GICD_BASE + 0x6000U + 8U*(n)))
|
||||
|
||||
/* Generic Interrupt Controller Redistributor (GICR) */
|
||||
#define GICR_CTLR *((volatile uint32_t *)(GICR_BASE + 0x0000U))
|
||||
#define GICR_WAKER *((volatile uint32_t *)(GICR_BASE + 0x0014U))
|
||||
#define GICR_PWRR *((volatile uint32_t *)(GICR_BASE + 0x0024U))
|
||||
|
||||
#define CHILDREN_ASLEEP (1U << 2U)
|
||||
#define PROCESSOR_SLEEP (1U << 1U)
|
||||
#define RDPOWER_DOWN (1U << 0U)
|
||||
|
||||
/*******************************************************************************
|
||||
** Global Data Types **
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
** Function Prototypes **
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
** Macro **
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions for CPU system register interface to GICv3
|
||||
******************************************************************************/
|
||||
/* ICC_SRE_EL3 */
|
||||
#define ICC_SRE_EN_BIT (8U)
|
||||
#define ICC_SRE_DIB_BIT (4U)
|
||||
#define ICC_SRE_DFB_BIT (2U)
|
||||
#define ICC_SRE_SRE_BIT (1U)
|
||||
|
||||
/* SCR_EL3 */
|
||||
#define SCR_NS_BIT (1U)
|
||||
|
||||
/* Affinity Leve mask value */
|
||||
#define AFFINITY0_MASK (0xFFU)
|
||||
#define AFFINITY1_MASK (0xFF00U)
|
||||
#define AFFINITY2_MASK (0xFF0000U)
|
||||
#define AFFINITY3_MASK (0xFF00000000U)
|
||||
#define IRM_OFF (0x80000000U)
|
||||
|
||||
/* Get ICC_IAR0 */
|
||||
static inline uint64_t get_ICC_IAR0(void)
|
||||
{
|
||||
uint64_t value = 0U;
|
||||
__asm__ volatile("mrs %0, S3_0_c12_c8_0" : "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
/* Set ICC_PMR */
|
||||
static inline void set_ICC_PMR(uint64_t value)
|
||||
{
|
||||
__asm__ volatile ("msr S3_0_C4_C6_0, %0" :: "r" (value));
|
||||
}
|
||||
|
||||
/* Set ICC_IGRPEN0 */
|
||||
static inline void set_ICC_IGRPEN0(uint64_t value)
|
||||
{
|
||||
__asm__ volatile ("msr S3_0_c12_c12_6, %0" :: "r" (value));
|
||||
}
|
||||
|
||||
/* Set ICC_SRE_EL1 */
|
||||
static inline void set_ICC_SRE_EL1(uint64_t value)
|
||||
{
|
||||
__asm__ volatile ("msr S3_0_C12_C12_5, %0" :: "r" (value));
|
||||
}
|
||||
|
||||
/* Get ICC_SRE_EL3 */
|
||||
static inline uint64_t get_ICC_SRE_EL3(void)
|
||||
{
|
||||
uint64_t value = 0U;
|
||||
__asm__ volatile("mrs %0, S3_6_C12_C12_5" : "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
/* Set ICC_SRE_EL3 */
|
||||
static inline void set_ICC_SRE_EL3(uint64_t value)
|
||||
{
|
||||
__asm__ volatile ("msr S3_6_C12_C12_5, %0" :: "r" (value));
|
||||
}
|
||||
|
||||
/* Get MPIDR_EL1 */
|
||||
static inline uint64_t get_MPIDR_EL1(void)
|
||||
{
|
||||
uint64_t value = 0U;
|
||||
__asm__ volatile("mrs %0, mpidr_el1" : "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
/* ISB */
|
||||
static inline void GIC_isb(void)
|
||||
{
|
||||
__asm__ volatile ("isb");
|
||||
}
|
||||
|
||||
/* Enable the interrupt distributor using the GIC's CTLR register */
|
||||
static inline void GIC_EnableDistributor(void)
|
||||
{
|
||||
GICD_CTLR |= 0x31U;
|
||||
}
|
||||
|
||||
/* Disable the interrupt distributor using the GIC's CTLR register */
|
||||
static inline void GIC_DisableDistributor(void)
|
||||
{
|
||||
GICD_CTLR &= 0xFFFFFFFEU;
|
||||
}
|
||||
|
||||
/* Set the interrupt enable from the GIC's ISENABLER register */
|
||||
static inline void GIC_SetEnable(uint32_t intid, uint32_t value)
|
||||
{
|
||||
uint32_t reg = GICD_ISENABLER(intid / 32U);
|
||||
uint32_t shift = (intid % 32U);
|
||||
|
||||
reg &= (~(1U << shift));
|
||||
reg |= ( (value & 1U) << shift);
|
||||
|
||||
GICD_ISENABLER(intid / 32U) = reg;
|
||||
}
|
||||
|
||||
/* Set the interrupt disable from the GIC's ICENABLER register */
|
||||
static inline void GIC_SetClearEnable(uint32_t intid, uint32_t value)
|
||||
{
|
||||
uint32_t reg = GICD_ICENABLER(intid / 32U);
|
||||
uint32_t shift = (intid % 32U);
|
||||
|
||||
reg &= (~(1U << shift));
|
||||
reg |= ( (value & 1U) << shift);
|
||||
|
||||
GICD_ICENABLER(intid / 32U) = reg;
|
||||
}
|
||||
|
||||
/* Sets the interrupt configuration using GIC's ICFGR register */
|
||||
static inline void GIC_SetConfiguration(uint32_t intid, uint32_t int_config)
|
||||
{
|
||||
uint32_t icfgr = GICD_ICFGR(intid / 16U);
|
||||
uint32_t shift = (intid % 16U) << 1U;
|
||||
|
||||
icfgr &= (~(3U << shift));
|
||||
icfgr |= ( int_config << shift);
|
||||
|
||||
GICD_ICFGR(intid / 16U) = icfgr;
|
||||
}
|
||||
|
||||
/* Set the priority for the given interrupt in the GIC's IPRIORITYR register */
|
||||
static inline void GIC_SetPriority(uint32_t intid, uint32_t priority)
|
||||
{
|
||||
uint32_t mask = GICD_IPRIORITYR(intid / 4U);
|
||||
uint32_t shift = ((intid % 4U) * 8U);
|
||||
|
||||
mask &= (~(0xFFU << shift));
|
||||
mask |= ( (priority & 0xFFU) << shift);
|
||||
|
||||
GICD_IPRIORITYR(intid / 4U) = mask;
|
||||
}
|
||||
|
||||
/* Set the interrupt group from the GIC's IGROUPR register */
|
||||
static inline void GIC_SetGroup(uint32_t intid, uint32_t group)
|
||||
{
|
||||
uint32_t igroupr = GICD_IGROUPR(intid / 32U);
|
||||
uint32_t shift = (intid % 32U);
|
||||
|
||||
igroupr &= (~(1U << shift));
|
||||
igroupr |= ( (group & 1U) << shift);
|
||||
|
||||
GICD_IGROUPR(intid / 32U) = igroupr;
|
||||
}
|
||||
|
||||
/* Set the interrupt group from the GIC's IGRPMODR register */
|
||||
static inline void GIC_SetGrpMode(uint32_t intid, uint32_t mode)
|
||||
{
|
||||
uint32_t imode = GICD_IGRPMODR(intid / 32U);
|
||||
uint32_t shift = (intid % 32U);
|
||||
|
||||
imode &= (~(1U << shift));
|
||||
imode |= ( (mode & 1U) << shift);
|
||||
|
||||
GICD_IGRPMODR(intid / 32U) = imode;
|
||||
}
|
||||
|
||||
/* Set the interrupt routing from the GIC's IROUTER register */
|
||||
static inline void GIC_SetRouter(uint32_t intid)
|
||||
{
|
||||
uint64_t affinity = 0U;
|
||||
|
||||
/* Get Affinity level */
|
||||
affinity = get_MPIDR_EL1();
|
||||
affinity &= (AFFINITY0_MASK | AFFINITY1_MASK | AFFINITY2_MASK | AFFINITY3_MASK);
|
||||
/* Interrupt routing mode bit OFF */
|
||||
affinity &= (~(IRM_OFF));
|
||||
|
||||
GICD_IROUTER(intid) = affinity;
|
||||
}
|
||||
|
||||
/* Get power register value from the GIC's GICR_PWRR register */
|
||||
static inline uint32_t GIC_Getpwwr(void)
|
||||
{
|
||||
return (GICR_PWRR);
|
||||
}
|
||||
|
||||
/* Set power register value from the GIC's GICR_PWRR register */
|
||||
static inline void GIC_Setpwwr(uint32_t set_value)
|
||||
{
|
||||
GICR_PWRR = set_value;
|
||||
}
|
||||
|
||||
/* Get power management cotrol register from the GIC's GICR_WAKER register */
|
||||
static inline uint32_t GIC_Getwaker(void)
|
||||
{
|
||||
return (GICR_WAKER);
|
||||
}
|
||||
|
||||
/* Set power management cotrol register from the GIC's GICR_WAKER register */
|
||||
static inline void GIC_Setwaker(uint32_t set_value)
|
||||
{
|
||||
GICR_WAKER = set_value;
|
||||
}
|
||||
|
||||
/* Enables the given interrupt using GIC's ISENABLER register */
|
||||
static inline void GIC_EnableFIQ(uint32_t intid)
|
||||
{
|
||||
|
||||
/* Disable interrupt forwarding */
|
||||
GIC_DisableDistributor();
|
||||
|
||||
/* Set level-sensitive */
|
||||
GIC_SetConfiguration(intid, 0U);
|
||||
|
||||
/* Set priority */
|
||||
GIC_SetPriority(intid, 0U);
|
||||
|
||||
/* Set group 0 (secure) */
|
||||
GIC_SetGroup(intid, 0U);
|
||||
|
||||
/* Set group 0 (secure) */
|
||||
GIC_SetGrpMode(intid, 0U);
|
||||
|
||||
/* Enable distributor */
|
||||
GIC_EnableDistributor();
|
||||
|
||||
/* Enable the SPI interrupt */
|
||||
GIC_SetEnable(intid, 1U);
|
||||
|
||||
/* Set the interrupt routing */
|
||||
GIC_SetRouter(intid);
|
||||
}
|
||||
|
||||
/* Enable the interrupt redistributor wakeup */
|
||||
static inline void GIC_WakeupRedistributor(void)
|
||||
{
|
||||
uint32_t get_value = 0U;
|
||||
uint32_t set_value = 0U;
|
||||
|
||||
get_value = GIC_Getpwwr();
|
||||
set_value = get_value & ~(RDPOWER_DOWN);
|
||||
GIC_Setpwwr(set_value);
|
||||
|
||||
get_value = GIC_Getwaker();
|
||||
set_value = get_value & ~(PROCESSOR_SLEEP);
|
||||
GIC_Setwaker(set_value);
|
||||
|
||||
do
|
||||
{
|
||||
get_value = GIC_Getwaker();
|
||||
}while((get_value & CHILDREN_ASLEEP) == CHILDREN_ASLEEP);
|
||||
}
|
||||
|
||||
/* Enable the CPU's interrupt interface */
|
||||
static inline void GIC_EnableInterface(void)
|
||||
{
|
||||
uint64_t reg = 0U;
|
||||
uint64_t icc_sre_el3 = 0U;
|
||||
|
||||
/* Disable the legacy interrupt bypass */
|
||||
icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
|
||||
|
||||
reg = get_ICC_SRE_EL3();
|
||||
set_ICC_SRE_EL3(reg | icc_sre_el3);
|
||||
|
||||
set_ICC_SRE_EL1(ICC_SRE_SRE_BIT);
|
||||
GIC_isb();
|
||||
|
||||
set_ICC_IGRPEN0(1U); /* enable interface grp0 */
|
||||
GIC_isb();
|
||||
}
|
||||
|
||||
/* Disable the CPU's interrupt interface */
|
||||
static inline void GIC_DisableInterface(uint32_t intid)
|
||||
{
|
||||
uint32_t get_value = 0U;
|
||||
uint32_t set_value = 0U;
|
||||
|
||||
/* Clear Enable the SPI interrupt */
|
||||
GIC_SetClearEnable(intid, 1U);
|
||||
|
||||
/* Set ChildrenAsleep of GICR_WAKER to 1 and end processing */
|
||||
get_value = GIC_Getwaker();
|
||||
set_value = get_value | PROCESSOR_SLEEP;
|
||||
GIC_Setwaker(set_value);
|
||||
|
||||
do
|
||||
{
|
||||
get_value = GIC_Getwaker();
|
||||
}while((get_value & CHILDREN_ASLEEP) != CHILDREN_ASLEEP);
|
||||
|
||||
}
|
||||
|
||||
/* Read the CPU's IAR register */
|
||||
static inline uint32_t GIC_AcknowledgePending(void)
|
||||
{
|
||||
return (uint32_t)(get_ICC_IAR0());
|
||||
}
|
||||
|
||||
/* Set the interrupt priority mask using CPU's PMR register */
|
||||
static inline void GIC_SetInterfacePriorityMask(uint64_t priority)
|
||||
{
|
||||
/* Specify F8. 32 priority levels are bit0-2 invalid */
|
||||
set_ICC_PMR(priority << 3U);
|
||||
}
|
||||
|
||||
/* Initialize and enable the GIC */
|
||||
static inline void GIC_Enable(void)
|
||||
{
|
||||
GIC_WakeupRedistributor();
|
||||
/* Enable interface */
|
||||
GIC_EnableInterface();
|
||||
/* Set priority mask */
|
||||
GIC_SetInterfacePriorityMask(0xFFUL);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function **
|
||||
*******************************************************************************/
|
||||
/* Interrupt configuration */
|
||||
#define Interrupt_Config(void) GIC_Enable(void)
|
||||
|
||||
/* Enable */
|
||||
#define Interrupt_Enable(intid) GIC_EnableFIQ((uint32_t)intid)
|
||||
|
||||
/* Disable */
|
||||
#define Interrupt_Disable(intid) GIC_DisableInterface((uint32_t)intid)
|
||||
|
||||
#endif /* GIC_H */
|
||||
/*******************************************************************************
|
||||
** End of File **
|
||||
*******************************************************************************/
|
||||
@@ -0,0 +1,61 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : HSCIF register header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file hscif_register.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef HSCIF_REGISTER_H_
|
||||
#define HSCIF_REGISTER_H_
|
||||
|
||||
#include <rcar_register.h>
|
||||
|
||||
/* HSCIF0 base address */
|
||||
/* 0xE6540000U */
|
||||
#define HSCIF0_BASE (BASE_HSCIF_ADDR)
|
||||
|
||||
#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */
|
||||
#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */
|
||||
#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */
|
||||
#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */
|
||||
#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */
|
||||
#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */
|
||||
#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */
|
||||
#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */
|
||||
#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */
|
||||
#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */
|
||||
|
||||
#endif /* HSCIF_REGISTER_H_ */
|
||||
@@ -0,0 +1,246 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Image load function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file image_load.h
|
||||
* - Version : 0.09
|
||||
* @brief Access protection setting driver.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 10.02.2022 0.02 Change the number of CA programs
|
||||
* : 17.02.2022 0.03 Support AArch32
|
||||
* : 18.05.2022 0.04 Integrated LOAD_INFO
|
||||
* Defined value integration
|
||||
* Remove unused define values
|
||||
* Changed to processing for each device
|
||||
* Change structure member name
|
||||
* Remove LOGICAL_CONTENT_CERT_ADDR
|
||||
* Add get_logic_cont_cert_addr
|
||||
* Change the argument type of get_src_addr_offset_in_cert
|
||||
* Added argument check
|
||||
* Remove unnecessary macros
|
||||
* Add argument of load_init()
|
||||
* Change for memory map update
|
||||
* : 16.06.2022 0.05 Change log output
|
||||
* Support secure boot for S4
|
||||
* : 31.10.2022 0.06 License notation change.
|
||||
* : 21.08.2023 0.07 Add support for V4M.
|
||||
* : 19.12.2024 0.08 Add definitions for RTOS#1 and RTOS#2.
|
||||
* : 26.05.2025 0.09 Change address and size of CA program2.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef LOAD_IMAGE_H_
|
||||
#define LOAD_IMAGE_H_
|
||||
|
||||
#include "log.h"
|
||||
|
||||
/* define */
|
||||
/* For Build Option RTOS_LOAD_NUM */
|
||||
#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */
|
||||
#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
|
||||
|
||||
/* For Build Option OPTEE_LOAD_ENABLE */
|
||||
#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */
|
||||
#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */
|
||||
|
||||
/* DRAM address */
|
||||
#define DRAM_BASE (0x40000000U)
|
||||
#define DRAM_SIZE (0x80000000U)
|
||||
#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
|
||||
|
||||
/* RT-SRAM */
|
||||
/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */
|
||||
#define RTSRAM_BASE (0xEB200000U)
|
||||
#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */
|
||||
#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
|
||||
|
||||
/* RT-VRAM */
|
||||
/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */
|
||||
#define RTVRAM_BASE (0xE2000000U)
|
||||
#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */
|
||||
#define RTVRAM_VBUF_28M (28U) /* 28MB */
|
||||
#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */
|
||||
#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */
|
||||
#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U)
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
#define RTVRAM_8WAY_28M_SRAM_SIZE (0x00010000U) /* 64KiB */
|
||||
#define RTVRAM_SRAM_TOP (RTVRAM_BASE)
|
||||
#define RTVRAM_SRAM_END (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U) /* 0xE2000000 - 0xE200FFFF */
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
|
||||
/* System RAM */
|
||||
#define SYSRAM_BASE (0xE6300000U)
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define SYSRAM_SIZE (384U * 1024U) /* 384KB */
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U)
|
||||
|
||||
/* Cx Loader */
|
||||
#define IPL_TOP (0xE6300000U)
|
||||
#define IPL_SIZE (0x00030000U) /* 192KiB */
|
||||
#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U)
|
||||
|
||||
/* Certificate size */
|
||||
#define CONTENT_CERT_OFFSET (0x00006000U) /* certificate top offset */
|
||||
#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header area size(4KiB) */
|
||||
#define CONTENT_CERT_DST_SIZE (0x00000800U) /* content cert dst size */
|
||||
#define KEY_CERT_SIZE (0x00002000U) /* Key cert area size(8KiB) */
|
||||
|
||||
/* Load ID */ //Modify HKL
|
||||
#define RTOS_A_ID (2U) /* 2:RTOS#0 A*/
|
||||
#define CA_PROGRAM_A_ID (3U) /* 3:CX 2nd IPL A*/
|
||||
#define RTOS_B_ID (4U) /* 4:RTOS#0 B*/
|
||||
#define CA_PROGRAM_B_ID (5U) /* 5:CX 2nd IPL B*/
|
||||
|
||||
#define CA_OPTIONAL_ID (6U)
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
#define RTOS1_ID (16U) /* 16:RTOS#1 */
|
||||
#define RTOS2_ID (17U) /* 17:RTOS#2 */
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
|
||||
/* Number of Max loading image */
|
||||
#define CA_MAX_IMAGE (8U) /* CA Load program MAX image num */
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
|
||||
#define MAX_PLACED (16U) /* Load program MAX image num */
|
||||
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
#define MAX_PLACED (18U) /* Load program MAX image num */
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */
|
||||
|
||||
#define TARGET_MEM_DRAM (0U)
|
||||
#define TARGET_MEM_RTSRAM (1U)
|
||||
#define TARGET_MEM_RTVRAM (2U)
|
||||
#define TARGET_MEM_SYSRAM (3U)
|
||||
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
||||
#define TARGET_MEM_SRAM_IN_RTVRAM (4U)
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
|
||||
/* get info from cert address offset */
|
||||
#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
|
||||
#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
|
||||
#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
|
||||
#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
|
||||
#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */
|
||||
#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */
|
||||
|
||||
/* Certificate logical address */
|
||||
#define CONTENT_CERT_DEST_ADDR (0xEB230000U)
|
||||
|
||||
/* BL31/BL32 check */
|
||||
/* check image num */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
#define CA_IMAGESIZECHK_DEF (2U)
|
||||
#else
|
||||
#define CA_IMAGESIZECHK_DEF (3U)
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
/* load_id */
|
||||
#define CA_PROGRAM1_ID (6U)
|
||||
#define CA_PROGRAM2_ID (7U)
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
|
||||
#define CA_PROGRAM3_ID (8U)
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
|
||||
|
||||
#define CA_PROGRAM1_ADR (0x46400000U)
|
||||
#define CA_PROGRAM1_SIZE (0x00022000U)
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define CA_PROGRAM2_ADR (0x44100000U)
|
||||
#define CA_PROGRAM2_SIZE (0x00100000U)
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define CA_PROGRAM2_ADR (0x00000000U)
|
||||
#define CA_PROGRAM2_SIZE (0x00000000U)
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
|
||||
#define CA_PROGRAM3_ADR (0x44100000U)
|
||||
#define CA_PROGRAM3_SIZE (0x00100000U)
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
|
||||
|
||||
/* key cert address */
|
||||
#define TFMV_KEY_CERT_ADDR (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */
|
||||
#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xEB233000 */
|
||||
|
||||
/* struct */
|
||||
/* load image range */
|
||||
typedef struct {
|
||||
uint32_t load_id;
|
||||
uint32_t image_adr;
|
||||
uint32_t image_size;
|
||||
} IMAGE_RANGE;
|
||||
|
||||
/* load address range */
|
||||
typedef struct {
|
||||
uint32_t cx_topadd;
|
||||
uint32_t cx_endadd;
|
||||
} ADDRESS_RANGE;
|
||||
|
||||
/* load info */
|
||||
typedef struct{
|
||||
const char *name; /* store load image name */
|
||||
uint32_t image_size; /* store image size */
|
||||
uint32_t boot_addr; /* store boot address of image */
|
||||
uint32_t key_cert_addr; /* store key cert address */
|
||||
uint32_t cnt_cert_addr; /* store content cert address */
|
||||
uint32_t src_addr; /* store source address */
|
||||
uint32_t part_num; /* store eMMC partition number */
|
||||
uint32_t load_id; /* store Load ID */
|
||||
uint32_t cmac[4U]; /* store cmac */
|
||||
|
||||
} LOAD_INFO;
|
||||
|
||||
static inline uint32_t get_src_addr_offset_in_cert(uint32_t id)
|
||||
{
|
||||
/* INT30-C Pre confirmation */
|
||||
if (id > UINT32_MAX / 0x10U)
|
||||
{
|
||||
ERROR("get_src_addr_offset_in_cert id error.\n");
|
||||
panic;
|
||||
}
|
||||
|
||||
return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U));
|
||||
}
|
||||
|
||||
static inline uint32_t get_logic_cont_cert_addr(uint32_t num)
|
||||
{
|
||||
/* INT30-C Pre confirmation */
|
||||
if (num > UINT32_MAX / 0x10U)
|
||||
{
|
||||
ERROR("get_logic_cont_cert_addr num error.\n");
|
||||
panic;
|
||||
}
|
||||
return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE));
|
||||
}
|
||||
|
||||
/* Prototype */
|
||||
void load_image(LOAD_INFO* li);
|
||||
void load_init(LOAD_INFO* li, uint32_t num);
|
||||
void load_start(LOAD_INFO* li);
|
||||
#endif /* LOAD_IMAGE_H_ */
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Image load function for eMMC header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file image_load_emmc.h
|
||||
* - Version : 0.05
|
||||
* @brief Access protection setting driver.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 17.02.2022 0.02 Support AArch32
|
||||
* : 10.05.2022 0.03 Defined value integration
|
||||
* Change the argument type of get_part_num_in_cert
|
||||
* Added argument check
|
||||
* Changed define name
|
||||
* Change log output
|
||||
* Change the direct value reference
|
||||
* Remove Prototype
|
||||
* : 08.07.2022 0.04 Change log output
|
||||
* Adds the defined used in the emmc_trans_data argument
|
||||
* : 31.10.2022 0.05 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef LOAD_IMAGE_EMMC_H_
|
||||
#define LOAD_IMAGE_EMMC_H_
|
||||
|
||||
#include <image_load.h>
|
||||
#include <log.h>
|
||||
|
||||
/* define */
|
||||
/* eMMC */
|
||||
#define CX_EMMC_TOP (0x00000000U)
|
||||
#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */
|
||||
#define CX_EMMC_END ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U)
|
||||
#define SRC_TOP (CX_EMMC_TOP)
|
||||
|
||||
/* For eMMC */
|
||||
#define CX_EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
|
||||
#define CX_EMMC_SECTOR_SIZE (512U)
|
||||
#define CX_EMMC_CONTENT_CERT_ADDR (0x00240000U)
|
||||
#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT)
|
||||
|
||||
/* A side certificate setting */
|
||||
/* RT-SRAM Offset */
|
||||
#define SEC_BOOT_KEY_CERT_OFFSET (0x00001000U)
|
||||
#define SEC_DEBUG_SEC_CERT_OFFSET (0x00006000U)
|
||||
|
||||
/* A side RT-SRAM physical address */
|
||||
/* RT-SRAM(0xEB200000) + CERT_OFFSET */
|
||||
#define SEC_BOOT_KEY_CERT_ADDR (ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET)
|
||||
|
||||
/* A/B side certificate setting */
|
||||
/* Boot side Offset */
|
||||
#define CERT_OFFSET_2ND (0x8000U)
|
||||
|
||||
/* A/B side RT-SRAM physical address */
|
||||
/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/
|
||||
#define GET_SEC_BOOT_KEY_CERT_ADDR(a) ((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a)))
|
||||
|
||||
#define SEC_DEBUG_CERT_SIZE (6396U)
|
||||
|
||||
|
||||
static inline void load_image_info_print_for_emmc(LOAD_INFO* li)
|
||||
{
|
||||
|
||||
NOTICE("======== %s image load info ========\n", li->name);
|
||||
NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n"
|
||||
"source address \t= (p:%u)0x%x\n",
|
||||
(unsigned int)li->boot_addr, (unsigned int)(li->image_size),
|
||||
(unsigned int)li->part_num, (unsigned int)li->src_addr );
|
||||
}
|
||||
|
||||
static inline uint32_t get_part_num_in_cert(uint32_t id)
|
||||
{
|
||||
/* INT30-C Pre confirmation */
|
||||
if (UINT32_MAX - id < 1U)
|
||||
{
|
||||
ERROR("get_part_num_in_cert id error.\n");
|
||||
panic;
|
||||
}
|
||||
|
||||
return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U));
|
||||
}
|
||||
|
||||
#endif /* LOAD_IMAGE_EMMC_H_ */
|
||||
|
||||
@@ -0,0 +1,55 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : inline asm func header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef INLINE_ASM_H__
|
||||
#define INLINE_ASM_H__
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
static inline void syncm(void)
|
||||
{
|
||||
__asm__ __volatile__ ("SYNCM");
|
||||
}
|
||||
|
||||
static inline void synci(void)
|
||||
{
|
||||
__asm__ __volatile__ ("SYNCI");
|
||||
}
|
||||
#else
|
||||
static inline void syncm(void)
|
||||
{
|
||||
__asm__ volatile ("dsb");
|
||||
}
|
||||
|
||||
static inline void synci(void)
|
||||
{
|
||||
__asm__ volatile ("dsb");
|
||||
__asm__ volatile ("isb");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* INLINE_ASM_H__ */
|
||||
@@ -0,0 +1,56 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : INTC header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file interrupt.h
|
||||
* - Version : 0.05
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
* : 15.12.2022 0.03 V4H interrupt support.
|
||||
* : 27.12.2022 0.04 Change argument of pabort_error.
|
||||
* : 21.08.2023 0.05 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
#ifndef INTERRUPT_H_
|
||||
#define INTERRUPT_H_
|
||||
|
||||
/* Prototype */
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
extern void handler_fiq(void);
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar);
|
||||
void pabort_error(uint32_t ifsr, uint32_t ifar);
|
||||
void Undefined_error(uint32_t occ_add);
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
extern void handler_error(uint32_t ex_type);
|
||||
|
||||
#endif /* INTERRUPT_H_ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : IP's control header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ip_control.h
|
||||
* - Version : 0.03
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 02.08.2022 0.02 Added define value
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef IP_CONTROL_H_
|
||||
#define IP_CONTROL_H_
|
||||
|
||||
#define INTC_SPI_SWDT (548U)
|
||||
|
||||
/* Prototype */
|
||||
void ip_init(void);
|
||||
void ip_release(void);
|
||||
|
||||
#endif /* IP_CONTROL_H_ */
|
||||
@@ -0,0 +1,86 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Loader main header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file loader_main.h
|
||||
* - Version : 0.35
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 18.02.2022 0.02 Updated IPL_VERSION 0.7.0
|
||||
* : 22.03.2022 0.03 Updated IPL_VERSION 0.8.0
|
||||
* : 20.05.2022 0.04 Updated IPL_VERSION 0.9.0
|
||||
* : 12.07.2022 0.05 Updated IPL_VERSION 0.11.0
|
||||
* : 22.08.2022 0.06 Updated IPL_VERSION 0.12.0
|
||||
* : 03.10.2022 0.07 Updated IPL_VERSION 0.13.0
|
||||
* : 27.10.2022 0.08 Updated IPL_VERSION 0.14.0
|
||||
* : 31.10.2022 0.09 License notation change.
|
||||
* : 07.11.2022 0.10 Removed unnecessary define values.
|
||||
* : 14.12.2022 0.11 Updated IPL_VERSION 0.15.0
|
||||
* : 08.02.2023 0.12 Updated IPL_VERSION 0.17.0
|
||||
* : 17.02.2023 0.13 Updated IPL_VERSION 0.17.1
|
||||
* : 24.04.2023 0.14 Updated IPL_VERSION 0.18.0
|
||||
* : 22.05.2023 0.15 Updated IPL_VERSION 0.19.0
|
||||
* : 19.06.2023 0.16 Updated IPL_VERSION 0.21.0
|
||||
* : 22.08.2023 0.17 Updated IPL_VERSION 1.25.0
|
||||
* : 19.09.2023 0.18 Updated IPL_VERSION 1.30.0
|
||||
* : 23.10.2023 0.19 Updated IPL_VERSION 1.31.0
|
||||
* : 17.11.2023 0.20 Updated IPL_VERSION 1.41.0
|
||||
* : 26.01.2024 0.21 Updated IPL_VERSION 1.42.0
|
||||
* : 07.02.2024 0.22 Updated IPL_VERSION 1.44.0
|
||||
* : 05.04.2024 0.23 Updated IPL_VERSION 1.45.0
|
||||
* : 11.06.2024 0.24 Updated IPL_VERSION 1.48.0
|
||||
* : 19.08.2024 0.25 Updated IPL_VERSION 1.50.0
|
||||
* : 19.09.2024 0.26 Updated IPL_VERSION 1.51.2
|
||||
* : 22.10.2024 0.27 Updated IPL_VERSION 1.52.0
|
||||
* : 23.10.2024 0.28 Updated IPL_VERSION 1.53.0
|
||||
* : 28.10.2024 0.29 Updated IPL_VERSION 1.53.1
|
||||
* : 28.10.2024 0.30 Updated IPL_VERSION 1.54.0
|
||||
* : 05.12.2024 0.31 Updated IPL_VERSION 1.55.0
|
||||
* : 08.01.2025 0.32 Updated IPL_VERSION 1.56.0
|
||||
* : 09.04.2025 0.33 Updated IPL_VERSION 1.57.0
|
||||
* : 26.05.2025 0.34 Updated IPL_VERSION 1.58.0
|
||||
* : 28.07.2025 0.35 Updated IPL_VERSION 1.59.0
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef LOADER_MAIN_H_
|
||||
#define LOADER_MAIN_H_
|
||||
|
||||
/* define */
|
||||
#define IPL_VERSION "1.59.0"
|
||||
|
||||
/* Global */
|
||||
extern const char build_message[];
|
||||
|
||||
/* prototype */
|
||||
uint32_t loader_main(void);
|
||||
|
||||
#endif /* LOAD_MAIN_H_ */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Loader main common header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LOADER_MAIN_COMMON_H_
|
||||
#define LOADER_MAIN_COMMON_H_
|
||||
|
||||
#include <image_load.h>
|
||||
|
||||
/* prototype */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
void smoni_set_param(uint32_t smoni_entry_point,
|
||||
uint32_t uboot_entry_point);
|
||||
#else
|
||||
void smoni_set_param(uint32_t smoni_entry_point,
|
||||
uint32_t uboot_entry_point,
|
||||
uint32_t tee_entry_point);
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
|
||||
#endif /* LOADER_MAIN_COMMON_H_ */
|
||||
@@ -0,0 +1,80 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Definitions used by the MMU.
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file loader_mmu_table.h
|
||||
* - Version : 0.01
|
||||
* @brief MMU define.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 14.12.2022 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef MMU_TABLE_H_
|
||||
#define MMU_TABLE_H_
|
||||
|
||||
#include <stdint.h> /* for uint32_t */
|
||||
|
||||
/* b[1:0] Block and Table descriptors */
|
||||
#define MMU_TBL_TYPE_TABLE (3UL << 0)
|
||||
#define MMU_TBL_TYPE_BLOCK (1UL << 0)
|
||||
#define MMU_TBL_TYPE_PAGE (3UL << 0)
|
||||
|
||||
/* Lower attributes:SH[1:0] unused */
|
||||
#define MMU_TBL_BLOCK_OUTER_SHARE (2ULL << 8)
|
||||
#define MMU_TBL_BLOCK_INNER_SHARE (3ULL << 8)
|
||||
|
||||
/* Lower attributes:AF[10] */
|
||||
#define MMU_TBL_BLOCK_AF (1UL << 10)
|
||||
|
||||
/* Lower attributes:AP[2:1] access permissions model */
|
||||
#define MMU_TBL_AP_APP_RW (1UL << 6)
|
||||
#define MMU_TBL_AP_APP_R (3UL << 6)
|
||||
|
||||
/* Lower attributes:AttrIndx[2:0] */
|
||||
#define MMU_TBL_ATTRINDX0 (0UL << 2) /* Device-nGnRnE memory */
|
||||
#define MMU_TBL_ATTRINDX1 (1UL << 2) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
|
||||
#define MMU_TBL_ATTRINDX2 (2UL << 2) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
|
||||
|
||||
/* Upper attributes:Block descriptors */
|
||||
#define MMU_TBL_BLOCK_XN (1UL << 54)
|
||||
|
||||
#define MMU_TBL_BLOCK_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
|
||||
#define MMU_TBL_BLOCK_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
|
||||
#define MMU_TBL_BLOCK_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK)
|
||||
/* Level 3 */
|
||||
#define MMU_TBL_PAGE_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
|
||||
#define MMU_TBL_PAGE_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
|
||||
#define MMU_TBL_PAGE_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE)
|
||||
|
||||
extern const uint64_t g_loader_level1_table[];
|
||||
extern const uint64_t g_loader_level2_table[];
|
||||
extern const uint64_t g_loader_level3_table[];
|
||||
|
||||
#endif /* MMU_TABLE_H_ */
|
||||
@@ -0,0 +1,98 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : log header file
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file log.h
|
||||
* - Version : 0.06
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 12.05.2022 0.02 Changed __LOG_H__ to LOG_H_
|
||||
* Changed panic (Static analysis)
|
||||
* : 16.06.2022 0.03 Change log output
|
||||
* : 31.10.2022 0.04 License notation change.
|
||||
* : 07.11.2022 0.05 Change log macro.
|
||||
* : 04.04.2023 0.06 Removed stdio.h.
|
||||
*****************************************************************************/
|
||||
#ifndef LOG_H_
|
||||
#define LOG_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#define LOG_NONE (0)
|
||||
#define LOG_ERROR (1)
|
||||
#define LOG_NOTICE (2)
|
||||
#define LOG_WARNING (3)
|
||||
#define LOG_INFO (4)
|
||||
#define LOG_VERBOSE (5)
|
||||
|
||||
|
||||
#if LOG_LEVEL >= LOG_NOTICE
|
||||
# define NOTICE(...) log_printf("N:" __VA_ARGS__)
|
||||
#else
|
||||
# define NOTICE(...)
|
||||
#endif
|
||||
|
||||
#if LOG_LEVEL >= LOG_ERROR
|
||||
# define ERROR(...) log_printf("E:" __VA_ARGS__)
|
||||
#else
|
||||
# define ERROR(...)
|
||||
#endif
|
||||
|
||||
#if LOG_LEVEL >= LOG_WARNING
|
||||
# define WARN(...) log_printf("W:" __VA_ARGS__)
|
||||
#else
|
||||
# define WARN(...)
|
||||
#endif
|
||||
|
||||
#if LOG_LEVEL >= LOG_INFO
|
||||
# define INFO(...) log_printf("I:" __VA_ARGS__)
|
||||
#else
|
||||
# define INFO(...)
|
||||
#endif
|
||||
|
||||
#if LOG_LEVEL >= LOG_VERBOSE
|
||||
# define VERBOSE(...) log_printf("V:" __VA_ARGS__)
|
||||
#else
|
||||
# define VERBOSE(...)
|
||||
#endif
|
||||
|
||||
|
||||
#define panic \
|
||||
do { \
|
||||
log_printf("P:%s\n", __func__); \
|
||||
while(true){} \
|
||||
} while (false)
|
||||
|
||||
|
||||
void log_printf(const char *fmt, ...);
|
||||
|
||||
#endif /* LOG_H_ */
|
||||
@@ -0,0 +1,104 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Memory access driver header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file mem_io.h
|
||||
* - Version : 0.05
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 17.02.2022 0.02 Change the return type of mem_read64
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 07.11.2022 0.04 Added to convert mmio.
|
||||
* : 21.08.2023 0.05 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
#ifndef MEM_IO_H_
|
||||
#define MEM_IO_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
static inline void mem_write8(uintptr_t addr, uint8_t data)
|
||||
{
|
||||
*(volatile uint8_t*)addr = data;
|
||||
}
|
||||
|
||||
static inline uint8_t mem_read8(uintptr_t addr)
|
||||
{
|
||||
return (*(volatile uint8_t*)addr);
|
||||
}
|
||||
|
||||
static inline void mem_write16(uintptr_t addr, uint16_t data)
|
||||
{
|
||||
*(volatile uint16_t*)addr = data;
|
||||
}
|
||||
|
||||
static inline uint16_t mem_read16(uintptr_t addr)
|
||||
{
|
||||
return (*(volatile uint16_t*)addr);
|
||||
}
|
||||
|
||||
static inline void mem_write32(uintptr_t addr, uint32_t data)
|
||||
{
|
||||
*(volatile uint32_t*)addr = data;
|
||||
}
|
||||
|
||||
static inline uint32_t mem_read32(uintptr_t addr)
|
||||
{
|
||||
return (*(volatile uint32_t*)addr);
|
||||
}
|
||||
|
||||
static inline void mem_write64(uintptr_t addr, uint64_t data)
|
||||
{
|
||||
*(volatile uint64_t*)addr = data;
|
||||
}
|
||||
|
||||
static inline uint64_t mem_read64(uintptr_t addr)
|
||||
{
|
||||
return (*(volatile uint64_t*)addr);
|
||||
}
|
||||
|
||||
static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
|
||||
{
|
||||
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
|
||||
}
|
||||
|
||||
static inline void mem_bitset32(uintptr_t addr, uint32_t set)
|
||||
{
|
||||
mem_write32(addr, (mem_read32(addr) | set) );
|
||||
}
|
||||
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define mmio_write_32(a,b) mem_write32(a,b)
|
||||
#define mmio_read_32(a) mem_read32(a)
|
||||
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
|
||||
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
|
||||
|
||||
#endif /* MEM_IO_H_ */
|
||||
@@ -0,0 +1,33 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : QoS driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef QOS_INIT_H_
|
||||
#define QOS_INIT_H_
|
||||
|
||||
extern void qos_init(void);
|
||||
|
||||
#endif /* QOS_INIT_H_ */
|
||||
@@ -0,0 +1,150 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2024-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : RAM protection driver header
|
||||
******************************************************************************/
|
||||
#ifndef RAM_PROTECTION_H_
|
||||
#define RAM_PROTECTION_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <image_load.h>
|
||||
|
||||
#define RTVRAM0_AREA1_TOP (0xE0040000U)
|
||||
#define RTVRAM0_ADDR_END (0xE0100000U)
|
||||
|
||||
#define RTVRAM1_AREA1_TOP (0xE2010000U)
|
||||
#define RTVRAM1_AREA2_TOP (0xE2100000U)
|
||||
#define RTVRAM1_ADDR_END (0xE3C00000U)
|
||||
|
||||
#define SYSTEM_RAM_AREA1_TOP (0xE635E000U)
|
||||
#define SYSTEM_RAM_AREA2_TOP (0xE6360000U)
|
||||
#define SYSTEM_RAM_ADDR_END (0xE6400000U)
|
||||
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
|
||||
#define DRAM_ADDR_AREA2 (0x0401D00000ULL)
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
#define DRAM_ADDR_AREA3 (0x0406400000ULL)
|
||||
#define DRAM_ADDR_AREA4 (0x0406440000ULL)
|
||||
#define DRAM_ADDR_AREA5 (0x0407FC0000ULL)
|
||||
#define DRAM_ADDR_AREA6 (0x0408000000ULL)
|
||||
#define DRAM_ADDR_AREA7 (0x041DC00000ULL)
|
||||
#define DRAM_ADDR_AREA8 (0x0420000000ULL)
|
||||
#define DRAM_ADDR_AREA9 (0x0440000000ULL)
|
||||
#define DRAM_ADDR_AREA10 (0x0460000000ULL)
|
||||
#define DRAM_ADDR_AREA11 (0x0480000000ULL)
|
||||
#define DRAM_ADDR_AREA12 (0x0500000000ULL)
|
||||
#define DRAM_ADDR_AREA13 (0x0600000000ULL)
|
||||
#else
|
||||
#define DRAM_ADDR_AREA3 (0x0404100000ULL)
|
||||
#define DRAM_ADDR_AREA4 (0x0406400000ULL)
|
||||
#define DRAM_ADDR_AREA5 (0x0406440000ULL)
|
||||
#define DRAM_ADDR_AREA6 (0x0407E00000ULL)
|
||||
#define DRAM_ADDR_AREA7 (0x0407F00000ULL)
|
||||
#define DRAM_ADDR_AREA8 (0x0407FC0000ULL)
|
||||
#define DRAM_ADDR_AREA9 (0x0408000000ULL)
|
||||
#define DRAM_ADDR_AREA10 (0x041DC00000ULL)
|
||||
#define DRAM_ADDR_AREA11 (0x0420000000ULL)
|
||||
#define DRAM_ADDR_AREA12 (0x0440000000ULL)
|
||||
#define DRAM_ADDR_AREA13 (0x0460000000ULL)
|
||||
#define DRAM_ADDR_AREA14 (0x0480000000ULL)
|
||||
#define DRAM_ADDR_AREA15 (0x0500000000ULL)
|
||||
#define DRAM_ADDR_AREA16 (0x0600000000ULL)
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
|
||||
#else
|
||||
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
|
||||
#define DRAM_ADDR_AREA2 (0x0406400000ULL)
|
||||
#define DRAM_ADDR_AREA3 (0x0406440000ULL)
|
||||
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
||||
#define DRAM_ADDR_END (0x0700000000ULL)
|
||||
|
||||
#define NOT_USED_VALUE (0x00000000U)
|
||||
|
||||
/* RAM DIVISION AREA ID */
|
||||
/* RT-SRAM */
|
||||
#define RTVRAM0_ICUMX_IPL_AREA (0U) /* 0xEB200000 -- 0xEB23FFFF */
|
||||
#define RTVRAM0_ICUMX_FW_AREA (1U) /* 0xEB240000 -- 0xEB2FFFFF */
|
||||
/* RT-VRAM */
|
||||
#define RTVRAM1_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */
|
||||
#define RTVRAM1_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */
|
||||
#define RTVRAM1_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */
|
||||
/* System RAM */
|
||||
#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */
|
||||
#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */
|
||||
/* SDRAM */
|
||||
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
|
||||
#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */
|
||||
#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF
|
||||
* OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */
|
||||
#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF
|
||||
* OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */
|
||||
#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
|
||||
#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
|
||||
#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
|
||||
#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
|
||||
#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
|
||||
#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
|
||||
#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
|
||||
#else
|
||||
#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */
|
||||
#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */
|
||||
#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */
|
||||
#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */
|
||||
#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
|
||||
#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
|
||||
#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
|
||||
#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
|
||||
#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
|
||||
#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
|
||||
#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
|
||||
#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
|
||||
#else
|
||||
#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
|
||||
#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
|
||||
#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
|
||||
#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
|
||||
#else
|
||||
#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
|
||||
#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
|
||||
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
|
||||
#endif /* RCAR_LSI == RCAR_V4H */
|
||||
#else
|
||||
#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
|
||||
#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */
|
||||
#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */
|
||||
#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */
|
||||
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
||||
|
||||
#endif /* RAM_PROTECTION_H_ */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : R-Car common header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file rcar_def.h
|
||||
* - Version : 0.05
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 17.02.2022 0.02 Support V4H
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 23.05.2023 0.04 Add the define "PRR_PRODUCT_21" for V4H v2.1.
|
||||
* : 21.08.2023 0.05 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef RCAR_DEF_H_
|
||||
#define RCAR_DEF_H_
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U) /* PRR register */
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
|
||||
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
|
||||
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
|
||||
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
|
||||
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
|
||||
#define PRR_MAJOR_OFFSET (1U)
|
||||
|
||||
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
|
||||
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
|
||||
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
|
||||
|
||||
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
|
||||
#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */
|
||||
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
|
||||
#define PRR_PRODUCT_21 (0x00000011U) /* ver 2.1 */
|
||||
#define PRR_PRODUCT_22 (0x00000012U) /* ver 2.2 */
|
||||
#endif /* RCAR_DEF_H_ */
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : rcar register header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file rcar_register.h
|
||||
* - Version : 0.07
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 17.02.2022 0.02 Add APMU
|
||||
* Support AArch32
|
||||
* : 09.05.2022 0.03 Changed to processing for each device
|
||||
* : 24.10.2022 0.04 Add supports for HS200/400
|
||||
* : 31.10.2022 0.05 License notation change.
|
||||
* : 07.11.2022 0.06 Added QOS and RTVRAM related registers.
|
||||
* : 21.08.2023 0.07 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef RCAR_REGISTER_H_
|
||||
#define RCAR_REGISTER_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define BASE_ADDR_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET */
|
||||
#define BASE_ADDR_RPC (0xEE200000U) /* RPC */
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define BASE_ADDR_SCIF (0xE6C00000U) /* SCIF */
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define BASE_ADDR_SCIF (0xE6E00000U) /* SCIF */
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#define BASE_ADDR_MMC (0xEE000000U) /* MMC */
|
||||
#define BASE_ADDR_HSCIF (0xE6400000U) /* HSCIF */
|
||||
#define BASE_AP_CORE_ADDR (0xE6280000U) /* ECM */
|
||||
|
||||
/* Base address offset of each register */
|
||||
/* CPGA */
|
||||
#define OFFSET_CPGA (0x00150000U)
|
||||
/* RESET */
|
||||
#define OFFSET_RESET (0x00160000U)
|
||||
/* APMU */
|
||||
#define OFFSET_APMU (0x00170000U)
|
||||
|
||||
/*RPC*/
|
||||
#define OFFSET_RPC (0x00000000U)
|
||||
|
||||
/*SCIF*/
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define OFFSET_SCIF3 (0x00050000U)
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define OFFSET_SCIF0 (0x00060000U)
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
/* SDHI2/MMC0 */
|
||||
#define OFFSET_SDHI (0x00140000U)
|
||||
|
||||
/* HSCIF */
|
||||
#define OFFSET_HSCIF0 (0x00140000U)
|
||||
|
||||
/* PFC0 */
|
||||
#define OFFSET_PFC0 (0x00050000U)
|
||||
|
||||
/* PFC1 */
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define OFFSET_PFC1 (0x00051000U)
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define OFFSET_PFC1 (0x00058000U)
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
/* Port Group */
|
||||
#define OFFSET_PORTGR (0x00000800U)
|
||||
|
||||
/* CPGWPR */
|
||||
#define OFFSET_CPG_CPGWPR (0x00000000U)
|
||||
|
||||
/* SD0CKCR */
|
||||
#define OFFSET_CPG_SD0CKCR (0x00000870U)
|
||||
|
||||
/* PLL2CR0 */
|
||||
#define OFFSET_CPG_PLL2CR0 (0x00000834U)
|
||||
|
||||
/* PLLECR */
|
||||
#define OFFSET_CPG_PLLECR (0x00000820U)
|
||||
|
||||
/* QOS */
|
||||
#define ICU_CC (0xE6600000U) /* CC63S,I2C,AXMM,QoS */
|
||||
#define ICU_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */
|
||||
#define BASE_CCI_ADDR (ICU_CC + ICU_OFFSET_CCI)
|
||||
|
||||
/* RTVRAM */
|
||||
#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL)
|
||||
#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */
|
||||
|
||||
#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
|
||||
#define BASE_RESET_ADDR (BASE_ADDR_PFC + OFFSET_RESET)
|
||||
#define BASE_APMU_ADDR (BASE_ADDR_PFC + OFFSET_APMU)
|
||||
#define BASE_RPC_ADDR (BASE_ADDR_RPC + OFFSET_RPC)
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF3)
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF0)
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#define BASE_MMC0_ADDR (BASE_ADDR_MMC + OFFSET_SDHI)
|
||||
#define BASE_HSCIF_ADDR (BASE_ADDR_HSCIF + OFFSET_HSCIF0)
|
||||
#define BASE_PFC0_ADDR (BASE_ADDR_PFC + OFFSET_PFC0)
|
||||
#define BASE_PFC1_ADDR (BASE_ADDR_PFC + OFFSET_PFC1)
|
||||
#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
|
||||
#define PFC_GP1_BASE (BASE_PFC0_ADDR + OFFSET_PORTGR)
|
||||
#define PFC_GP3_BASE (BASE_PFC1_ADDR + OFFSET_PORTGR)
|
||||
#define CPG_CPGWPR (BASE_CPG_ADDR + OFFSET_CPG_CPGWPR)
|
||||
#define CPG_PLL2CR0 (BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0)
|
||||
#define CPG_PLLECR (BASE_CPG_ADDR + OFFSET_CPG_PLLECR)
|
||||
#define CPG_SD0CKCR (BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR)
|
||||
#define CPG_FRQCRC0 (BASE_CPG_ADDR + OFFSET_CPG_FRQCRC0 0x0808U)
|
||||
|
||||
#define OFFSET_PFC_DRV0CTRL (0x00000080U)
|
||||
#define OFFSET_PFC_DRV1CTRL (0x00000084U)
|
||||
#define OFFSET_PFC_DRV2CTRL (0x00000088U)
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define PFC_DRVCTRL1_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register0 PortGroup 3
|
||||
#define PFC_DRVCTRL2_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL) // R/W 32 POC control register1 PortGroup 3
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define PFC_DRVCTRL0_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL) // R/W 32 POC control register0 PortGroup 3
|
||||
#define PFC_DRVCTRL1_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register1 PortGroup 3
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
#define PFC_PMMR(addr) ((addr) & (uintptr_t)0xFFFFF800U) // R/W 32 LSI Multiplexed Pin Setting Mask Register
|
||||
|
||||
#endif /* RCAR_REGISTER_H_ */
|
||||
@@ -0,0 +1,65 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : RST register header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file rst_register.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef RST_REGISTER_H_
|
||||
#define RST_REGISTER_H_
|
||||
|
||||
#include <rcar_register.h>
|
||||
|
||||
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
|
||||
|
||||
#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */
|
||||
#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */
|
||||
#define RST_MODEMR0_MD31 (1U << 31U)
|
||||
#define RST_MODEMR1_MD32 (1U << 0U)
|
||||
|
||||
#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU)
|
||||
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U)
|
||||
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U)
|
||||
#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
|
||||
#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU)
|
||||
|
||||
/* SCIF / HSCIF clock speed */
|
||||
#define MODEMR_SCIF_DLMODE (0x00000000U)
|
||||
#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U)
|
||||
#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
|
||||
#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
|
||||
|
||||
#endif /* RST_REGISTER_H_ */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : RT-VRAM driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef RTVRAM_H_
|
||||
#define RTVRAM_H_
|
||||
|
||||
#include <rtvram_register.h>
|
||||
|
||||
void rtvram_extendmode(void);
|
||||
|
||||
#endif /* RTVRAM_H__ */
|
||||
@@ -0,0 +1,92 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : RT-VRAM register header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef RTVRAM_REGISTER_H__
|
||||
#define RTVRAM_REGISTER_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* RT-VRAM register base address */
|
||||
#define RTVRAM_REG_BASE (0xFFEC0000U)
|
||||
|
||||
#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U)
|
||||
#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U)
|
||||
#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U)
|
||||
#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U)
|
||||
#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U)
|
||||
#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U)
|
||||
#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U)
|
||||
|
||||
/* RT-VRAM0 register base address */
|
||||
#define RTVRAM0_REG_BASE (0xFFE90000U)
|
||||
/* RT-VRAM1 register base address */
|
||||
#define RTVRAM1_REG_BASE (0xFFEC0000U)
|
||||
|
||||
#define RTVRAM0_SECDIVD (RTVRAM0_REG_BASE + 0x0000U)
|
||||
#define RTVRAM0_SECCTRRD (RTVRAM0_REG_BASE + 0x0040U)
|
||||
#define RTVRAM0_SECCTRWD (RTVRAM0_REG_BASE + 0x0340U)
|
||||
|
||||
#define RTVRAM1_SECDIVD (RTVRAM1_REG_BASE + 0x0000U)
|
||||
#define RTVRAM1_SECCTRRD (RTVRAM1_REG_BASE + 0x0040U)
|
||||
#define RTVRAM1_SECCTRWD (RTVRAM1_REG_BASE + 0x0340U)
|
||||
|
||||
static inline uint32_t get_rtvram0_secdivd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM0_SECDIVD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_rtvram0_secctrrd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM0_SECCTRRD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_rtvram0_secctrwd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM0_SECCTRWD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_rtvram1_secdivd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM1_SECDIVD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_rtvram1_secctrrd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM1_SECCTRRD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_rtvram1_secctrwd_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM1_SECCTRWD + (num * 4U)));
|
||||
}
|
||||
|
||||
static inline uint32_t get_vbuf_baddr_addr(uint32_t num)
|
||||
{
|
||||
return ((RTVRAM_VBUF_BADDR + (num * 4U)));
|
||||
}
|
||||
|
||||
#endif /* RTVRAM_REGISTER_H__ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : SCIF driver header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file scif.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef SCIF_H_
|
||||
#define SCIF_H_
|
||||
|
||||
#include <scif_register.h>
|
||||
#include <hscif_register.h>
|
||||
|
||||
/* Prototype */
|
||||
void scif_init(void);
|
||||
void console_putc(uint8_t outchar);
|
||||
|
||||
#endif /* SCIF_H_ */
|
||||
@@ -0,0 +1,60 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : SCIF register header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file scif_register.h
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef SCIF_REGISTER_H_
|
||||
#define SCIF_REGISTER_H_
|
||||
|
||||
#include <rcar_register.h>
|
||||
|
||||
/* SCIF3 base address */
|
||||
/* 0xE6C50000 */
|
||||
#define SCIF_BASE (BASE_SCIF_ADDR)
|
||||
|
||||
#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */
|
||||
#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */
|
||||
#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */
|
||||
#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
|
||||
#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */
|
||||
#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */
|
||||
#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */
|
||||
#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */
|
||||
|
||||
#endif /* SCIF_REGISTER_H_ */
|
||||
@@ -0,0 +1,60 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ICUMIF control function header
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file secure_boot.h
|
||||
* - Version : 0.03
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 17.06.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
* : 16.02.2023 0.03 Added prototype declaration of final_hash_cmp.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef SECURE_BOOT_H_
|
||||
#define SECURE_BOOT_H_
|
||||
|
||||
#define SECURE_BOOT (0x0U)
|
||||
#define NORMAL_BOOT (0x211883DFU)
|
||||
|
||||
#define ROMAPI_OK (0x00000000U)
|
||||
#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU)
|
||||
|
||||
/*******************************************************************************
|
||||
* Function & variable prototypes
|
||||
******************************************************************************/
|
||||
void secureboot_init(void);
|
||||
uint32_t judge_bootmode(void);
|
||||
void secureboot_verify(LOAD_INFO* li, uint32_t num);
|
||||
void secureboot_image(LOAD_INFO* li);
|
||||
void final_hash_cmp(void);
|
||||
|
||||
#endif /* SECURE_BOOT_H_ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user