update

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/2_CAN/20260225_memo.txt

@@ -0,0 +1,19 @@
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ȯ<><C8AF>
+Core0(<28><><EFBFBD>뷮 <20><><EFBFBD><EFBFBD> 100%): TMU x3(Task), CAN, 
+Core1: Driver <20><><EFBFBD><EFBFBD>.
+Core2: SPI x 2, GPT,
+
+* <20>̱<EFBFBD><CCB1>ھ<EFBFBD> ȯ<>濡<EFBFBD><E6BFA1> Test <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.(<28><><EFBFBD><EFBFBD> <20><>Ȳ<EFBFBD><C8B2><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ƽ<EFBFBD>ھ<DABE><EEB8B8> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ƴ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD>)
+EB <20><><EFBFBD><EFBFBD><EFBFBD>ҽ<EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ, <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD><EFBFBD>ϴµ<CFB4>, 
+
+Driver <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ư<EFBFBD><C6B0><EFBFBD>?
+Core0<EFBFBD><EFBFBD> <20>ƹ<EFBFBD> <20>͵<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>¿<EFBFBD><C2BF><EFBFBD> <20>ε<EFBFBD><CEB5><EFBFBD> <20><> 100% <20><><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD>?(HKL Ȯ<><C8AE>)
+
+TC397, CET<45><54> 700us
+
+AI
+TX: 20 Messages (32-byte payload) @ 10ms Cycle
+* RX: 150 Messages (32-byte payload) @ 10ms Incoming Cycle (Processed at 5ms Task Rate)
+TX<EFBFBD><EFBFBD> 20<32><30> <20><><EFBFBD><EFBFBD>, RX<52><58> 9<><39><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>µ<EFBFBD>, 10<31><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͱ<EFBFBD> <20><><EFBFBD><EFBFBD>.
+
+Driver<EFBFBD><EFBFBD><EFBFBD><EFBFBD> Time<6D><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE>.

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/4_I2C/cddiic/I2C.si4project/I2C.SearchResults

@@ -1,10 +1,10 @@
----- MasterMesg Matches (9 in 1 files) ----
-App_CDD_IIC_Common_Sample.c (sample_application\src) line 95 : volatile IicMessageType MasterMesg;
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   MasterMesg = IIC_NOTICE_IDLE;
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   MasterMesg = IIC_NOTICE_IDLE;
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   MasterMesg = IIC_NOTICE_IDLE;
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   while((IIC_NOTICE_END != MasterMesg) || (IIC_NOTICE_END != SlaveMesg))
-main in App_CDD_IIC_Common_Sample.c (sample_application\src) :   MasterMesg = IIC_NOTICE_IDLE;
-IicAppNotice in App_CDD_IIC_Common_Sample.c (sample_application\src) :   MasterMesg = NoticeInfo->Message;
+---- I2c3 Matches (0 in 0 files) ----
+---- I2c3 Search Errors Encountered (7) ----
+The following 7 files could not be processed:
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.siproj : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_sym : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xab : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xad : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xm : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xsb : File could not be opened.
+C:\Work\Customer\HL_Klemove\DRV2.5(ADCU)_for_HKMC\Issue\4_I2C\cddiic\I2C.si4project\I2C.sip_xsd : File could not be opened.

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/5_PMIC_I2C/Jira_#2863_History.txt

@@ -0,0 +1,39 @@
+Jira 2863
+
+
+IPL <20><><EFBFBD><EFBFBD>Ʈ <20>ڵ<EFBFBD>
+IPL <20><><EFBFBD><EFBFBD> <20>ڵ<EFBFBD>
+IPL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+<EFBFBD><EFBFBD>ġ <20><><EFBFBD>̵<EFBFBD><CCB5><EFBFBD>? GHS<48><53> <20><><EFBFBD>׻罺 <20><><EFBFBD>̵尡 <20><><EFBFBD><EFBFBD>. <20><><EFBFBD>̼<EFBFBD><CCBC><EFBFBD><EFBFBD><EFBFBD> <20>ʿ<EFBFBD><CABF><EFBFBD>.
+
+IPL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ڵ尡 <20><><EFBFBD><EFBFBD>.
+<EFBFBD>ñ<EFBFBD><EFBFBD><EFBFBD> <20><>ġ, GHS <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ġ
+IPL<EFBFBD><EFBFBD> HKL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD><D3B4><EFBFBD> <20><><EFBFBD><EFBFBD>
+
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>忡<EFBFBD><E5BFA1> F/W <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>(IPL. Autosar, Uboot)
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴµ<CFB4> I2C <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB>ϴ°<CFB4>?
+Chip <20><><EFBFBD><EFBFBD> WDG, I2C <20><>Ŷ<EFBFBD><C5B6> <20><><EFBFBD><EFBFBD>?
+
+
+case1 CR<43>ھ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>. -> I2C<32><43><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
+
+
+
+
+case2 (HKL <20>ó<EFBFBD><C3B3><EFBFBD><EFBFBD><EFBFBD>.)
+CR<EFBFBD><EFBFBD><EFBFBD><EFBFBD> PMIC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD> 10ms <20><><EFBFBD>͹<EFBFBD><CDB9><EFBFBD> <20><><EFBFBD><EFBFBD> <20>д´<D0B4>. 
+
+QNX<EFBFBD><EFBFBD><EFBFBD><EFBFBD> OTA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߰<EFBFBD><DFB0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB>Ѵ<EFBFBD>. -> IPL<50><4C> <20><><EFBFBD><EFBFBD> <20>ʱ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ȴ<EFBFBD>.
+QNX <20><><EFBFBD><EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ִ°<D6B4>?
+HKL PMIC I2C
+<EFBFBD><EFBFBD>HKL <20>̹<EFBFBD><CCB9><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ٽ<EFBFBD> <20>־ Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ʿ<EFBFBD>.
+
+Case2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB>ϰ<EFBFBD> IPL <20><><EFBFBD>ý<EFBFBD>, I2C <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB><EFBFBD>.
+
+
+

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/7_MPU/20260428/Mk_ARM_reset_Woody_20260428.asm

@@ -0,0 +1,300 @@
+/* MK_ARM_reset.asm
+ *
+ * This file contains the early initialization function for the RCARV4MCR52.
+ * This functionality should be executed before the microkernel is started
+ * in the first place.
+ *
+ * Warning: This file has not been developed in accordance with a safety
+ * standard (no ASIL)!
+ *
+ * (c) Elektrobit Automotive GmbH
+*/
+
+#include <private/Mk_asm.h>
+#include <private/ARM/Mk_ARM_mpu_v8r_memoryprotection.h>
+#include "Mk_board.h"
+#include "Mk_qmboard.h"
+
+	MK_global	boardResetStart
+	MK_extern	MK_QM_Entry
+
+/* Macros for setting up the MPU and the caches.
+ */
+/* Base and limit addresses for peripheral region. */
+#define MK_QM_DEV_BASE			0xe4000000
+#define MK_QM_DEV_LIMIT			0xffffffff
+
+
+#define MK_QM_MAIR_ATTR(a,i)	((a) << ((i) * 8))
+
+#define MK_QM_MAIR0_ATTR0	MK_ARM_MPU_MAIR_ATT_DEV | MK_ARM_MPU_MAIR_ATT_DEV_NGNRNE
+#define MK_QM_MAIR0_ATTR	MK_QM_MAIR_ATTR(MK_QM_MAIR0_ATTR0,0)
+
+/* Boot address of CR core */
+#define CR_START_ADDRESS                   0xE2100000UL
+#define MPU_AREA0_BASE_ADDRESS             0xE2100000UL
+/* (BASE + 0x1FFFFF) & ~(0x3F) */
+#define MPU_AREA0_LIMIT_ADDRESS            0xFFFFFFC0UL
+
+#define RW_Access         0b01
+#define Non_Shareable     0b00
+#define ENable            0b1
+#define AttrIndx1         0b001
+
+	MK_SECTION_EXCTABLE
+	MK_CODE_COMMON
+	MK_ALIGN_CODE_ARM
+
+	MK_ALIGN_EXCTABLE
+/* Exception table for HYP mode */
+MK_LABEL(MK_StartupExceptionTableHyp)
+	ldr		pc, MK_QM_ResetAddr
+MK_LABEL(MK_QM_HypUndef)
+	b		MK_QM_HypUndef
+MK_LABEL(MK_QM_HypSvc)
+	b		MK_QM_HypSvc
+MK_LABEL(MK_QM_HypPrefetchAbort)
+	b		MK_QM_HypPrefetchAbort
+MK_LABEL(MK_QM_HypDataAbort)
+	b		MK_QM_HypDataAbort
+MK_LABEL(MK_QM_HypTrap)
+	b		MK_QM_HypTrap
+MK_LABEL(MK_QM_HypIrq)
+	b		MK_QM_HypIrq
+MK_LABEL(MK_QM_HypFiq)
+	b		MK_QM_HypFiq
+
+MK_LABEL(MK_QM_ResetAddr)
+	MK_word		boardResetStart
+
+	MK_SECTION_RESET
+	MK_CODE_ARM
+
+	MK_FUNC(boardResetStart)
+MK_LABEL(boardResetStart)
+	//ldr		r0, =MK_QM_ResetArmMode
+	//bx		r0
+	b MK_QM_ResetArmMode
+	MK_FUNC_END(boardResetStart)
+
+
+/* Arm mode entry point after reset. Cortex-R52 boots up in Hyp mode (EL2). See r52 trm, sec 7.3 */
+	MK_FUNC(MK_QM_ResetArmMode)
+MK_LABEL(MK_QM_ResetArmMode)
+
+
+	mov	r0, #0
+	mov	r1, #0
+	mov	r2, #0
+	mov	r3, #0
+	mov	r4, #0
+	mov	r5, #0
+	mov	r6, #0
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
+	mov	r10, #0
+	mov	r11, #0
+	mov	r12, #0
+	mov lr, #0
+
+    /* Disable all regions */
+    mov r0, #0
+    mov r1, #0
+    mov r2, #24
+        
+MK_LABEL(loop)
+    mcr p15, #0, r0, c6, c2, #1
+    mcr p15, #0, r1, c6, c3, #1
+    add r0, r0, #1
+    cmp r0, r2
+    bne loop
+
+	/* Setup TCM base addresses. */
+	MK_QM_GET_CORE_ID	r0, r1			/* Load CoreID into r0; r1 will be clobbered. */
+
+	ldr		r1, =MK_QM_ATcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 0		/* Set A-TCM base. */
+
+	ldr		r1, =MK_QM_BTcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 1		/* Set B-TCM base. */
+
+	ldr		r1, =MK_QM_CTcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 2		/* Set C-TCM base. */
+
+    LDR r0, =0x00EEFF44
+    MCR p15, 0, r0, c10, c2, 0   // MAIR0
+
+    /* 0x00000000 - 0x3FFFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
+    LDR     r0, =0x00000002  // PRBAR0
+    MCR     p15, 0, r0, c6, c8, 0
+    LDR     r0, =0x3FFFFFC3  // PRLAR0
+    MCR     p15, 0, r0, c6, c8, 1
+
+    /* DDR 0x40000000 - 0xBFFFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
+    LDR     r0, =0x40000002  // PRBAR1
+    MCR     p15, 0, r0, c6, c8, 4
+    LDR     r0, =0xBFFFFFC3  // PRLAR1
+    MCR     p15, 0, r0, c6, c8, 5
+
+    /* Reserved 0xC0000000 - 0xDFFFFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
+    LDR     r0, =0xC0000003  // PRBAR2
+    MCR     p15, 0, r0, c6, c9, 0
+    LDR     r0, =0xDFFFFFC7  // PRLAR2
+    MCR     p15, 0, r0, c6, c9, 1
+
+    /* RT-VRAM 0xE0000000 - 0xE3FFFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
+    LDR     r0, =0xE0000002  // PRBAR3
+    MCR     p15, 0, r0, c6, c9, 4
+    LDR     r0, =0xE3FFFFC3  // PRLAR3
+    MCR     p15, 0, r0, c6, c9, 5
+
+    /* TCM 0xE4000000 - 0xE4BFFFFF, Index0, Non-Share, Read/Write, Execute, Non-Cacheable */
+    LDR     r0, =0xE4000002  // PRBAR4
+    MCR     p15, 0, r0, c6, c10, 0
+    LDR     r0, =0xE4BFFFC1  // PRLAR4
+    MCR     p15, 0, r0, c6, c10, 1
+
+    /* Reserved 0xE4C00000 - 0xE62FFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
+    LDR     r0, =0xE4C00003  // PRBAR5
+    MCR     p15, 0, r0, c6, c10, 4
+    LDR     r0, =0xE62FFFC7  // PRLAR5
+    MCR     p15, 0, r0, c6, c10, 5
+
+    /* System RAM 0xE6300000 - 0xE63FFFFF, Index1, Inner Shareable, Read/Write, Execute-Never, Non-Cacheable */
+    LDR     r0, =0xE630001B  // PRBAR6
+    MCR     p15, 0, r0, c6, c11, 0
+    LDR     r0, =0xE63FFFC1  // PRLAR6
+    MCR     p15, 0, r0, c6, c11, 1
+
+    /* Reserved 0xE6400000 - 0xEB0FFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
+    LDR     r0, =0xE6400003  // PRBAR7
+    MCR     p15, 0, r0, c6, c11, 4
+    LDR     r0, =0xEB0FFFC7  // PRLAR7
+    MCR     p15, 0, r0, c6, c11, 5
+
+    /* BootROM & RT-VRAM0 0xEB100000 - 0xEB2FFFFF, Index1, Non-Share, Read/Write, Execute, Cacheable */
+    LDR     r0, =0xEB100002  // PRBAR8
+    MCR     p15, 0, r0, c6, c12, 0
+    LDR     r0, =0xEB2FFFC3  // PRLAR8
+    MCR     p15, 0, r0, c6, c12, 1
+
+    /* Reserved 0xEB300000 - 0xFFFFFFFF, Index3, Non-Share, Read/Write, Execute-Never, Non-Cacheable */
+    LDR     r0, =0xEB300003  // PRBAR9
+    MCR     p15, 0, r0, c6, c12, 4
+    LDR     r0, =0xFFFFFFC7  // PRLAR9
+    MCR     p15, 0, r0, c6, c12, 5
+
+    /* Enable MPU */
+    mrc p15, #0, r0, c1, c0, #0
+    orr r0, r0, #1
+    dsb
+    mcr p15, #0, r0, c1, c0, #0
+    isb
+
+	MK_QM_GET_CORE_ID	r0, r1			/* Load CoreID into r0; r1 will be clobbered. */
+
+mov		 r4, r0					/* Preserve CoreID for TCM selection. */
+mov		 r2, #0
+mov		 r3, #0
+
+	/* ATCM base = 0xE4000000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE400
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop
+
+mov		 r2, #0
+mov		 r3, #0
+
+	/* BTCM base = 0xE4100000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE410
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop_2)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop_2
+
+mov		 r2, #0
+mov		 r3, #0
+
+	/* CTCM base = 0xE4200000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE420
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop_3)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop_3
+
+	ldr		r0, =MK_StartupExceptionTableHyp
+	mcr		p15,4,r0,c12,c0,0				/* Set Hypervisor table in HVBAR */
+
+	/* Set up the Peripheral Port Region Register (IMP_PERIPHPREGIONR)
+		Enable peripheral port at  EL1 and EL0 */
+	mrc		p15, 0, r0, c15, c0, 0
+	orr		r0, 1
+	mcr		p15, 0, r0, c15, c0, 0
+
+	/* Setup TCM base addresses. */
+
+	/* Enable TCM regions in MPU before enabling it. */
+	/* Enable TCM regions in MPU before enabling it. */
+	
+	mrc		p15, 0, r0, c1, c0, 0		/* Load SCTLR */
+	bic		r0, r0, #0x1 << 30			/* Clear TE bit (Exceptions taken in A32 state) */
+	mcr		p15, 0, r0, c1, c0, 0		/* Store SCTLR */
+
+	mrs		r0, cpsr
+	bic		r0, r0, #0x1 << 5			/* Clear Thumb bit */
+	orr		r0, r0, #0x1 << 6			/* Set mask bit F. Disable FIQ. */
+	orr		r0, r0, #0x1 << 7			/* Set mask bit I. Disable IRQ. */
+	orr		r0, r0, #0x1 << 8			/* Set mask bit A. Disable async-aborts. */
+	msr		cpsr, r0					/* Setup mask bits A, F, I and Thumb bit */
+	msr		SPSR_cxsf, r0				/* Will stay set after ERET */
+	
+	
+	ldr		r0, =MK_QM_ResetStartEl1	/* Prepare to switch to EL1 */
+	msr		ELR_hyp, r0					/* Write r0 into ELR_hyp */
+	mrs		r0, SPSR_hyp				/* Read SPSR_hyp into r0 */
+	ldr		r1, =0xffffffc0
+	and		r0, r0, r1					/* r0 = r0 & FFFF FFC0. Clear SPSR_hyp bits [5:0] -> Execution state bit + Mode bits. */
+	ldr		r1, =0x13
+	orr		r0, r0, r1					/* r0 = r0 | 0x13. Set bits b010011 -> Set mode to SVC and A32 */
+	
+	msr		SPSR_hyp, r0				/* Write r0 into SPSR_hyp */	
+	eret
+
+
+MK_LABEL(MK_QM_ResetStartEl1)
+	b		MK_QM_Entry
+	MK_FUNC_END(MK_QM_ResetArmMode)
+
+
+/* Entry vector for cores that are disabled in current configuration. */
+MK_LABEL(MK_QM_CoreIdle)
+	/* We do a pseudo "bl" so the debugger will show this core as disabled in the stack frame. */
+	bl		MK_QM_CoreIdleLoop
+MK_LABEL(MK_QM_CoreIdleLoop)
+	wfe		/* save power */
+	b		MK_QM_CoreIdleLoop
+

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/7_MPU/20260428/Mk_ARM_reset_original_20260228.asm

@@ -0,0 +1,339 @@
+/* MK_ARM_reset.asm
+ *
+ * This file contains the early initialization function for the RCARV4MCR52.
+ * This functionality should be executed before the microkernel is started
+ * in the first place.
+ *
+ * Warning: This file has not been developed in accordance with a safety
+ * standard (no ASIL)!
+ *
+ * (c) Elektrobit Automotive GmbH
+*/
+
+#include <private/Mk_asm.h>
+#include <private/ARM/Mk_ARM_mpu_v8r_memoryprotection.h>
+#include "Mk_board.h"
+#include "Mk_qmboard.h"
+
+	MK_global	boardResetStart
+	MK_extern	MK_QM_Entry
+
+/* Macros for setting up the MPU and the caches.
+ */
+/* Base and limit addresses for peripheral region. */
+#define MK_QM_DEV_BASE			0xe4000000
+#define MK_QM_DEV_LIMIT			0xffffffff
+
+
+#define MK_QM_MAIR_ATTR(a,i)	((a) << ((i) * 8))
+
+#define MK_QM_MAIR0_ATTR0	MK_ARM_MPU_MAIR_ATT_DEV | MK_ARM_MPU_MAIR_ATT_DEV_NGNRNE
+#define MK_QM_MAIR0_ATTR	MK_QM_MAIR_ATTR(MK_QM_MAIR0_ATTR0,0)
+
+/* Boot address of CR core */
+#define CR_START_ADDRESS                   0xE2100000UL
+#define MPU_AREA0_BASE_ADDRESS             0xE2100000UL
+/* (BASE + 0x1FFFFF) & ~(0x3F) */
+#define MPU_AREA0_LIMIT_ADDRESS            0xFFFFFFC0UL
+
+#define RW_Access         0b01
+#define Non_Shareable     0b00
+#define ENable            0b1
+#define AttrIndx1         0b001
+
+	MK_SECTION_EXCTABLE
+	MK_CODE_COMMON
+	MK_ALIGN_CODE_ARM
+
+	MK_ALIGN_EXCTABLE
+/* Exception table for HYP mode */
+MK_LABEL(MK_StartupExceptionTableHyp)
+	ldr		pc, MK_QM_ResetAddr
+MK_LABEL(MK_QM_HypUndef)
+	b		MK_QM_HypUndef
+MK_LABEL(MK_QM_HypSvc)
+	b		MK_QM_HypSvc
+MK_LABEL(MK_QM_HypPrefetchAbort)
+	b		MK_QM_HypPrefetchAbort
+MK_LABEL(MK_QM_HypDataAbort)
+	b		MK_QM_HypDataAbort
+MK_LABEL(MK_QM_HypTrap)
+	b		MK_QM_HypTrap
+MK_LABEL(MK_QM_HypIrq)
+	b		MK_QM_HypIrq
+MK_LABEL(MK_QM_HypFiq)
+	b		MK_QM_HypFiq
+
+MK_LABEL(MK_QM_ResetAddr)
+	MK_word		boardResetStart
+
+	MK_SECTION_RESET
+	MK_CODE_ARM
+
+	MK_FUNC(boardResetStart)
+MK_LABEL(boardResetStart)
+	//ldr		r0, =MK_QM_ResetArmMode
+	//bx		r0
+	b MK_QM_ResetArmMode
+	MK_FUNC_END(boardResetStart)
+
+
+/* Arm mode entry point after reset. Cortex-R52 boots up in Hyp mode (EL2). See r52 trm, sec 7.3 */
+	MK_FUNC(MK_QM_ResetArmMode)
+MK_LABEL(MK_QM_ResetArmMode)
+
+
+	mov	r0, #0
+	mov	r1, #0
+	mov	r2, #0
+	mov	r3, #0
+	mov	r4, #0
+	mov	r5, #0
+	mov	r6, #0
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
+	mov	r10, #0
+	mov	r11, #0
+	mov	r12, #0
+	mov lr, #0
+
+    /* Disable all regions */
+    mov r0, #0
+    mov r1, #0
+    mov r2, #24
+        
+MK_LABEL(loop)
+    mcr p15, #0, r0, c6, c2, #1
+    mcr p15, #0, r1, c6, c3, #1
+    add r0, r0, #1
+    cmp r0, r2
+    bne loop
+
+	/* Setup TCM base addresses. */
+	MK_QM_GET_CORE_ID	r0, r1			/* Load CoreID into r0; r1 will be clobbered. */
+
+	ldr		r1, =MK_QM_ATcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 0		/* Set A-TCM base. */
+
+	ldr		r1, =MK_QM_BTcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 1		/* Set B-TCM base. */
+
+	ldr		r1, =MK_QM_CTcmBase
+	ldr		r1, [r1, r0, LSL #2]
+	orr     r1, r1, #0x3
+	mcr		p15, 0, r1, c9, c1, 2		/* Set C-TCM base. */
+
+    /* Attribute index 1, normal, cache */
+    mov r0, #0xFF00
+    mcr p15, #0, r0, c10, c2, #0
+    /* Select Region 0 via PRSELR */
+    mov r0, #0
+    mcr p15, #0, r0, c6, c2, #1
+
+    /* BASE - PRBAR[31:6] */
+    ldr r0, =MPU_AREA0_BASE_ADDRESS
+    /* PRBAR[4:3] SH=b'00 - Normal memory, Non-shareable,
+        PRBAR[2:1] AP=b'01 - Read/Write Allocation
+        PRBAR[0]   XN=b'0  - Instruction permitted */
+    ldr r1, =((Non_Shareable<<3) | (RW_Access<<1))
+    orr r0, r0, r1
+    /* Set XN, AP, SH, BASE */
+    mcr p15, #0, r0, c6, c3, #0
+	
+
+
+    /* BASE - PRLAR[31:6] */
+	    LDR r0, =0xDDEEFF44
+    MCR p15, 0, r0, c10, c2, 0   // MAIR0
+
+    LDR     r0, =0xE2100002  // PRBAR0
+    MCR     p15, 0, r0, c6, c8, 0
+    LDR     r0, =0xE2A3FFC3  // PRLAR0
+    MCR     p15, 0, r0, c6, c8, 1
+    LDR     r0, =0x2  // PRBAR1
+    MCR     p15, 0, r0, c6, c8, 4
+    LDR     r0, =0x7FFFFC3  // PRLAR1
+    MCR     p15, 0, r0, c6, c8, 5
+    LDR     r0, =0x8000002  // PRBAR2
+    MCR     p15, 0, r0, c6, c9, 0
+    LDR     r0, =0xBFFFFC1  // PRLAR2
+    MCR     p15, 0, r0, c6, c9, 1
+    LDR     r0, =0xC000002  // PRBAR3
+    MCR     p15, 0, r0, c6, c9, 4
+    LDR     r0, =0x3FFFFFC3  // PRLAR3
+    MCR     p15, 0, r0, c6, c9, 5
+    LDR     r0, =0x40000002  // PRBAR4
+    MCR     p15, 0, r0, c6, c10, 0
+    LDR     r0, =0x402FFFC3  // PRLAR4
+    MCR     p15, 0, r0, c6, c10, 1
+    LDR     r0, =0x40300003  // PRBAR5
+    MCR     p15, 0, r0, c6, c10, 4
+    LDR     r0, =0xBFFFFFC9  // PRLAR5
+    MCR     p15, 0, r0, c6, c10, 5
+    LDR     r0, =0xC0000003  // PRBAR6
+    MCR     p15, 0, r0, c6, c11, 0
+    LDR     r0, =0xDFFFFFC9  // PRLAR6
+    MCR     p15, 0, r0, c6, c11, 1
+    LDR     r0, =0xE2A4001B  // PRBAR7
+    MCR     p15, 0, r0, c6, c11, 4
+    LDR     r0, =0xE2FFFFC1  // PRLAR7
+    MCR     p15, 0, r0, c6, c11, 5
+    LDR     r0, =0xE4C00002  // PRBAR8
+    MCR     p15, 0, r0, c6, c12, 0
+    LDR     r0, =0xE62FFFC9  // PRLAR8
+    MCR     p15, 0, r0, c6, c12, 1
+    LDR     r0, =0xE20E001B  // PRBAR9
+    MCR     p15, 0, r0, c6, c12, 4
+    LDR     r0, =0xE20FFFC3  // PRLAR9
+    MCR     p15, 0, r0, c6, c12, 5
+    LDR     r0, =0xE630001B  // PRBAR10
+    MCR     p15, 0, r0, c6, c13, 0
+    LDR     r0, =0xE63FFFC3  // PRLAR10
+    MCR     p15, 0, r0, c6, c13, 1
+    LDR     r0, =0xE6400003  // PRBAR11
+    MCR     p15, 0, r0, c6, c13, 4
+    LDR     r0, =0xEB0FFFC9  // PRLAR11
+    MCR     p15, 0, r0, c6, c13, 5
+    LDR     r0, =0xEB100002  // PRBAR12
+    MCR     p15, 0, r0, c6, c14, 0
+    LDR     r0, =0xEB127FC3  // PRLAR12
+    MCR     p15, 0, r0, c6, c14, 1
+    LDR     r0, =0xEB128003  // PRBAR13
+    MCR     p15, 0, r0, c6, c14, 4
+    LDR     r0, =0xEB1FFFC9  // PRLAR13
+    MCR     p15, 0, r0, c6, c14, 5
+    LDR     r0, =0xEB200002  // PRBAR14
+    MCR     p15, 0, r0, c6, c15, 0
+    LDR     r0, =0xEB3FFFC3  // PRLAR14
+    MCR     p15, 0, r0, c6, c15, 1
+    LDR     r0, =0xEB400003  // PRBAR15
+    MCR     p15, 0, r0, c6, c15, 4
+    LDR     r0, =0xFFFFFFC9  // PRLAR15
+    MCR     p15, 0, r0, c6, c15, 5
+
+	MOV     r1, #16
+    MCR     p15, 0, r1, c6, c2, 1      // PRSELR = 16
+	LDR     r0, =0xE3000002  // PRBAR16
+    MCR     p15, 0, r0, c6, c3, 0
+    LDR     r0, =0xE3FFFFC9  // PRLAR16
+    MCR     p15, 0, r0, c6, c3, 1
+
+	MOV     r1, #17
+	MCR     p15, 0, r1, c6, c2, 1      // PRSELR = 17
+    LDR     r0, =0xE4000003  // PRBAR17: SH=0b00(Non-Shareable), AP=R/W, XN
+    MCR     p15, 0, r0, c6, c3, 0
+    LDR     r0, =0xE4BFFFC1  // PRLAR17: Attr0(0x44), Non-Cacheable (TCM region)
+    MCR     p15, 0, r0, c6, c3, 1
+
+    /* Enable MPU */
+    mrc p15, #0, r0, c1, c0, #0
+    orr r0, r0, #1
+    dsb
+    mcr p15, #0, r0, c1, c0, #0
+    isb
+
+	MK_QM_GET_CORE_ID	r0, r1			/* Load CoreID into r0; r1 will be clobbered. */
+
+mov		 r4, r0					/* Preserve CoreID for TCM selection. */
+mov		 r2, #0
+mov		 r3, #0
+
+	/* ATCM base = 0xE4000000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE400
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop
+
+mov		 r2, #0
+mov		 r3, #0
+
+	/* BTCM base = 0xE4100000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE410
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop_2)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop_2
+
+mov		 r2, #0
+mov		 r3, #0
+
+	/* CTCM base = 0xE4200000 + (core_id << 22) */
+	movw	 r0, #0x0000
+	movt	 r0, #0xE420
+	mov		 r1, r4, LSL #22
+	add		 r0, r0, r1
+	add		 r1, r0, #0x4000
+
+MK_LABEL(MK_QM_ClearAtcmLoop_3)
+strd	 r2, r3, [r0], #8		/* 8-byte stores also initialize ECC syndrome. */
+cmp		 r0, r1
+bne		 MK_QM_ClearAtcmLoop_3
+
+	ldr		r0, =MK_StartupExceptionTableHyp
+	mcr		p15,4,r0,c12,c0,0				/* Set Hypervisor table in HVBAR */
+
+	/* Set up the Peripheral Port Region Register (IMP_PERIPHPREGIONR)
+		Enable peripheral port at  EL1 and EL0 */
+	mrc		p15, 0, r0, c15, c0, 0
+	orr		r0, 1
+	mcr		p15, 0, r0, c15, c0, 0
+
+	/* Setup TCM base addresses. */
+
+	/* Enable TCM regions in MPU before enabling it. */
+	/* Enable TCM regions in MPU before enabling it. */
+	
+	mrc		p15, 0, r0, c1, c0, 0		/* Load SCTLR */
+	bic		r0, r0, #0x1 << 30			/* Clear TE bit (Exceptions taken in A32 state) */
+	mcr		p15, 0, r0, c1, c0, 0		/* Store SCTLR */
+
+	mrs		r0, cpsr
+	bic		r0, r0, #0x1 << 5			/* Clear Thumb bit */
+	orr		r0, r0, #0x1 << 6			/* Set mask bit F. Disable FIQ. */
+	orr		r0, r0, #0x1 << 7			/* Set mask bit I. Disable IRQ. */
+	orr		r0, r0, #0x1 << 8			/* Set mask bit A. Disable async-aborts. */
+	msr		cpsr, r0					/* Setup mask bits A, F, I and Thumb bit */
+	msr		SPSR_cxsf, r0				/* Will stay set after ERET */
+	
+	
+	ldr		r0, =MK_QM_ResetStartEl1	/* Prepare to switch to EL1 */
+	msr		ELR_hyp, r0					/* Write r0 into ELR_hyp */
+	mrs		r0, SPSR_hyp				/* Read SPSR_hyp into r0 */
+	ldr		r1, =0xffffffc0
+	and		r0, r0, r1					/* r0 = r0 & FFFF FFC0. Clear SPSR_hyp bits [5:0] -> Execution state bit + Mode bits. */
+	ldr		r1, =0x13
+	orr		r0, r0, r1					/* r0 = r0 | 0x13. Set bits b010011 -> Set mode to SVC and A32 */
+	
+	msr		SPSR_hyp, r0				/* Write r0 into SPSR_hyp */	
+	eret
+
+
+MK_LABEL(MK_QM_ResetStartEl1)
+	b		MK_QM_Entry
+	MK_FUNC_END(MK_QM_ResetArmMode)
+
+
+/* Entry vector for cores that are disabled in current configuration. */
+MK_LABEL(MK_QM_CoreIdle)
+	/* We do a pseudo "bl" so the debugger will show this core as disabled in the stack frame. */
+	bl		MK_QM_CoreIdleLoop
+MK_LABEL(MK_QM_CoreIdleLoop)
+	wfe		/* save power */
+	b		MK_QM_CoreIdleLoop
+

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/7_MPU/20260428/Readme.txt

@@ -0,0 +1,6 @@
+<EFBFBD>ý<EFBFBD><EFBFBD><EFBFBD> <20>ٿ<EFBFBD>
+<EFBFBD>ӵ<EFBFBD> <20>輱.
+
+1<EFBFBD><EFBFBD> 8õ <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD> CPU<50><55> memcopy, DDR to RT-VRAM1(Ȯ<><C8AE> <20><><EFBFBD><EFBFBD>) or system 1.3m<EFBFBD><EFBFBD> <20>ɸ<EFBFBD> <20>̰<EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>°<EFBFBD>?
+
+

Customer/HL_Klemove/DRV2.5(ADCU)_for_HKMC/Issue/8_SPI/20260327_debug.txt

@@ -0,0 +1,55 @@
+https://onefieldjira.renesas.com/browse/SOC-3502
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SMA <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ü<><C3BC><EFBFBD>߽<EFBFBD><DFBD>ϱ<EFBFBD>?
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(<28><>: <20><><EFBFBD><EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20>׽<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>)<29><> <20><EFBFBD><EEB6BB> <20>˴ϱ<CBB4>?
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>û<EFBFBD><C3BB> <20><><EFBFBD><EFBFBD> MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϱ<D4B4>?
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ٰ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ߴµ<DFB4>, <20>ش<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI <20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD> <20>ڵ忡<DAB5><E5BFA1> <20>߻<EFBFBD><DFBB>ϴ<EFBFBD><CFB4><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ֽʽÿ<CABD>. <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB>ϴ<EFBFBD> <20><>ġ<EFBFBD><C4A1> SPI API/<2F>ڵ忡 <20><><EFBFBD><EFBFBD> <20>ڼ<EFBFBD><DABC><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֽñ<D6BD> <20>ٶ<EFBFBD><D9B6>ϴ<EFBFBD>.
+
+
+1.<2E><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE>-Ȯ<><C8AE><EFBFBD><EFBFBD>
+
+2. ȸ<>ε<EFBFBD> Ȯ<><C8AE> - Ȯ<><C8AE><EFBFBD><EFBFBD>
+Core0
+Core1 - ADC, MSIOF1
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŷ 1<><31> + ch <20><>Ŷ 4<><34>, ä<>δ<EFBFBD> 1<><31><EFBFBD><EFBFBD> RX <20><><EFBFBD><EFBFBD>, 
+<EFBFBD>ѹ<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ŷ 5<><35>(<28><><EFBFBD><EFBFBD>,1<><31>,~4<><34>) <20><><EFBFBD><EFBFBD>.
+
+<EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> -> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>۸<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
+<EFBFBD>ͼ<EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD> -> <20>ܺ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>۸<EFBFBD> <20><><EFBFBD><EFBFBD>.
+10ms Task<73><6B><EFBFBD><EFBFBD> <20><><EFBFBD>ư<EFBFBD>
+
+Core2 - USS, MSIOF5
+min200<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ũ<EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
+<EFBFBD>ͽ<EFBFBD><EFBFBD>ͳ<EFBFBD> <20><><EFBFBD><EFBFBD>
+
+3. <20>ٺ<EFBFBD>ġ <20><><EFBFBD><EFBFBD>Ȯ<EFBFBD><C8AE> -Ȯ<><C8AE><EFBFBD><EFBFBD>.
+*SpiSupportConcurrentAsyncTransmit 
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> EVB<56><42> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
+
+4. Binh <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ǻ<EFBFBD><C7BB><EFBFBD>
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߻<EFBFBD><DFBB><EFBFBD><EFBFBD><EFBFBD> <20><>, 
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Spi_GulActiveHWUnits<74><73> <20><><EFBFBD><EFBFBD> -> 0
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD> SPI Hw Unit<69><74> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20>ֽʽÿ<CABD>.(arxml)?
+
+AI
+<EFBFBD><EFBFBD><EFBFBD>ɶ<EFBFBD>
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
+<EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>Ʈ
+
+AI.
+arxml<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>
+0.<2E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, Ȯ<><C8AE> <20>ؼ<EFBFBD> <20>ֱ<EFBFBD> -> 
+1. <20><><EFBFBD>ͳ<EFBFBD> -> <20>ͽ<EFBFBD><CDBD>ͳ<EFBFBD>.
+2. <20><><EFBFBD>ɶ<EFBFBD> <20><><EFBFBD><EFBFBD> - not, all(O), cat2
+Not -> 
+Cate2
+3. <20><><EFBFBD><EFBFBD>
+ȭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>8<EFBFBD><38>.
+
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Ƽ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>.
+
+<EFBFBD><EFBFBD>ũ<EFBFBD><EFBFBD>Ʈ,
+<EFBFBD><EFBFBD>ī<EFBFBD>̺<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٽ<EFBFBD>.
+
+*MISO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 104<30><34><EFBFBD><EFBFBD>ũ<EFBFBD>η<EFBFBD> HI<48><49> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.(<28><><EFBFBD><EFBFBD>) <20><><EFBFBD>̽<EFBFBD> <20>̻<EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>
+
+