/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2022 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : Registers of SDMAC on ICUMX ******************************************************************************/ #ifndef SDMAC_REGISTER_H__ #define SDMAC_REGISTER_H__ /* SDMAC on ICUMX base address */ #define ICUMX_SDMAC_BASE (0xFF600000U) /* Channel offset address */ #define ICUMX_SDMAC_CH0 (0x80U * 0U) #define ICUMX_SDMAC_CH1 (0x80U * 1U) #define ICUMX_SDMAC_CH2 (0x80U * 2U) /* SDMAC Interrupt Status Register */ #define ICUMX_DMAISTA (ICUMX_SDMAC_BASE + 0x0020U) /* SDMAC Operation Register */ #define ICUMX_DMAOR (ICUMX_SDMAC_BASE + 0x0060U) /* SDMAC Channel Reset Register */ #define ICUMX_DMACHRST (ICUMX_SDMAC_BASE + 0x0080U) /* SDMAC Source Address Register */ #define ICUMX_DMASAR_0 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0) #define ICUMX_DMASAR_1 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1) #define ICUMX_DMASAR_2 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2) /* SDMAC Destination Address Register */ #define ICUMX_DMADAR_0 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0) #define ICUMX_DMADAR_1 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1) #define ICUMX_DMADAR_2 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2) /* SDMAC Transfer Size Register */ #define ICUMX_DMATSR_0 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0) #define ICUMX_DMATSR_1 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1) #define ICUMX_DMATSR_2 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2) /* SDMAC Transfer Mode Register */ #define ICUMX_DMATMR_0 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0) #define ICUMX_DMATMR_1 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1) #define ICUMX_DMATMR_2 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2) /* SDMAC Channel Control Register */ #define ICUMX_DMACHCR_0 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0) #define ICUMX_DMACHCR_1 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1) #define ICUMX_DMACHCR_2 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2) /* SDMAC Channel Status Register */ #define ICUMX_DMACHSTA_0 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0) #define ICUMX_DMACHSTA_1 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1) #define ICUMX_DMACHSTA_2 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2) /* SDMAC Channel Flag Clear Register */ #define ICUMX_DMACHFCR_0 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0) #define ICUMX_DMACHFCR_1 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1) #define ICUMX_DMACHFCR_2 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2) /* SDMAC Resource Select Register */ #define ICUMX_DMARS_1 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1) #define ICUMX_DMARS_2 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2) #endif /* SDMAC_REGISTER_H__ */