48 lines
2.5 KiB
C
48 lines
2.5 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : SCIF register header
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******************************************************************************/
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#ifndef SCIF_REGISTER_H_
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#define SCIF_REGISTER_H_
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#include <remap_register.h>
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/* SCIF base address */
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/* S4:0xE6C50000(CH3), V4H:0xE6E60000(CH0) */
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#define SCIF_BASE (BASE_SCIF_ADDR)
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#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */
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#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */
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#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */
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#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
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#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */
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#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */
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#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */
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#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */
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#endif /* SCIF_REGISTER_H_ */
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