58 lines
2.8 KiB
C
58 lines
2.8 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : RST register header
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******************************************************************************/
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#ifndef RST_REGISTER_H_
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#define RST_REGISTER_H_
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#include <remap_register.h>
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#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
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#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */
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#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */
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#define RST_MODEMR0_MD31 (1U << 31U)
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#define RST_MODEMR1_MD32 (1U << 0U)
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#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU)
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#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U)
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#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U)
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#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH40 (0x00000008U)
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#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH (0x0000000CU)
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#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH80 (0x0000000EU)
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#define RST_MODEMR0_BOOT_DEV_HYPER_XIP160 (0x00000014U)
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#define RST_MODEMR0_BOOT_DEV_HYPER_XIP80 (0x00000016U)
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#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU)
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#define RST_WDTRSTCR (RST_BASE + 0x0010U)
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/* SCIF / HSCIF clock speed */
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#define MODEMR_SCIF_DLMODE (0x00000000U)
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#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U)
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#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
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#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
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#endif /* RST_REGISTER_H_ */
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