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 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : RST register header
 ******************************************************************************/

#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_

#include <remap_register.h>

#define RST_BASE        (BASE_RESET_ADDR)   /* 0xE6160000 */

#define RST_MODEMR0         (RST_BASE + 0x0000U)    /* Mode pin register0 */
#define RST_MODEMR1         (RST_BASE + 0x0004U)    /* Mode pin register1 */
#define RST_MODEMR0_MD31    (1U << 31U)
#define RST_MODEMR1_MD32    (1U << 0U)

#define RST_MODEMR0_BOOT_DEV_MASK           (0x0000001EU)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160  (0x00000004U)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80   (0x00000006U)
#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH40 (0x00000008U)
#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH   (0x0000000CU)
#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH80   (0x0000000EU)
#define RST_MODEMR0_BOOT_DEV_HYPER_XIP160   (0x00000014U)
#define RST_MODEMR0_BOOT_DEV_HYPER_XIP80    (0x00000016U)
#define RST_MODEMR0_BOOT_DEV_EMMC_50X8      (0x0000001AU)
#define RST_WDTRSTCR        (RST_BASE + 0x0010U)

/* SCIF / HSCIF clock speed */
#define MODEMR_SCIF_DLMODE          (0x00000000U)
#define MODEMR_HSCIF_DLMODE_921600  (0x00000001U)
#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)

#endif /* RST_REGISTER_H_ */