130 lines
6.2 KiB
C
130 lines
6.2 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : CPG register header
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******************************************************************************/
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#ifndef CPG_REGISTER_H__
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#define CPG_REGISTER_H__
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#include <remap_register.h>
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/* CPG base address */
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/* 0xE6150000 */
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#define CPG_BASE (BASE_CPG_ADDR)
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/* Domain Offset Addresses */
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#define D0 (0x4000U * 0U)
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#define D1 (0x4000U * 1U)
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#define D2 (0x4000U * 2U)
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#define D3 (0x4000U * 3U)
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/* CPG write protect */
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#define CPG_CPGWPR (CPG_BASE + 0x0000U + D0)
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/* CPG write protect control */
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#define CPG_CPGWPCR (CPG_BASE + 0x0004U + D0)
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/* Module Stop Control register */
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/* Registers of domain 0 */
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#define CPG_MSTPCR5D0 (CPG_BASE + 0x2D14U + D0) /* HSCIF0, I2C3 */
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#define CPG_MSTPCR6 (CPG_BASE + 0x2D18U) /* R/W 32 Domain0 module stop control register 6 */
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#define CPG_MSTPCR7D0 (CPG_BASE + 0x2D1CU + D0) /* SCIF0 */
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#define CPG_MSTPCR28D0 (CPG_BASE + 0x2D70U + D0) /* FCPR */
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/* Module Stop Status register */
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/* Registers of domain 0 */
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#define CPG_MSTPSR5D0 (CPG_BASE + 0x2E14U + D0) /* HSCIF0, I2C3 */
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#define CPG_MSTPSR6 (CPG_BASE + 0x2E18U) /* R 32 Module stop status register 6 */
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#define CPG_MSTPSR7D0 (CPG_BASE + 0x2E1CU + D0) /* SCIF0 */
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#define CPG_MSTPSR28D0 (CPG_BASE + 0x2E70U + D0) /* FCPR */
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/* Module standby , Software reset */
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#define CPG_SRCR6 (CPG_BASE + 0x2C18U) /* R/W 32 Software reset register 6 */
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#define CPG_SRCR11 (CPG_BASE + 0x2C2CU)
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#define CPG_SRSTCLR6 (CPG_BASE + 0x2C98U) /* W 32 Software reset clearing register 6 */
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#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU)
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#if (RCAR_LSI == RCAR_V4H)
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#define CPG_SRCR28 (CPG_BASE + 0x2C70U)
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#define CPG_SRCR29 (CPG_BASE + 0x2C74U)
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#endif /* RCAR_LSI == RCAR_V4H */
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#define CPGSRCR_PDR11 (0x00002000U) /* Bit13 */
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#if (RCAR_LSI == RCAR_V4H)
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#define CPGSRCR28_VAL (0xCF600000U)
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#define CPGSRCR29_VAL (0x007B3D9EU)
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#endif /* RCAR_LSI == RCAR_V4H */
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#define CPG_D1WACRA00 (CPG_BASE + 0x3900U)
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#define CPG_D2WACRA00 (CPG_BASE + 0x3A00U)
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#define CPG_D3WACRA00 (CPG_BASE + 0x3B00U)
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#define CPG_D1WACR_MSTPCR0 (CPG_BASE + 0x3100U)
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#define CPG_D1WACR_RAHSR0 (CPG_BASE + 0x3180U)
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#define CPG_D1WACR_SRCR0 (CPG_BASE + 0x3500U)
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#define CPG_D1WACR_SRSTCLR0 (CPG_BASE + 0x3580U)
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#define CPG_D2WACR_MSTPCR0 (CPG_BASE + 0x3200U)
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#define CPG_D2WACR_RAHSR0 (CPG_BASE + 0x3280U)
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#define CPG_D2WACR_SRCR0 (CPG_BASE + 0x3600U)
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#define CPG_D2WACR_SRSTCLR0 (CPG_BASE + 0x3680U)
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#define CPG_D3WACR_MSTPCR0 (CPG_BASE + 0x3300U)
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#define CPG_D3WACR_RAHSR0 (CPG_BASE + 0x3380U)
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#define CPG_D3WACR_SRCR0 (CPG_BASE + 0x3700U)
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#define CPG_D3WACR_SRSTCLR0 (CPG_BASE + 0x3780U)
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/* APMU */
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#define APMU_BASE (BASE_APMU_ADDR)
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#if (RCAR_LSI == RCAR_S4)
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#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 only) */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define CORTEX_R_CORE (1U) /* Target Cortex R52 cores (0 to 2) */
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#endif /* RCAR_LSI == RCAR_S4 */
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#define APMU_WPR (APMU_BASE + 0x0004U) /* Write protection register */
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#define APMU_D0_ACCENR (APMU_BASE + 0x0010U) /* Domain0 Access enable register */
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#define APMU_D1_ACCENR (APMU_BASE + 0x0014U) /* Domain1 Access enable register */
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#define APMU_D2_ACCENR (APMU_BASE + 0x0018U) /* Domain2 Access enable register */
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#define APMU_D3_ACCENR (APMU_BASE + 0x001CU) /* Domain3 Access enable register */
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#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */
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#define APMU_CRBAR (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0334U) /* Cortex-R Boot Address Register */
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#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */
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#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */
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#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */
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#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */
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/* SD-IF */
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#define CPG_SD0CKCR0 (CPG_BASE + 0x0870U)
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/* RPC */
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#define CPG_RPCCKCR (CPG_BASE + 0x0874U)
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/* for CPG register setting */
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#define RPCCKCR_RPCFC_MASK (0x1FU) /* Mask for RPCFC bit of CPG_RPCCKCR */
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#define RPCCKCR_RPCFC_160M (0x11U) /* RPC clock 160MHz */
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#define RPCCKCR_RPCFC_80M (0x13U) /* RPC clock 80MHz */
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#define RPCCKCR_RPCFC_40M (0x17U) /* RPC clock 40MHz */
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#define CPG_PLL6CR0 (CPG_BASE + 0x084CU)
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#define CPG_PLLECR (CPG_BASE + 0x0820U)
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#endif /* CPG_REGISTER_H__ */
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