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ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : CPG register header ******************************************************************************/ #ifndef CPG_REGISTER_H__ #define CPG_REGISTER_H__ #include /* CPG base address */ /* 0xE6150000 */ #define CPG_BASE (BASE_CPG_ADDR) /* Domain Offset Addresses */ #define D0 (0x4000U * 0U) #define D1 (0x4000U * 1U) #define D2 (0x4000U * 2U) #define D3 (0x4000U * 3U) /* CPG write protect */ #define CPG_CPGWPR (CPG_BASE + 0x0000U + D0) /* CPG write protect control */ #define CPG_CPGWPCR (CPG_BASE + 0x0004U + D0) /* Module Stop Control register */ /* Registers of domain 0 */ #define CPG_MSTPCR5D0 (CPG_BASE + 0x2D14U + D0) /* HSCIF0, I2C3 */ #define CPG_MSTPCR6 (CPG_BASE + 0x2D18U) /* R/W 32 Domain0 module stop control register 6 */ #define CPG_MSTPCR7D0 (CPG_BASE + 0x2D1CU + D0) /* SCIF0 */ #define CPG_MSTPCR28D0 (CPG_BASE + 0x2D70U + D0) /* FCPR */ /* Module Stop Status register */ /* Registers of domain 0 */ #define CPG_MSTPSR5D0 (CPG_BASE + 0x2E14U + D0) /* HSCIF0, I2C3 */ #define CPG_MSTPSR6 (CPG_BASE + 0x2E18U) /* R 32 Module stop status register 6 */ #define CPG_MSTPSR7D0 (CPG_BASE + 0x2E1CU + D0) /* SCIF0 */ #define CPG_MSTPSR28D0 (CPG_BASE + 0x2E70U + D0) /* FCPR */ /* Module standby , Software reset */ #define CPG_SRCR6 (CPG_BASE + 0x2C18U) /* R/W 32 Software reset register 6 */ #define CPG_SRCR11 (CPG_BASE + 0x2C2CU) #define CPG_SRSTCLR6 (CPG_BASE + 0x2C98U) /* W 32 Software reset clearing register 6 */ #define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) #if (RCAR_LSI == RCAR_V4H) #define CPG_SRCR28 (CPG_BASE + 0x2C70U) #define CPG_SRCR29 (CPG_BASE + 0x2C74U) #endif /* RCAR_LSI == RCAR_V4H */ #define CPGSRCR_PDR11 (0x00002000U) /* Bit13 */ #if (RCAR_LSI == RCAR_V4H) #define CPGSRCR28_VAL (0xCF600000U) #define CPGSRCR29_VAL (0x007B3D9EU) #endif /* RCAR_LSI == RCAR_V4H */ #define CPG_D1WACRA00 (CPG_BASE + 0x3900U) #define CPG_D2WACRA00 (CPG_BASE + 0x3A00U) #define CPG_D3WACRA00 (CPG_BASE + 0x3B00U) #define CPG_D1WACR_MSTPCR0 (CPG_BASE + 0x3100U) #define CPG_D1WACR_RAHSR0 (CPG_BASE + 0x3180U) #define CPG_D1WACR_SRCR0 (CPG_BASE + 0x3500U) #define CPG_D1WACR_SRSTCLR0 (CPG_BASE + 0x3580U) #define CPG_D2WACR_MSTPCR0 (CPG_BASE + 0x3200U) #define CPG_D2WACR_RAHSR0 (CPG_BASE + 0x3280U) #define CPG_D2WACR_SRCR0 (CPG_BASE + 0x3600U) #define CPG_D2WACR_SRSTCLR0 (CPG_BASE + 0x3680U) #define CPG_D3WACR_MSTPCR0 (CPG_BASE + 0x3300U) #define CPG_D3WACR_RAHSR0 (CPG_BASE + 0x3380U) #define CPG_D3WACR_SRCR0 (CPG_BASE + 0x3700U) #define CPG_D3WACR_SRSTCLR0 (CPG_BASE + 0x3780U) /* APMU */ #define APMU_BASE (BASE_APMU_ADDR) #if (RCAR_LSI == RCAR_S4) #define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 only) */ #elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #define CORTEX_R_CORE (1U) /* Target Cortex R52 cores (0 to 2) */ #endif /* RCAR_LSI == RCAR_S4 */ #define APMU_WPR (APMU_BASE + 0x0004U) /* Write protection register */ #define APMU_D0_ACCENR (APMU_BASE + 0x0010U) /* Domain0 Access enable register */ #define APMU_D1_ACCENR (APMU_BASE + 0x0014U) /* Domain1 Access enable register */ #define APMU_D2_ACCENR (APMU_BASE + 0x0018U) /* Domain2 Access enable register */ #define APMU_D3_ACCENR (APMU_BASE + 0x001CU) /* Domain3 Access enable register */ #define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */ #define APMU_CRBAR (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0334U) /* Cortex-R Boot Address Register */ #define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */ #define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */ #define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */ #define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */ /* SD-IF */ #define CPG_SD0CKCR0 (CPG_BASE + 0x0870U) /* RPC */ #define CPG_RPCCKCR (CPG_BASE + 0x0874U) /* for CPG register setting */ #define RPCCKCR_RPCFC_MASK (0x1FU) /* Mask for RPCFC bit of CPG_RPCCKCR */ #define RPCCKCR_RPCFC_160M (0x11U) /* RPC clock 160MHz */ #define RPCCKCR_RPCFC_80M (0x13U) /* RPC clock 80MHz */ #define RPCCKCR_RPCFC_40M (0x17U) /* RPC clock 40MHz */ #define CPG_PLL6CR0 (CPG_BASE + 0x084CU) #define CPG_PLLECR (CPG_BASE + 0x0820U) #endif /* CPG_REGISTER_H__ */