193 lines
11 KiB
Plaintext
193 lines
11 KiB
Plaintext
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Loader linker directive
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******************************************************************************/
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DEFAULTS {
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//Memory
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remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000)
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remap_size = 1M //RT-SRAM size
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rt_sram_addr = 0xEB200000 //RT-SRAM address
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local_ram_addr = 0xfede0000 //LRAM address
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local_ram_size = 128K //LRAM size
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// Size
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//No override area
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stack_size = 16K //ICUMX Loader stack size
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sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K)
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bss_size = 16K
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// Configuration Table
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qosbw_table_size = 4K
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qoswt_table_size = 4K
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rgid_m_table_size = 1K
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rgid_r_table_size = 8K
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rgid_w_table_size = 8K
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rgid_sec_table_size = 8K
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rgid_axi_table_size = 1K
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rgid_gid_table_size = 1K //include .data section
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configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size
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// ICUMX Loader
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ipl_top_addr = 0xEB210000
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ipl_size = 128K //ICUMX Loader size
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vector_table_size = 2K //vector table size
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ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size)
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// Address
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// ICUMX Loader
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vector_table_address_offset = ipl_top_addr - rt_sram_addr
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code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset
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code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size)
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// No override area
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stack_addr_offset = remap_size - stack_size
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sa9_addr_offset = 0x30000
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bss_addr_offset = sa9_addr_offset - bss_size
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// Configuration Table
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configuration_table_address_offset = vector_table_address_offset + vector_table_size
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configuration_table_address = code_fetch_remap_vector_table + vector_table_size
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qosbw_table_address = configuration_table_address
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qoswt_table_address = qosbw_table_address + qosbw_table_size
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rgid_m_table_address = qoswt_table_address + qoswt_table_size
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rgid_r_table_address = rgid_m_table_address + rgid_m_table_size
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rgid_w_table_address = rgid_r_table_address + rgid_r_table_size
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rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size
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rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size
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rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size
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// Offset
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qosbw_table_address_offset = vector_table_address_offset + vector_table_size
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qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size
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rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size
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rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size
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rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size
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rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size
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rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size
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rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size
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ipl_rom_address_offset = configuration_table_address_offset + configuration_size
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}
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MEMORY
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{
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vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP)
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qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW)
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qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT)
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rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
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rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
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rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
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rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
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rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI)
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rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID)
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ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size
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// Physical address
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phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM)
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phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW)
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phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT)
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phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
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phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
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phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
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phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
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phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI))
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phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID))
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phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM)
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// No override area
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sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert
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stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack
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bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area
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local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size // Local RAM
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}
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//
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// Program layout for starting in ROM, copying data to RAM,
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// and continuing to execute out of ROM.
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//
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SECTIONS
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{
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//
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// ROM SECTIONS(Remap)
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//
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// Place .text into fast_memory. Fail if it does not fit.
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.reset ALIGN(4) : > vector_table
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.EIINTTBL_ICU ALIGN(512) : > .
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.qosbw_tbl ALIGN(4) : > qosbw_table
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.qoswt_tbl ALIGN(4) : > qoswt_table
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.rgid_m_tbl ALIGN(4) : > rgid_m_table
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.rgid_r_tbl ALIGN(4) : > rgid_r_table
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.rgid_w_tbl ALIGN(4) : > rgid_w_table
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.rgid_sec_tbl ALIGN(4) : > rgid_sec_table
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.rgid_axi_tbl ALIGN(4) : > rgid_axi_table
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.rgid_gid_tbl ALIGN(4) : > rgid_gid_table
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.data ALIGN(4) : > .
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.text ALIGN(4) : > ipl_rom
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.RE_CR.text ALIGN(4) : > .
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.rosdata ALIGN(4) : > .
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.rodata ALIGN(4) : > .
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.secinfo ALIGN(4) : > .
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.rom_end ALIGN(4) : > .
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.canary ALIGN(4) : > bss
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.bss ALIGN(4) : > .
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// ROM mirror SECTIONS(RT-SRAM)
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_start = ipl_top_addr;
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.ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table
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.ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > .
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.ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table
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.ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table
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.ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table
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.ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table
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.ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table
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.ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table
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.ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table
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.ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table
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.ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > .
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.ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom
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.ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > .
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.ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > .
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.ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > .
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.ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > .
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.cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary.
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//
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// RAM SECTIONS
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//
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.top_stack : > stack
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.RT.stack ALIGN(4) PAD(stack_size) ABS : > .
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.end_stack : > .
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.top.local.ram : > local_ram
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.sdata ALIGN(4) : > .
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.tdata ALIGN(4) : > .
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.sdabase ALIGN(4) : > .
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.end.local.ram : > .
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.sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load
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}
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