/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : Loader linker directive ******************************************************************************/ DEFAULTS { //Memory remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) remap_size = 1M //RT-SRAM size rt_sram_addr = 0xEB200000 //RT-SRAM address local_ram_addr = 0xfede0000 //LRAM address local_ram_size = 128K //LRAM size // Size //No override area stack_size = 16K //ICUMX Loader stack size sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K) bss_size = 16K // Configuration Table qosbw_table_size = 4K qoswt_table_size = 4K rgid_m_table_size = 1K rgid_r_table_size = 8K rgid_w_table_size = 8K rgid_sec_table_size = 8K rgid_axi_table_size = 1K rgid_gid_table_size = 1K //include .data section configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size // ICUMX Loader ipl_top_addr = 0xEB210000 ipl_size = 128K //ICUMX Loader size vector_table_size = 2K //vector table size ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size) // Address // ICUMX Loader vector_table_address_offset = ipl_top_addr - rt_sram_addr code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size) // No override area stack_addr_offset = remap_size - stack_size sa9_addr_offset = 0x30000 bss_addr_offset = sa9_addr_offset - bss_size // Configuration Table configuration_table_address_offset = vector_table_address_offset + vector_table_size configuration_table_address = code_fetch_remap_vector_table + vector_table_size qosbw_table_address = configuration_table_address qoswt_table_address = qosbw_table_address + qosbw_table_size rgid_m_table_address = qoswt_table_address + qoswt_table_size rgid_r_table_address = rgid_m_table_address + rgid_m_table_size rgid_w_table_address = rgid_r_table_address + rgid_r_table_size rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size // Offset qosbw_table_address_offset = vector_table_address_offset + vector_table_size qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size ipl_rom_address_offset = configuration_table_address_offset + configuration_size } MEMORY { vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP) qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW) qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT) rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI) rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID) ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size // Physical address phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM) phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW) phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT) phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI)) phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID)) phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM) // No override area sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size // Local RAM } // // Program layout for starting in ROM, copying data to RAM, // and continuing to execute out of ROM. // SECTIONS { // // ROM SECTIONS(Remap) // // Place .text into fast_memory. Fail if it does not fit. .reset ALIGN(4) : > vector_table .EIINTTBL_ICU ALIGN(512) : > . .qosbw_tbl ALIGN(4) : > qosbw_table .qoswt_tbl ALIGN(4) : > qoswt_table .rgid_m_tbl ALIGN(4) : > rgid_m_table .rgid_r_tbl ALIGN(4) : > rgid_r_table .rgid_w_tbl ALIGN(4) : > rgid_w_table .rgid_sec_tbl ALIGN(4) : > rgid_sec_table .rgid_axi_tbl ALIGN(4) : > rgid_axi_table .rgid_gid_tbl ALIGN(4) : > rgid_gid_table .data ALIGN(4) : > . .text ALIGN(4) : > ipl_rom .RE_CR.text ALIGN(4) : > . .rosdata ALIGN(4) : > . .rodata ALIGN(4) : > . .secinfo ALIGN(4) : > . .rom_end ALIGN(4) : > . .canary ALIGN(4) : > bss .bss ALIGN(4) : > . // ROM mirror SECTIONS(RT-SRAM) _start = ipl_top_addr; .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . .ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table .ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table .ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table .ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table .ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table .ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table .ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table .ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom .ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > . .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . .cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary. // // RAM SECTIONS // .top_stack : > stack .RT.stack ALIGN(4) PAD(stack_size) ABS : > . .end_stack : > . .top.local.ram : > local_ram .sdata ALIGN(4) : > . .tdata ALIGN(4) : > . .sdabase ALIGN(4) : > . .end.local.ram : > . .sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load }