woody/Tool
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add IPL

Browse Source
This commit is contained in:
woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot.h Normal file
View File

@@ -0,0 +1,39 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Access Protection header
******************************************************************************/
#ifndef ACC_PROT_H_
#define ACC_PROT_H_
/* Prototype */
void acc_prot_init(void);
#endif /* ACC_PROT_H_ */

57
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_lifec.h Normal file
View File

@@ -0,0 +1,57 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : LifeC Access Protection header
******************************************************************************/
#ifndef ACC_PROT_LIFEC_H__
#define ACC_PROT_LIFEC_H__
#include <stdint.h>
typedef struct {
uintptr_t address;
uint32_t value;
} LIFEC_SETTING_TABLE;
void acc_prot_lifec(void);
#define LIFEC_GROUP3 (3U)
#define LIFEC_GROUP2 (2U)
#define LIFEC_GROUP1 (1U)
#define LIFEC_GROUP0 (0U)
#define LIFEC_PUBLIC (0U)
#define LIFEC_REG_TGT(RegNo, Bits) (((uint32_t)(RegNo) << 16U) | (uint32_t)(Bits))
#define LIFEC_TGT_M_ICUMX LIFEC_REG_TGT(3U, 13U)
void lifec_set_master_grp(uint32_t target, uint32_t sec_grp, uint32_t safe_grp);
#endif /* ACC_PROT_LIFEC_H__ */

131
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_memory.h Normal file
View File

@@ -0,0 +1,131 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory Access Protection header
******************************************************************************/
#ifndef ACC_PROT_MEMORY_H_
#define ACC_PROT_MEMORY_H_
#include <stdint.h>
#include <remap_register.h>
#define SECDIVnD_BASE (0xFFE90000U)
#define SECDIVnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a)))
#define SECCTRnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a)) + 0x0040U)
#define SPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0500U)/* 0xE6784500U */
#define SPTDIVCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define SPTCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)
#define DPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0400U)/* 0xE6784400U */
#define DPTDIVCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define DPTCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)
#define PROT_GRP0_R_ (uint8_t)(1U << 7U)
#define PROT_GRP0__W (uint8_t)(1U << 3U)
#define PROT_GRP0_RW (PROT_GRP0_R | PROT_GRP0_W)
#define PROT_GRP1_R_ (uint8_t)(1U << 6U)
#define PROT_GRP1__W (uint8_t)(1U << 2U)
#define PROT_GRP1_RW (PROT_GRP1_R | PROT_GRP1_W)
#define PROT_GRP2_R_ (uint8_t)(1U << 5U)
#define PROT_GRP2__W (uint8_t)(1U << 1U)
#define PROT_GRP2_RW (PROT_GRP2_R | PROT_GRP2_W)
#define PROT_GRP3_R_ (uint8_t)(1U << 4U)
#define PROT_GRP3__W (uint8_t)(1U << 0U)
#define PROT_GRP3_RW (PROT_GRP3_R | PROT_GRP3_W)
#define PROT_GRP_ALL (PROT_GRP0__W | PROT_GRP1__W | PROT_GRP2__W | PROT_GRP3__W)
/* 3210 */
#define R_NNNN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NNNY (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ )
#define R_NNYN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP0_R_)
#define R_NNYY (PROT_GRP3_R_ | PROT_GRP2_R_ )
#define R_NYNN (PROT_GRP3_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NYNY (PROT_GRP3_R_ | PROT_GRP1_R_ )
#define R_NYYN (PROT_GRP3_R_ | PROT_GRP0_R_)
#define R_NYYY (PROT_GRP3_R_ )
#define R_YNNN ( PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YNNY ( PROT_GRP2_R_ | PROT_GRP1_R_ | )
#define R_YNYN ( PROT_GRP2_R_ | PROT_GRP0_R_)
#define R_YNYY ( PROT_GRP2_R_ )
#define R_YYNN ( PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YYNY ( PROT_GRP1_R_ )
#define R_YYYN ( PROT_GRP0_R_)
#define R_YYYY ( 0U )
/* 3210 */
#define W_NNNN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_NNNY (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W )
#define W_NNYN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP0__W)
#define W_NNYY (PROT_GRP3__W | PROT_GRP2__W )
#define W_NYNN (PROT_GRP3__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_NYNY (PROT_GRP3__W | PROT_GRP1__W )
#define W_NYYN (PROT_GRP3__W | PROT_GRP0__W)
#define W_NYYY (PROT_GRP3__W )
#define W_YNNN ( PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_YNNY ( PROT_GRP2__W | PROT_GRP1__W | )
#define W_YNYN ( PROT_GRP2__W | PROT_GRP0__W)
#define W_YNYY ( PROT_GRP2__W )
#define W_YYNN ( PROT_GRP1__W | PROT_GRP0__W)
#define W_YYNY ( PROT_GRP1__W )
#define W_YYYN ( PROT_GRP0__W)
#define W_YYYY ( 0U )
#define RT_SRAM_ADDR_END (0x000FF000U)
#define SYSTEM_RAM_ADDR_END (0xFFFFF000U)
#define DRAM_ADDR_END (0x0000002FFFFF0000ULL)
typedef struct {
uint8_t reg_sec;
uint8_t reg_saf;
uint8_t acc_sec;
uint8_t acc_saf;
}RAM_GROUP;
typedef struct {
uint32_t addr_off; /* RT_SRAM_PROT[0] is must be 0x00000000 */
RAM_GROUP prot;
}RT_SRAM_PROT;
typedef struct {
uint32_t addr; /* SYSTEM_RAM_PROT[0] is must be 0xE6300000 */
RAM_GROUP prot;
}SYSTEM_RAM_PROT;
typedef struct {
uint64_t addr; /* DRAM_PROT[0] is must be 0x00000040_00000000 */
RAM_GROUP prot;
}DRAM_PROT;
void acc_prot_rt_sram(void);
void acc_prot_system_ram(void);
void acc_prot_dram(void);
#endif /* ACC_PROT_LIFEC_H__ */

119
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/axi_register.h Normal file
View File

@@ -0,0 +1,119 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AXI-Bus register header
******************************************************************************/
#ifndef AXI_REGISTER_H_
#define AXI_REGISTER_H_
#include <remap_register.h>
/* AXI base address */
#define AXI_BASE (BASE_AXI_ADDR)
/* SDRAM protection */
#define DPTDIVCR0 (AXI_BASE + 0x4400U) /* AXI dram protected area division 0 */
#define DPTDIVCR1 (AXI_BASE + 0x4404U) /* AXI dram protected area division 1 */
#define DPTDIVCR2 (AXI_BASE + 0x4408U) /* AXI dram protected area division 2 */
#define DPTDIVCR3 (AXI_BASE + 0x440CU) /* AXI dram protected area division 3 */
#define DPTDIVCR4 (AXI_BASE + 0x4410U) /* AXI dram protected area division 4 */
#define DPTDIVCR5 (AXI_BASE + 0x4414U) /* AXI dram protected area division 5 */
#define DPTDIVCR6 (AXI_BASE + 0x4418U) /* AXI dram protected area division 6 */
#define DPTDIVCR7 (AXI_BASE + 0x441CU) /* AXI dram protected area division 7 */
#define DPTDIVCR8 (AXI_BASE + 0x4420U) /* AXI dram protected area division 8 */
#define DPTDIVCR9 (AXI_BASE + 0x4424U) /* AXI dram protected area division 9 */
#define DPTDIVCR10 (AXI_BASE + 0x4428U) /* AXI dram protected area division 10 */
#define DPTDIVCR11 (AXI_BASE + 0x442CU) /* AXI dram protected area division 11 */
#define DPTDIVCR12 (AXI_BASE + 0x4430U) /* AXI dram protected area division 12 */
#define DPTDIVCR13 (AXI_BASE + 0x4434U) /* AXI dram protected area division 13 */
#define DPTDIVCR14 (AXI_BASE + 0x4438U) /* AXI dram protected area division 14 */
#define DPTCR0 (AXI_BASE + 0x4440U) /* AXI dram protected area setting 0 */
#define DPTCR1 (AXI_BASE + 0x4444U) /* AXI dram protected area setting 1 */
#define DPTCR2 (AXI_BASE + 0x4448U) /* AXI dram protected area setting 2 */
#define DPTCR3 (AXI_BASE + 0x444CU) /* AXI dram protected area setting 3 */
#define DPTCR4 (AXI_BASE + 0x4450U) /* AXI dram protected area setting 4 */
#define DPTCR5 (AXI_BASE + 0x4454U) /* AXI dram protected area setting 5 */
#define DPTCR6 (AXI_BASE + 0x4458U) /* AXI dram protected area setting 6 */
#define DPTCR7 (AXI_BASE + 0x445CU) /* AXI dram protected area setting 7 */
#define DPTCR8 (AXI_BASE + 0x4460U) /* AXI dram protected area setting 8 */
#define DPTCR9 (AXI_BASE + 0x4464U) /* AXI dram protected area setting 9 */
#define DPTCR10 (AXI_BASE + 0x4468U) /* AXI dram protected area setting 10 */
#define DPTCR11 (AXI_BASE + 0x446CU) /* AXI dram protected area setting 11 */
#define DPTCR12 (AXI_BASE + 0x4470U) /* AXI dram protected area setting 12 */
#define DPTCR13 (AXI_BASE + 0x4474U) /* AXI dram protected area setting 13 */
#define DPTCR14 (AXI_BASE + 0x4478U) /* AXI dram protected area setting 14 */
#define DPTCR15 (AXI_BASE + 0x447CU) /* AXI dram protected area setting 15 */
/* System RAM protection */
#define SPTDIVCR0 (AXI_BASE + 0x4500U) /* AXI system ram protected area division 0 */
#define SPTDIVCR1 (AXI_BASE + 0x4504U) /* AXI system ram protected area division 1 */
#define SPTDIVCR2 (AXI_BASE + 0x4508U) /* AXI system ram protected area division 2 */
#define SPTDIVCR3 (AXI_BASE + 0x450CU) /* AXI system ram protected area division 3 */
#define SPTDIVCR4 (AXI_BASE + 0x4510U) /* AXI system ram protected area division 4 */
#define SPTDIVCR5 (AXI_BASE + 0x4514U) /* AXI system ram protected area division 5 */
#define SPTDIVCR6 (AXI_BASE + 0x4518U) /* AXI system ram protected area division 6 */
#define SPTDIVCR7 (AXI_BASE + 0x451CU) /* AXI system ram protected area division 7 */
#define SPTDIVCR8 (AXI_BASE + 0x4520U) /* AXI system ram protected area division 8 */
#define SPTDIVCR9 (AXI_BASE + 0x4524U) /* AXI system ram protected area division 9 */
#define SPTDIVCR10 (AXI_BASE + 0x4528U) /* AXI system ram protected area division 10 */
#define SPTDIVCR11 (AXI_BASE + 0x452CU) /* AXI system ram protected area division 11 */
#define SPTDIVCR12 (AXI_BASE + 0x4530U) /* AXI system ram protected area division 12 */
#define SPTDIVCR13 (AXI_BASE + 0x4534U) /* AXI system ram protected area division 13 */
#define SPTDIVCR14 (AXI_BASE + 0x4538U) /* AXI system ram protected area division 14 */
#define SPTCR0 (AXI_BASE + 0x4540U) /* AXI system ram protected area setting 0 */
#define SPTCR1 (AXI_BASE + 0x4544U) /* AXI system ram protected area setting 1 */
#define SPTCR2 (AXI_BASE + 0x4548U) /* AXI system ram protected area setting 2 */
#define SPTCR3 (AXI_BASE + 0x454CU) /* AXI system ram protected area setting 3 */
#define SPTCR4 (AXI_BASE + 0x4550U) /* AXI system ram protected area setting 4 */
#define SPTCR5 (AXI_BASE + 0x4554U) /* AXI system ram protected area setting 5 */
#define SPTCR6 (AXI_BASE + 0x4558U) /* AXI system ram protected area setting 6 */
#define SPTCR7 (AXI_BASE + 0x455CU) /* AXI system ram protected area setting 7 */
#define SPTCR8 (AXI_BASE + 0x4560U) /* AXI system ram protected area setting 8 */
#define SPTCR9 (AXI_BASE + 0x4564U) /* AXI system ram protected area setting 9 */
#define SPTCR10 (AXI_BASE + 0x4568U) /* AXI system ram protected area setting 10 */
#define SPTCR11 (AXI_BASE + 0x456CU) /* AXI system ram protected area setting 11 */
#define SPTCR12 (AXI_BASE + 0x4570U) /* AXI system ram protected area setting 12 */
#define SPTCR13 (AXI_BASE + 0x4574U) /* AXI system ram protected area setting 13 */
#define SPTCR14 (AXI_BASE + 0x4578U) /* AXI system ram protected area setting 14 */
#define SPTCR15 (AXI_BASE + 0x457CU) /* AXI system ram protected area setting 15 */
#define EDCINTEN0 (0xFF840040U) /* EDC Interrupt Enable Register 0 */
#define EDCINTEN1 (0xFF840044U) /* EDC Interrupt Enable Register 1 */
#define EDCINTEN2 (0xFF840048U) /* EDC Interrupt Enable Register 2 */
#define EDCINTEN3 (0xFF84004CU) /* EDC Interrupt Enable Register 3 */
#define EDCINTEN5 (0xFF8401C0U) /* EDC Interrupt Enable Register 5 */
#define EDCINTEN6 (0xFF8401C4U) /* EDC Interrupt Enable Register 6 */
#define EDCINTEN7 (0xFF8401C8U) /* EDC Interrupt Enable Register 8 */
#define EDC_CFG (0xFFE90110U) /* EDC Error control Register(RT-SRAM) V3H_2 */
#endif /* AXI_REGISTER_H_ */

42
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg.h Normal file
View File

@@ -0,0 +1,42 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG driver header
******************************************************************************/
#ifndef CPG_H_
#define CPG_H_
#include <stdint.h>
/* Prototype */
void cpg_init(void);
void cpg_release(void);
void cpg_reg_write(uintptr_t mstpcr, uintptr_t mstpsr, uint32_t data);
#endif /* CPG_H_ */

125
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg_register.h Normal file
View File

@@ -0,0 +1,125 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG register header
******************************************************************************/
#ifndef CPG_REGISTER_H__
#define CPG_REGISTER_H__
#include <remap_register.h>
/* CPG base address */
/* 0xE6150000 */
#define CPG_BASE (BASE_CPG_ADDR)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
/* CPG write protect control */
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) /* Module stop status register 0 */
#define CPG_MSTPSR1 (CPG_BASE + 0x0038U) /* Module stop status register 1 */
#define CPG_MSTPSR2 (CPG_BASE + 0x0040U) /* Module stop status register 2 */
#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* Module stop status register 3 */
#define CPG_MSTPSR4 (CPG_BASE + 0x004CU) /* Module stop status register 4 */
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) /* Module stop status register 5 */
#define CPG_MSTPSR6 (CPG_BASE + 0x01C0U) /* Module stop status register 6 */
#define CPG_MSTPSR7 (CPG_BASE + 0x01C4U) /* Module stop status register 7 */
#define CPG_MSTPSR8 (CPG_BASE + 0x09A0U) /* Module stop status register 8 */
#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) /* Module stop status register 9 */
#define CPG_MSTPSR10 (CPG_BASE + 0x09A8U) /* Module stop status register 10 */
#define CPG_MSTPSR11 (CPG_BASE + 0x09ACU) /* Module stop status register 11 */
/* CPG (Realtime) registers */
#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) /* Realtime Module Stop Control Register 0 */
#define CPG_RMSTPCR1 (CPG_BASE + 0x0114U) /* Realtime Module Stop Control Register 1 */
#define CPG_RMSTPCR2 (CPG_BASE + 0x0118U) /* Realtime Module Stop Control Register 2 */
#define CPG_RMSTPCR3 (CPG_BASE + 0x011CU) /* Realtime Module Stop Control Register 3 */
#define CPG_RMSTPCR4 (CPG_BASE + 0x0120U) /* Realtime Module Stop Control Register 4 */
#define CPG_RMSTPCR5 (CPG_BASE + 0x0124U) /* Realtime Module Stop Control Register 5 */
#define CPG_RMSTPCR6 (CPG_BASE + 0x0128U) /* Realtime Module Stop Control Register 6 */
#define CPG_RMSTPCR7 (CPG_BASE + 0x012CU) /* Realtime Module Stop Control Register 7 */
#define CPG_RMSTPCR8 (CPG_BASE + 0x0980U) /* Realtime Module Stop Control Register 8 */
#define CPG_RMSTPCR9 (CPG_BASE + 0x0984U) /* Realtime Module Stop Control Register 9 */
#define CPG_RMSTPCR10 (CPG_BASE + 0x0988U) /* Realtime Module Stop Control Register 10 */
#define CPG_RMSTPCR11 (CPG_BASE + 0x098CU) /* Realtime Module Stop Control Register 11 */
/* CPG (System) registers */
#define CPG_SMSTPCR0 (CPG_BASE + 0x0130U) /* System Module Stop Control Register 0 */
#define CPG_SMSTPCR1 (CPG_BASE + 0x0134U) /* System Module Stop Control Register 1 */
#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) /* System Module Stop Control Register 2 */
#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) /* System Module Stop Control Register 3 */
#define CPG_SMSTPCR4 (CPG_BASE + 0x0140U) /* System Module Stop Control Register 4 */
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) /* System Module Stop Control Register 5 */
#define CPG_SMSTPCR6 (CPG_BASE + 0x0148U) /* System Module Stop Control Register 6 */
#define CPG_SMSTPCR7 (CPG_BASE + 0x014CU) /* System Module Stop Control Register 7 */
#define CPG_SMSTPCR8 (CPG_BASE + 0x0990U) /* System Module Stop Control Register 8 */
#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) /* System Module Stop Control Register 9 */
#define CPG_SMSTPCR10 (CPG_BASE + 0x0998U) /* System Module Stop Control Register 10 */
#define CPG_SMSTPCR11 (CPG_BASE + 0x099CU) /* System Module Stop Control Register 11 */
/* CPG (SECURITY) registers */
#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U) /* Secure Module Stop Control Register 0 */
#define CPG_SCMSTPCR1 (CPG_BASE + 0x0B24U) /* Secure Module Stop Control Register 1 */
#define CPG_SCMSTPCR2 (CPG_BASE + 0x0B28U) /* Secure Module Stop Control Register 2 */
#define CPG_SCMSTPCR3 (CPG_BASE + 0x0B2CU) /* Secure Module Stop Control Register 3 */
#define CPG_SCMSTPCR4 (CPG_BASE + 0x0B30U) /* Secure Module Stop Control Register 4 */
#define CPG_SCMSTPCR5 (CPG_BASE + 0x0B34U) /* Secure Module Stop Control Register 5 */
#define CPG_SCMSTPCR6 (CPG_BASE + 0x0B38U) /* Secure Module Stop Control Register 6 */
#define CPG_SCMSTPCR7 (CPG_BASE + 0x0B3CU) /* Secure Module Stop Control Register 7 */
#define CPG_SCMSTPCR8 (CPG_BASE + 0x0B40U) /* Secure Module Stop Control Register 8 */
#define CPG_SCMSTPCR9 (CPG_BASE + 0x0B44U) /* Secure Module Stop Control Register 9 */
#define CPG_SCMSTPCR10 (CPG_BASE + 0x0B48U) /* Secure Module Stop Control Register 10 */
#define CPG_SCMSTPCR11 (CPG_BASE + 0x0B4CU) /* Secure Module Stop Control Register 11 */
/* CPG (SAFETY) registers */
#define CPG_SAMSTPCR0 (CPG_BASE + 0x0C20U) /* Safety Module Stop Control Register 0 */
#define CPG_SAMSTPCR1 (CPG_BASE + 0x0C24U) /* Safety Module Stop Control Register 1 */
#define CPG_SAMSTPCR2 (CPG_BASE + 0x0C28U) /* Safety Module Stop Control Register 2 */
#define CPG_SAMSTPCR3 (CPG_BASE + 0x0C2CU) /* Safety Module Stop Control Register 3 */
#define CPG_SAMSTPCR4 (CPG_BASE + 0x0C30U) /* Safety Module Stop Control Register 4 */
#define CPG_SAMSTPCR5 (CPG_BASE + 0x0C34U) /* Safety Module Stop Control Register 5 */
#define CPG_SAMSTPCR6 (CPG_BASE + 0x0C38U) /* Safety Module Stop Control Register 6 */
#define CPG_SAMSTPCR7 (CPG_BASE + 0x0C3CU) /* Safety Module Stop Control Register 7 */
#define CPG_SAMSTPCR8 (CPG_BASE + 0x0C40U) /* Safety Module Stop Control Register 8 */
#define CPG_SAMSTPCR9 (CPG_BASE + 0x0C44U) /* Safety Module Stop Control Register 9 */
#define CPG_SAMSTPCR10 (CPG_BASE + 0x0C48U) /* Safety Module Stop Control Register 10 */
#define CPG_SAMSTPCR11 (CPG_BASE + 0x0C4CU) /* Safety Module Stop Control Register 11 */
#define CPG_SRSTCLR2 (CPG_BASE + 0x0948U) /* Software Reset Clearing Register 2 */
/* APMU */
#define APMU_CA53WUPCR (CPG_BASE + 0x1010U) /* Wake-up control register for A53 */
#define APMU_CR7PSTR (CPG_BASE + 0x3040U) /* Wake-up control register for A53 */
/* IMP core */
#define ASTPOFFR (CPG_BASE + 0x0278U) /* Automatic Module clock stop function off register */
#endif /* CPG_REGISTER_H__ */

45
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpu_on.h Normal file
View File

@@ -0,0 +1,45 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Power management driver header
******************************************************************************/
#ifndef CPU_ON_H__
#define CPU_ON_H__
#define RCAR_PWR_TARGET_CR7 (0U)
#define RCAR_PWR_TARGET_CA53 (1U)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
void arm_cpu_on(uint32_t target, uint32_t boot_addr);
#endif /* CPU_ON_H__ */

46
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma.h Normal file
View File

@@ -0,0 +1,46 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA driver header
******************************************************************************/
#ifndef DMA_DRIVER_H__
#define DMA_DRIVER_H__
#include <stdint.h>
#define DMACH (0U)
#define BIT21 (1U << 21U)
void dma_init(void);
void load_start(uint32_t dst, uint32_t src, uint32_t len);
void load_end(void);
void dma_release(void);
#endif /* DMA_DRIVER_H__ */

54
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma_register.h Normal file
View File

@@ -0,0 +1,54 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA register header
******************************************************************************/
#ifndef DMA_REGISTER_H_
#define DMA_REGISTER_H_
#include <remap_register.h>
#define DMACH (0U)
#define BIT21 (1U << 21U)
/* RT-DMAC0(foe RPC) */
#define RTDMA_BASE (BASE_RTDMA_ADDR)
#define DMA_RDMOR (RTDMA_BASE + 0x0060U) /* DMA operation register */
#define DMA_RDMSEC (RTDMA_BASE + 0x0030U)
#define DMA_RDMCHCLR (RTDMA_BASE + 0x0080U) /* DMA channel clear register */
#define DMA_RDMSAR(a) (RTDMA_BASE + 0x8000U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMDAR(a) (RTDMA_BASE + 0x8004U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMTCR(a) (RTDMA_BASE + 0x8008U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMCHCR(a) (RTDMA_BASE + 0x800CU + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMRS(a) (RTDMA_BASE + 0x8040U + ((uint32_t)(a) * 0x0080U))
#endif /* DMA_REGISTER_H_ */

39
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/edcinten.h Normal file
View File

@@ -0,0 +1,39 @@
/*******************************************************************************
* Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : EDC's control header
******************************************************************************/
#ifndef EDCINTEN_H_
#define EDCINTEN_H_
/* Prototype */
void edc_init(void);
#endif /* EDCINTEN_H_ */

118
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/image_load.h Normal file
View File

@@ -0,0 +1,118 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function header
******************************************************************************/
#ifndef LOAD_IMAGE_H_
#define LOAD_IMAGE_H_
/* define */
/* Flash address */
#define FLASH_BASE (0x08000000U)
#define FLASH_SIZE (0x04000000U)
#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U)
/* DRAM address */
#define DRAM_BASE (0x40000000U)
#define DRAM_SIZE (0x80000000U)
#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
/* RT-SRAM */
#define RTSRAM_BASE (0xEB200000U)
#define RTSRAM_SIZE ((1024U-18U)*1024U)
#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
/* ICUMXA Loader */
#define IPL_TOP (0xEB2D8000U)
#define IPL_END (0xEB2FFFFFU)
/* Flash address of content certificate */
#define CONTENT_CERT_SA (6U) /* Content Cert SA6 */
#define SA_SIZE (0x00040000U)
#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA6 offset */
/* Certificate logical address */
extern char __ghsbegin_key_load[];
extern char __ghsbegin_cert_load[];
#define KEY_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_key_load[0])
#define CONTENT_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_cert_load[0])
/* Certificate size */
#define KEY_CERT_SRC_OFFSET (0x00000F00U)
#define KEY_CERT_SIZE (0x00000400U) /* Key cert size */
#define CONTENT_CERT_INFO_SIZE (0x00000400U) /* CA53 program num */
#define CONTENT_CERT_SRC_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_SEC_SIZE)) /* content cert src offsett */
#define CONTENT_CERT_DST_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_DST_SIZE)) /* content cert dst offset */
#define CONTENT_CERT_SEC_SIZE (0x00000800U) /* content cert src size */
#define CONTENT_CERT_DST_SIZE (0x00000400U) /* content cert dst size */
/* Load ID */
#define SECURE_FW_ID (0U)
#define RTOS_ID (1U)
#define CA53_PROGRAM_ID (2U)
/* Number of Max loading image */
#define CA53_MAX_IMAGE (8U) /* CA53 program MAX image num */
#define MAX_PLACED (10U)
/* Cert Info Source Address Offset */
#define SRC_ADDR_OFFSET(x) (((uint32_t)(x) * 0x10U) + 0x08U)
#define TARGET_MEM_DRAM (0U)
#define TARGET_MEM_RTSRAM (1U)
/* get info from cert address offset */
#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
/* struct */
/* load address range */
typedef struct {
uint32_t topadd;
uint32_t endadd;
} ADDRESS_RANGE;
/* load info */
typedef struct{
const char *name; /* store load image name */
uint32_t boot_addr; /* store boot address of image */
uint32_t cert_addr; /* store content cert address */
uint32_t src_addr; /* store source address */
} LOAD_INFO;
/* Prototype */
void load_key_cert(void);
uint32_t load_content_cert(void);
uint32_t load_image(uint32_t cert_addr, uint32_t flash_src_offset,
const char *name);
#endif /* LOAD_IMAGE_H_ */

40
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/ip_control.h Normal file
View File

@@ -0,0 +1,40 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : IP's control header
******************************************************************************/
#ifndef IP_CONTROL_H_
#define IP_CONTROL_H_
/* Prototype */
void ip_init(void);
void ip_release(void);
#endif /* IP_CONTROL_H_ */

307
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/lifec_register.h Normal file
View File

@@ -0,0 +1,307 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : LifeC register header
******************************************************************************/
#ifndef LIFEC_REGISTER_H__
#define LIFEC_REGISTER_H__
#include <remap_register.h>
/* LIFEC0 (SECURITY) registers */
/* LIFEC0 (SECURITY) base address */
#define LIFEC_SEC_BASE (BASE_LIFEC_ADDR)
/* Security attribute setting for master ports */
#define LIFEC_SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
/* Security attribute setting for slave ports 0 */
#define LIFEC_SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
/* Security attribute setting for slave ports 1 */
#define LIFEC_SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
/* Security attribute setting for slave ports 2 */
#define LIFEC_SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
/* Security attribute setting for slave ports 3 */
#define LIFEC_SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
/* Security attribute setting for slave ports 4 */
#define LIFEC_SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
/* Security attribute setting for slave ports 5 */
#define LIFEC_SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
/* Security attribute setting for slave ports 6 */
#define LIFEC_SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
/* Security attribute setting for slave ports 7 */
#define LIFEC_SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
/* Security attribute setting for slave ports 8 */
#define LIFEC_SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
/* Security attribute setting for slave ports 9 */
#define LIFEC_SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
/* Security attribute setting for slave ports 10 */
#define LIFEC_SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
/* Security attribute setting for slave ports 11 */
#define LIFEC_SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
/* Security attribute setting for slave ports 12 */
#define LIFEC_SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
/* Security attribute setting for slave ports 13 */
#define LIFEC_SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
/* Security attribute setting for slave ports 14 */
#define LIFEC_SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
/* Security attribute setting for slave ports 15 */
#define LIFEC_SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
/* Security group 0 attribute setting for master ports 0 */
#define LIFEC_SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
/* Security group 1 attribute setting for master ports 0 */
#define LIFEC_SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
/* Security group 0 attribute setting for master ports 1 */
#define LIFEC_SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
/* Security group 1 attribute setting for master ports 1 */
#define LIFEC_SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
/* Security group 0 attribute setting for master ports 2 */
#define LIFEC_SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
/* Security group 1 attribute setting for master ports 2 */
#define LIFEC_SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
/* Security group 0 attribute setting for master ports 3 */
#define LIFEC_SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
/* Security group 1 attribute setting for master ports 3 */
#define LIFEC_SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
/* Security group 0 attribute setting for slave ports 0 */
#define LIFEC_SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
/* Security group 1 attribute setting for slave ports 0 */
#define LIFEC_SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
/* Security group 0 attribute setting for slave ports 1 */
#define LIFEC_SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
/* Security group 1 attribute setting for slave ports 1 */
#define LIFEC_SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
/* Security group 0 attribute setting for slave ports 2 */
#define LIFEC_SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
/* Security group 1 attribute setting for slave ports 2 */
#define LIFEC_SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
/* Security group 0 attribute setting for slave ports 3 */
#define LIFEC_SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
/* Security group 1 attribute setting for slave ports 3 */
#define LIFEC_SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
/* Security group 0 attribute setting for slave ports 4 */
#define LIFEC_SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
/* Security group 1 attribute setting for slave ports 4 */
#define LIFEC_SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
/* Security group 0 attribute setting for slave ports 5 */
#define LIFEC_SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
/* Security group 1 attribute setting for slave ports 5 */
#define LIFEC_SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
/* Security group 0 attribute setting for slave ports 6 */
#define LIFEC_SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
/* Security group 1 attribute setting for slave ports 6 */
#define LIFEC_SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
/* Security group 0 attribute setting for slave ports 7 */
#define LIFEC_SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
/* Security group 1 attribute setting for slave ports 7 */
#define LIFEC_SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
/* Security group 0 attribute setting for slave ports 8 */
#define LIFEC_SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
/* Security group 1 attribute setting for slave ports 8 */
#define LIFEC_SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
/* Security group 0 attribute setting for slave ports 9 */
#define LIFEC_SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
/* Security group 1 attribute setting for slave ports 9 */
#define LIFEC_SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
/* Security group 0 attribute setting for slave ports 10 */
#define LIFEC_SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
/* Security group 1 attribute setting for slave ports 10 */
#define LIFEC_SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
/* Security group 0 attribute setting for slave ports 11 */
#define LIFEC_SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
/* Security group 1 attribute setting for slave ports 11 */
#define LIFEC_SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
/* Security group 0 attribute setting for slave ports 12 */
#define LIFEC_SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
/* Security group 1 attribute setting for slave ports 12 */
#define LIFEC_SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
/* Security group 0 attribute setting for slave ports 13 */
#define LIFEC_SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
/* Security group 1 attribute setting for slave ports 13 */
#define LIFEC_SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
/* Security group 0 attribute setting for slave ports 14 */
#define LIFEC_SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
/* Security group 1 attribute setting for slave ports 14 */
#define LIFEC_SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
/* Security group 0 attribute setting for slave ports 15 */
#define LIFEC_SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
/* Security group 1 attribute setting for slave ports 15 */
#define LIFEC_SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
/* Security write protection attribute setting for slave ports 0 */
#define LIFEC_SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
/* Security write protection attribute setting for slave ports 1 */
#define LIFEC_SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
/* Security write protection attribute setting for slave ports 2 */
#define LIFEC_SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
/* Security write protection attribute setting for slave ports 3 */
#define LIFEC_SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
/* Security write protection attribute setting for slave ports 4 */
#define LIFEC_SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
/* Security write protection attribute setting for slave ports 5 */
#define LIFEC_SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
/* Security write protection attribute setting for slave ports 6 */
#define LIFEC_SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
/* Security write protection attribute setting for slave ports 7 */
#define LIFEC_SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
/* Security write protection attribute setting for slave ports 8 */
#define LIFEC_SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
/* Security write protection attribute setting for slave ports 9 */
#define LIFEC_SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
/* Security write protection attribute setting for slave ports 10 */
#define LIFEC_SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
/* Security write protection attribute setting for slave ports 11 */
#define LIFEC_SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
/* Security write protection attribute setting for slave ports 12 */
#define LIFEC_SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
/* Security write protection attribute setting for slave ports 13 */
#define LIFEC_SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
/* Security write protection attribute setting for slave ports 14 */
#define LIFEC_SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
/* Security write protection attribute setting for slave ports 15 */
#define LIFEC_SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
/* LIFEC1 (SAFETY) registers */
/* LIFEC1 (SAFETY) base address */
#define LIFEC_SAFE_BASE (LIFEC_SEC_BASE + 0x00010000U)
/* Safety group 0 attribute setting for master ports 0 */
#define LIFEC_SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
/* Safety group 1 attribute setting for master ports 0 */
#define LIFEC_SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
/* Safety group 0 attribute setting for master ports 1 */
#define LIFEC_SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
/* Safety group 1 attribute setting for master ports 1 */
#define LIFEC_SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
/* Safety group 0 attribute setting for master ports 2 */
#define LIFEC_SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
/* Safety group 1 attribute setting for master ports 2 */
#define LIFEC_SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
/* Safety group 0 attribute setting for master ports 3 */
#define LIFEC_SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
/* Safety group 1 attribute setting for master ports 3 */
#define LIFEC_SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
/* Safety group 0 attribute setting for slave ports 0 */
#define LIFEC_SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
/* Safety group 1 attribute setting for slave ports 0 */
#define LIFEC_SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
/* Safety group 0 attribute setting for slave ports 1 */
#define LIFEC_SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
/* Safety group 1 attribute setting for slave ports 1 */
#define LIFEC_SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
/* Safety group 0 attribute setting for slave ports 2 */
#define LIFEC_SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
/* Safety group 1 attribute setting for slave ports 2 */
#define LIFEC_SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
/* Safety group 0 attribute setting for slave ports 3 */
#define LIFEC_SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
/* Safety group 1 attribute setting for slave ports 3 */
#define LIFEC_SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
/* Safety group 0 attribute setting for slave ports 4 */
#define LIFEC_SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
/* Safety group 1 attribute setting for slave ports 4 */
#define LIFEC_SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
/* Safety group 0 attribute setting for slave ports 5 */
#define LIFEC_SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
/* Safety group 1 attribute setting for slave ports 5 */
#define LIFEC_SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
/* Safety group 0 attribute setting for slave ports 6 */
#define LIFEC_SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
/* Safety group 1 attribute setting for slave ports 6 */
#define LIFEC_SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
/* Safety group 0 attribute setting for slave ports 7 */
#define LIFEC_SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
/* Safety group 1 attribute setting for slave ports 7 */
#define LIFEC_SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
/* Safety group 0 attribute setting for slave ports 8 */
#define LIFEC_SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
/* Safety group 1 attribute setting for slave ports 8 */
#define LIFEC_SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
/* Safety group 0 attribute setting for slave ports 9 */
#define LIFEC_SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
/* Safety group 1 attribute setting for slave ports 9 */
#define LIFEC_SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
/* Safety group 0 attribute setting for slave ports 10 */
#define LIFEC_SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
/* Safety group 1 attribute setting for slave ports 10 */
#define LIFEC_SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
/* Safety group 0 attribute setting for slave ports 11 */
#define LIFEC_SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
/* Safety group 1 attribute setting for slave ports 11 */
#define LIFEC_SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
/* Safety group 0 attribute setting for slave ports 12 */
#define LIFEC_SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
/* Safety group 1 attribute setting for slave ports 12 */
#define LIFEC_SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
/* Safety group 0 attribute setting for slave ports 13 */
#define LIFEC_SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
/* Safety group 1 attribute setting for slave ports 13 */
#define LIFEC_SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
/* Safety group 0 attribute setting for slave ports 14 */
#define LIFEC_SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
/* Safety group 1 attribute setting for slave ports 14 */
#define LIFEC_SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
/* Safety group 0 attribute setting for slave ports 15 */
#define LIFEC_SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
/* Safety group 1 attribute setting for slave ports 15 */
#define LIFEC_SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
/* Safety write protection attribute setting for slave ports 0 */
#define LIFEC_SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
/* Safety write protection attribute setting for slave ports 1 */
#define LIFEC_SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
/* Safety write protection attribute setting for slave ports 2 */
#define LIFEC_SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
/* Safety write protection attribute setting for slave ports 3 */
#define LIFEC_SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
/* Safety write protection attribute setting for slave ports 4 */
#define LIFEC_SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
/* Safety write protection attribute setting for slave ports 5 */
#define LIFEC_SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
/* Safety write protection attribute setting for slave ports 6 */
#define LIFEC_SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
/* Safety write protection attribute setting for slave ports 7 */
#define LIFEC_SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
/* Safety write protection attribute setting for slave ports 8 */
#define LIFEC_SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
/* Safety write protection attribute setting for slave ports 9 */
#define LIFEC_SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
/* Safety write protection attribute setting for slave ports 10 */
#define LIFEC_SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
/* Safety write protection attribute setting for slave ports 11 */
#define LIFEC_SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
/* Safety write protection attribute setting for slave ports 12 */
#define LIFEC_SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
/* Safety write protection attribute setting for slave ports 13 */
#define LIFEC_SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
/* Safety write protection attribute setting for slave ports 14 */
#define LIFEC_SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
/* Safety write protection attribute setting for slave ports 15 */
#define LIFEC_SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTER_H__ */

45
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/loader_main.h Normal file
View File

@@ -0,0 +1,45 @@
/*******************************************************************************
* Copyright (c) 2018-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main header
******************************************************************************/
#ifndef LOADER_MAIN_H_
#define LOADER_MAIN_H_
/* define */
#define IPL_VERSION "2.0.5"
/* Global */
extern const char build_message[];
/* prototype */
uint32_t loader_main(void);
#endif /* LOAD_MAIN_H_ */

85
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/log.h Normal file
View File

@@ -0,0 +1,85 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver header
******************************************************************************/
#ifndef LOG_H__
#define LOG_H__
#include <stdint.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) local_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) local_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) local_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) local_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) local_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#define panic \
do { \
local_printf("P:%s\n", __func__); \
while(1){} \
} while (0)
#define FORCE(...) local_printf(__VA_ARGS__)
void local_printf(const char *fmt, ...);
#endif /* LOG_H__ */

54
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mem_io.h Normal file
View File

@@ -0,0 +1,54 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory access driver header
******************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
/* Prototype */
void mem_write8(uintptr_t addr, uint8_t data);
uint8_t mem_read8(uintptr_t addr);
void mem_write16(uintptr_t addr, uint16_t data);
uint16_t mem_read16(uintptr_t addr);
void mem_write32(uintptr_t addr, uint32_t data);
uint32_t mem_read32(uintptr_t addr);
void mem_write64(uintptr_t addr, uint64_t data);
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set);
#if defined(__RH850G3K__)
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif
#endif /* MEM_IO_H_ */

49
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis.h Normal file
View File

@@ -0,0 +1,49 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS driver header
******************************************************************************/
#ifndef MFIS_H__
#define MFIS_H__
#include <stdint.h>
#define MFIS_PROT_CODEVALUE (0xACCE0000U)
#define MFISWPCNTR_WPD_BIT (((uint32_t)1U) << 0U)
typedef struct {
uintptr_t address;
uint32_t value;
} MFIS_SETTING_TABLE;
void mfis_init(void);
#endif /* MFIS_H__ */

76
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis_register.h Normal file
View File

@@ -0,0 +1,76 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS register header
******************************************************************************/
#ifndef MFIS_REGISTER_H_
#define MFIS_REGISTER_H_
#include <remap_register.h>
/* MFIS */
#define MFIS_BASE (BASE_MFIS_ADDR)
#define MFIS_MFIERRCTLR0 (MFIS_BASE + 0x0200U)
#define MFIS_MFIERRCTLR1 (MFIS_BASE + 0x0204U)
#define MFIS_MFIERRCTLR2 (MFIS_BASE + 0x0208U)
#define MFIS_MFIERRCTLR3 (MFIS_BASE + 0x020CU)
#define MFIS_MFIERRCTLR4 (MFIS_BASE + 0x0210U)
#define MFIS_MFIERRCTLR5 (MFIS_BASE + 0x0214U)
#define MFIS_MFIERRCTLR6 (MFIS_BASE + 0x0218U)
#define MFIS_MFIERRCTLR7 (MFIS_BASE + 0x0260U)
#define MFIS_MFIERRCTLR8 (MFIS_BASE + 0x026CU)
#define MFIS_MFIERRCTLR9 (MFIS_BASE + 0x0804U)
#define MFIS_MFIERRCTLR10 (MFIS_BASE + 0x0808U)
#define MFIS_MFIERRCTLR11 (MFIS_BASE + 0x080CU)
#define MFIS_MFIERRCTLR12 (MFIS_BASE + 0x0908U)
#define MFIS_MFIERRCTLR13 (MFIS_BASE + 0x0918U)
#define MFIS_MFIERRTGTR0 (MFIS_BASE + 0x0280U)
#define MFIS_MFIERRTGTR1 (MFIS_BASE + 0x0284U)
#define MFIS_MFIERRTGTR2 (MFIS_BASE + 0x0288U)
#define MFIS_MFIERRTGTR3 (MFIS_BASE + 0x028CU)
#define MFIS_MFIERRTGTR4 (MFIS_BASE + 0x0290U)
#define MFIS_MFIERRTGTR5 (MFIS_BASE + 0x0294U)
#define MFIS_MFIERRTGTR6 (MFIS_BASE + 0x025CU)
#define MFIS_MFIERRTGTR7 (MFIS_BASE + 0x0268U)
#define MFIS_MFIERRTGTR8 (MFIS_BASE + 0x0274U)
#define MFIS_MFIERRTGTR9 (MFIS_BASE + 0x081CU)
#define MFIS_MFIERRTGTR10 (MFIS_BASE + 0x0820U)
#define MFIS_MFIERRTGTR11 (MFIS_BASE + 0x0824U)
#define MFIS_MFIERRTGTR12 (MFIS_BASE + 0x0910U)
#define MFIS_MFIERRTGTR13 (MFIS_BASE + 0x0920U)
#define MFIS_MFISBTSTSR (MFIS_BASE + 0x0604U)
#define MFIS_MFIEXTRQMSKCNTR (MFIS_BASE + 0x08A0U)
#define MFIS_MFISWPCNTR (MFIS_BASE + 0x0900U)
#define MFIS_MFISWACNTR (MFIS_BASE + 0x0904U)
#endif /* MFIS_REGISTER_H_ */

44
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/micro_wait.h Normal file
View File

@@ -0,0 +1,44 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver header
******************************************************************************/
#ifndef MICRO_WAIT_H_
#define MICRO_WAIT_H_
#include <stdint.h>
/* Define */
/* Prototype */
void micro_wait(uint32_t count_us);
#endif /* MICRO_WAIT_H_ */

41
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc.h Normal file
View File

@@ -0,0 +1,41 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC driver header
******************************************************************************/
#ifndef PFC_H__
#define PFC_H__
#include <stdint.h>
void pfc_init(void);
void pfc_reg_write(uintptr_t addr, uint32_t data);
#endif /* PFC_H__ */

207
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc_register.h Normal file
View File

@@ -0,0 +1,207 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC register header
******************************************************************************/
#ifndef PFC_REGISTER_H__
#define PFC_REGISTER_H__
#include <remap_register.h>
/* GPIO base address */
/* 0xE6050000 */
#define GPIO_BASE (BASE_GPIO_ADDR)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
/* Pin functon base address */
/* 0xE6060000 */
#define PFC_BASE (BASE_PFC_ADDR)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IOCTRL0 (PFC_BASE + 0x0300U)
#define PFC_IOCTRL1 (PFC_BASE + 0x0304U)
#define PFC_IOCTRL2 (PFC_BASE + 0x0308U)
#define PFC_IOCTRL3 (PFC_BASE + 0x030CU)
#define PFC_IOCTRL4 (PFC_BASE + 0x0310U)
#define PFC_IOCTRL5 (PFC_BASE + 0x0314U)
#define PFC_IOCTRL6 (PFC_BASE + 0x0318U)
#define PFC_IOCTRL7 (PFC_BASE + 0x031CU)
#define PFC_IOCTRL8 (PFC_BASE + 0x0320U)
#define PFC_IOCTRL9 (PFC_BASE + 0x0324U)
#define PFC_IOCTRL10 (PFC_BASE + 0x0328U)
#define PFC_IOCTRL11 (PFC_BASE + 0x032CU)
#define PFC_IOCTRL12 (PFC_BASE + 0x0330U)
#define PFC_IOCTRL13 (PFC_BASE + 0x0334U)
#define PFC_IOCTRL14 (PFC_BASE + 0x0338U)
#define PFC_IOCTRL15 (PFC_BASE + 0x033CU)
#define PFC_IOCTRL16 (PFC_BASE + 0x0340U)
#define PFC_IOCTRL17 (PFC_BASE + 0x0344U)
#define PFC_IOCTRL18 (PFC_BASE + 0x0348U)
#define PFC_IOCTRL19 (PFC_BASE + 0x034CU)
#define PFC_IOCTRL30 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
#define PFC_IOCTRL32 (PFC_BASE + 0x0388U)
#define PFC_IOCTRL33 (PFC_BASE + 0x038CU)
#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#endif /* PFC_REGISTER_H__ */

38
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos.h Normal file
View File

@@ -0,0 +1,38 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS driver header
******************************************************************************/
#ifndef QOS_INIT_H_
#define QOS_INIT_H_
extern void qos_init(void);
#endif /* QOS_INIT_H_ */

152
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_mstat.h Normal file
View File

@@ -0,0 +1,152 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS MSTAT table header
******************************************************************************/
#ifndef QOS_MSTAT_H_
#define QOS_MSTAT_H_
typedef struct{
uint16_t offset;
uint64_t mstat_fix;
uint64_t mstat_be;
} QOS_MSTAT_SETTING_TABLE;
const QOS_MSTAT_SETTING_TABLE mstat_v2_tbl[] = {
{0x0278U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0298U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0320U, 0x000C04080000FFFFULL, 0x0000000000000000ULL},
{0x0328U, 0x000C04080000FFFFULL, 0x0000000000000000ULL}
};
const QOS_MSTAT_SETTING_TABLE mstat_tbl[] = {
{0x0000U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0008U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0010U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0018U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0020U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0028U, 0x000C04320000FFFFULL, 0x0000000000000000ULL},
{0x0030U, 0x001004040000FFFFULL, 0x0000000000000000ULL},
{0x0038U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0040U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0048U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0050U, 0x001004280000FFFFULL, 0x0000000000000000ULL},
{0x0058U, 0x001004280000FFFFULL, 0x0000000000000000ULL},
{0x0060U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0068U, 0x001404300000FFFFULL, 0x0000000000000000ULL},
{0x0070U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0078U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0080U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0088U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0090U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x0098U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x00A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00A8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00B0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00B8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00C0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00C8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00D0U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x00D8U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL},
{0x00E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x00E8U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL},
{0x00F0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00F8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0100U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0108U, 0x000C04010000FFFFULL, 0x0000000000000000ULL},
{0x0110U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0118U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0120U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL},
{0x0128U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0130U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0138U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0140U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL},
{0x0148U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL},
{0x0150U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL},
{0x0158U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0160U, 0x001404280000FFFFULL, 0x0000000000000000ULL},
{0x0168U, 0x001404280000FFFFULL, 0x0000000000000000ULL},
{0x0170U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0178U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0180U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0188U, 0x000C08200000FFFFULL, 0x0000000000000000ULL},
{0x0190U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x0198U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x01A0U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01A8U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01B0U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01B8U, 0x000C00000000FFFFULL, 0x0000000000000000ULL},
{0x01C0U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x01C8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01D0U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01D8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01E0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x01E8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01F0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x01F8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0200U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0208U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x0210U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0218U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x0220U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0228U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0230U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0238U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0240U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0248U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0250U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0258U, 0x001400000000FFFFULL, 0x0000000000000000ULL},
{0x0260U, 0x001400000000FFFFULL, 0x0000000000000000ULL},
{0x0268U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0270U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0278U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0280U, 0x000C04010000FFFFULL, 0x00100080063FFC01ULL},
{0x0288U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0290U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0298U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x02A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x02A8U, 0x000C04010000FFFFULL, 0x00100060063FFC01ULL},
{0x02B0U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x02B8U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x02C0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02C8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02D0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02D8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02E0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02E8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x02F0U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x02F8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0300U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0308U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0310U, 0x000000000000FFFFULL, 0x00100100063FFC01ULL},
{0x0318U, 0x001404010000FFFFULL, 0x0000000000000000ULL}
};
#endif /* QOS_MSTAT_H_ */

146
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_qoswt.h Normal file
View File

@@ -0,0 +1,146 @@
/*******************************************************************************
* Copyright (c) 2019-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS Write Training table header
******************************************************************************/
#ifndef QOS_QOSWT_H_
#define QOS_QOSWT_H_
typedef struct{
uint16_t offset;
uint64_t qoswt_fix;
uint64_t qoswt_be;
} QOS_QOSWT_SETTING_TABLE;
const QOS_QOSWT_SETTING_TABLE qoswt_tbl[] = {
{0x0800U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0808U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0810U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0818U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0820U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0828U, 0x000C04320000FFFFULL, 0x0000000000000000ULL},
{0x0830U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0838U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0840U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0848U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0850U, 0x001004200000FFFFULL, 0x0000000000000000ULL},
{0x0858U, 0x001004200000FFFFULL, 0x0000000000000000ULL},
{0x0860U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0868U, 0x001404300000C010ULL, 0x0000000000000000ULL},
{0x0870U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0878U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0880U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0888U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0890U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0898U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08A0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08A8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08B0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08B8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08C0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08C8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08D0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08D8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x08E8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08F0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08F8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0900U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0908U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0910U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0918U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0920U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0928U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0930U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0938U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0940U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0948U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0950U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0958U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0960U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0968U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0970U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0978U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0980U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0988U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0990U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0998U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09A0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09A8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09B0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09B8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09C0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09C8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09D0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09D8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09E0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09E8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09F0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09F8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A00U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A08U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A10U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A18U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A20U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A28U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A30U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A38U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0A40U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A48U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A50U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A58U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A60U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A68U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A70U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A78U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A80U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A88U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A90U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A98U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AA0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AA8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AB0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AB8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AC0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AC8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AD0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AD8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AE0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AE8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AF0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AF8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B00U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B08U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B10U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B18U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B20U, 0x0000000000000000ULL, 0x0000000000000000ULL}, /* Ver.2.x only */
{0x0B28U, 0x0000000000000000ULL, 0x0000000000000000ULL} /* Ver.2.x only */
};
#endif /* QOS_QOSWT_H_ */

55
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rcar_def.h Normal file
View File

@@ -0,0 +1,55 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : R-Car common header
******************************************************************************/
#ifndef RCAR_DEF_H_
#define RCAR_DEF_H_
#include "remap_register.h"
/* Product Register */
#define PRR (BASE_PRR_ADDR) /* PRR register */
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */
#define PRR_MAJOR_OFFSET (1U)
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#define PRR_PRODUCT_10 (0x00000000U)
#define PRR_PRODUCT_11 (0x00000001U)
#define PRR_PRODUCT_20 (0x00000010U)
#endif /* RCAR_DEF_H_ */

40
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap.h Normal file
View File

@@ -0,0 +1,40 @@
/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : remap driver header
******************************************************************************/
#ifndef REMAP_H_
#define REMAP_H_
uint32_t remap_get_phys_addr(uint32_t remap_addr);
uint32_t remap_get_remap_addr(uint32_t phys_addr);
void remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr);
void remap_unregister(uint32_t remap_addr);
#endif /* REMAP_H_ */

208
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap_register.h Normal file
View File

@@ -0,0 +1,208 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : remap register header
******************************************************************************/
#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_
#define REMAP_BASE (0xFF1FC400U)
#define SICREMAP2M(a) (REMAP_BASE + ((uint32_t)(a) * (0x0004U)))
#define ICUMX_PROT0PCMD (0xFFFEE090U)
#define ICUMX_PROT0PS (0xFFFEE094U)
#define PROTCMD_START (0xA5U)
#define PROTS0ERR (0x01U)
/* REMAP setting */
/* Remap ID(0 -- 15) */
#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */
#define ICU_REMAP_NUM_CC (14U) /* CC63S */
#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */
#define ICU_REMAP_NUM_RPC (11U) /* RPC */
#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */
#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */
#define ICU_REMAP_NUM_MMC (8U) /* MMC */
#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */
#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */
#define ICU_REMAP_NUM_PRR (0U) /* PRR Register */
/* SICREMAP2M15 */
#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */
/* SICREMAP2M14 */
#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */
/* SICREMAP2M13 */
#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
/* SICREMAP2M12 */
#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */
/* SICREMAP2M11 */
#define ICU_REMAP_RPC (0xEE200000U) /* RPC */
/* SICREMAP2M10 */
#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF */
/* SICREMAP2M9 */
#define ICU_REMAP_MMC (0xEE000000U) /* MMC */
/* SICREMAP2M8 */
#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */
/* SICREMAP2M7 */
#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */
/* SICREMAP2M6 */
#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */
/* SICREMAP2M0 */
#define ICU_REMAP_PRR (0xFFE00000U) /* PRR register */
#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */
#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */
#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */
#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */
#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */
#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */
#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */
#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */
#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */
#define ICU_REMAP5_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP0_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection */
/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U)
/* REMAP14(0xE6600000U) */
#define ICU_REMAP_OFFSET_CC63S (0x00000000U)
#define ICU_REMAP_OFFSET_AXI (0x00184000U) /* (0xE6784000U) */
#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */
#define ICU_REMAP_OFFSET_MSTAT (0x001e0000U) /* (0xE67e0000U) */
#define ICU_REMAP_OFFSET_QOS (0x001F0000U) /* (0xE67F0000U) */
/* REMAP13(0xE6000000U) */
/* GPIO */
#define ICU_REMAP_OFFSET_GPIO0 (0x00050000U)
#define ICU_REMAP_OFFSET_GPIO1 (0x00051000U)
#define ICU_REMAP_OFFSET_GPIO2 (0x00052000U)
#define ICU_REMAP_OFFSET_GPIO3 (0x00053000U)
#define ICU_REMAP_OFFSET_GPIO4 (0x00054000U)
#define ICU_REMAP_OFFSET_GPIO5 (0x00055000U)
/* PFC */
#define ICU_REMAP_OFFSET_PFC (0x00060000U)
/* LIFEC */
#define ICU_REMAP_OFFSET_LIFEC (0x00110000U)
/* CPGA */
#define ICU_REMAP_OFFSET_CPGA (0x00150000U)
/* RESET */
#define ICU_REMAP_OFFSET_RESET (0x00160000U)
/* SYSC */
#define ICU_REMAP_OFFSET_SYSC (0x00180000U)
/* THS1 */
#define ICU_REMAP_OFFSET_THS1 (0x00198000U) /* (0xE6198000U) */
/* REMAP12(0xE6200000U) */
/* MFIS */
#define ICU_REMAP_OFFSET_MFIS (0x00060000U)
/* REMAP11(0xEE200000U) */
/*RPC*/
#define ICU_REMAP_OFFSET_RPC (0x00000000U)
/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define ICU_REMAP_OFFSET_RTDMA (0x00010000U)
#define ICU_REMAP_OFFSET_RTACT (0x00050800U)
/* REMAP9(0xE6E00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U)
/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define ICU_REMAP_OFFSET_SDHI (0x00140000U)
/* REMAP7(0xE6400000U) */
/* HSCIF */
#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U)
/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U)
/* REMAP0(0xFFE00000U) */
/* RT-SRAM Register */
#define ICU_REMAP_OFFSET_RTSRAM_REG (0x00090000U)
/* PRR */
#define ICU_REMAP_OFFSET_PRR (0x00100044U)
/* Calculate the base address of each register after remapping */
#define ICU_REMAP0 (0xFC000000U)
#define ICU_REMAP_CALC(val) (ICU_REMAP0 + ((uint32_t)(val) * 0x00200000U))
/* REMAP15(0xEB200000U) */
#define BASE_RTSRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM)
/* REMAP14(0xE6600000U) */
#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI)
#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT)
#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
/* REMAP13(0xE6000000U) */
#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0)
#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC)
#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1)
/* REMAP12(0xE6200000U) */
#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS)
/* REMAP11(0xEE200000U) */
#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA)
#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTACT)
/* REMAP9(0xE6E00000U) */
#define BASE_SCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP0(0xFFE00000U) */
#define BASE_RTSRAM_REG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_RTSRAM_REG)
#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR)
#endif /* REMAP_REGISTER_H_ */

72
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rom_api.h Normal file
View File

@@ -0,0 +1,72 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : boot ROM API header
******************************************************************************/
#ifndef ROM_API_H__
#define ROM_API_H__
#include <stdint.h>
#include <image_load.h>
#define SBROM_OK (0x00000000U)
#define SBROM_ILLEGAL_INPUT_PARAM_ERR (0x0B000001U)
#define SBROM_ILLEGAL_OEM_HASH_VALUE_ERR (0x0B000008U)
#define SBROM_ILLEGAL_LCS_FOR_OPERATION_ERR (0x0B000010U)
#define SBROM_HASH_NOT_PROGRAMMED_ERR (0x0B000100U)
#define SBROM_PUB_KEY_HASH_VALIDATION_FAILURE (0xF1000006U)
#define SBROM_RSA_SIG_VERIFICATION_FAILED (0xF1000007U)
#define GETLCS_OK (0x00000000U)
#define LCS_CM (0x00000000U) /* CM */
#define LCS_DM (0x00000001U) /* DM */
#define LCS_SD (0x00000003U) /* SD */
#define LCS_SE (0x00000005U) /* SE */
#define LCS_FA (0x00000007U) /* FA */
/* Certificate Logical address */
#define LOGICAL_BOOT_KEY_ADDR (uint32_t)(KEY_CERT_DEST_ADDR)
#define LOGICAL_CONTENT_CERT_ADDR(x) (uint32_t)(CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE + CERT_OFFSET(x))
#define CERT_OFFSET(x) (uint32_t)((uint32_t)(x) * CONTENT_CERT_DST_SIZE)
/* BOOTROM API address for V3H */
#define ROM_SECUREBOOT_API_V3H (0x01104400U)
#define ROM_GET_LCS_V3H (0x01104418U)
typedef uint32_t (*ROM_SECURE_BOOT_API)(uint32_t *pKeyCert,
uint32_t *pContentCert,
void *param);
typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs);
uint32_t ROM_SecureBootAPI(uint32_t *pContentCert);
uint32_t ROM_GetLcs(uint32_t *pLcs);
extern uint32_t rom_api_wrap(uint32_t a, uint32_t b, uint32_t c, uint32_t d);
#endif /* ROM_API_H__ */

42
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc.h Normal file
View File

@@ -0,0 +1,42 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RPC driver header
******************************************************************************/
#ifndef RPC_H__
#define RPC_H__
#include <stdint.h>
void rpc_init(void);
void rpc_release(void);
void rpc_end_state_check(void);
#endif /* RPC_H__ */

67
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc_register.h Normal file
View File

@@ -0,0 +1,67 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RPC register header
******************************************************************************/
#ifndef RPC_REGISTER_H_
#define RPC_REGISTER_H_
#include <remap_register.h>
/* RPC base address */
/* 0xEE200000 */
#define RPC_BASE (BASE_RPC_ADDR)
#define RPC_CMNCR (RPC_BASE + 0x0000U) /* Common control register */
#define RPC_SSLDR (RPC_BASE + 0x0004U) /* SSL delay register */
#define RPC_DRCR (RPC_BASE + 0x000CU) /* Data read control register */
#define RPC_DRCMR (RPC_BASE + 0x0010U) /* Data read command setting register */
#define RPC_DREAR (RPC_BASE + 0x0014U) /* Data read extended address register */
#define RPC_DRENR (RPC_BASE + 0x001CU) /* Data read enable setting register */
#define RPC_SMCR (RPC_BASE + 0x0020U) /* Manual mode control register */
#define RPC_SMCMR (RPC_BASE + 0x0024U) /* Manual mode command setting register */
#define RPC_SMADR (RPC_BASE + 0x0028U) /* Manual mode address setting register */
#define RPC_SMOPR (RPC_BASE + 0x002CU) /* Manual mode option setting register */
#define RPC_SMENR (RPC_BASE + 0x0030U) /* Manual mode enable setting register */
#define RPC_SMRDR0 (RPC_BASE + 0x0038U) /* Manual mode read data register 0 */
#define RPC_SMRDR1 (RPC_BASE + 0x003CU) /* Manual mode read data register 1 */
#define RPC_SMWDR0 (RPC_BASE + 0x0040U) /* Manual mode write data register 0 */
#define RPC_CMNSR (RPC_BASE + 0x0048U) /* Common status register */
#define RPC_DRDMCR (RPC_BASE + 0x0058U) /* Data read dummy cycle setting register */
#define RPC_DRDRENR (RPC_BASE + 0x005CU) /* Data read DDR enable register */
#define RPC_SMDMCR (RPC_BASE + 0x0060U) /* Manual mode dummy cycle setting register */
#define RPC_SMDRENR (RPC_BASE + 0x0064U) /* Manual mode DDR enable registerv */
#define RPC_PHYCNT (RPC_BASE + 0x007CU) /* PHY control register */
#define RPC_OFFSET1 (RPC_BASE + 0x0080U) /* DDR operation */
#define RPC_OFFSET2 (RPC_BASE + 0x0084U) /* */
#define RPC_PHYINT (RPC_BASE + 0x0088U) /* PHY interrupt register */
#define RPC_SEC_CONF (RPC_BASE + 0x00B8U) /* Secure configuration register */
#endif /* RPC_REGISTER_H_ */

53
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rst_register.h Normal file
View File

@@ -0,0 +1,53 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RST register header
******************************************************************************/
#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_
#include <remap_register.h>
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_CR7BAR (RST_BASE + 0x0070U)
#define RST_CR7BAR2 (RST_BASE + 0x0074U)
#define RST_CR7BAR_BAREN ((uint32_t)1U << 4U)
#define RST_CR7BAR2_VLD ((uint32_t)1U << 0U)
#define RST_ICUMXBAR (RST_BASE + 0x0078U)
#define RST_ICUMXBAR_BAREN ((uint32_t)1U << 4U)
#define RST_MODEMR (RST_BASE + 0x0060U) /* Mode pin register */
#define RST_CA53RESCNT (RST_BASE + 0x0044U) /* Reset control register for A53 */
#define RST_CA53CPU0BARL (RST_BASE + 0x0084U)
#define RST_CA53CPU0BARH (RST_BASE + 0x0080U)
#endif /* RST_REGISTER_H_ */

76
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rtsram_register.h Normal file
View File

@@ -0,0 +1,76 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-SRAM register header
******************************************************************************/
#ifndef RTSRAM_REGISTER_H_
#define RTSRAM_REGISTER_H_
#include <remap_register.h>
/* AXI base address */
#define RTSRAM_REG__BASE (BASE_RTSRAM_REG_ADDR)
/* RT-SRAM protection */
#define SECDIV0D (RTSRAM_REG__BASE + 0x0000U) /* RT-SRAM protected area division 0 */
#define SECDIV1D (RTSRAM_REG__BASE + 0x0004U) /* RT-SRAM protected area division 1 */
#define SECDIV2D (RTSRAM_REG__BASE + 0x0008U) /* RT-SRAM protected area division 2 */
#define SECDIV3D (RTSRAM_REG__BASE + 0x000CU) /* RT-SRAM protected area division 3 */
#define SECDIV4D (RTSRAM_REG__BASE + 0x0010U) /* RT-SRAM protected area division 4 */
#define SECDIV5D (RTSRAM_REG__BASE + 0x0014U) /* RT-SRAM protected area division 5 */
#define SECDIV6D (RTSRAM_REG__BASE + 0x0018U) /* RT-SRAM protected area division 6 */
#define SECDIV7D (RTSRAM_REG__BASE + 0x001CU) /* RT-SRAM protected area division 7 */
#define SECDIV8D (RTSRAM_REG__BASE + 0x0020U) /* RT-SRAM protected area division 8 */
#define SECDIV9D (RTSRAM_REG__BASE + 0x0024U) /* RT-SRAM protected area division 9 */
#define SECDIV10D (RTSRAM_REG__BASE + 0x0028U) /* RT-SRAM protected area division 10 */
#define SECDIV11D (RTSRAM_REG__BASE + 0x002CU) /* RT-SRAM protected area division 11 */
#define SECDIV12D (RTSRAM_REG__BASE + 0x0030U) /* RT-SRAM protected area division 12 */
#define SECDIV13D (RTSRAM_REG__BASE + 0x0034U) /* RT-SRAM protected area division 13 */
#define SECDIV14D (RTSRAM_REG__BASE + 0x0038U) /* RT-SRAM protected area division 14 */
#define SECCTR0D (RTSRAM_REG__BASE + 0x0040U) /* RT-SRAM protected area setting 0 */
#define SECCTR1D (RTSRAM_REG__BASE + 0x0044U) /* RT-SRAM protected area setting 1 */
#define SECCTR2D (RTSRAM_REG__BASE + 0x0048U) /* RT-SRAM protected area setting 2 */
#define SECCTR3D (RTSRAM_REG__BASE + 0x004CU) /* RT-SRAM protected area setting 3 */
#define SECCTR4D (RTSRAM_REG__BASE + 0x0050U) /* RT-SRAM protected area setting 4 */
#define SECCTR5D (RTSRAM_REG__BASE + 0x0054U) /* RT-SRAM protected area setting 5 */
#define SECCTR6D (RTSRAM_REG__BASE + 0x0058U) /* RT-SRAM protected area setting 6 */
#define SECCTR7D (RTSRAM_REG__BASE + 0x005CU) /* RT-SRAM protected area setting 7 */
#define SECCTR8D (RTSRAM_REG__BASE + 0x0060U) /* RT-SRAM protected area setting 8 */
#define SECCTR9D (RTSRAM_REG__BASE + 0x0064U) /* RT-SRAM protected area setting 9 */
#define SECCTR10D (RTSRAM_REG__BASE + 0x0068U) /* RT-SRAM protected area setting 10 */
#define SECCTR11D (RTSRAM_REG__BASE + 0x006CU) /* RT-SRAM protected area setting 11 */
#define SECCTR12D (RTSRAM_REG__BASE + 0x0070U) /* RT-SRAM protected area setting 12 */
#define SECCTR13D (RTSRAM_REG__BASE + 0x0074U) /* RT-SRAM protected area setting 13 */
#define SECCTR14D (RTSRAM_REG__BASE + 0x0078U) /* RT-SRAM protected area setting 14 */
#define SECCTR15D (RTSRAM_REG__BASE + 0x007CU) /* RT-SRAM protected area setting 15 */
#endif /* RTSRAM_REGISTER_H_ */

41
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif.h Normal file
View File

@@ -0,0 +1,41 @@
/*******************************************************************************
* Copyright (c) 2018-2019 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver header
******************************************************************************/
#ifndef SCIF_H_
#define SCIF_H_
/* Prototype */
void scif_init(void);
void console_putc(uint8_t outchar);
void scif_release(void);
#endif /* SCIF_H_ */

56
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif_register.h Normal file
View File

@@ -0,0 +1,56 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF register header
******************************************************************************/
#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_
#include <remap_register.h>
/* SCIF0 base address */
/* 0xE6E60000 */
#define SCIF0_BASE (BASE_SCIF_ADDR)
#define SCIF_SCSMR (SCIF0_BASE + 0x0000U) /* 16 Serial mode register */
#define SCIF_SCBRR (SCIF0_BASE + 0x0004U) /* 8 Bit rate register */
#define SCIF_SCSCR (SCIF0_BASE + 0x0008U) /* 16 Serial control register */
#define SCIF_SCFTDR (SCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR (SCIF0_BASE + 0x0010U) /* 16 Serial status register */
#define SCIF_SCFRDR (SCIF0_BASE + 0x0014U) /* 8 Receive FIFO data register */
#define SCIF_SCFCR (SCIF0_BASE + 0x0018U) /* 16 FIFO control register */
#define SCIF_SCFDR (SCIF0_BASE + 0x001CU) /* 16 FIFO data count register */
#define SCIF_SCSPTR (SCIF0_BASE + 0x0020U) /* 16 Serial port register */
#define SCIF_SCLSR (SCIF0_BASE + 0x0024U) /* 16 Line status register */
#define SCIF_DL (SCIF0_BASE + 0x0030U) /* 16 Frequency division register */
#define SCIF_CKS (SCIF0_BASE + 0x0034U) /* 16 Clock Select register */
#endif /* SCIF_REGISTER_H_ */

54
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/sysc_register.h Normal file
View File

@@ -0,0 +1,54 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SYSC register header
******************************************************************************/
#ifndef SYSC_REGISTER_H_
#define SYSC_REGISTER_H_
#include "mem_io.h"
#include "remap_register.h"
#define SYSC_BASE (BASE_SYSC_ADDR) /* (0xE6180000U) */
#define SYSC_PWRSR3 (SYSC_BASE + 0x0140U) /* Power status register CA53-SCU */
#define SYSC_PWRSR7 (SYSC_BASE + 0x0240U) /* Power status register 7 (CR7) */
#define SYSC_SYSCIER (SYSC_BASE + 0x000CU) /* Interrupt enable register */
#define SYSC_SYSCIMR (SYSC_BASE + 0x0010U) /* Interrupt mask register */
#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC status register */
#define SYSC_PWRONCR3 (SYSC_BASE + 0x014CU) /* Power resume control register CA53-SCU */
#define SYSC_PWRONCR7 (SYSC_BASE + 0x024CU) /* Power resume control register 7 (CR7) */
#define SYSC_PWRER3 (SYSC_BASE + 0x0154U) /* Power shutoff/resume error register CA53-SCU */
#define SYSC_PWRER7 (SYSC_BASE + 0x0254U) /* Power shutoff/resume error register 7 (CR7) */
#define SYSC_SYSCISR (SYSC_BASE + 0x0004U) /* Interrupt status register */
#define SYSC_SYSCISCR (SYSC_BASE + 0x0008U) /* Interrupt status clear register */
#define SYSC_WUPMSKCA53 (SYSC_BASE + 0x0018U) /* Wake-up mask register for A53 */
#endif /* SYSC_REGISTER_H_ */

40
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/wdt.h Normal file
View File

@@ -0,0 +1,40 @@
/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : window watchdog timer function header
******************************************************************************/
#ifndef WDT_H__
#define WDT_H__
void wdt_init(void);
void wdt_restart(void);
#endif /* WDT_H__ */