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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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49
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/boot_mon.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;##### Stack Pointer (Memory Image) #####################
;## #
;## H'E632F600 System_stack (MiniMon) #
;## H'E632F800 UND_stack #
;## H'E632FA00 SVC(SWI)_stack #
;## H'E632FC00 ABT_stack #
;## H'E632FE00 FIQ_stack #
;## H'E6323000 IRQ_stack #
;## #
;########################################################
;#System RAM
.EQU STACK_IRQ_ADR, __STACKS_END__ ;# IRQ mode (unused)
.EQU STACK_FIQ_ADR, __STACKS_END__ ;# FIQ mode (unused)
.EQU STACK_ABT_ADR, __STACKS_END__ ;# ABT mode (unused)
.EQU STACK_SVC_ADR, __STACKS_END__ ;# SVC(SWI) mode (unused)
.EQU STACK_UND_ADR, __STACKS_END__ ;# UND mode(unused)
.EQU STACK_SYS_ADR, __STACKS_END__ ;# SYS mode
;#################### CPSR bit ##########################
.EQU PSR_MODE_USER, 0x10 ;#USR mode
.EQU PSR_MODE_FIQ, 0x11 ;#FIQ mode
.EQU PSR_MODE_IRQ, 0x12 ;#IRQ mode
.EQU PSR_MODE_SVC, 0x13 ;#SVC mode
.EQU PSR_MODE_ABT, 0x17 ;#ABT mode
.EQU PSR_MODE_UND, 0x1B ;#UND mode
.EQU PSR_MODE_SYS, 0x1F ;#SYS mode
;# PRR
.EQU PRR , 0xFFF00044 ;#Product Register
;#RWDT
;#R-CarH3 77. RCLK Watchdog Timer
.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter
.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A
.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B
;#SystemWDT
;#R-CarH3 78. System Watchdog Timer
.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter
.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A
.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B

217
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/boot_mon.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.INCLUDE "boot_mon.h"
.ALIGN 4
;#---CACHE_SET--------------------------------------------------------------------------------------
.equ CACHE_MODE,ENABLE ;# ENABLE
;#.equ CACHE_MODE,DISABLE ;# DISABLE
;#--------------------------------------------------------------------------------------------------
;####################################################################################################
;# Vector table
;####################################################################################################
Vector_Table:
LDR PC,=Reset_Handler
LDR PC,=Undefined_Handler
LDR PC,=SVC_Handler
LDR PC,=Prefetch_Handler
LDR PC,=Abort_Handler
NOP
LDR PC,=IRQ_Handler
LDR PC,=FIQ_Handler
;####################################################################################################
;# Exception handler
;####################################################################################################
Undefined_Handler:
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
SVC_Handler:
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
Prefetch_Handler:
SUB R14, R14 , #4
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
Abort_Handler:
SUB R14,R14,#8
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
IRQ_Handler:
SUB R14, R14 , #4
STMFD SP!, {R0-R12,LR}
LDMFD SP!, {R0-R12,PC}^
FIQ_Handler:
SUB R14,R14,#4
STMFD SP!, {R0-R7,LR}
LDMFD SP!, {R0-R7,PC}^
;####################################################################################################
;####################################################################################################
;######
;###### reset handler
;######
;####################################################################################################
;####################################################################################################
Reset_Handler:
Register_init:
LDR R0, =0
LDR R1, =0
LDR R2, =0
LDR R3, =0
LDR R4, =0
LDR R5, =0
LDR R6, =0
LDR R7, =0
LDR R8, =0
LDR R9, =0
LDR R10, =0
LDR R11, =0
LDR R12, =0
LDR R13, =0
LDR R14, =0
;# LDR R15, =0
Set_EnableRAM:
LDR R0, =0xE67F0018
LDR R1, =0x00000001 ;#Resource Alloc On
STR R1, [R0]
Stack_init:
;#--------------------------------------------------------------------------------------------------
Stack_init_irq:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_IRQ
MSR CPSR_c, R1
LDR R0, =STACK_IRQ_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_frq:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_FIQ
MSR CPSR_c, R1
LDR R0, =STACK_FIQ_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_abt:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_ABT
MSR CPSR_c, R1
LDR R0, =STACK_ABT_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_svc:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_SVC
MSR CPSR_c, R1
LDR R0, =STACK_SVC_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_und:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_UND
MSR CPSR_c, R1
LDR R0, =STACK_UND_ADR
MOV SP, R0
;#--------------------------------------------------------------------------------------------------
Stack_init_sys:
MRS R1, CPSR
BIC R1, R1, #0x1F
ORR R1, R1, #PSR_MODE_SYS
MSR CPSR_c, R1
LDR R0, =STACK_SYS_ADR
MOV SP, R0
;####################################################################################################
;#
;# board initialize
;#
;####################################################################################################
;####################################################################################################
;#### RWDT,SystemWDT setting (Timer Disable setting)
;####################################################################################################
.ifdef Area0Boot
Init_set_WDT:
LDR R0, =RWDT_RWTCSRA
LDR R1, =0xA5A5A500 ;#Timer disabled
STR R1, [R0]
Init_set_SYSWDT:
LDR R0, =SYSWDT_WTCSRA
LDR R1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
STR R1, [R0]
.endif
.IF CACHE_MODE == ENABLE
;####################################################################################################
;##### enable I cache
;####################################################################################################
CACHE_ENABLE:
MRC p15, 0, R1, c1, c0, 0 ;# Read System Control Register configuration data
ORR R1, R1, #0x1 <<12 ;# instruction cache enable
MCR p15, 0, r0, c7, c5, 0 ;# Invalidate entire instruction cache
MCR p15, 0, R1, c1, c0, 0 ;# enabled instruction cache
ISB
B CACHE_ENABLE_END
.ENDIF
CACHE_ENABLE_END:
/* clear bss section */
mov r0, #0x0
ldr r1, =__BSS_START__
ldr r2, =__BSS_SIZE__
bss_loop:
subs r2, r2, #4
bcc bss_end
str r0, [r1, +r2]
b bss_loop
bss_end:
.ifdef Area0Boot
/* copy data section */
ldr r0, =__DATA_COPY_START__
ldr r1, =__DATA_START__
ldr r2, =__DATA_SIZE__
data_loop:
subs r2, r2, #4
bcc data_end
ldr r3, [r0, +r2]
str r3, [r1, +r2]
b data_loop
data_end:
.endif
BL InitScif
;####################################################################################################
;#### go to main
;####################################################################################################
Jmp_MAIN_C:
BL Main
.END

11
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/stack.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.section writer_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end

17
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;#RWDT
;#R-CarH3 77. RCLK Watchdog Timer
.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter
.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A
.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B
;#SystemWDT
;#R-CarH3 78. System Watchdog Timer
.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter
.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A
.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B
.EQU PRR , 0xFFF00044 ;#Product Register

126
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;# W0-W30 : 32bit Register (W30=Link Register)
;# X0-X30 : 64bit Register (X30=Link Register)
;# WZR : 32bit Zero Register
;# XZR : 64bit Zero Register
;# WSP : 32bit Stack Pointer
;# SP : 64bit Stack Pointer
.INCLUDE "boot_mon.h"
.ALIGN 4
;# Initialize registers
Register_init:
LDR X0, =0
LDR X1, =0
LDR X2, =0
LDR X3, =0
LDR X4, =0
LDR X5, =0
LDR X6, =0
LDR X7, =0
LDR X8, =0
LDR X9, =0
LDR X10, =0
LDR X11, =0
LDR X12, =0
LDR X13, =0
LDR X14, =0
LDR X15, =0
LDR X16, =0
LDR X17, =0
LDR X18, =0
LDR X19, =0
LDR X20, =0
LDR X21, =0
LDR X22, =0
LDR X23, =0
LDR X24, =0
LDR X25, =0
LDR X26, =0
LDR X27, =0
LDR X28, =0
LDR X29, =0
LDR X30, =0
Set_EnableRAM:
LDR X0, =0xE67F0018
LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM
STR W1, [X0]
;# Loader
LDR x0, =__STACKS_END__
MSR SP_EL0,x0
MSR SP_EL1,x0
MSR SP_EL2,x0
MOV sp,x0
MSR ELR_EL1,x0
MSR ELR_EL2,x0
MSR ELR_EL3,x0
MSR SPSR_EL1,x0
MSR SPSR_EL2,x0
MSR SPSR_EL3,x0
;# Board Initialize
.ifdef Area0Boot
Init_set_WDT:
LDR W0, =RWDT_RWTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled
STR W1, [X0]
Init_set_SYSWDT:
LDR W0, =SYSWDT_WTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
STR W1, [X0]
.endif
;# Enable cache
;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el3
orr x0, x0, #(0x1 << 12)
orr x0, x0, #(0x1 << 1)
orr x0, x0, #(0x1 << 3)
msr sctlr_el3, x0
isb
/* clear bss section */
mov X0, #0x0
ldr X1, =__BSS_START__
ldr X2, =__BSS_SIZE__
bss_loop:
subs X2, X2, #4
bcc bss_end
str W0, [X1, X2]
b bss_loop
bss_end:
.ifdef Area0Boot
/* copy data section */
ldr X0, =__DATA_COPY_START__
ldr X1, =__DATA_START__
ldr X2, =__DATA_SIZE__
data_loop:
subs X2, X2, #4
bcc data_end
ldr W3, [X0, X2]
str W3, [X1, X2]
b data_loop
.endif
data_end:
BL InitScif
BL Main
.END

11
IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/stack.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.section writer_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end

1
IPL/SDK/v3h/src/Dummy_CA53_Program/LICENSE.md Normal file
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Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.

16
IPL/SDK/v3h/src/Dummy_CA53_Program/cert_param.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
/* 0xE6300400 */
const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000;
/* 0xE630048C */
const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000;
/* 0xE63005D4 */
const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000;
/* 0xE63006E4 */
const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000;
/* 0xE6301154 */
const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000;
/* 0xE6301264 */
const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000;

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IPL/SDK/v3h/src/Dummy_CA53_Program/common.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "types.h"
#include "common.h"
#include "devdrv.h"
__attribute__((aligned(32))) uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE];
/************************************************************************/
/*NAME : PutMes */
/************************************************************************/
int32_t PutMess(const char *const mess[])
{
int32_t i=0;
while(mess[i]){
PutStr(mess[i],ENB_RTN);
i++;
}
return(0);
}
/************************************************************************/
/*NAME : PutStr */
/************************************************************************/
int32_t PutStr(const char *str,char rtn)
{
while(*str){
PutChar(*str);
str++;
}
if(rtn == 1){
PutChar(CR_CODE);
PutChar(LF_CODE);
}
return(0);
}
/************************************************************************/
/*NAME : Hex2Ascii */
/************************************************************************/
uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt)
{
long i;
char ch;
for( i = 7; i >= 0; i-- ) {
ch = (char)(hexdata & 0x0F);
if( ch > 9 )
ch += 7;
ch += 0x30;
hexdata >>= 4;
*(str + i) = ch;
}
*(str + 8) = '\0';
*chcnt = 8;
return 0U;
}
uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt)
{
char Count;
char countstart;
uint32_t Compdata;
unsigned char dataB;
uint32_t dataL;
uint32_t i;
Count = 0;
countstart = 0x0;
dataB = 0;
dataL = 10;
while( dataL > 0 ){
Compdata = 1;
i = 1;
while( i < dataL ){
Compdata *= 10;
i++;
}
while( hexdata >= Compdata ){
hexdata -= Compdata;
dataB++;
countstart = 1;
}
if( countstart == 1 ){
*(str++) = dataB + '0';
Count++;
}
dataB = 0;
dataL--;
}
if(Count==0){
*str = '0';
str++;
Count++;
}
*str = '\0';
*chcnt = Count;
return(0);
}
/************************************************************************/
void ChgLtl2Lrg(char *str)
{
while(*str!=0){
if(('a' <= *str)&&(*str<='z'))
*str -= 0x20;
str++;
}
}
char HexAscii2Data(unsigned char *buf,uint32_t *data)
{
char chCnt;
uint32_t tmpData;
*data = 0;
chCnt = 0;
ChgLtl2Lrg(buf);
if(*buf=='@') return(3);
while(*buf){
if(('0'<= *buf)&&(*buf<='9')){
tmpData = (uint32_t)(*buf - '0');
*data <<= 4;
*data |= tmpData;
}else if(('A'<= *buf)&&(*buf<='F')){
tmpData = (uint32_t)(*buf - 55);
*data <<= 4;
*data |= tmpData;
}else{
return(1);
}
buf++;
chCnt++;
if(chCnt>(SIZE_32BIT*2)) return(1);
}
return(0);
}
char HexAscii2Data_64(unsigned char *buf,uintptr_t *data)
{
char chCnt;
uintptr_t tmpData;
*data = 0;
chCnt = 0;
ChgLtl2Lrg(buf);
if(*buf=='@') return(3);
while(*buf){
if(('0'<= *buf)&&(*buf<='9')){
tmpData = (uintptr_t)(*buf - '0');
*data <<= 4;
*data |= tmpData;
}else if(('A'<= *buf)&&(*buf<='F')){
tmpData = (uintptr_t)(*buf - 55);
*data <<= 4;
*data |= tmpData;
}else{
return(1);
}
buf++;
chCnt++;
if(chCnt>(CPU_BYTE_SIZE*2)) return(1);
}
return(0);
}
char Data2HexAscii(uint32_t data,char *buf,char size)
{
char loopCnt,i;
uint32_t tmpData;
switch(size){
case SIZE_8BIT:
data <<= (SIZE_32BIT*8-8);
loopCnt=2;
break;
case SIZE_16BIT:
data <<= (SIZE_32BIT*8-16);
loopCnt=4;
break;
case SIZE_32BIT:
data <<= (SIZE_32BIT*8-32);
loopCnt=8;
break;
}
for(i=0;i<loopCnt;i++,buf++){
tmpData = (data >> (SIZE_32BIT*8-4));
if(tmpData < 0x0a){ /* case 1 to 9 */
*buf = (char)(tmpData + '0');
}else{ /* case A to F */
*buf = (char)(tmpData + 55);
}
data <<= 4;
}
*buf = 0;
return(0);
}
char Data2HexAscii_64(uintptr_t data,char *buf,char size)
{
char loopCnt,i;
uintptr_t tmpData;
switch(size){
case SIZE_8BIT:
data <<= (CPU_BYTE_SIZE*8-8);
loopCnt=2;
break;
case SIZE_16BIT:
data <<= (CPU_BYTE_SIZE*8-16);
loopCnt=4;
break;
case SIZE_32BIT:
data <<= (CPU_BYTE_SIZE*8-32);
loopCnt=8;
break;
#ifdef AArch64
case SIZE_64BIT:
data <<= (CPU_BYTE_SIZE*8-64);
loopCnt=16;
break;
#endif
}
for(i=0;i<loopCnt;i++,buf++){
tmpData = (data >> (CPU_BYTE_SIZE*8-4));
if(tmpData < 0x0a){ /* case 1 to 9 */
*buf = (char)(tmpData + '0');
}else{ /* case A to F */
*buf = (char)(tmpData + 55);
}
data <<= 4;
}
*buf = 0;
return(0);
}
void SoftDelay(uint32_t loop)
{
uint32_t i;
for(i=0;i<loop;i++);
}
void *memset(void *dst, int val, unsigned long count)
{
char *ptr = dst;
while (count--)
*ptr++ = val;
return dst;
}

62
IPL/SDK/v3h/src/Dummy_CA53_Program/devdrv.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "devdrv.h"
#include "scifdrv0.h"
#include "scifdrv0_v3h.h"
#include "scifdrv2.h"
#include "reg_rcargen3.h"
/************************
PutChar *
*************************/
int32_t PutChar(char outChar)
{
uint32_t product;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_H3: /* H3, M3 and M3N setting values are same */
case PRR_PRODUCT_M3:
case PRR_PRODUCT_M3N:
case PRR_PRODUCT_D3:
PutCharSCIF2(outChar);
break;
case PRR_PRODUCT_V3M:
PutCharSCIF0(outChar);
break;
case PRR_PRODUCT_V3H:
PutCharSCIF0_v3h(outChar);
break;
default:
break;
}
return(0);
}
int32_t WaitPutCharSendEnd(void)
{
uint32_t product;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_H3: /* H3, M3 and M3N setting values are same */
case PRR_PRODUCT_M3:
case PRR_PRODUCT_M3N:
case PRR_PRODUCT_D3:
WaitPutScif2SendEnd();
break;
case PRR_PRODUCT_V3M:
WaitPutScif0SendEnd();
break;
case PRR_PRODUCT_V3H:
WaitPutScif0_v3h_SendEnd();
break;
default:
break;
}
}

41
IPL/SDK/v3h/src/Dummy_CA53_Program/include/bit.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef BIT_H
#define BIT_H
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif /* BIT_H */

58
IPL/SDK/v3h/src/Dummy_CA53_Program/include/common.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef COMMON_H
#define COMMON_H
#include <stdint.h>
#ifdef AArch64
//typedef uint64_t uintptr_t;
#define CPU_BYTE_SIZE SIZE_64BIT
#endif
#ifdef AArch32
//typedef uint32_t uintptr_t;
#define CPU_BYTE_SIZE SIZE_32BIT
#endif
#define DIS_RTN 0 /* Disable Return */
#define ENB_RTN 1 /* Enable Return */
#define OK 0x1
#ifndef NULL
#define NULL 0x0
#endif
#define INT_CODE 0x25 /* "%" */
#define BS_CODE 0x08 /* "BS" */
#define CR_CODE 0x0d /* "CR" */
#define SP_CODE 0x20 /* "LF" */
#define LF_CODE 0x0a /* "LF" */
#define SIZE_8BIT 1 // Old name : BYTE_SIZE
#define SIZE_16BIT 2 // Old name : WORD_SIZE
#define SIZE_32BIT 4 // Old name : LONG_SIZE
#define SIZE_64BIT 8 // New
#define COMMAND_BUFFER_SIZE 1024
/****************************
Module Proto Type *
****************************/
int32_t PutMess(const char *const mess[]);
int32_t PutStr(const char *str,char rtn);
uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt);
uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt);
void ChgLtl2Lrg(char *str);
char HexAscii2Data(unsigned char *buf,uint32_t *data);
char HexAscii2Data_64(unsigned char *buf,uintptr_t *data);
char Data2HexAscii(uint32_t data,char *buf,char size);
char Data2HexAscii_64(uintptr_t data,char *buf,char size);
void SoftDelay(uint32_t roop);
#endif

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IPL/SDK/v3h/src/Dummy_CA53_Program/include/devdrv.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef DEVDRV_H
#define DEVDRV_H
int32_t PutChar(char outChar);
int32_t WaitPutCharSendEnd(void);
#endif /* DEVDRV_H */

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IPL/SDK/v3h/src/Dummy_CA53_Program/include/init_scif.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef INITSCIF_H
#define INITSCIF_H
void InitScif(void);
#endif /* INITSCIF_H */

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IPL/SDK/v3h/src/Dummy_CA53_Program/include/main.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef MAIN_H
#define MAIN_H
void Main(void);
#endif /* MAIN_H */

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IPL/SDK/v3h/src/Dummy_CA53_Program/include/reg_rcargen3.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef REG_RCARGEN3_H
#define REG_RCARGEN3_H
//CPG
#define CPG_CPGWPCR 0xE6150904 // R/W 32 CPG Write Protect Control Register
#define CPG_CPGWPR 0xE6150900 // R/W 32 CPG Write Protect Register
#define CPG_FRQCRB 0xE6150004 // R/W 32 Frequency control register B
#define CPG_FRQCRC 0xE61500E0 // R/W 32 Frequency control register C
#define CPG_PLLECR 0xE61500D0 // R/W 32 PLL Enable Control Register
#define CPG_PLL0CR 0xE61500D8 // R/W 32 PLL0 control register
#define CPG_PLL2CR 0xE615002C // R/W 32 PLL2 control register
#define CPG_PLL3CR 0xE61500DC // R/W 32 PLL2 control register
#define CPG_PLL0STPCR 0xE61500F0 // R/W 32 PLL0 Stop Condition Register
#define CPG_PLL2STPCR 0xE61500F8 // R/W 32 PLL2 Stop Condition Register
#define CPG_PLL3STPCR 0xE61500FC // R/W 32 PLL3 Stop Condition Register
#define CPG_PLL4STPCR 0xE61501F8 // R/W 32 PLL4 Stop Condition Register
#define CPG_SD0CKCR 0xE6150074 // R/W 32 SD-IF0 clock frequency control register
#define CPG_SD1CKCR 0xE6150078 // R/W 32 SD-IF1 clock frequency control register
#define CPG_SD2CKCR 0xE6150268 // R/W 32 SD-IF2 clock frequency control register
#define CPG_SD3CKCR 0xE615026C // R/W 32 SD-IF3 clock frequency control register
#define CPG_RPCCKCR 0xE6150238 // R/W 32 RPC clock frequency control register
#define CPG_SSPSRCCKCR 0xE6150248 // R/W 32 SSPSRC clock frequency control register
#define CPG_SSPRSCKCR 0xE615024C // R/W 32 SSPRS clock frequency control register
#define CPG_CANFDCKCR 0xE6150244 // R/W 32 CAN-FD clock frequency control register
#define CPG_MSOCKCR 0xE6150014 // R/W 32 MSIOF clock frequency control register
#define CPG_HDMICKCR 0xE6150250 // R/W 32 HDMI-IF clock frequency control register
#define CPG_CSI0CKCR 0xE615000C // R/W 32 CSI0 clock frequency control register
#define CPG_CSIREFCKCR 0xE6150034 // R/W 32 CSIREF clock frequency control register
#define CPG_RCKCR 0xE6150240 // R/W 32 RCLK frequency control register
#define CPG_DVFSCR0 0xE6150058 // R/W 32 DVFS control register 0
#define CPG_DVFSCR1 0xE615005C // R/W 32 DVFS control register 1
#define CPG_FSAPBR 0xE6150700 // R/W 32 Functional safety of APB bus interface register
#define CPG_FSCLKCSR 0xE6150704 // R/W 32 Functional safety of clocks control/status register
#define CPG_FSCNTCHKH0 0xE6150710 // R/W 32 Functional safety of clocks counter check H register 0
#define CPG_FSCNTCHKH1 0xE6150714 // R/W 32 Functional safety of clocks counter check H register 1
#define CPG_FSCNTCHKH2 0xE6150718 // R/W 32 Functional safety of clocks counter check H register 2
#define CPG_FSCNTCHKH3 0xE615071C // R/W 32 Functional safety of clocks counter check H register 3
#define CPG_FSCNTCHKH4 0xE6150720 // R/W 32 Functional safety of clocks counter check H register 4
#define CPG_FSCNTCHKH5 0xE6150724 // R/W 32 Functional safety of clocks counter check H register 5
#define CPG_FSCNTCHKH6 0xE6150728 // R/W 32 Functional safety of clocks counter check H register 6
#define CPG_FSCNTCHKL0 0xE6150730 // R/W 32 Functional safety of clocks counter check L register 0
#define CPG_FSCNTCHKL1 0xE6150734 // R/W 32 Functional safety of clocks counter check L register 1
#define CPG_FSCNTCHKL2 0xE6150738 // R/W 32 Functional safety of clocks counter check L register 2
#define CPG_FSCNTCHKL3 0xE615073C // R/W 32 Functional safety of clocks counter check L register 3
#define CPG_FSCNTCHKL4 0xE6150740 // R/W 32 Functional safety of clocks counter check L register 4
#define CPG_FSCNTCHKL5 0xE6150744 // R/W 32 Functional safety of clocks counter check L register 5
#define CPG_FSCNTCHKL6 0xE6150748 // R/W 32 Functional safety of clocks counter check L register 6
#define CPG_FSCNTMON0 0xE6150750 // R 32 Functional safety of clocks monitor register 0
#define CPG_FSCNTMON1 0xE6150754 // R 32 Functional safety of clocks monitor register 1
#define CPG_FSCNTMON2 0xE6150758 // R 32 Functional safety of clocks monitor register 2
#define CPG_FSCNTMON3 0xE615075C // R 32 Functional safety of clocks monitor register 3
#define CPG_FSCNTMON4 0xE6150760 // R 32 Functional safety of clocks monitor register 4
#define CPG_FSCNTMON5 0xE6150764 // R 32 Functional safety of clocks monitor register 5
#define CPG_FSCNTMON6 0xE6150768 // R 32 Functional safety of clocks monitor register 6
#define CPG_FSRCHKRA0 0xE6150A00 // R 32 Functional safety reset check register A 0
#define CPG_FSRCHKRA1 0xE6150A04 // R 32 Functional safety reset check register A 1
#define CPG_FSRCHKRA2 0xE6150A08 // R 32 Functional safety reset check register A 2
#define CPG_FSRCHKRA3 0xE6150A0C // R 32 Functional safety reset check register A 3
#define CPG_FSRCHKRA4 0xE6150A10 // R 32 Functional safety reset check register A 4
#define CPG_FSRCHKRA5 0xE6150A14 // R 32 Functional safety reset check register A 5
#define CPG_FSRCHKRA6 0xE6150A18 // R 32 Functional safety reset check register A 6
#define CPG_FSRCHKRA7 0xE6150A1C // R 32 Functional safety reset check register A 7
#define CPG_FSRCHKRA8 0xE6150A20 // R 32 Functional safety reset check register A 8
#define CPG_FSRCHKRA9 0xE6150A24 // R 32 Functional safety reset check register A 9
#define CPG_FSRCHKRA10 0xE6150A28 // R 32 Functional safety reset check register A 10
#define CPG_FSRCHKRA11 0xE6150A2C // R 32 Functional safety reset check register A 11
#define CPG_FSRCHKRA12 0xE6150A30 // R 32 Functional safety reset check register A 12
#define CPG_FSRCHKRA13 0xE6150A34 // R 32 Functional safety reset check register A 13
#define CPG_FSRCHKRA14 0xE6150A38 // R 32 Functional safety reset check register A 14
#define CPG_FSRCHKRA15 0xE6150A3C // R 32 Functional safety reset check register A 15
#define CPG_FSRCHKRA16 0xE6150B50 // R 32 Functional safety reset check register A 16
#define CPG_FSRCHKRA17 0xE6150B54 // R 32 Functional safety reset check register A 17
#define CPG_FSRCHKRA18 0xE6150B58 // R 32 Functional safety reset check register A 18
#define CPG_FSRCHKRB0 0xE6150A30 // R 32 Functional safety reset check register B 0
#define CPG_FSRCHKRB1 0xE6150A34 // R 32 Functional safety reset check register B 1
#define CPG_FSRCHKRB2 0xE6150A38 // R 32 Functional safety reset check register B 2
#define CPG_FSRCHKRB3 0xE6150A3C // R 32 Functional safety reset check register B 3
#define CPG_FSRCHKRB4 0xE6150A40 // R 32 Functional safety reset check register B 4
#define CPG_FSRCHKRB5 0xE6150A44 // R 32 Functional safety reset check register B 5
#define CPG_FSRCHKRB6 0xE6150A48 // R 32 Functional safety reset check register B 6
#define CPG_FSRCHKRB7 0xE6150A4C // R 32 Functional safety reset check register B 7
#define CPG_FSRCHKRB8 0xE6150A50 // R 32 Functional safety reset check register B 8
#define CPG_FSRCHKRB9 0xE6150A54 // R 32 Functional safety reset check register B 9
#define CPG_FSRCHKRB10 0xE6150A58 // R 32 Functional safety reset check register B 10
#define CPG_FSRCHKRB11 0xE6150A5C // R 32 Functional safety reset check register B 11
#define CPG_FSRCHKRB13 0xE6150A74 // R 32 Functional safety reset check register B 13
#define CPG_FSRCHKSETR0 0xE6150A60 // W 32 Functional safety reset check set register 0
#define CPG_FSRCHKSETR1 0xE6150A64 // W 32 Functional safety reset check set register 1
#define CPG_FSRCHKSETR2 0xE6150A68 // W 32 Functional safety reset check set register 2
#define CPG_FSRCHKSETR3 0xE6150A6C // W 32 Functional safety reset check set register 3
#define CPG_FSRCHKSETR4 0xE6150A70 // W 32 Functional safety reset check set register 4
#define CPG_FSRCHKSETR5 0xE6150A74 // W 32 Functional safety reset check set register 5
#define CPG_FSRCHKSETR6 0xE6150A78 // W 32 Functional safety reset check set register 6
#define CPG_FSRCHKSETR7 0xE6150A7C // W 32 Functional safety reset check set register 7
#define CPG_FSRCHKSETR8 0xE6150A80 // W 32 Functional safety reset check set register 8
#define CPG_FSRCHKSETR9 0xE6150A84 // W 32 Functional safety reset check set register 9
#define CPG_FSRCHKSETR10 0xE6150A88 // W 32 Functional safety reset check set register 10
#define CPG_FSRCHKSETR11 0xE6150A8C // W 32 Functional safety reset check set register 11
#define CPG_FSRCHKSETR12 0xE6150AB0 // W 32 Functional safety reset check set register 12
#define CPG_FSRCHKSETR13 0xE6150AB4 // W 32 Functional safety reset check set register 13
#define CPG_FSRCHKSETR14 0xE6150AB8 // W 32 Functional safety reset check set register 14
#define CPG_FSRCHKSETR15 0xE6150ABC // W 32 Functional safety reset check set register 15
#define CPG_FSRCHKSETR16 0xE6150B60 // W 32 Functional safety reset check set register 16
#define CPG_FSRCHKSETR17 0xE6150B64 // W 32 Functional safety reset check set register 17
#define CPG_FSRCHKSETR18 0xE6150B68 // W 32 Functional safety reset check set register 18
#define CPG_FSRCHKCLRR0 0xE6150A90 // W 32 Functional safety reset check clear register 0
#define CPG_FSRCHKCLRR1 0xE6150A94 // W 32 Functional safety reset check clear register 1
#define CPG_FSRCHKCLRR2 0xE6150A98 // W 32 Functional safety reset check clear register 2
#define CPG_FSRCHKCLRR3 0xE6150A9C // W 32 Functional safety reset check clear register 3
#define CPG_FSRCHKCLRR4 0xE6150AA0 // W 32 Functional safety reset check clear register 4
#define CPG_FSRCHKCLRR5 0xE6150AA4 // W 32 Functional safety reset check clear register 5
#define CPG_FSRCHKCLRR6 0xE6150AA8 // W 32 Functional safety reset check clear register 6
#define CPG_FSRCHKCLRR7 0xE6150AAC // W 32 Functional safety reset check clear register 7
#define CPG_FSRCHKCLRR8 0xE6150AB0 // W 32 Functional safety reset check clear register 8
#define CPG_FSRCHKCLRR9 0xE6150AB4 // W 32 Functional safety reset check clear register 9
#define CPG_FSRCHKCLRR10 0xE6150AB8 // W 32 Functional safety reset check clear register 10
#define CPG_FSRCHKCLRR11 0xE6150ABC // W 32 Functional safety reset check clear register 11
#define CPG_FSRCHKCLRR12 0xE6150AF0 // W 32 Functional safety reset check clear register 12
#define CPG_FSRCHKCLRR13 0xE6150AF4 // W 32 Functional safety reset check clear register 13
#define CPG_FSRCHKCLRR14 0xE6150AF8 // W 32 Functional safety reset check clear register 14
#define CPG_FSRCHKCLRR15 0xE6150AFC // W 32 Functional safety reset check clear register 15
#define CPG_FSRCHKCLRR16 0xE6150B70 // W 32 Functional safety reset check clear register 16
#define CPG_FSRCHKCLRR17 0xE6150B74 // W 32 Functional safety reset check clear register 17
#define CPG_FSRCHKCLRR18 0xE6150B78 // W 32 Functional safety reset check clear register 18
#define CPG_FSSEQCHKR 0xE6150AF0 // R 32 Functional safety Power on sequence Check Register
#define CPG_FSSEQCHKCSR 0xE6150AF4 // R/W 32 Functional safety Power on sequence Check Control/Status Register
//GPIO
#define GPIO_IOINTSEL0 0xE6050000 // R/W 32 General IO/interrupt switching register 0
#define GPIO_INOUTSEL0 0xE6050004 // R/W 32 General input/output switching register 0
#define GPIO_OUTDT0 0xE6050008 // R/W 32 General output register 0
#define GPIO_INDT0 0xE605000C // R 32 General input register 0
#define GPIO_INTDT0 0xE6050010 // R 32 Interrupt display register 0
#define GPIO_INTCLR0 0xE6050014 // R/W 32 Interrupt clear register 0
#define GPIO_INTMSK0 0xE6050018 // R/W 32 Interrupt mask register 0
#define GPIO_MSKCLR0 0xE605001C // R/W 32 Interrupt mask clear register 0
#define GPIO_POSNEG0 0xE6050020 // R/W 32 Positive/negative logic select register 0
#define GPIO_EDGLEVEL0 0xE6050024 // R/W 32 Edge/level select register 0
#define GPIO_FILONOFF0 0xE6050028 // R/W 32 Chattering prevention on/off register 0
#define GPIO_INTMSKS0 0xE6050038 // R/W 32 Interrupt sub mask register 0
#define GPIO_MSKCLRS0 0xE605003C // R/W 32 Interrupt sub mask clear register 0
#define GPIO_OUTDTSEL0 0xE6050040 // R/W 32 Output data select register 0
#define GPIO_OUTDTH0 0xE6050044 // R/W 32 Output data high register 0
#define GPIO_OUTDTL0 0xE6050048 // R/W 32 Output data low register 0
#define GPIO_BOTHEDGE0 0xE605004C // R/W 32 One edge/both edge select register 0
#define GPIO_IOINTSEL1 0xE6051000 // R/W 32 General IO/interrupt switching register 1
#define GPIO_INOUTSEL1 0xE6051004 // R/W 32 General input/output switching register 1
#define GPIO_OUTDT1 0xE6051008 // R/W 32 General output register 1
#define GPIO_INDT1 0xE605100C // R 32 General input register 1
#define GPIO_INTDT1 0xE6051010 // R 32 Interrupt display register 1
#define GPIO_INTCLR1 0xE6051014 // R/W 32 Interrupt clear register 1
#define GPIO_INTMSK1 0xE6051018 // R/W 32 Interrupt mask register 1
#define GPIO_MSKCLR1 0xE605101C // R/W 32 Interrupt mask clear register 1
#define GPIO_POSNEG1 0xE6051020 // R/W 32 Positive/negative logic select register 1
#define GPIO_EDGLEVEL1 0xE6051024 // R/W 32 Edge/level select register 1
#define GPIO_FILONOFF1 0xE6051028 // R/W 32 Chattering prevention on/off register 1
#define GPIO_INTMSKS1 0xE6051038 // R/W 32 Interrupt sub mask register 1
#define GPIO_MSKCLRS1 0xE605103C // R/W 32 Interrupt sub mask clear register 1
#define GPIO_OUTDTSEL1 0xE6051040 // R/W 32 Output data select register 1
#define GPIO_OUTDTH1 0xE6051044 // R/W 32 Output data high register 1
#define GPIO_OUTDTL1 0xE6051048 // R/W 32 Output data low register 1
#define GPIO_BOTHEDGE1 0xE605104C // R/W 32 One edge/both edge select register 1
#define GPIO_IOINTSEL2 0xE6052000 // R/W 32 General IO/interrupt switching register 2
#define GPIO_INOUTSEL2 0xE6052004 // R/W 32 General input/output switching register 2
#define GPIO_OUTDT2 0xE6052008 // R/W 32 General output register 2
#define GPIO_INDT2 0xE605200C // R 32 General input register 2
#define GPIO_INTDT2 0xE6052010 // R 32 Interrupt display register 2
#define GPIO_INTCLR2 0xE6052014 // R/W 32 Interrupt clear register 2
#define GPIO_INTMSK2 0xE6052018 // R/W 32 Interrupt mask register 2
#define GPIO_MSKCLR2 0xE605201C // R/W 32 Interrupt mask clear register 2
#define GPIO_POSNEG2 0xE6052020 // R/W 32 Positive/negative logic select register 2
#define GPIO_EDGLEVEL2 0xE6052024 // R/W 32 Edge/level select register 2
#define GPIO_FILONOFF2 0xE6052028 // R/W 32 Chattering prevention on/off register 2
#define GPIO_INTMSKS2 0xE6052038 // R/W 32 Interrupt sub mask register 2
#define GPIO_MSKCLRS2 0xE605203C // R/W 32 Interrupt sub mask clear register 2
#define GPIO_OUTDTSEL2 0xE6052040 // R/W 32 Output data select register 2
#define GPIO_OUTDTH2 0xE6052044 // R/W 32 Output data high register 2
#define GPIO_OUTDTL2 0xE6052048 // R/W 32 Output data low register 2
#define GPIO_BOTHEDGE2 0xE605204C // R/W 32 One edge/both edge select register 2
#define GPIO_IOINTSEL3 0xE6053000 // R/W 32 General IO/interrupt switching register 3
#define GPIO_INOUTSEL3 0xE6053004 // R/W 32 General input/output switching register 3
#define GPIO_OUTDT3 0xE6053008 // R/W 32 General output register 3
#define GPIO_INDT3 0xE605300C // R 32 General input register 3
#define GPIO_INTDT3 0xE6053010 // R 32 Interrupt display register 3
#define GPIO_INTCLR3 0xE6053014 // R/W 32 Interrupt clear register 3
#define GPIO_INTMSK3 0xE6053018 // R/W 32 Interrupt mask register 3
#define GPIO_MSKCLR3 0xE605301C // R/W 32 Interrupt mask clear register 3
#define GPIO_POSNEG3 0xE6053020 // R/W 32 Positive/negative logic select register 3
#define GPIO_EDGLEVEL3 0xE6053024 // R/W 32 Edge/level select register 3
#define GPIO_FILONOFF3 0xE6053028 // R/W 32 Chattering prevention on/off register 3
#define GPIO_INTMSKS3 0xE6053038 // R/W 32 Interrupt sub mask register 3
#define GPIO_MSKCLRS3 0xE605303C // R/W 32 Interrupt sub mask clear register 3
#define GPIO_OUTDTSEL3 0xE6053040 // R/W 32 Output data select register 3
#define GPIO_OUTDTH3 0xE6053044 // R/W 32 Output data high register 3
#define GPIO_OUTDTL3 0xE6053048 // R/W 32 Output data low register 3
#define GPIO_BOTHEDGE3 0xE605304C // R/W 32 One edge/both edge select register 3
#define GPIO_IOINTSEL4 0xE6054000 // R/W 32 General IO/interrupt switching register 4
#define GPIO_INOUTSEL4 0xE6054004 // R/W 32 General input/output switching register 4
#define GPIO_OUTDT4 0xE6054008 // R/W 32 General output register 4
#define GPIO_INDT4 0xE605400C // R 32 General input register 4
#define GPIO_INTDT4 0xE6054010 // R 32 Interrupt display register 4
#define GPIO_INTCLR4 0xE6054014 // R/W 32 Interrupt clear register 4
#define GPIO_INTMSK4 0xE6054018 // R/W 32 Interrupt mask register 4
#define GPIO_MSKCLR4 0xE605401C // R/W 32 Interrupt mask clear register 4
#define GPIO_POSNEG4 0xE6054020 // R/W 32 Positive/negative logic select register 4
#define GPIO_EDGLEVEL4 0xE6054024 // R/W 32 Edge/level select register 4
#define GPIO_FILONOFF4 0xE6054028 // R/W 32 Chattering prevention on/off register 4
#define GPIO_INTMSKS4 0xE6054038 // R/W 32 Interrupt sub mask register 4
#define GPIO_MSKCLRS4 0xE605403C // R/W 32 Interrupt sub mask clear register 4
#define GPIO_OUTDTSEL4 0xE6054040 // R/W 32 Output data select register 4
#define GPIO_OUTDTH4 0xE6054044 // R/W 32 Output data high register 4
#define GPIO_OUTDTL4 0xE6054048 // R/W 32 Output data low register 4
#define GPIO_BOTHEDGE4 0xE605404C // R/W 32 One edge/both edge select register 4
#define GPIO_IOINTSEL5 0xE6055000 // R/W 32 General IO/interrupt switching register 5
#define GPIO_INOUTSEL5 0xE6055004 // R/W 32 General input/output switching register 5
#define GPIO_OUTDT5 0xE6055008 // R/W 32 General output register 5
#define GPIO_INDT5 0xE605500C // R 32 General input register 5
#define GPIO_INTDT5 0xE6055010 // R 32 Interrupt display register 5
#define GPIO_INTCLR5 0xE6055014 // R/W 32 Interrupt clear register 5
#define GPIO_INTMSK5 0xE6055018 // R/W 32 Interrupt mask register 5
#define GPIO_MSKCLR5 0xE605501C // R/W 32 Interrupt mask clear register 5
#define GPIO_POSNEG5 0xE6055020 // R/W 32 Positive/negative logic select register 5
#define GPIO_EDGLEVEL5 0xE6055024 // R/W 32 Edge/level select register 5
#define GPIO_FILONOFF5 0xE6055028 // R/W 32 Chattering prevention on/off register 5
#define GPIO_INTMSKS5 0xE6055038 // R/W 32 Interrupt sub mask register 5
#define GPIO_MSKCLRS5 0xE605503C // R/W 32 Interrupt sub mask clear register 5
#define GPIO_OUTDTSEL5 0xE6055040 // R/W 32 Output data select register 5
#define GPIO_OUTDTH5 0xE6055044 // R/W 32 Output data high register 5
#define GPIO_OUTDTL5 0xE6055048 // R/W 32 Output data low register 5
#define GPIO_BOTHEDGE5 0xE605504C // R/W 32 One edge/both edge select register 5
#define GPIO_IOINTSEL6 0xE6055400 // R/W 32 General IO/interrupt switching register 6
#define GPIO_INOUTSEL6 0xE6055404 // R/W 32 General input/output switching register 6
#define GPIO_OUTDT6 0xE6055408 // R/W 32 General output register 6
#define GPIO_INDT6 0xE605540C // R 32 General input register 6
#define GPIO_INTDT6 0xE6055410 // R 32 Interrupt display register 6
#define GPIO_INTCLR6 0xE6055414 // R/W 32 Interrupt clear register 6
#define GPIO_INTMSK6 0xE6055418 // R/W 32 Interrupt mask register 6
#define GPIO_MSKCLR6 0xE605541C // R/W 32 Interrupt mask clear register 6
#define GPIO_POSNEG6 0xE6055420 // R/W 32 Positive/negative logic select register 6
#define GPIO_EDGLEVEL6 0xE6055424 // R/W 32 Edge/level select register 6
#define GPIO_FILONOFF6 0xE6055428 // R/W 32 Chattering prevention on/off register 6
#define GPIO_INTMSKS6 0xE6055438 // R/W 32 Interrupt sub mask register 6
#define GPIO_MSKCLRS6 0xE605543C // R/W 32 Interrupt sub mask clear register 6
#define GPIO_OUTDTSEL6 0xE6055440 // R/W 32 Output data select register 6
#define GPIO_OUTDTH6 0xE6055444 // R/W 32 Output data high register 6
#define GPIO_OUTDTL6 0xE6055448 // R/W 32 Output data low register 6
#define GPIO_BOTHEDGE6 0xE605544C // R/W 32 One edge/both edge select register 6
#define GPIO_IOINTSEL7 0xE6055800 // R/W 32 General IO/interrupt switching register 7
#define GPIO_INOUTSEL7 0xE6055804 // R/W 32 General input/output switching register 7
#define GPIO_OUTDT7 0xE6055808 // R/W 32 General output register 7
#define GPIO_INDT7 0xE605580C // R 32 General input register 7
#define GPIO_INTDT7 0xE6055810 // R 32 Interrupt display register 7
#define GPIO_INTCLR7 0xE6055814 // R/W 32 Interrupt clear register 7
#define GPIO_INTMSK7 0xE6055818 // R/W 32 Interrupt mask register 7
#define GPIO_MSKCLR7 0xE605581C // R/W 32 Interrupt mask clear register 7
#define GPIO_POSNEG7 0xE6055820 // R/W 32 Positive/negative logic select register 7
#define GPIO_EDGLEVEL7 0xE6055824 // R/W 32 Edge/level select register 7
#define GPIO_FILONOFF7 0xE6055828 // R/W 32 Chattering prevention on/off register 7
#define GPIO_INTMSKS7 0xE6055838 // R/W 32 Interrupt sub mask register 7
#define GPIO_MSKCLRS7 0xE605583C // R/W 32 Interrupt sub mask clear register 7
#define GPIO_OUTDTSEL7 0xE6055840 // R/W 32 Output data select register 7
#define GPIO_OUTDTH7 0xE6055844 // R/W 32 Output data high register 7
#define GPIO_OUTDTL7 0xE6055848 // R/W 32 Output data low register 7
#define GPIO_BOTHEDGE7 0xE605584C // R/W 32 One edge/both edge select register 7
//LBSC.h
#define LBSC_CS0CTRL 0xEE220200 // R/W 32 Area 0 control register
#define LBSC_CS1CTRL 0xEE220204 // R/W 32 Area 1 control register
#define LBSC_CSWCR0 0xEE220230 // R/W 32 Area 0 RD/WE pulse control register
#define LBSC_CSWCR1 0xEE220234 // R/W 32 Area 1 RD/WE pulse control register
#define LBSC_CSPWCR0 0xEE220280 // R/W 32 Area 0 external wait control register
#define LBSC_CSPWCR1 0xEE220284 // R/W 32 Area 1 external wait control register
#define LBSC_EXWTSYNC 0xEE2202A0 // R/W 32 External wait input control register
#define LBSC_CS0BSTCTL 0xEE2202B0 // R/W 32 Area 0 burst control register
#define LBSC_CS0BTPH 0xEE2202B4 // R/W 32 Area 0 burst pitch set register
#define LBSC_CS1GDST 0xEE2202C0 // R/W 32 Area 1 guard setting register
#define LBSC_BCINTSR 0xEE220330 // R 32 BSC interrupt source status register
#define LBSC_BCINTCR 0xEE220334 // -/WC1 32 BSC interrupt source clear register
#define LBSC_BCINTMR 0xEE220338 // R/W 32 BSC interrupt enable register
#define LBSC_EXWTSTS 0xEE220344 // R 32 External wait status register
#define LBSC_EXBCT 0xEE2203C0 // R/W 32 EX-BUS wait timeout detection base counter register
#define LBSC_EXTCT 0xEE2203C4 // R/W 32 EX-BUS wait timeout detection counter register
#define LBSC_EXTSR 0xEE220010 // R/WC1 32 EX-BUS wait timeout detection access source indication register
#define LBSC_EXTADR 0xEE220014 // R/W 32 EX-BUS wait timeout detection address indication register
//MSTPRST
#define CPG_MSTPSR0 0xE6150030 // R 32 Module stop status register 0
#define CPG_MSTPSR1 0xE6150038 // R 32 Module stop status register 1
#define CPG_MSTPSR2 0xE6150040 // R 32 Module stop status register 2
#define CPG_MSTPSR3 0xE6150048 // R 32 Module stop status register 3
#define CPG_MSTPSR4 0xE615004C // R 32 Module stop status register 4
#define CPG_MSTPSR5 0xE615003C // R 32 Module stop status register 5
#define CPG_MSTPSR6 0xE61501C0 // R 32 Module stop status register 6
#define CPG_MSTPSR7 0xE61501C4 // R 32 Module stop status register 7
#define CPG_MSTPSR8 0xE61509A0 // R 32 Module stop status register 8
#define CPG_MSTPSR9 0xE61509A4 // R 32 Module stop status register 9
#define CPG_MSTPSR10 0xE61509A8 // R 32 Module stop status register 10
#define CPG_MSTPSR11 0xE61509AC // R 32 Module stop status register 11
#define CPG_RMSTPCR0 0xE6150110 // R/W 32 Realtime module stop control register 0
#define CPG_RMSTPCR1 0xE6150114 // R/W 32 Realtime module stop control register 1
#define CPG_RMSTPCR2 0xE6150118 // R/W 32 Realtime module stop control register 2
#define CPG_RMSTPCR3 0xE615011C // R/W 32 Realtime module stop control register 3
#define CPG_RMSTPCR4 0xE6150120 // R/W 32 Realtime module stop control register 4
#define CPG_RMSTPCR5 0xE6150124 // R/W 32 Realtime module stop control register 5
#define CPG_RMSTPCR6 0xE6150128 // R/W 32 Realtime module stop control register 6
#define CPG_RMSTPCR7 0xE615012C // R/W 32 Realtime module stop control register 7
#define CPG_RMSTPCR8 0xE6150980 // R/W 32 Realtime module stop control register 8
#define CPG_RMSTPCR9 0xE6150984 // R/W 32 Realtime module stop control register 9
#define CPG_RMSTPCR10 0xE6150988 // R/W 32 Realtime module stop control register 10
#define CPG_RMSTPCR11 0xE615098C // R/W 32 Realtime module stop control register 11
#define CPG_SMSTPCR0 0xE6150130 // R/W 32 System module stop control register 0
#define CPG_SMSTPCR1 0xE6150134 // R/W 32 System module stop control register 1
#define CPG_SMSTPCR2 0xE6150138 // R/W 32 System module stop control register 2
#define CPG_SMSTPCR3 0xE615013C // R/W 32 System module stop control register 3
#define CPG_SMSTPCR4 0xE6150140 // R/W 32 System module stop control register 4
#define CPG_SMSTPCR5 0xE6150144 // R/W 32 System module stop control register 5
#define CPG_SMSTPCR6 0xE6150148 // R/W 32 System module stop control register 6
#define CPG_SMSTPCR7 0xE615014C // R/W 32 System module stop control register 7
#define CPG_SMSTPCR8 0xE6150990 // R/W 32 System module stop control register 8
#define CPG_SMSTPCR9 0xE6150994 // R/W 32 System module stop control register 9
#define CPG_SMSTPCR10 0xE6150998 // R/W 32 System module stop control register 10
#define CPG_SMSTPCR11 0xE615099C // R/W 32 System module stop control register 11
#define CPG_SRCR0 0xE61500A0 // R/W 32 Software reset register 0
#define CPG_SRCR1 0xE61500A8 // R/W 32 Software reset register 1
#define CPG_SRCR2 0xE61500B0 // R/W 32 Software reset register 2
#define CPG_SRCR3 0xE61500B8 // R/W 32 Software reset register 3
#define CPG_SRCR4 0xE61500BC // R/W 32 Software reset register 4
#define CPG_SRCR5 0xE61500C4 // R/W 32 Software reset register 5
#define CPG_SRCR6 0xE61501C8 // R/W 32 Software reset register 6
#define CPG_SRCR7 0xE61501CC // R/W 32 Software reset register 7
#define CPG_SRCR8 0xE6150920 // R/W 32 Software reset register 8
#define CPG_SRCR9 0xE6150924 // R/W 32 Software reset register 9
#define CPG_SRCR10 0xE6150928 // R/W 32 Software reset register 10
#define CPG_SRCR11 0xE615092C // R/W 32 Software reset register 11
#define CPG_SRSTCLR0 0xE6150940 // W 32 Software reset clearing register 0
#define CPG_SRSTCLR1 0xE6150944 // W 32 Software reset clearing register 1
#define CPG_SRSTCLR2 0xE6150948 // W 32 Software reset clearing register 2
#define CPG_SRSTCLR3 0xE615094C // W 32 Software reset clearing register 3
#define CPG_SRSTCLR4 0xE6150950 // W 32 Software reset clearing register 4
#define CPG_SRSTCLR5 0xE6150954 // W 32 Software reset clearing register 5
#define CPG_SRSTCLR6 0xE6150958 // W 32 Software reset clearing register 6
#define CPG_SRSTCLR7 0xE615095C // W 32 Software reset clearing register 7
#define CPG_SRSTCLR8 0xE6150960 // W 32 Software reset clearing register 8
#define CPG_SRSTCLR9 0xE6150964 // W 32 Software reset clearing register 9
#define CPG_SRSTCLR10 0xE6150968 // W 32 Software reset clearing register 10
#define CPG_SRSTCLR11 0xE615096C // W 32 Software reset clearing register 11
#define CPG_SAMSTPCR0 0xE6150C20 // R/W 32 Safety Module Stop Control Register 0
#define CPG_SAMSTPCR1 0xE6150C24 // R/W 32 Safety Module Stop Control Register 1
#define CPG_SAMSTPCR2 0xE6150C28 // R/W 32 Safety Module Stop Control Register 2
#define CPG_SAMSTPCR3 0xE6150C2C // R/W 32 Safety Module Stop Control Register 3
#define CPG_SAMSTPCR4 0xE6150C30 // R/W 32 Safety Module Stop Control Register 4
#define CPG_SAMSTPCR5 0xE6150C34 // R/W 32 Safety Module Stop Control Register 5
#define CPG_SAMSTPCR6 0xE6150C38 // R/W 32 Safety Module Stop Control Register 6
#define CPG_SAMSTPCR7 0xE6150C3C // R/W 32 Safety Module Stop Control Register 7
#define CPG_SAMSTPCR8 0xE6150C40 // R/W 32 Safety Module Stop Control Register 8
#define CPG_SAMSTPCR9 0xE6150C44 // R/W 32 Safety Module Stop Control Register 9
#define CPG_SAMSTPCR10 0xE6150C48 // R/W 32 Safety Module Stop Control Register 10
#define CPG_SAMSTPCR11 0xE6150C4C // R/W 32 Safety Module Stop Control Register 11
#define CPG_SASRSTECR0 0xE6150C80 // R/W 32 Safety Software Reset Access Enable Control Register 0
#define CPG_SASRSTECR1 0xE6150C84 // R/W 32 Safety Software Reset Access Enable Control Register 1
#define CPG_SASRSTECR2 0xE6150C88 // R/W 32 Safety Software Reset Access Enable Control Register 2
#define CPG_SASRSTECR3 0xE6150C8C // R/W 32 Safety Software Reset Access Enable Control Register 3
#define CPG_SASRSTECR4 0xE6150C90 // R/W 32 Safety Software Reset Access Enable Control Register 4
#define CPG_SASRSTECR5 0xE6150C94 // R/W 32 Safety Software Reset Access Enable Control Register 5
#define CPG_SASRSTECR6 0xE6150C98 // R/W 32 Safety Software Reset Access Enable Control Register 6
#define CPG_SASRSTECR7 0xE6150C9C // R/W 32 Safety Software Reset Access Enable Control Register 7
#define CPG_SASRSTECR8 0xE6150CA0 // R/W 32 Safety Software Reset Access Enable Control Register 8
#define CPG_SASRSTECR9 0xE6150CA4 // R/W 32 Safety Software Reset Access Enable Control Register 9
#define CPG_SASRSTECR10 0xE6150CA8 // R/W 32 Safety Software Reset Access Enable Control Register 10
#define CPG_SASRSTECR11 0xE6150CAC // R/W 32 Safety Software Reset Access Enable Control Register 11
#define CPG_SAPTCSR 0xE6150C00 // R/W 32 Safety Protect Control/Status Register
#define CPG_SAERMIDR 0xE6150C04 // R 32 Safety Error Master ID Register
#define CPG_SAERADR 0xE6150C08 // R 32 Safety Error Address Regsiter
//PFC
#define PFC_PMMR 0xE6060000 // R/W 32 LSI Multiplexed Pin Setting Mask Register
#define PFC_GPSR0 0xE6060100 // R/W 32 GPIO/Peripheral Function Select register 0
#define PFC_GPSR1 0xE6060104 // R/W 32 GPIO/Peripheral Function Select register 1
#define PFC_GPSR2 0xE6060108 // R/W 32 GPIO/Peripheral_Function Select register 2
#define PFC_GPSR3 0xE606010C // R/W 32 GPIO/Peripheral Function Select register 3
#define PFC_GPSR4 0xE6060110 // R/W 32 GPIO/Peripheral Function Select register 4
#define PFC_GPSR5 0xE6060114 // R/W 32 GPIO/Peripheral Function Select register 5
#define PFC_GPSR6 0xE6060118 // R/W 32 GPIO/Peripheral Function Select register 6
#define PFC_GPSR7 0xE606011C // R/W 32 GPIO/Peripheral Function Select register 7
#define PFC_IPSR0 0xE6060200 // R/W 32 Peripheral Function Select register 0
#define PFC_IPSR1 0xE6060204 // R/W 32 Peripheral Function Select register 1
#define PFC_IPSR2 0xE6060208 // R/W 32 Peripheral Function Select register 2
#define PFC_IPSR3 0xE606020C // R/W 32 Peripheral Function Select register 3
#define PFC_IPSR4 0xE6060210 // R/W 32 Peripheral Function Select register 4
#define PFC_IPSR5 0xE6060214 // R/W 32 Peripheral Function Select register 5
#define PFC_IPSR6 0xE6060218 // R/W 32 Peripheral Function Select register 6
#define PFC_IPSR7 0xE606021C // R/W 32 Peripheral Function Select register 7
#define PFC_IPSR8 0xE6060220 // R/W 32 Peripheral Function Select register 8
#define PFC_IPSR9 0xE6060224 // R/W 32 Peripheral Function Select register 9
#define PFC_IPSR10 0xE6060228 // R/W 32 Peripheral Function Select register 10
#define PFC_IPSR11 0xE606022C // R/W 32 Peripheral Function Select register 11
#define PFC_IPSR12 0xE6060230 // R/W 32 Peripheral Function Select register 12
#define PFC_IPSR13 0xE6060234 // R/W 32 Peripheral Function Select register 13
#define PFC_IPSR14 0xE6060238 // R/W 32 Peripheral Function Select register 14
#define PFC_IPSR15 0xE606023C // R/W 32 Peripheral Function Select register 15
#define PFC_IPSR16 0xE6060240 // R/W 32 Peripheral Function Select register 16
#define PFC_IPSR17 0xE6060244 // R/W 32 Peripheral Function Select register 17
#define PFC_IPSR18 0xE6060248 // R/W 32 Peripheral Function Select register 18
#define PFC_DRVCTRL0 0xE6060300 // R/W 32 DRV control register0
#define PFC_DRVCTRL1 0xE6060304 // R/W 32 DRV control register1
#define PFC_DRVCTRL2 0xE6060308 // R/W 32 DRV control register2
#define PFC_DRVCTRL3 0xE606030C // R/W 32 DRV control register3
#define PFC_DRVCTRL4 0xE6060310 // R/W 32 DRV control register4
#define PFC_DRVCTRL5 0xE6060314 // R/W 32 DRV control register5
#define PFC_DRVCTRL6 0xE6060318 // R/W 32 DRV control register6
#define PFC_DRVCTRL7 0xE606031C // R/W 32 DRV control register7
#define PFC_DRVCTRL8 0xE6060320 // R/W 32 DRV control register8
#define PFC_DRVCTRL9 0xE6060324 // R/W 32 DRV control register9
#define PFC_DRVCTRL10 0xE6060328 // R/W 32 DRV control register10
#define PFC_DRVCTRL11 0xE606032C // R/W 32 DRV control register11
#define PFC_DRVCTRL12 0xE6060330 // R/W 32 DRV control register12
#define PFC_DRVCTRL13 0xE6060334 // R/W 32 DRV control register13
#define PFC_DRVCTRL14 0xE6060338 // R/W 32 DRV control register14
#define PFC_DRVCTRL15 0xE606033C // R/W 32 DRV control register15
#define PFC_DRVCTRL16 0xE6060340 // R/W 32 DRV control register16
#define PFC_DRVCTRL17 0xE6060344 // R/W 32 DRV control register17
#define PFC_DRVCTRL18 0xE6060348 // R/W 32 DRV control register18
#define PFC_DRVCTRL19 0xE606034C // R/W 32 DRV control register19
#define PFC_DRVCTRL20 0xE6060350 // R/W 32 DRV control register20
#define PFC_DRVCTRL21 0xE6060354 // R/W 32 DRV control register21
#define PFC_DRVCTRL22 0xE6060358 // R/W 32 DRV control register22
#define PFC_DRVCTRL23 0xE606035C // R/W 32 DRV control register23
#define PFC_DRVCTRL24 0xE6060360 // R/W 32 DRV control register24
#define PFC_POCCTRL0 0xE6060380 // R/W 32 POC control register0
#define PFC_TDSELCTRL0 0xE60603C0 // R/W 32 TDSEL control register0
#define PFC_IOCTRL 0xE60603E0 // R/W 32 IO cell control for IICDVFS
#define PFC_FUSEMON 0xE60603E4 // R 32 Fuse Monitor register0
#define PFC_PUEN0 0xE6060400 // R/W 32 LSI pin pull-enable register 0
#define PFC_PUEN1 0xE6060404 // R/W 32 LSI pin pull-enable register 1
#define PFC_PUEN2 0xE6060408 // R/W 32 LSI pin pull-enable register 2
#define PFC_PUEN3 0xE606040C // R/W 32 LSI pin pull-enable register 3
#define PFC_PUEN4 0xE6060410 // R/W 32 LSI pin pull-enable register 4
#define PFC_PUEN5 0xE6060414 // R/W 32 LSI pin pull-enable register 5
#define PFC_PUEN6 0xE6060418 // R/W 32 LSI pin pull-enable register 6
#define PFC_PUD0 0xE6060440 // R/W 32 LSI pin pull-up/down control register 0
#define PFC_PUD1 0xE6060444 // R/W 32 LSI pin pull-up/down control register 1
#define PFC_PUD2 0xE6060448 // R/W 32 LSI pin pull-up/down control register 2
#define PFC_PUD3 0xE606044C // R/W 32 LSI pin pull-up/down control register 3
#define PFC_PUD4 0xE6060450 // R/W 32 LSI pin pull-up/down control register 4
#define PFC_PUD5 0xE6060454 // R/W 32 LSI pin pull-up/down control register 5
#define PFC_PUD6 0xE6060458 // R/W 32 LSI pin pull-up/down control register 6
#define PFC_MOD_SEL0 0xE6060500 // R/W 32 Module select register 0
#define PFC_MOD_SEL1 0xE6060504 // R/W 32 Module select register 1
#define PFC_MOD_SEL2 0xE6060508 // R/W 32 Module select register 2
//V3M
#define PFC_IOCTRL30 0xE6060380 // R/W 32 MPOC control register 0
#define PFC_IOCTRL31 0xE6060384 // R/W 32 MPOC control register 0
#define PFC_IOCTRL32 0xE6060388 // R/W 32 MPOC control register 0
#define PFC_IOCTRL40 0xE60603C0 // R/W 32 MPOC control register 0
//RST
#define RST_MODEMR 0xE6160060 // R 32 Mode Monitor Register
#define RST_CA57RESCNT 0xE6160040 // R/W 32 CA57 Reset Control Register
#define RST_CA53RESCNT 0xE6160044 // R/W 32 CA53 Reset Control Register
#define RST_WDTRSTCR 0xE6160054 // R/W 32 Watchdog Timer Reset Control Register
#define RST_RSTOUTCR 0xE6160058 // R/W 32 PRESETOUT# Control Register
#define RST_SBAR 0xE6160010 // R/W 32 SYS Boot Address Register
#define RST_SBAR2 0xE6160014 // R/W 32 SYS Boot Address Register2
#define RST_CA53BAR 0xE6160030 // R/W 32 CA53 Boot Address Register
#define RST_CA53BAR2 0xE6160034 // R/W 32 CA53 Boot Address Register2
#define RST_CA57BAR 0xE6160020 // R/W 32 CA57 Boot Address Register
#define RST_CA57BAR2 0xE6160024 // R/W 32 CA57 Boot Address Register2
#define RST_CR7BAR 0xE6160070 // R/W 32 CR7 Boot Address Register
#define RST_CR7BAR2 0xE6160074 // R/W 32 CR7 Boot Address Register2
#define RST_CA57CPU0BARH 0xE61600C0 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode H
#define RST_CA57CPU0BARL 0xE61600C4 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode L
#define RST_CA57CPU1BARH 0xE61600D0 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode H
#define RST_CA57CPU1BARL 0xE61600D4 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode L
#define RST_CA57CPU2BARH 0xE61600E0 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode H
#define RST_CA57CPU2BARL 0xE61600E4 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode L
#define RST_CA57CPU3BARH 0xE61600F0 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode H
#define RST_CA57CPU3BARL 0xE61600F4 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode L
#define RST_CA53CPU0BARH 0xE6160080 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode H
#define RST_CA53CPU0BARL 0xE6160084 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode L
#define RST_CA53CPU1BARH 0xE6160090 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode H
#define RST_CA53CPU1BARL 0xE6160094 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode L
#define RST_CA53CPU2BARH 0xE61600A0 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode H
#define RST_CA53CPU2BARL 0xE61600A4 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode L
#define RST_CA53CPU3BARH 0xE61600B0 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode H
#define RST_CA53CPU3BARL 0xE61600B4 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode L
#define RST_APBSFTYCHKR 0xE616005C // R/W 32 APB bus Safety Check Register
#define RST_STBCHR0 0xE6160100 // R/W 32 Standby Flag Register 0
#define RST_STBCHR1 0xE6160104 // R/W 32 Standby Flag Register 1
#define RST_STBCHR2 0xE6160108 // R/W 32 Standby Flag Register 2
#define RST_STBCHR3 0xE616010C // R/W 32 Standby Flag Register 3
#define RST_STBCHR4 0xE6160120 // R/W 32 Standby Flag Register 4
#define RST_STBCHR5 0xE6160124 // R/W 32 Standby Flag Register 5
#define RST_STBCHR6 0xE6160128 // R/W 32 Standby Flag Register 6
#define RST_STBCHR7 0xE616012C // R/W 32 Standby Flag Register 7
#define RST_SRESCR 0xE6160110 // R/W 32 Soft Power On Reset Control Register
#define RST_RRSTFR 0xE6160114 // R/W 32 RT Reset Flag Register
#define RST_SRSTFR 0xE6160118 // R/W 32 SYS Reset Flag Register
#define RST_SCPTCSR 0xE6160180 // R/W 32 Secure Protect Control/Status Register
#define RST_SCERMIDR 0xE6160184 // R 32 Secure Error Master ID Register
#define RST_SCERADR 0xE6160188 // R 32 Secure Error Address Register
#define RST_SAPTCSR 0xE6160190 // R/W 32 Safety Protect Control/Status Register
#define RST_SAERMIDR 0xE6160194 // R 32 Safety Error Master ID Register
#define RST_SAERADR 0xE6160198 // R 32 Safety Error Address Register
#define MODEMR_BOOT_CPU_MASK (0x000000C0U)
#define MODEMR_BOOT_CPU_CR7 (0x000000C0U)
#define MODEMR_BOOT_CPU_CA57 (0x00000000U)
#define MODEMR_BOOT_CPU_CA53 (0x00000040U)
#define MODEMR_BOOT_DEV_MASK (0x0000001EU)
#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU)
#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU)
#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU)
#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU)
#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU)
#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU)
#define MODEMR_BOOT_PLL_MASK (0x00006000U)
#define MODEMR_BOOT_PLL_SHIFT (13U)
//
#define MFIS_SOFTMDR (0xE6260600U)
//SCIF0
#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register
#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register
#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register
#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register
#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register
#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register
#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register
#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register
#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register
#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register
#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register
#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register
//SCIF2
#define SCIF2_SCSMR 0xE6E88000 // R/W 16 Serial mode register
#define SCIF2_SCBRR 0xE6E88004 // R/W 8 Bit rate register
#define SCIF2_SCSCR 0xE6E88008 // R/W 16 Serial control register
#define SCIF2_SCFTDR 0xE6E8800C // W 8 Transmit FIFO data register
#define SCIF2_SCFSR 0xE6E88010 // R/W 16 Serial status register
#define SCIF2_SCFRDR 0xE6E88014 // R 8 Receive FIFO data register
#define SCIF2_SCFCR 0xE6E88018 // R/W 16 FIFO control register
#define SCIF2_SCFDR 0xE6E8801C // R 16 FIFO data count register
#define SCIF2_SCSPTR 0xE6E88020 // R/W 16 Serial port register
#define SCIF2_SCLSR 0xE6E88024 // R/W 16 Line status register
#define SCIF2_DL 0xE6E88030 // R/W 16 Frequency division register
#define SCIF2_CKS 0xE6E88034 // R/W 16 Clock Select register
/* Appendix A. */
#define PRR (0xFFF00044) /* Product Register */
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
#define PRR_PRODUCT_V3H (0x00005600U)
#define PRR_CUT_10 (0x00U)
#define PRR_CUT_11 (0x01U)
#define PRR_CUT_20 (0x10U)
#define PRR_CUT_30 (0x20U)
#define PRR_CUT_MAJOR_MASK (0x000000F0U)
#define PRR_CUT_MINOR_MASK (0x0000000FU)
#define PRR_PRODUCT_SHIFT (8U)
#define PRR_MAJOR_SHIFT (4U)
#define PRR_MINOR_SHIFT (0U)
#define PRR_MAJOR_OFFSET (1U)
#endif /* REG_RCARGEN3_H */

13
IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV0_H
#define SCIFDRV0_H
int32_t PutCharSCIF0(char outChar);
void PowerOnScif0(void);
void WaitPutScif0SendEnd(void);
void InitScif0_SCIFCLK(void);
#endif /* SCIFDRV0_H */

13
IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0_v3h.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV0_V3H_H
#define SCIFDRV0_V3H_H
int32_t PutCharSCIF0_v3h(char outChar);
void PowerOnScif0_v3h(void);
void WaitPutScif0_v3h_SendEnd(void);
void InitScif0_v3h_SCIFCLK(void);
#endif /* SCIFDRV0_V3H_H */

14
IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv2.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef SCIFDRV2_H
#define SCIFDRV2_H
int32_t PutCharSCIF2(char outChar);
void PowerOnScif2(void);
void WaitPutScif2SendEnd(void);
void InitScif2_SCIFCLK(void);
void InitScif2_SCIFCLK_D3(void);
#endif /* SCIFDRV2_H */

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IPL/SDK/v3h/src/Dummy_CA53_Program/include/types.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef TYPES_H
#define TYPES_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
/****************************************************************************
* File Name: types.h
* Contents : Types Define
****************************************************************************/
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef SUCCESS
#define SUCCESS 0UL
#endif
#ifndef YES
#define YES 1
#endif
#ifndef NO
#define NO 0
#endif
#ifndef NULL
#define NULL (void *)0UL
#endif
#define PFAR /**/
#define FFAR /**/
typedef signed char BYTE;
typedef signed short WORD;
typedef signed long DWORD;
#if 0
typedef unsigned long uint32;
typedef long int32;
typedef unsigned short uint16;
typedef short int16;
typedef unsigned char uint8;
typedef char int8;
typedef unsigned int uint;
typedef unsigned char bool8;
typedef unsigned long long uint64;
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef signed short int16_t;
typedef unsigned short uint16_t;
typedef signed long int32_t;
typedef unsigned long uint32_t;
typedef unsigned long long int uint64_t;
#endif
typedef signed char B; /* signed 8-bit integer */
typedef long W; /* signed 32-bit integer */
typedef unsigned char UB; /* unsigned 8-bit integer */
typedef unsigned long UW; /* unsigned 32-bit integer */
typedef short H; /* signed 16-bit integer */
typedef unsigned short UH; /* unsigned 16-bit integer */
typedef int INT;
typedef unsigned int UINT;
typedef INT BOOL;
typedef void (FFAR *FP)();
typedef INT FN;
typedef INT ID;
typedef INT BOOL_ID;
typedef INT HNO;
typedef INT RNO;
typedef INT RDVNO;
typedef UINT RDVPTN;
typedef UINT ATR;
typedef UINT MODE;
typedef INT ER;
typedef INT PRI;
typedef ER ER_ID;
typedef UINT STAT;
typedef INT ER_UINT;
typedef UINT TEXPTN;
typedef UINT FLGPTN;
typedef UINT INHNO;
typedef UINT INTNO;
typedef unsigned long SIZE;
typedef W TMO;
typedef W DLYTIME;
typedef DLYTIME RELTIM;
typedef void PFAR *VP;
typedef VP VP_INT;
#ifdef __cplusplus
}
#endif
#endif

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IPL/SDK/v3h/src/Dummy_CA53_Program/init_scif.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "reg_rcargen3.h"
#include "common.h"
#include "scifdrv0.h"
#include "scifdrv0_v3h.h"
#include "scifdrv2.h"
#include "init_scif.h"
void InitScif(void)
{
uint32_t product;
product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK;
switch (product) {
case PRR_PRODUCT_H3: /* H3, M3 and M3N setting values are same */
case PRR_PRODUCT_M3:
case PRR_PRODUCT_M3N:
InitScif2_SCIFCLK();
break;
case PRR_PRODUCT_D3:
InitScif2_SCIFCLK_D3();
break;
case PRR_PRODUCT_V3M:
InitScif0_SCIFCLK();
break;
case PRR_PRODUCT_V3H:
// InitScif0_v3h_SCIFCLK();
break;
default:
break;
}
}

37
IPL/SDK/v3h/src/Dummy_CA53_Program/main.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include <stdio.h>
#include "common.h"
#include "main.h"
#include "devdrv.h"
static void StartMess(void);
void Main(void)
{
volatile uint32_t i;
for (i = 0; i < 0x00600000U; i++) {
;
}
StartMess();
while(1) {
__asm__ volatile ("wfi");
}
}
static void StartMess(void)
{
PutStr(" ",1);
PutStr("Dummy CA53 Program",1);
PutStr("Dummy CA53 Program boot end",1);
}

169
IPL/SDK/v3h/src/Dummy_CA53_Program/makefile Normal file
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#
# Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
#
#/* Select BOOT("CR7"or"ICUMXA")*************************
ifeq ("$(BOOT)", "")
BOOT = ICUMXA
endif
#/* Select AArch("64"or"32" )***************************************************
ifeq ("$(AArch)", "")
AArch = 64
endif
#CPU
ifeq ("$(AArch)", "64")
CPU = -march=armv8-a
endif
ifeq ("$(AArch)", "32")
CPU = -mcpu=cortex-r7
endif
ifeq ("$(AArch)", "32")
THUMB = -marm
AS_NEON =
CC_NEON =
ALIGN = -mno-unaligned-access
endif
ifeq ("$(AArch)", "64")
THUMB =
AS_NEON =
CC_NEON = -mgeneral-regs-only
ALIGN = -mstrict-align
endif
ifeq ("$(AArch)", "32")
AArch32_64 = AArch32
BOOTDIR = AArch32_boot
OUTPUT_DIR = AArch32_output
OBJECT_DIR = AArch32_obj
CROSS_COMPILE ?= arm-eabi-
endif
ifeq ("$(AArch)", "64")
AArch32_64 = AArch64
BOOTDIR = AArch64_boot
OUTPUT_DIR = AArch64_output
OBJECT_DIR = AArch64_obj
CROSS_COMPILE ?= aarch64-elf-
endif
ifeq ("$(BOOT)", "CR7")
# BOOT_DEF = Writer
MEMORY_DEF = memory_cr7.def
FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA53_Program$(FILENAME_ADD)
endif
ifeq ("$(BOOT)", "ICUMXA")
# BOOT_DEF = Writer
MEMORY_DEF = memory_icumxa.def
FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA53_Program$(FILENAME_ADD)
endif
LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc
LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc
INCLUDE_DIR = include
OUTPUT_FILE = $(FILE_NAME).axf
#Object file
OBJ_FILE_BOOT = \
$(OBJECT_DIR)/boot_mon.o \
$(OBJECT_DIR)/stack.o
SRC_FILE := \
main.c \
init_scif.c \
scifdrv0.c \
scifdrv0_v3h.c \
scifdrv2.c \
devdrv.c \
common.c
ifeq ("$(BOOT)", "WRITER_WITH_CERT")
SRC_FILE += cert_param.c
endif
OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE)))
#Dependency File
DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d))
###################################################
#C compiler
CC = $(CROSS_COMPILE)gcc
#Assembler
AS = $(CROSS_COMPILE)as
#Linker
LD = $(CROSS_COMPILE)ld
#Liblary
AR = $(CROSS_COMPILE)ar
#Object dump
OBJDMP = $(CROSS_COMPILE)objdump
#Object copy
OBJCOPY = $(CROSS_COMPILE)objcopy
#clean
CL = rm -rf
###################################################
# Suffixes
.SUFFIXES : .s .c .o
###################################################
# Command
.PHONY: all
all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE)
#------------------------------------------
# Make Directory
#------------------------------------------
$(OBJECT_DIR):
-mkdir "$(OBJECT_DIR)"
$(OUTPUT_DIR):
-mkdir "$(OUTPUT_DIR)"
#------------------------------------------
# Compile
#------------------------------------------
$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s
$(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0
$(OBJECT_DIR)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
$(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 $(CFLAGS)
#------------------------------------------
# Linker
#------------------------------------------
$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF)
$(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) \
-T '$(MEMORY_DEF)' \
-o '$(OUTPUT_FILE)' \
-Map '$(FILE_NAME).map' \
-static \
$(LIBS)
# Make SREC file
$(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).srec"
# Make Binary file
$(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin"
# Dis assemble
$(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt"
# Time Stamp
@echo ========== %date% %time% ==========
@echo ========== !!! Compile Complete !!! ==========
.PHONY: clean
clean:
$(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/*
-include $(DEPEND_FILE)

38
IPL/SDK/v3h/src/Dummy_CA53_Program/memory_cr7.def Normal file
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MEMORY {
RAM (rwxa): ORIGIN = 0x44000000, LENGTH = 0x00014000
}
SECTIONS
{
.text : {
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}

38
IPL/SDK/v3h/src/Dummy_CA53_Program/memory_icumxa.def Normal file
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MEMORY {
RAM (rwxa): ORIGIN = 0x46400000, LENGTH = 0x00014000
}
SECTIONS
{
.text : {
*(.text*)
*(.rodata*)
. = NEXT(64);
__RO_END__ = .;
} > RAM
.data : {
__DATA_START__ = .;
*(.data)
. = NEXT(64);
__DATA_END__ = .;
} > RAM
__DATA_SIZE__ = SIZEOF(.data);
.bss : {
__BSS_START__ = .;
*(.bss)
*(COMMON)
. = NEXT(64);
__BSS_END__ = .;
} > RAM
stacks (NOLOAD) : ALIGN(64) {
__STACKS_START__ = .;
KEEP(*(writer_stack))
__STACKS_END__ = .;
} > RAM
__BSS_SIZE__ = SIZEOF(.bss);
}

91
IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv0.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF0) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF0(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) ));
*((volatile uint8_t*)SCIF0_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif0(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR2);
if(dataL & BIT7){ // case SCIF0
dataL &= ~BIT7;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR2) = dataL;
while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0
}
}
void WaitPutScif0SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF0_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif0PinFunction(void)
{
uint32_t dataL;
/* SCIF0 */
dataL = *((volatile uint32_t*)PFC_IPSR7);
dataL &= ~(0x0FF00000);
dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR7) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif0_SCIFCLK(void)
{
uint16_t dataW;
PowerOnScif0();
InitScif0PinFunction();
dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
*((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */
SoftDelay(100);
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}

91
IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0_v3h.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv0.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF0) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF0_v3h(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) ));
*((volatile uint8_t*)SCIF0_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif0_v3h(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR2);
if(dataL & BIT7){ // case SCIF0
dataL &= ~BIT7;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR2) = dataL;
while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0
}
}
void WaitPutScif0_v3h_SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF0_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif0_v3h_PinFunction(void)
{
uint32_t dataL;
/* SCIF0 */
dataL = *((volatile uint32_t*)PFC_IPSR7);
dataL &= ~(0x0FF00000);
dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR7) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif0_v3h_SCIFCLK(void)
{
uint16_t dataW;
PowerOnScif0_v3h();
InitScif0_v3h_PinFunction();
dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
*((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */
SoftDelay(100);
*((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}

158
IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv2.c Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include "common.h"
#include "scifdrv2.h"
#include "bit.h"
#include "reg_rcargen3.h"
//////////////////////////////////////////////////////////////////////////////////
// //
// Debug Seirial(SCIF2) //
// //
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF2(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR) ));
*((volatile unsigned char*)SCIF2_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60; /* TEND,TDFE clear */
return(0);
}
void PowerOnScif2(void)
{
uint32_t dataL;
dataL = *((volatile uint32_t*)CPG_MSTPSR3);
if(dataL & BIT10){ // case SCIF2(IrDA) Standby
dataL &= ~BIT10;
*((volatile uint32_t*)CPG_CPGWPR) = ~dataL;
*((volatile uint32_t*)CPG_SMSTPCR3) = dataL;
while( BIT10 & *((volatile uint32_t*)CPG_MSTPSR3) ); // wait bit=0
}
}
void WaitPutScif2SendEnd(void)
{
uint16_t dataW;
uint32_t loop;
loop=1;
while(loop){
dataW = *((volatile uint16_t*)SCIF2_SCFSR);
if(dataW & BIT6) loop = 0;
}
}
void InitScif2PinFunction(void)
{
uint32_t dataL;
/* SCIF2 */
dataL = *((volatile uint32_t*)PFC_IPSR13);
dataL &= ~0x000000FF; /* IP13[7:4]=4'b0000, IP13[3:0]=4'b0000 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR13) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR5);
dataL |= 0x00000C00; /* GP5[11],GP5[10] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR5) = dataL;
}
void InitScif2_SCIFCLK(void)
{
uint16_t dataW;
uint32_t prr;
PowerOnScif2();
InitScif2PinFunction();
dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */
SoftDelay(100);
#ifdef Writer
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */
#else /* Writer */
prr = *((volatile uint32_t*)PRR);
prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if (prr == PRR_PRODUCT_H3 | PRR_CUT_10) {
*((volatile uint8_t*)SCIF2_SCBRR) = 0x08; /* 115200bps@33MHz */
} else {
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */
}
#endif /* Writer */
SoftDelay(100);
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */
SoftDelay(100);
}
void InitScif2PinFunction_D3(void)
{
uint32_t dataL;
/* SCIF2 */
dataL = *((volatile uint32_t*)PFC_IPSR12);
dataL &= ~0x00000F00U; /* IP12[11:8]=4'b0000 */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_IPSR12) = dataL;
dataL = *((volatile uint32_t*)PFC_GPSR4);
dataL |= 0x0C000000U; /* GP4[27],GP4[26] */
*((volatile uint32_t*)PFC_PMMR) = ~dataL;
*((volatile uint32_t*)PFC_GPSR4) = dataL;
}
void InitScif2_SCIFCLK_D3(void)
{
uint16_t dataW;
uint32_t md;
uint32_t sscg;
PowerOnScif2();
InitScif2PinFunction_D3();
md = *((volatile uint32_t*)RST_MODEMR);
sscg = (md & 0x00001000) >> 12;
dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */
*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */
*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */
*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, S3D4/1 */
SoftDelay(100);
if(sscg == 0x0){ //MD12=0 (SSCG off) : S3D4C=66.6MHz
*((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200 bit-rate */
}
else if(sscg == 0x1){ //MD12=1 (SSCG on) : S3D4C=62.5MHz
*((volatile uint8_t*)SCIF2_SCBRR) = 0x10; /* 115200 bit-rate */
}
SoftDelay(100);
*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */
*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SCK pin is not used */
SoftDelay(100);
}

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IPL/SDK/v3h/src/Dummy_FW/Makefile Normal file
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# ******************************************************************************
# * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
# *
# * DESCRIPTION : makefile for Dummy FW
# ******************************************************************************
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude
OUTDIR := build
#output file name
FILE_NAME = dummy_fw
OUTPUT_FILE = $(FILE_NAME).elf
#object file name
OBJ_FILE = common/mem_io.o \
common/scif.o \
common/log.o \
common/micro_wait.o \
common/remap.o \
fw/dummy_fw_main.o \
fw/dummy_fw.o \
fw/vecttbl.o
#linker script name
MEMORY_DEF = fw/dummy_fw.ld
###################################################
# Debug build
DEBUG:=0
# Process DEBUG flag
$(eval $(call assert_boolean,DEBUG))
$(eval $(call add_define,DEBUG))
ifeq (${DEBUG},0)
$(eval $(call add_define,NDEBUG))
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Ogeneral
else
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Odebug
endif
###################################################
OUTDIR_REL := $(OUTDIR)/release
OUTDIR_OBJ := $(OUTDIR)/obj
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
CC = cxrh850
AS = cxrh850
LD = cxrh850
OC = gsrec
OD = gdump
ASFLAGS += -asm="-preprocess_assembly_files" \
-asm="-nostartfiles" \
-D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -nostartfiles \
-c99 \
$(INCLUDE_DIR) $(DEFINES)
LDFLAGS = -nostartfiles
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c
@$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
@$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
-T $(MEMORY_DEF) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
$(LDFLAGS) \
-map=$(OUTDIR_REL)/$(FILE_NAME).map
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
@$(OD) -full -ytext $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
###################################################
# Compile
###################################################
$(OUTDIR_OBJ)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(CC) $(CFLAGS) -o $@ -c $<
$(OUTDIR_OBJ)/%.o:%.S
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(AS) $(ASFLAGS) -o $@ -c $<
.PHONY: clean
clean:
@rm -rf $(OUTDIR)

34
IPL/SDK/v3h/src/Dummy_FW/common/log.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Log driver
******************************************************************************/
#include <stdarg.h>
#include <stdint.h>
#include <log.h>
#include <scif.h>
void local_printf(const char *fmt, ...)
{
va_list ap;
static char buffer[1024];
int32_t num;
uint32_t loop;
va_start(ap, fmt);
num = vsprintf(buffer, fmt, ap);
va_end(ap);
if (0 < num) {
for (loop = 0; loop < num; loop++) {
(void)console_putc(buffer[loop]);
if (buffer[loop] == '\n') {
(void)console_putc('\r');
}
}
} else {
panic();
}
}

48
IPL/SDK/v3h/src/Dummy_FW/common/mem_io.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : memory access driver
******************************************************************************/
#include <stdint.h>
void mem_write8(uintptr_t addr, uint8_t data)
{
*(volatile uint8_t*)addr = data;
}
uint8_t mem_read8(uintptr_t addr)
{
return (*(volatile uint8_t*)addr);
}
void mem_write16(uintptr_t addr, uint16_t data)
{
*(volatile uint16_t*)addr = data;
}
uint16_t mem_read16(uintptr_t addr)
{
return (*(volatile uint16_t*)addr);
}
void mem_write32(uintptr_t addr, uint32_t data)
{
*(volatile uint32_t*)addr = data;
}
uint32_t mem_read32(uintptr_t addr)
{
return (*(volatile uint32_t*)addr);
}
void mem_write64(uintptr_t addr, uint64_t data)
{
*(volatile uint64_t*)addr = data;
}
uint64_t mem_read64(uintptr_t addr)
{
return (*(volatile uint64_t*)addr);
}
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
}

72
IPL/SDK/v3h/src/Dummy_FW/common/micro_wait.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Time wait driver
******************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (*(volatile uint16_t*)0xFFFEEA14U)
#define INTCR_RF (1U <<12)
#define OSTM0_BASE (0xFFFEE000UL)
#define OSTM0CMP (*(volatile uint32_t*)(OSTM0_BASE))
#define OSTM0CNT (*(volatile uint32_t*)(OSTM0_BASE + 0x4UL))
#define OSTM0TE (*(volatile uint8_t*)(OSTM0_BASE + 0x10UL))
#define OSTM0TS (*(volatile uint8_t*)(OSTM0_BASE + 0x14UL))
#define OSTM0TT (*(volatile uint8_t*)(OSTM0_BASE + 0x18UL))
#define OSTM0CTL (*(volatile uint8_t*)(OSTM0_BASE + 0x20L))
#define OSTM0EMU (*(volatile uint32_t*)(OSTM0_BASE + 0x24L))
#define OSTM0TS_TS (1U) /* b0:1: Start */
#define OSTM0TT_TT (1U) /* b0:1: Stop */
#define OSTM0TE_TE (1U) /* b0:1: Counter enabled */
#define OSTM0CMP_MICRO_VALUE (0x190UL) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (0x2U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
/************************************************************************************************/
/* Prototypes */
/************************************************************************************************/
static void start_microtimer(uint32_t val);
static void stop_microtimer(void);
static void start_microtimer(uint32_t val)
{
OSTM0TT = OSTM0TT_TT;
OSTM0CMP = val;
OSTM0CTL = OSTM0CTL_MD10;
OSTM0TS = OSTM0TS_TS;
}
static void stop_microtimer(void)
{
OSTM0TT = OSTM0TT_TT;
}
void micro_wait(uint32_t count_us)
{
uint32_t val;
if (count_us == 0) {
return;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
start_microtimer(val);
while (1) {
if (INTICUOSTM0 & INTCR_RF) {
INTICUOSTM0 &= (uint16_t)(~INTCR_RF);
stop_microtimer();
break;
}
}
}

171
IPL/SDK/v3h/src/Dummy_FW/common/remap.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap driver
******************************************************************************/
#include <stdint.h>
#include <remap.h>
#include <remap_register.h>
#include <mem_io.h>
#include <log.h>
typedef struct {
uint8_t number;
uint32_t address;
}REMAP_ADDRESS_TABLE;
#define REMAP_TBL_MAX (sizeof(remap_tbl)/sizeof(remap_tbl[0]))
static REMAP_ADDRESS_TABLE remap_tbl[] = {
[0] = {0xFF, 0x00000000U},
[1] = {0xFF, 0x00000000U},
[2] = {0xFF, 0x00000000U},
[3] = {0xFF, 0x00000000U},
[4] = {0xFF, 0x00000000U},
[5] = {0xFF, 0x00000000U},
[6] = {6, 0xE7200000U},
[7] = {7, 0xE6400000U},
[8] = {8, 0xFFC10000U},
[9] = {9, 0xE6E00000U},
[10] = {10, 0xFFC10000U},
[11] = {11, 0xEE200000U},
[12] = {12, 0xE6200000U},
[13] = {13, 0xE6000000U},
[14] = {14, 0xE6600000U},
[15] = {15, 0xEB200000U},
};
void remap_write_SICREMAP2M(uint32_t num, uint32_t value)
{
/* Write-Protected Register Write Procedure */
do {
mem_write32(ICUMX_PROT0PCMD, PROTCMD_START);
mem_write32(SICREMAP2M(num), value);
mem_write32(SICREMAP2M(num), ~value);
mem_write32(SICREMAP2M(num), value);
} while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR);
}
uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr)
{
uint32_t loop;
uint32_t loop2;
uint32_t map_num;
uint32_t set_addr;
for (loop = 0; loop < REMAP_TBL_MAX; ++loop) {
if (0xFF == remap_tbl[loop].number) {
map_num = (addr & REMAP_2M_MASK) + size;
map_num = (map_num + REMAP_2M_MASK)
/ (1 << REMAP_2M_BITS);
for (loop2 = 0; loop2 < map_num; ++loop2) {
if (0xFF != remap_tbl[loop].number) {
break;
}
}
if (map_num <= loop2) {
break;
}
}
}
if (REMAP_TBL_MAX <= loop) {
return 2;
}
__asm__ __volatile__ ("SYNCM");
set_addr = addr & ~REMAP_2M_MASK;
for (loop2 = loop; loop2 < (map_num + loop); ++loop2) {
remap_tbl[loop2].address = set_addr;
remap_tbl[loop2].number = loop;
remap_write_SICREMAP2M(loop2, set_addr);
set_addr += (1 << REMAP_2M_BITS);
}
__asm__ __volatile__ ("SYNCM");
*remap_addr = ICU_REMAP_CALC(loop);
*remap_addr += addr & REMAP_2M_MASK;
return 0;
}
uint32_t remap_unregister(uint32_t remap_addr)
{
uint32_t loop;
uint32_t loop2;
uint32_t remove_num;
for (loop = 0; loop < REMAP_TBL_MAX; ++loop) {
if ((0xFF != remap_tbl[loop].number)
&& ((ICU_REMAP_CALC(loop) <= remap_addr)
&& (remap_addr < ICU_REMAP_CALC(loop+1)))) {
break;
}
}
if (REMAP_TBL_MAX <= loop) {
return 1;
}
__asm__ __volatile__ ("SYNCM");
remove_num = remap_tbl[loop].number;
for (loop2 = remove_num; loop2 < REMAP_TBL_MAX; ++loop2) {
if (remap_tbl[loop2].number != remove_num) {
break;
}
remap_tbl[loop2].address = 0;
remap_tbl[loop2].number = 0xFF;
remap_write_SICREMAP2M(loop2, ICU_REMAP_CALC(loop2));
}
__asm__ __volatile__ ("SYNCM");
return 0;
}
uint32_t remap_get_phys_addr(uint32_t remap_addr)
{
uint32_t phys_addr;
uint32_t reg;
if ((ICU_REMAP0 > remap_addr)
|| (ICU_REMAP_CALC(REMAP_REG_MAX) <= remap_addr)) {
ERROR("remap address Error\n");
panic();
}
phys_addr = remap_addr - ICU_REMAP0;
phys_addr >>= REMAP_2M_BITS;
reg = SICREMAP2M(phys_addr);
reg = mem_read32(reg);
phys_addr = reg + (remap_addr & REMAP_2M_MASK);
return phys_addr;
}
uint32_t remap_get_remap_addr(uint32_t phys_addr)
{
uint32_t remap_addr;
uint32_t reg;
uint32_t loop;
for (loop = 0; loop < REMAP_REG_MAX; loop++) {
reg = mem_read32(SICREMAP2M(loop));
if ((reg <= phys_addr)
&& (phys_addr <= (reg + REMAP_2M_MASK))) {
break;
}
}
if (REMAP_REG_MAX <= loop) {
ERROR("remap address Error\n");
panic();
}
remap_addr = ICU_REMAP_CALC(loop);
remap_addr += phys_addr - reg;
return remap_addr;
}

62
IPL/SDK/v3h/src/Dummy_FW/common/scif.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF driver
******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <scif_register.h>
#include <rcar_def.h>
#include <scif.h>
#include <mem_io.h>
void scif_init(void)
{
volatile uint16_t reg;
mem_write16(SCIF_SCSMRIR, 0x0000U); /* SCIF channel0 as SCIF */
reg = mem_read16(SCIF_SCLSR); /* dummy read */
mem_write16(SCIF_SCLSR, 0x0000U); /* clear ORER bit */
mem_write16(SCIF_SCFSR, 0x0000U); /* clear all error bit */
mem_write16(SCIF_SCSCR, 0x0000U); /* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCFCR, 0x0006U); /* reset tx-fifo, reset rx-fifo. */
mem_write16(SCIF_SCSCR, 0x0000U); /* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSMR, 0x0000U); /* 8bit data, no-parity, 1 stop, Po/1 */
// micro_wait(10U); /* 10us */
mem_write16(SCIF_SCBRR, 0x11U); /* Pclk(66MHz)/1, 115.2kBps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
// micro_wait(10U); /* 10us */
mem_write16(SCIF_SCFCR, 0x0000U); /* reset-off tx-fifo, rx-fifo. */
mem_write16(SCIF_SCSCR, 0x0030U); /* enable TE, RE; SC_CLK=no output */
// micro_wait(10U); /* 10us */
}
void console_puts(char *str,char rtn)
{
while (*str) {
console_putc(*str);
str++;
}
if(rtn == 1){
console_putc(CR_CODE);
console_putc(LF_CODE);
}
}
void console_putc(uint8_t outchar)
{
uint16_t reg;
while (!(0x60U & mem_read16(SCIF_SCFSR))) {
}
mem_write8(SCIF_SCFTDR, outchar);
reg = mem_read16(SCIF_SCFSR);
reg &= ~0x60U; /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR, reg);
}

57
IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.S Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW start code
******************************************************************************/
.global code_start
.global _dummy_fw_main
.global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */
.section ".text"
.align 2
code_start:
mov r0, r1
mov r0, r2
mov r0, r3
mov r0, r4
mov r0, r5
mov r0, r6
mov r0, r7
mov r0, r8
mov r0, r9
mov r0, r10
mov r0, r11
mov r0, r12
mov r0, r13
mov r0, r14
mov r0, r15
mov r0, r16
mov r0, r17
mov r0, r18
mov r0, r19
mov r0, r20
mov r0, r21
mov r0, r22
mov r0, r23
mov r0, r24
mov r0, r25
mov r0, r26
mov r0, r27
mov r0, r28
mov r0, r29
ldsr r0, 0, 0
ldsr r0, 16, 0
mov ___ghsend_RT_stack, sp
jarl _dummy_fw_main, lp
jmp [r10]
nop
halt

76
IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.ld Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW linker directive
******************************************************************************/
DEFAULTS {
remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000)
remap_size = 1M //RT-SRAM size
rt_sram_addr = 0xEB200000 //RT-SRAM address
// fw_size = 110K //Dummy FW size
fw_size = 93K //Dummy FW size
fw_rom_size = 89K
fw_stack_size = 4K //Dummy FW stack size
fw_addr = 0xFDEB4000 //Dummy FW start address
fw_stack_addr = fw_addr + fw_rom_size //Dummy FW stack address
fw_phy_addr = 0xEB2B4000 //Dummy FW physical start address
fw_phy_stack_addr = fw_phy_addr + fw_rom_size //Dummy FW physical stack address
}
MEMORY
{
fw_start : ORIGIN = fw_addr, LENGTH = fw_rom_size //Dummy FW ROM(Start address)
stack : ORIGIN = fw_stack_addr, LENGTH = fw_stack_size//Dummy FW stack
fw_phys_start : ORIGIN = fw_phy_addr, LENGTH = fw_rom_size //Dummy FW(RT-SRAM)
}
//
// Program layout for starting in ROM, copying data to RAM,
// and continuing to execute out of ROM.
//
SECTIONS
{
//
// ROM SECTIONS(Remap)
//
// Place .text into fast_memory. Fail if it does not fit.
.reset ALIGN(4) : > fw_start
.EIINTTBL_ICU ALIGN(4) : > .
.version ALIGN(1024) :{*(.version)} > .
.text ALIGN(4) : > .
.data ALIGN(4) : > .
.rosdata ALIGN(4) : > .
.rodata ALIGN(4) : > .
.bss ALIGN(4) : > .
.sdata ALIGN(4) : > .
.tdata ALIGN(4) : > .
.sdabase ALIGN(4) : > .
.secinfo ALIGN(4) : > .
// .note.renesas ALIGN(4) : > .
// .linfix ALIGN(4) : > .
// .gstackfix ALIGN(4) : > .
// ROM mirror SECTIONS(RT-SRAM)
.ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > fw_phys_start
.ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > .
.ROM_NOCOPY.version ROM_NOCOPY(.version) ALIGN(1024) : > .
.ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > .
.ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > .
.ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > .
.ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > .
.ROM_NOCOPY.bss ROM_NOCOPY(.bss) ALIGN(4) : > .
.ROM_NOCOPY.sdata ROM_NOCOPY(.sdata) ALIGN(4) : > .
.ROM_NOCOPY.tdata ROM_NOCOPY(.tdata) ALIGN(4) : > .
.ROM_NOCOPY.sdabase ROM_NOCOPY(.sdabase) ALIGN(4) : > .
.ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > .
//
// RAM SECTIONS
//
.RT.stack ALIGN(4) PAD(fw_stack_size) ABS : > stack
}

36
IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw_main.c Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : dummy fw main function
******************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <log.h>
#include <dummy_fw_main.h>
#include <mem_io.h>
#include <remap.h>
#include <remap_register.h>
#include <rcar_def.h>
#include <scif.h>
#include <rst_register.h>
/* Global */
extern const char build_message[];
static void boot_message(void);
uint32_t dummy_fw_main(void)
{
scif_init();
boot_message();
while(1);
}
static void boot_message(void)
{
/* boot message */
console_puts("",1);
console_puts("Dummy FW Program",1);
console_puts("Dummy FW Program boot end",1);
}

98
IPL/SDK/v3h/src/Dummy_FW/fw/vecttbl.S Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW vector table
******************************************************************************/
.global code_start
.section ".reset"
.align 512
.align 16
_start:
jr32 code_start //RESET
.align 16
jr32 _Dummy //SYSERR
.align 16
jr32 _Dummy //HVTRAP
.align 16
jr32 _Dummy //FETRAP
.align 16
jr32 _Dummy //TRAP0
.align 16
jr32 _Dummy //TRAP1
.align 16
jr32 _Dummy //RIE
.align 16
jr32 _Dummy //FPP/FPI
.align 16
jr32 _Dummy //UCPOP
.align 16
jr32 _Dummy //MIP/MDP
.align 16
jr32 _Dummy //PIE
.align 16
jr32 _Dummy //Debug
.align 16
jr32 _Dummy //MAE
.align 16
jr32 _Dummy //(R.F.U)
.align 16
jr32 _Dummy //FENMI
.align 16
jr32 _Dummy //FEINT
.align 16
jr32 _Dummy //INTn(priority0)
.align 16
jr32 _Dummy //INTn(priority1)
.align 16
jr32 _Dummy //INTn(priority2)
.align 16
jr32 _Dummy //INTn(priority3)
.align 16
jr32 _Dummy //INTn(priority4)
.align 16
jr32 _Dummy //INTn(priority5)
.align 16
jr32 _Dummy //INTn(priority6)
.align 16
jr32 _Dummy //INTn(priority7)
.align 16
jr32 _Dummy //INTn(priority8)
.align 16
jr32 _Dummy //INTn(priority9)
.align 16
jr32 _Dummy //INTn(priority10)
.align 16
jr32 _Dummy //INTn(priority11)
.align 16
jr32 _Dummy //INTn(priority12)
.align 16
jr32 _Dummy //INTn(priority13)
.align 16
jr32 _Dummy //INTn(priority14)
.align 16
jr32 _Dummy //INTn(priority15)
.section ".EIINTTBL_ICU", const
.align 512
.rept 7
.word _Dummy_EI //INTn
.endr
.word _Dummy_EI //OSTM0
.rept 20
.word _Dummy_EI //INTn
.endr
.word _Dummy_EI //_Dummy
.word _Dummy_EI //_Dummy
.rept 98
.word _Dummy_EI //INTn
.endr
.section ".text"
.align 2
_Dummy:
br _Dummy
_Dummy_EI:
br _Dummy_EI

16
IPL/SDK/v3h/src/Dummy_FW/include/dummy_fw_main.h Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Dummy FW main header
******************************************************************************/
#ifndef DUMMY_FW_MAIN_H_
#define DUMMY_FW_MAIN_H_
/* define */
#define VERSION "1.0.0"
/* prototype */
uint32_t dummy_fw_main(void);
#endif /* DUMMY_FW_MAIN_H_ */

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IPL/SDK/v3h/src/Dummy_FW/include/log.h Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Log driver header
******************************************************************************/
#ifndef LOG_H__
#define LOG_H__
#include <stdint.h>
#include <stdio.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#ifndef LOG_LEVEL
#define LOG_LEVEL (LOG_WARNING)
#endif
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) local_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) local_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) local_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) local_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) local_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#define panic(...) \
do { \
local_printf("P:%s[%d]\n", __func__, __LINE__); \
while(1); \
} while (0)
#define FORCE(...) local_printf(__VA_ARGS__)
void local_printf(const char *fmt, ...);
#endif /* LOG_H__ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Memory access driver header
******************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
/* Prototype */
void mem_write8(uintptr_t addr, uint8_t data);
uint8_t mem_read8(uintptr_t addr);
void mem_write16(uintptr_t addr, uint16_t data);
uint16_t mem_read16(uintptr_t addr);
void mem_write32(uintptr_t addr, uint32_t data);
uint32_t mem_read32(uintptr_t addr);
void mem_write64(uintptr_t addr, uint64_t data);
uint64_t mem_read64(uintptr_t addr);
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set);
#if defined(__RH850G3K__)
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif
#endif /* MEM_IO_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : Time wait driver header
******************************************************************************/
#ifndef MICRO_WAIT_H_
#define MICRO_WAIT_H_
#include <stdint.h>
/* Define */
/* Prototype */
void micro_wait(uint32_t count_us);
#endif /* MICRO_WAIT_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : R-Car common header
******************************************************************************/
#ifndef RCAR_DEF_H_
#define RCAR_DEF_H_
#include "remap_register.h"
/* Product Register */
#define PRR (BASE_PRR_ADDR) /* PRR register */
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */
#define PRR_MAJOR_OFFSET (1U)
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#define PRR_PRODUCT_10 (0x00U)
#define RCAR_PRR (PRR) /* PRR register */
#define RCAR_PRODUCT_MASK (PRR_PRODUCT_MASK) /* Product mask */
#define RCAR_PRODUCT_V3H (PRR_PRODUCT_V3H) /* R-Car V3H */
#endif /* RCAR_DEF_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap driver header
******************************************************************************/
#ifndef REMAP_H_
#define REMAP_H_
#define REMAP_SIZE_MIN (2*1024*1024)
#define REMAP_ALIGN_MASK (~((1 << 21) - 1))
void remap_write_SICREMAP2M(uint32_t num, uint32_t value);
uint32_t remap_get_phys_addr(uint32_t remap_addr);
uint32_t remap_get_remap_addr(uint32_t phys_addr);
uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr);
uint32_t remap_unregister(uint32_t remap_addr);
#endif /* REMAP_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : remap register header
******************************************************************************/
#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_
#define REMAP_BASE (0xFF1FC400U)
#define REMAP_2M_BITS (21U)
#define REMAP_2M_MASK ((1 << REMAP_2M_BITS) - 1U)
#define REMAP_REG_MAX (16U)
#define SICREMAP2M(a) (REMAP_BASE + ((a) * (0x4U)))
#define ICUMX_PROT0PCMD (0xFFFEE090U)
#define ICUMX_PROT0PS (0xFFFEE094U)
#define PROTCMD_START (0x000000A5U)
#define PROTS0ERR (0x00000001U)
/* REMAP setting */
/* Remap ID(0 -- 15) */
#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */
#define ICU_REMAP_NUM_CC (14U) /* CC63S */
#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */
#define ICU_REMAP_NUM_RPC (11U) /* RPC */
#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */
#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */
#define ICU_REMAP_NUM_MMC (8U) /* MMC */
#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */
#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */
#define ICU_REMAP_NUM_PRR (5U) /* PRR */
#define ICU_REMAP_NUM_RTACT (4U) /* RT-ACT */
/* SICREMAP2M15 */
#define ICU_REMAP_RTRAM (0xEB200000U) /* RTRAM */
/* SICREMAP2M14 */
#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */
/* SICREMAP2M13 */
#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
/* SICREMAP2M12 */
#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */
/* SICREMAP2M11 */
#define ICU_REMAP_RPC (0xEE200000U) /* RPC */
/* SICREMAP2M10 */
#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF */
/* SICREMAP2M9 */
#define ICU_REMAP_MMC (0xEE000000U) /* MMC */
/* SICREMAP2M8 */
#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */
/* SICREMAP2M7 */
#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */
/* SICREMAP2M6 */
#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */
/* SICREMAP2M5 */
#define ICU_REMAP_PRR (0xFFE00000U) /* PRR */
/* SICREMAP2M4 */
#define ICU_REMAP_RTACT (0xFFC00000U) /* RT-ACT */
#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */
#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */
#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */
#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */
#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */
#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */
#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */
#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */
#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */
#define ICU_REMAP5_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection*/
#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */
/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define ICU_REMAP_OFFSET_RTRAM (0x000000U)
/* REMAP14(0xE6600000U) */
#define ICU_REMAP_OFFSET_CC63S (0x000000U)
#define ICU_REMAP_OFFSET_AXI (0x184000U) /* (0xE6784000U) */
#define ICU_REMAP_OFFSET_DBSC (0x190000U) /* (0xE6790000U) */
#define ICU_REMAP_OFFSET_MSTAT (0x1e0000U) /* (0xE67e0000U) */
#define ICU_REMAP_OFFSET_QOS (0x1F0000U) /* (0xE67F0000U) */
/* REMAP13(0xE6000000U) */
/* GPIO */
#define ICU_REMAP_OFFSET_GPIO0 (0x050000U)
#define ICU_REMAP_OFFSET_GPIO1 (0x051000U)
#define ICU_REMAP_OFFSET_GPIO2 (0x052000U)
#define ICU_REMAP_OFFSET_GPIO3 (0x053000U)
#define ICU_REMAP_OFFSET_GPIO4 (0x054000U)
#define ICU_REMAP_OFFSET_GPIO5 (0x055000U)
/* PFC */
#define ICU_REMAP_OFFSET_PFC (0x060000U)
/* LIFEC */
#define ICU_REMAP_OFFSET_LIFEC (0x110000U)
/* CPGA */
#define ICU_REMAP_OFFSET_CPGA (0x150000U)
/* RESET */
#define ICU_REMAP_OFFSET_RESET (0x160000U)
/* SYSC */
#define ICU_REMAP_OFFSET_SYSC (0x180000U)
/* THS1 */
#define ICU_REMAP_OFFSET_THS1 (0x198000U) /* (0xE6198000U) */
/* REMAP12(0xE6200000U) */
/* MFIS */
#define ICU_REMAP_OFFSET_MFIS (0x060000U)
/* REMAP11(0xEE200000U) */
/*RPC*/
#define ICU_REMAP_OFFSET_RPC (0x000000U)
/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define ICU_REMAP_OFFSET_RTDMA (0x010000U)
/* REMAP9(0xE6E00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF0 (0x060000U)
/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define ICU_REMAP_OFFSET_SDHI (0x140000U)
/* REMAP7(0xE6400000U) */
/* HSCIF */
#define ICU_REMAP_OFFSET_HSCIF0 (0x140000U)
/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define ICU_REMAP_OFFSET_SYSDMAC (0x100000U)
/* REMAP5(0xFFE00000U) */
/* PRR */
#define ICU_REMAP_OFFSET_PRR (0x100044U)
/* REMAP4(0xFFE00000U) */
/* RT-ACT */
#define ICU_REMAP_OFFSET_RTACT (0x050800U)
/* Calculate the base address of each register after remapping */
#define ICU_REMAP0 (0xFC000000U)
#define ICU_REMAP_CALC( val ) (ICU_REMAP0 + (val * 0x200000U))
/* REMAP15(0xEB200000U) */
#define BASE_RTRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTRAM)
/* REMAP14(0xE6600000U) */
#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI)
#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT)
#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
/* REMAP13(0xE6000000U) */
#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0)
#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC)
#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1)
/* REMAP12(0xE6200000U) */
#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS)
/* REMAP11(0xEE200000U) */
#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA)
/* REMAP9(0xE6E00000U) */
#define BASE_SCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP5(0xFFE00000U) */
#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR)
/* REMAP4(0xFFE00000U) */
#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTACT) + ICU_REMAP_OFFSET_RTACT)
/* MFIS */
#define MFIS_MFISSOFTMDR (BASE_MFIS_ADDR + 0x0600U) /* SOFTMD register */
#define MFIS_MFISBTSTSR (BASE_MFIS_ADDR + 0x0604U) /* (0xE6260604U) */
#define MFIS_MFISWACNTR (BASE_MFIS_ADDR + 0x0904U) /* (0xE6260904U) */ /* Write Access Control Register */
#endif /* REMAP_REGISTER_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : RST register header
******************************************************************************/
#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_
#include <remap_register.h>
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_CR7BAR (RST_BASE + 0x0070U)
#define RST_CR7BAR_BAREN ((uint32_t)1U << 4)
#define WDTRSTCR_PASSWORD (0xA55A0000U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
#define RST_ICUMXBAR (RST_BASE + 0x0078U)
#define RST_ICUMXBAR_BAREN ((uint32_t)1U << 4)
#define RST_MODEMR (RST_BASE + 0x0060U) /* Mode pin register */
#define RST_MODEMR_A (RST_BASE + 0x0060U) /* Mode pin register for Assembly language */
#define RST_MODEMR2 (RST_BASE + 0x0068U) /* Mode Monitor Register2 */
#define RST_CA57RESCNT (RST_BASE + 0x0040U) /* Reset control register for A57 */
#define RST_CA53RESCNT (RST_BASE + 0x0044U) /* Reset control register for A53 */
#define RST_CA57CPU0BARL (RST_BASE + 0x00C4U)
#define RST_CA57CPU0BARH (RST_BASE + 0x00C0U)
#define RST_CA53CPU0BARL (RST_BASE + 0x0084U)
#define RST_CA53CPU0BARH (RST_BASE + 0x0080U)
#define MODEMR_BOOT_CPU_MASK (0x000000C0U)
#define MODEMR_BOOT_CPU_CR7 (0x000000C0U)
#define MODEMR_BOOT_CPU_CA57 (0x00000000U)
#define MODEMR_BOOT_CPU_CA53 (0x00000040U)
#define MODEMR_BOOT_DEV_MASK (0x0000001EU)
#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU)
#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU)
#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU)
#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU)
#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU)
#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU)
#endif /* RST_REGISTER_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF driver header
******************************************************************************/
#ifndef SCIF_H_
#define SCIF_H_
/* Define */
#define PFC_GPSR_SCIF_MASK (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_GPSR_SCIF_VAL (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_IPSR_SCIF_MASK (0x0FF00000UL) /* SCIF0 RX/TX */
#define PFC_IPSR_SCIF_VAL (0x04400000UL) /* SCIF0 RX/TX */
#define BIT7 (uint32_t)(1U << 7U) /* Module Stop 2 bit7(SCIF0) */
#define CR_CODE (0x0DU)
#define LF_CODE (0x0AU)
/* Prototype */
void scif_init(void);
void console_puts(char* str,char rtn);
void console_putc(uint8_t outchar);
#endif /* SCIF_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* DESCRIPTION : SCIF register header
******************************************************************************/
#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_
#include <remap_register.h>
/* SCIF0 base address */
/* 0xE6E60000 */
#define SCIF0_BASE (BASE_SCIF_ADDR)
#define SCIF_SCSMR (SCIF0_BASE + 0x00U) /* 16 Serial mode register */
#define SCIF_SCBRR (SCIF0_BASE + 0x04U) /* 8 Bit rate register */
#define SCIF_SCSCR (SCIF0_BASE + 0x08U) /* 16 Serial control register */
#define SCIF_SCFTDR (SCIF0_BASE + 0x0CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR (SCIF0_BASE + 0x10U) /* 16 Serial status register */
#define SCIF_SCFRDR (SCIF0_BASE + 0x14U) /* 8 Receive FIFO data register */
#define SCIF_SCFCR (SCIF0_BASE + 0x18U) /* 16 FIFO control register */
#define SCIF_SCFDR (SCIF0_BASE + 0x1CU) /* 16 FIFO data count register */
#define SCIF_SCSPTR (SCIF0_BASE + 0x20U) /* 16 Serial port register */
#define SCIF_SCLSR (SCIF0_BASE + 0x24U) /* 16 Line status register */
#define SCIF_DL (SCIF0_BASE + 0x30U) /* 16 Frequency division register */
#define SCIF_CKS (SCIF0_BASE + 0x34U) /* 16 Clock Select register */
#define SCIF_SCFER (SCIF0_BASE + 0x44U) /* 16 FIFO error count register */
#define SCIF_SCSMRIR (SCIF0_BASE + 0x40U) /* 16 Serial mode register */
/*HSCIF0 base address*/
/* 0xE6540000 */
#define HSCIF_BASE (BASE_HSCIF_ADDR)
#define HSCIF_HSSMR (HSCIF_BASE + 0x00U) /* 16 Serial mode register */
#define HSCIF_HSBRR (HSCIF_BASE + 0x04U) /* 8 Bit rate register */
#define HSCIF_HSSCR (HSCIF_BASE + 0x08U) /* 16 Serial control register */
#define HSCIF_HSFTDR (HSCIF_BASE + 0x0CU) /* 8 Transmit FIFO data register */
#define HSCIF_HSFSR (HSCIF_BASE + 0x10U) /* 16 Serial status register */
#define HSCIF_HSFRDR (HSCIF_BASE + 0x14U) /* 8 Receive FIFO data register */
#define HSCIF_HSFCR (HSCIF_BASE + 0x18U) /* 16 FIFO control register */
#define HSCIF_HSFDR (HSCIF_BASE + 0x1CU) /* 16 FIFO data count register */
#define HSCIF_HSSPTR (HSCIF_BASE + 0x20U) /* 16 Serial port register */
#define HSCIF_HSLSR (HSCIF_BASE + 0x24U) /* 16 Line status register */
#define HSCIF_HSSRR (HSCIF_BASE + 0x40U) /* 16 Sampling rate register */
#define HSCIF_HSRER (HSCIF_BASE + 0x44U) /* 16 Serial error register */
#define HSCIF_HSRTGR (HSCIF_BASE + 0x50U) /* 16 RTS output active trigger register */
#define HSCIF_HSRTRGR (HSCIF_BASE + 0x54U) /* 16 Receive FIFO data count trigger register */
#define HSCIF_HSTTRGR (HSCIF_BASE + 0x58U) /* 16 Transmit FIFO data count trigger register */
#define HSCIF_DL (HSCIF_BASE + 0x30U) /* 16 Frequency division register */
#define HSCIF_CKS (HSCIF_BASE + 0x34U) /* 16 Clock Select register */
#endif /* SCIF_REGISTER_H_ */

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#
# Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
#
###################################################
# makefile
###################################################
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude
#output file name
FILE_NAME = dummy_rtos
OUTPUT_FILE = $(FILE_NAME).elf
OUTPUT_DIR = output
OBJECT_DIR = obj
#object file name
OBJ_FILE = common/scif.o \
common/div.o \
rtos/rtos.o \
rtos/rtos_main.o
#linker script name
MEMORY_DEF = rtos/rtos.ld.S
###################################################
# Process LOG_LEVEL flag
ifndef LOG_LEVEL
LOG_LEVEL := 20
endif
$(eval $(call add_define,LOG_LEVEL))
###################################################
CC = $(CROSS_COMPILE)gcc
CPP = ${CROSS_COMPILE}cpp
AS = ${CROSS_COMPILE}gcc
AR = ${CROSS_COMPILE}ar
LD = $(CROSS_COMPILE)ld
OC = ${CROSS_COMPILE}objcopy
OD = ${CROSS_COMPILE}objdump
ASFLAGS = -marm -march=armv7-r \
-nostdinc -ffreestanding -Wa,--fatal-warnings \
-Werror -Wmissing-include-dirs \
-c -D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS = -marm -march=armv7-r \
-nostdinc -ffreestanding -Wall \
-Werror -Wmissing-include-dirs \
-std=c99 -c -Os \
-ffunction-sections -fdata-sections \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -g
ASFLAGS += -g -Wa,--gdwarf-2
LDFLAGS = --fatal-warnings -O1 --gc-sections
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OUTPUT_FILE)
###################################################
# Make Directory
###################################################
$(OBJECT_DIR):
mkdir -p $(OBJECT_DIR)
$(OUTPUT_DIR):
mkdir -p $(OUTPUT_DIR)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
$(LD) $(OBJ_FILE) \
-T $(MEMORY_DEF) \
-o $(OUTPUT_FILE) \
$(LDFLAGS) \
-Map $(FILE_NAME).map
$(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec
$(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin
$(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump
###################################################
# Compile
###################################################
%.o:../%.c
$(CC) $(CFLAGS) -o $@ $<
%.o:../%.s
$(AS) $(ASFLAGS) -o $@ $<
.PHONY: clean
clean:
$(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(FILE_NAME).*

39
IPL/SDK/v3h/src/Dummy_RTOS/common/div.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.global __aeabi_uidivmod
/*****************************************************************************
* input:
* r0: divided
* r1: divisor
*
* output
* r0: quot
* r1: rem
*****************************************************************************/
__aeabi_uidivmod:
push {r4, r5}
mov r4, #0
mov r5, #1
clz r2, r1
mov r3, r1, LSL r2
1:
cmp r3, r0
subls r0, r0, r3
addls r4, r5, LSL r2
lsr r3, r3, #1
subs r2, r2, #1
bpl 1b
mov r1, r0
mov r0, r4
pop {r4, r5}
bx lr
.end

29
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include <stdint.h>
#include <scif.h>
/************************************************************************/
/*NAME : PutStr */
/************************************************************************/
void PutStr(const char *str,char rtn)
{
while(*str){
PutChar(*str);
str++;
}
if(rtn == 1){
PutChar(CR_CODE);
PutChar(LF_CODE);
}
}
void PutChar(char outChar)
{
while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) ));
*((volatile uint8_t*)SCIF0_SCFTDR) = outChar;
*((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */
}

63
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef __DEBUG_H__
#define __DEBUG_H__
#include <stdio.h>
/* The log output macros print output to the console. These macros produce
* compiled log output only if the LOG_LEVEL defined in the makefile (or the
* make command line) is greater or equal than the level required for that
* type of log output.
* The format expected is the same as for printf(). For example:
* INFO("Info %s.\n", "message") -> INFO: Info message.
* WARN("Warning %s.\n", "message") -> WARNING: Warning message.
*/
#define LOG_LEVEL_NONE 0
#define LOG_LEVEL_ERROR 10
#define LOG_LEVEL_NOTICE 20
#define LOG_LEVEL_WARNING 30
#define LOG_LEVEL_INFO 40
#define LOG_LEVEL_VERBOSE 50
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_ERROR
# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_WARNING
# define WARN(...) tf_printf("WARNING: " __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_INFO
# define INFO(...) tf_printf("INFO: " __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
void __dead2 do_panic(void);
#define panic() do_panic()
void tf_printf(const char *fmt, ...) __printflike(1, 2);
#endif /* __DEBUG_H__ */

164
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/*-
* Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## L)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## UL)
#define INTMAX_C(c) INT64_C(c)
#define UINTMAX_C(c) UINT64_C(c)
#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
/*
* ISO/IEC 9899:1999
* 7.18.2.1 Limits of exact-width integer types
*/
/* Minimum values of exact-width signed integer types. */
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffUL
/*
* ISO/IEC 9899:1999
* 7.18.2.2 Limits of minimum-width integer types
*/
/* Minimum values of minimum-width signed integer types. */
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
/* Maximum values of minimum-width signed integer types. */
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
/* Maximum values of minimum-width unsigned integer types. */
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.3 Limits of fastest minimum-width integer types
*/
/* Minimum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MIN INT32_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
/* Maximum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MAX INT32_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
/* Maximum values of fastest minimum-width unsigned integer types. */
#define UINT_FAST8_MAX UINT32_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.4 Limits of integer types capable of holding object pointers
*/
#define INTPTR_MIN INT64_MIN
#define INTPTR_MAX INT64_MAX
#define UINTPTR_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.5 Limits of greatest-width integer types
*/
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.3 Limits of other integer types
*/
/* Limits of ptrdiff_t. */
#define PTRDIFF_MIN INT64_MIN
#define PTRDIFF_MAX INT64_MAX
/* Limits of sig_atomic_t. */
#define SIG_ATOMIC_MIN INT32_MIN
#define SIG_ATOMIC_MAX INT32_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT64_MAX
#ifndef WCHAR_MIN /* Also possibly defined in <wchar.h> */
/* Limits of wchar_t. */
#define WCHAR_MIN INT32_MIN
#define WCHAR_MAX INT32_MAX
#endif
/* Limits of wint_t. */
#define WINT_MIN INT32_MIN
#define WINT_MAX INT32_MAX
#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
#endif /* !_MACHINE__STDINT_H_ */

110
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/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
* $FreeBSD$
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#ifndef _SYS_CDEFS_H_
#error this file needs sys/cdefs.h as a prerequisite
#endif
/*
* Basic types upon which most other types are built.
*/
typedef __signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
typedef long long __int64_t;
typedef unsigned long long __uint64_t;
/*
* Standard type definitions.
*/
typedef __int32_t __clock_t; /* clock()... */
typedef __int32_t __critical_t;
typedef double __double_t;
typedef float __float_t;
typedef __int32_t __intfptr_t;
typedef __int32_t __intmax_t;
typedef __int32_t __intptr_t;
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int32_t __int_fast64_t;
typedef __int8_t __int_least8_t;
typedef __int16_t __int_least16_t;
typedef __int32_t __int_least32_t;
typedef __int64_t __int_least64_t;
typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */
typedef __int32_t __register_t;
typedef __int32_t __segsz_t; /* segment size (in pages) */
typedef __uint32_t __size_t; /* sizeof() */
typedef __int32_t __ssize_t; /* byte count or error */
typedef __int32_t __time_t; /* time()... */
typedef __uint32_t __uintfptr_t;
typedef __uint64_t __uintmax_t;
typedef __uint32_t __uintptr_t;
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint8_t __uint_least8_t;
typedef __uint16_t __uint_least16_t;
typedef __uint32_t __uint_least32_t;
typedef __uint64_t __uint_least64_t;
typedef __uint32_t __u_register_t;
typedef __uint32_t __vm_offset_t;
typedef __int32_t __vm_ooffset_t;
typedef __uint32_t __vm_paddr_t;
typedef __uint32_t __vm_pindex_t;
typedef __uint32_t __vm_size_t;
/*
* Unusual type definitions.
*/
#ifdef __GNUCLIKE_BUILTIN_VARARGS
typedef __builtin_va_list __va_list; /* internally known to gcc */
#else
typedef char * __va_list;
#endif /* __GNUCLIKE_BUILTIN_VARARGS */
#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \
&& !defined(__NO_GNUC_VA_LIST)
#define __GNUC_VA_LIST
typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/
#endif
#endif /* !_MACHINE__TYPES_H_ */

50
IPL/SDK/v3h/src/Dummy_RTOS/include/mmio.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef __MMIO_H__
#define __MMIO_H__
#include <stdint.h>
static inline void mmio_write_8(uintptr_t addr, uint8_t value)
{
*(volatile uint8_t* )addr = value;
}
static inline uint8_t mmio_read_8(uintptr_t addr)
{
return *(volatile uint8_t *)addr;
}
static inline void mmio_write_16(uintptr_t addr, uint16_t value)
{
*(volatile uint16_t *)addr = value;
}
static inline uint16_t mmio_read_16(uintptr_t addr)
{
return *(volatile uint16_t *)addr;
}
static inline void mmio_write_32(uintptr_t addr, uint32_t value)
{
*(volatile uint32_t *)addr = value;
}
static inline uint32_t mmio_read_32(uintptr_t addr)
{
return *(volatile uint32_t *)addr;
}
static inline void mmio_write_64(uintptr_t addr, uint64_t value)
{
*(volatile uint64_t *)addr = value;
}
static inline uint64_t mmio_read_64(uintptr_t addr)
{
return *(volatile uint64_t *)addr;
}
#endif /* __MMIO_H__ */

93
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef __H_REG_RCAR_GEN3_
#define __H_REG_RCAR_GEN3_
/*********************** RCarGen3_MFI *************************/
#define MFISSOFTMDR 0xE6260600 //SOFTMD register
#define MFISSHESTSR 0xE6260604 //SHE status register
/*********************** RCarGen3_LIFEC *************************/
#define LIFEC_CC_LCS 0xE6110028 // cc_lcs Life cycle state read
/*********************** RCarGen3_RST *************************/
#define RST_MODEMR 0xE6160060 // Mode Monitor Register
/*********************** RCarGen3_DMA *************************/
#define DMA_DMAOR 0xE6700060 //DMA operation register (for west channel)
#define DMA_CHCLR 0xE6700080 //DMA channel clear register (for west channel)
#define DMA_SAR0 0xE6708000 //DMA source address register
#define DMA_DAR0 0xE6708004 //DMA destination address register
#define DMA_TCR0 0xE6708008 //DMA transfer count register
#define DMA_CHCR0 0xE670800C //DMA channel control register
#define DMA_DMARS0 0xE6708040 //DMA extended resource register
/*********************** RCarGen3_RPC/QSPI *************************/
//RPC/QSPI
#define RPC_BASE 0xEE200000
#define RPC_CMNCR (RPC_BASE + 0x0000) //
//#define RPC_DRCR (RPC_BASE + 0x000C) //
//#define RPC_DRCMR (RPC_BASE + 0x0010) //
//#define RPC_DRENR (RPC_BASE + 0x001C) //
#define RPC_SMCR (RPC_BASE + 0x0020) //
#define RPC_SMCMR (RPC_BASE + 0x0024) //
#define RPC_SMENR (RPC_BASE + 0x0030) //
#define RPC_CMNSR (RPC_BASE + 0x0048) //
//#define RPC_DRDMCR (RPC_BASE + 0x0058) //
//#define RPC_DRDRENR (RPC_BASE + 0x005C) //
//#define RPC_PHY_OFFSET1 (RPC_BASE + 0x0080) //
#define RPC_PHY_INT (RPC_BASE + 0x0088) //
/*********************** RCarH3_PFC *************************/
// 5 . PFC
#define PFC_BASE 0xE6060000
#define RCarH3_PFC_PMMR (PFC_BASE + 0x0000) // LSI Multiplexed Pin Setting Mask Register
#define RCarH3_PFC_GPSR5 (PFC_BASE + 0x0114) // GPIO/peripheral function select register 5
#define RCarH3_PFC_IPSR12 (PFC_BASE + 0x0230) // Peripheral function select register 12
#define RCarH3_PFC_MOD_SEL1 (PFC_BASE + 0x0504) // Module select register 1
/*********************** RCarH3_SCIF ****************************************************/
// 51 . Serial Communication Interface with FIFO (SCIF)
/* H3 SCIF2 */
#define H3_SCIF2_BASE 0xE6E88000
#define RCarH3_SCIF2_SCSMR (H3_SCIF2_BASE + 0x00) // 16 Serial mode register
#define RCarH3_SCIF2_SCBRR (H3_SCIF2_BASE + 0x04) // 8 Bit rate register
#define RCarH3_SCIF2_SCSCR (H3_SCIF2_BASE + 0x08) // 16 Serial control register
#define RCarH3_SCIF2_SCFTDR (H3_SCIF2_BASE + 0x0C) // 8 Transmit FIFO data register
#define RCarH3_SCIF2_SCFSR (H3_SCIF2_BASE + 0x10) // 16 Serial status register
#define RCarH3_SCIF2_SCFRDR (H3_SCIF2_BASE + 0x14) // 8 Receive FIFO data register
#define RCarH3_SCIF2_SCFCR (H3_SCIF2_BASE + 0x18) // 16 FIFO control register
#define RCarH3_SCIF2_SCFDR (H3_SCIF2_BASE + 0x1C) // 16 FIFO data count register
#define RCarH3_SCIF2_SCSPTR (H3_SCIF2_BASE + 0x20) // 16 Serial port register
#define RCarH3_SCIF2_SCLSR (H3_SCIF2_BASE + 0x24) // 16 Line status register
#define RCarH3_SCIF2_DL (H3_SCIF2_BASE + 0x30) // 16 Frequency division register
#define RCarH3_SCIF2_CKS (H3_SCIF2_BASE + 0x34) // 16 Clock Select register
#define RCarH3_SCIF2_SCFER (H3_SCIF2_BASE + 0x44) // 16 FIFO error count register
#define RCarH3_SCIF2_SCSMRIR (H3_SCIF2_BASE + 0x40) // 16 Serial mode register
/*********************** RCarH3_CPG_Module Standby, Software Reset *************************/
// 7A . Module Standby, Software Reset
#define H3_CPG_MSTPRST_BASE 0xE6150000
#define RCarH3_CPG_MSTPSR3 (H3_CPG_MSTPRST_BASE+0x0048) // Module stop status register 3
#define RCarH3_CPG_SMSTPCR3 (H3_CPG_MSTPRST_BASE+0x013C) // System module stop control register 3
//#define RCarH3_CPG_SRCR3 (H3_CPG_MSTPRST_BASE+0x00B8) // Software reset register 3
#define RCarH3_CPG_CPGWPCR (H3_CPG_MSTPRST_BASE+0x0904) // CPG Write Protect Control Register
#define RCarH3_CPG_CPGWPR (H3_CPG_MSTPRST_BASE+0x0900) // CPG Write Protect Register
#endif /* __H_REG_RCAR_GEN3_ */

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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef __SCIF_H__
#define __SCIF_H__
//SCIF0
#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register
#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register
#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register
#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register
#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register
#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register
#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register
#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register
#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register
#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register
#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register
#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register
#define CR_CODE (0x0DU)
#define LF_CODE (0x0AU)
void PutStr(const char *str,char rtn);
void PutChar(char outChar);
#endif /* __SCIF_H__ */

75
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/*-
* Copyright (c) 2002 David E. O'Brien. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_STDARG_H_
#define _MACHINE_STDARG_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
#ifndef _VA_LIST_DECLARED
#define _VA_LIST_DECLARED
typedef __va_list va_list;
#endif
#ifdef __GNUCLIKE_BUILTIN_STDARG
#define va_start(ap, last) \
__builtin_va_start((ap), (last))
#define va_arg(ap, type) \
__builtin_va_arg((ap), type)
#define __va_copy(dest, src) \
__builtin_va_copy((dest), (src))
#if __ISO_C_VISIBLE >= 1999
#define va_copy(dest, src) \
__va_copy(dest, src)
#endif
#define va_end(ap) \
__builtin_va_end(ap)
#elif defined(lint)
/* Provide a fake implementation for lint's benefit */
#define __va_size(type) \
(((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long))
#define va_start(ap, last) \
((ap) = (va_list)&(last) + __va_size(last))
#define va_arg(ap, type) \
(*(type *)((ap) += __va_size(type), (ap) - __va_size(type)))
#define va_end(ap)
#else
#error this file needs to be ported to your compiler
#endif
#endif /* !_MACHINE_STDARG_H_ */

64
IPL/SDK/v3h/src/Dummy_RTOS/include/stddef.h Normal file
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/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)stddef.h 8.1 (Berkeley) 6/2/93
*
* $FreeBSD$
*/
#ifndef _STDDEF_H_
#define _STDDEF_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
typedef __ptrdiff_t ptrdiff_t;
#if __BSD_VISIBLE
#ifndef _RUNE_T_DECLARED
typedef __rune_t rune_t;
#define _RUNE_T_DECLARED
#endif
#endif
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef __cplusplus
#ifndef _WCHAR_T_DECLARED
typedef __wchar_t wchar_t;
#define _WCHAR_T_DECLARED
#endif
#endif
#define offsetof(type, member) __offsetof(type, member)
#endif /* _STDDEF_H_ */

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/*-
* Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS_STDINT_H_
#define _SYS_STDINT_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
#include <machine/_stdint.h>
#include <sys/_stdint.h>
typedef __int_least8_t int_least8_t;
typedef __int_least16_t int_least16_t;
typedef __int_least32_t int_least32_t;
typedef __int_least64_t int_least64_t;
typedef __uint_least8_t uint_least8_t;
typedef __uint_least16_t uint_least16_t;
typedef __uint_least32_t uint_least32_t;
typedef __uint_least64_t uint_least64_t;
typedef __int_fast8_t int_fast8_t;
typedef __int_fast16_t int_fast16_t;
typedef __int_fast32_t int_fast32_t;
typedef __int_fast64_t int_fast64_t;
typedef __uint_fast8_t uint_fast8_t;
typedef __uint_fast16_t uint_fast16_t;
typedef __uint_fast32_t uint_fast32_t;
typedef __uint_fast64_t uint_fast64_t;
#ifndef _INTMAX_T_DECLARED
typedef __intmax_t intmax_t;
#define _INTMAX_T_DECLARED
#endif
#ifndef _UINTMAX_T_DECLARED
typedef __uintmax_t uintmax_t;
#define _UINTMAX_T_DECLARED
#endif
/* GNU and Darwin define this and people seem to think it's portable */
#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX)
#define __WORDSIZE 64
#else
#define __WORDSIZE 32
#endif
#endif /* !_SYS_STDINT_H_ */

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/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Chris Torek.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)stdio.h 8.5 (Berkeley) 4/29/95
* $FreeBSD$
*/
/*
* Portions copyright (c) 2013-2014, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef _STDIO_H_
#define _STDIO_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef _SSIZE_T_DECLARED
#define _SSIZE_T_DECLARED
typedef __ssize_t ssize_t;
#endif
#define EOF (-1)
int printf(const char * __restrict, ...) __printflike(1, 2);
int putchar(int);
int puts(const char *);
int sprintf(char * __restrict, const char * __restrict, ...)
__printflike(2, 3);
int vsprintf(char * __restrict, const char * __restrict,
__va_list) __printflike(2, 0);
int sscanf(const char *__restrict, char const *__restrict, ...);
#if __ISO_C_VISIBLE >= 1999
int snprintf(char * __restrict, size_t, const char * __restrict,
...) __printflike(3, 4);
int vsnprintf(char * __restrict, size_t, const char * __restrict,
__va_list) __printflike(3, 0);
#endif
#endif /* !_STDIO_H_ */

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/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)string.h 8.1 (Berkeley) 6/2/93
* $FreeBSD$
*/
/*
* Portions copyright (c) 2013-2014, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef _STRING_H_
#define _STRING_H_
#include <sys/cdefs.h>
#include <sys/_null.h>
#include <sys/_types.h>
#ifndef _SIZE_T_DECLARED
typedef __size_t size_t;
#define _SIZE_T_DECLARED
#endif
__BEGIN_DECLS
void *memchr(const void *, int, size_t) __pure;
int memcmp(const void *, const void *, size_t) __pure;
void *memcpy(void * __restrict, const void * __restrict, size_t);
void *memmove(void *, const void *, size_t);
void *memset(void *, int, size_t);
char *strchr(const char *, int) __pure;
int strcmp(const char *, const char *) __pure;
size_t strlen(const char *) __pure;
int strncmp(const char *, const char *, size_t) __pure;
int strcasecmp(const char *, const char *);
__END_DECLS
#endif /* _STRING_H_ */

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/*-
* Copyright (c) 2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef NULL
#if !defined(__cplusplus)
#define NULL ((void *)0)
#else
#if __cplusplus >= 201103L
#define NULL nullptr
#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4
#define NULL __null
#else
#if defined(__LP64__)
#define NULL (0L)
#else
#define NULL 0
#endif /* __LP64__ */
#endif /* __GNUG__ */
#endif /* !__cplusplus */
#endif

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/*-
* Copyright (c) 2011 David E. O'Brien <obrien@FreeBSD.org>
* Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS__STDINT_H_
#define _SYS__STDINT_H_
#ifndef _INT8_T_DECLARED
typedef __int8_t int8_t;
#define _INT8_T_DECLARED
#endif
#ifndef _INT16_T_DECLARED
typedef __int16_t int16_t;
#define _INT16_T_DECLARED
#endif
#ifndef _INT32_T_DECLARED
typedef __int32_t int32_t;
#define _INT32_T_DECLARED
#endif
#ifndef _INT64_T_DECLARED
typedef __int64_t int64_t;
#define _INT64_T_DECLARED
#endif
#ifndef _UINT8_T_DECLARED
typedef __uint8_t uint8_t;
#define _UINT8_T_DECLARED
#endif
#ifndef _UINT16_T_DECLARED
typedef __uint16_t uint16_t;
#define _UINT16_T_DECLARED
#endif
#ifndef _UINT32_T_DECLARED
typedef __uint32_t uint32_t;
#define _UINT32_T_DECLARED
#endif
#ifndef _UINT64_T_DECLARED
typedef __uint64_t uint64_t;
#define _UINT64_T_DECLARED
#endif
#ifndef _INTPTR_T_DECLARED
typedef __intptr_t intptr_t;
#define _INTPTR_T_DECLARED
#endif
#ifndef _UINTPTR_T_DECLARED
typedef __uintptr_t uintptr_t;
#define _UINTPTR_T_DECLARED
#endif
#endif /* !_SYS__STDINT_H_ */

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/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SYS__TYPES_H_
#define _SYS__TYPES_H_
#include <sys/cdefs.h>
#include <machine/_types.h>
/*
* Standard type definitions.
*/
typedef __uint32_t __blksize_t; /* file block size */
typedef __int64_t __blkcnt_t; /* file block count */
typedef __int32_t __clockid_t; /* clock_gettime()... */
typedef __uint32_t __cap_rights_t; /* capability rights */
typedef __uint32_t __fflags_t; /* file flags */
typedef __uint32_t __fsblkcnt_t;
typedef __uint32_t __fsfilcnt_t;
typedef __uint32_t __gid_t;
typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */
typedef __uint32_t __ino_t; /* inode number */
typedef long __key_t; /* IPC key (for Sys V IPC) */
typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */
typedef __uint16_t __mode_t; /* permissions */
typedef int __accmode_t; /* access permissions */
typedef int __nl_item;
typedef __uint16_t __nlink_t; /* link count */
typedef __int32_t __off_t; /* file offset */
typedef __int32_t __pid_t; /* process [group] */
typedef __int32_t __rlim_t; /* resource limit - intentionally */
/* signed, because of legacy code */
/* that uses -1 for RLIM_INFINITY */
typedef __uint8_t __sa_family_t;
typedef __uint32_t __socklen_t;
typedef long __suseconds_t; /* microseconds (signed) */
typedef struct __timer *__timer_t; /* timer_gettime()... */
typedef struct __mq *__mqd_t; /* mq_open()... */
typedef __uint32_t __uid_t;
typedef unsigned int __useconds_t; /* microseconds (unsigned) */
typedef int __cpuwhich_t; /* which parameter for cpuset. */
typedef int __cpulevel_t; /* level parameter for cpuset. */
typedef int __cpusetid_t; /* cpuset identifier. */
/*
* Unusual type definitions.
*/
/*
* rune_t is declared to be an ``int'' instead of the more natural
* ``unsigned long'' or ``long''. Two things are happening here. It is not
* unsigned so that EOF (-1) can be naturally assigned to it and used. Also,
* it looks like 10646 will be a 31 bit standard. This means that if your
* ints cannot hold 32 bits, you will be in trouble. The reason an int was
* chosen over a long is that the is*() and to*() routines take ints (says
* ANSI C), but they use __ct_rune_t instead of int.
*
* NOTE: rune_t is not covered by ANSI nor other standards, and should not
* be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and
* rune_t must be the same type. Also, wint_t must be no narrower than
* wchar_t, and should be able to hold all members of the largest
* character set plus one extra value (WEOF), and must be at least 16 bits.
*/
typedef int __ct_rune_t; /* arg type for ctype funcs */
typedef __ct_rune_t __rune_t; /* rune_t (see above) */
typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */
typedef __ct_rune_t __wint_t; /* wint_t (see above) */
typedef __uint32_t __dev_t; /* device number */
typedef __uint32_t __fixpt_t; /* fixed point number */
/*
* mbstate_t is an opaque object to keep conversion state during multibyte
* stream conversions.
*/
typedef union {
char __mbstate8[128];
__int64_t _mbstateL; /* for alignment */
} __mbstate_t;
#endif /* !_SYS__TYPES_H_ */

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/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Berkeley Software Design, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)cdefs.h 8.8 (Berkeley) 1/9/95
* $FreeBSD$
*/
#ifndef _SYS_CDEFS_H_
#define _SYS_CDEFS_H_
#if defined(__cplusplus)
#define __BEGIN_DECLS extern "C" {
#define __END_DECLS }
#else
#define __BEGIN_DECLS
#define __END_DECLS
#endif
/*
* This code has been put in place to help reduce the addition of
* compiler specific defines in FreeBSD code. It helps to aid in
* having a compiler-agnostic source tree.
*/
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
#define __GNUCLIKE_ASM 3
#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS
#else
#define __GNUCLIKE_ASM 2
#endif
#define __GNUCLIKE___TYPEOF 1
#define __GNUCLIKE___OFFSETOF 1
#define __GNUCLIKE___SECTION 1
#ifndef __INTEL_COMPILER
# define __GNUCLIKE_CTOR_SECTION_HANDLING 1
#endif
#define __GNUCLIKE_BUILTIN_CONSTANT_P 1
# if defined(__INTEL_COMPILER) && defined(__cplusplus) \
&& __INTEL_COMPILER < 800
# undef __GNUCLIKE_BUILTIN_CONSTANT_P
# endif
#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER)
# define __GNUCLIKE_BUILTIN_VARARGS 1
# define __GNUCLIKE_BUILTIN_STDARG 1
# define __GNUCLIKE_BUILTIN_VAALIST 1
#endif
#if defined(__GNUC__)
# define __GNUC_VA_LIST_COMPATIBILITY 1
#endif
#ifndef __INTEL_COMPILER
# define __GNUCLIKE_BUILTIN_NEXT_ARG 1
# define __GNUCLIKE_MATH_BUILTIN_RELOPS
#endif
#define __GNUCLIKE_BUILTIN_MEMCPY 1
/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
#define __CC_SUPPORTS_INLINE 1
#define __CC_SUPPORTS___INLINE 1
#define __CC_SUPPORTS___INLINE__ 1
#define __CC_SUPPORTS___FUNC__ 1
#define __CC_SUPPORTS_WARNING 1
#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
#endif /* __GNUC__ || __INTEL_COMPILER */
/*
* Macro to test if we're using a specific version of gcc or later.
*/
#if defined(__GNUC__) && !defined(__INTEL_COMPILER)
#define __GNUC_PREREQ__(ma, mi) \
(__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi))
#else
#define __GNUC_PREREQ__(ma, mi) 0
#endif
/*
* The __CONCAT macro is used to concatenate parts of symbol names, e.g.
* with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
* The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
* mode -- there must be no spaces between its arguments, and for nested
* __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also
* concatenate double-quoted strings produced by the __STRING macro, but
* this only works with ANSI C.
*
* __XSTRING is like __STRING, but it expands any macros in its argument
* first. It is only available with ANSI C.
*/
#if defined(__STDC__) || defined(__cplusplus)
#define __P(protos) protos /* full-blown ANSI C */
#define __CONCAT1(x,y) x ## y
#define __CONCAT(x,y) __CONCAT1(x,y)
#define __STRING(x) #x /* stringify without expanding x */
#define __XSTRING(x) __STRING(x) /* expand x, then stringify */
#define __const const /* define reserved names to standard */
#define __signed signed
#define __volatile volatile
#if defined(__cplusplus)
#define __inline inline /* convert to C++ keyword */
#else
#if !(defined(__CC_SUPPORTS___INLINE))
#define __inline /* delete GCC keyword */
#endif /* ! __CC_SUPPORTS___INLINE */
#endif /* !__cplusplus */
#else /* !(__STDC__ || __cplusplus) */
#define __P(protos) () /* traditional C preprocessor */
#define __CONCAT(x,y) x/**/y
#define __STRING(x) "x"
#if !defined(__CC_SUPPORTS___INLINE)
#define __const /* delete pseudo-ANSI C keywords */
#define __inline
#define __signed
#define __volatile
/*
* In non-ANSI C environments, new programs will want ANSI-only C keywords
* deleted from the program and old programs will want them left alone.
* When using a compiler other than gcc, programs using the ANSI C keywords
* const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
* When using "gcc -traditional", we assume that this is the intent; if
* __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
*/
#ifndef NO_ANSI_KEYWORDS
#define const /* delete ANSI C keywords */
#define inline
#define signed
#define volatile
#endif /* !NO_ANSI_KEYWORDS */
#endif /* !__CC_SUPPORTS___INLINE */
#endif /* !(__STDC__ || __cplusplus) */
/*
* Compiler-dependent macros to help declare dead (non-returning) and
* pure (no side effects) functions, and unused variables. They are
* null except for versions of gcc that are known to support the features
* properly (old versions of gcc-2 supported the dead and pure features
* in a different (wrong) way). If we do not provide an implementation
* for a given compiler, let the compile fail if it is told to use
* a feature that we cannot live without.
*/
#ifdef lint
#define __dead2
#define __pure2
#define __unused
#define __packed
#define __aligned(x)
#define __section(x)
#else
#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
#define __dead2
#define __pure2
#define __unused
#endif
#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused
/* XXX Find out what to do for __packed, __aligned and __section */
#endif
#if __GNUC_PREREQ__(2, 7)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused __attribute__((__unused__))
#define __used __attribute__((__used__))
#define __packed __attribute__((__packed__))
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#endif
#if defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused __attribute__((__unused__))
#define __used __attribute__((__used__))
#define __packed __attribute__((__packed__))
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#endif
#endif
#if !__GNUC_PREREQ__(2, 95)
#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b)
#endif
/*
* Keywords added in C11.
*/
#if defined(__cplusplus) && __cplusplus >= 201103L
#define _Alignas(e) alignas(e)
#define _Alignof(e) alignof(e)
#define _Noreturn [[noreturn]]
#define _Static_assert(e, s) static_assert(e, s)
/* FIXME: change this to thread_local when clang in base supports it */
#define _Thread_local __thread
#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
/* Do nothing. They are language keywords. */
#else
/* Not supported. Implement them using our versions. */
#define _Alignas(x) __aligned(x)
#define _Alignof(x) __alignof(x)
#define _Noreturn __dead2
#define _Thread_local __thread
#ifdef __COUNTER__
#define _Static_assert(x, y) __Static_assert(x, __COUNTER__)
#define __Static_assert(x, y) ___Static_assert(x, y)
#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1]
#else
#define _Static_assert(x, y) struct __hack
#endif
#endif
/*
* Emulation of C11 _Generic(). Unlike the previously defined C11
* keywords, it is not possible to implement this using exactly the same
* syntax. Therefore implement something similar under the name
* __generic(). Unlike _Generic(), this macro can only distinguish
* between a single type, so it requires nested invocations to
* distinguish multiple cases.
*/
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
#define __generic(expr, t, yes, no) \
_Generic(expr, t: yes, default: no)
#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
#define __generic(expr, t, yes, no) \
__builtin_choose_expr( \
__builtin_types_compatible_p(__typeof(expr), t), yes, no)
#endif
#if __GNUC_PREREQ__(2, 96)
#define __malloc_like __attribute__((__malloc__))
#define __pure __attribute__((__pure__))
#else
#define __malloc_like
#define __pure
#endif
#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
#define __always_inline __attribute__((__always_inline__))
#else
#define __always_inline
#endif
#if __GNUC_PREREQ__(3, 1)
#define __noinline __attribute__ ((__noinline__))
#else
#define __noinline
#endif
#if __GNUC_PREREQ__(3, 3)
#define __nonnull(x) __attribute__((__nonnull__(x)))
#else
#define __nonnull(x)
#endif
#if __GNUC_PREREQ__(3, 4)
#define __fastcall __attribute__((__fastcall__))
#else
#define __fastcall
#endif
#if __GNUC_PREREQ__(4, 1)
#define __returns_twice __attribute__((__returns_twice__))
#else
#define __returns_twice
#endif
/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __func__ NULL
#endif
#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901
#define __LONG_LONG_SUPPORTED
#endif
/* C++11 exposes a load of C99 stuff */
#if defined(__cplusplus) && __cplusplus >= 201103L
#define __LONG_LONG_SUPPORTED
#ifndef __STDC_LIMIT_MACROS
#define __STDC_LIMIT_MACROS
#endif
#ifndef __STDC_CONSTANT_MACROS
#define __STDC_CONSTANT_MACROS
#endif
#endif
/*
* GCC 2.95 provides `__restrict' as an extension to C90 to support the
* C99-specific `restrict' type qualifier. We happen to use `__restrict' as
* a way to define the `restrict' type qualifier without disturbing older
* software that is unaware of C99 keywords.
*/
#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint)
#define __restrict
#else
#define __restrict restrict
#endif
#endif
/*
* GNU C version 2.96 adds explicit branch prediction so that
* the CPU back-end can hint the processor and also so that
* code blocks can be reordered such that the predicted path
* sees a more linear flow, thus improving cache behavior, etc.
*
* The following two macros provide us with a way to utilize this
* compiler feature. Use __predict_true() if you expect the expression
* to evaluate to true, and __predict_false() if you expect the
* expression to evaluate to false.
*
* A few notes about usage:
*
* * Generally, __predict_false() error condition checks (unless
* you have some _strong_ reason to do otherwise, in which case
* document it), and/or __predict_true() `no-error' condition
* checks, assuming you want to optimize for the no-error case.
*
* * Other than that, if you don't know the likelihood of a test
* succeeding from empirical or other `hard' evidence, don't
* make predictions.
*
* * These are meant to be used in places that are run `a lot'.
* It is wasteful to make predictions in code that is run
* seldomly (e.g. at subsystem initialization time) as the
* basic block reordering that this affects can often generate
* larger code.
*/
#if __GNUC_PREREQ__(2, 96)
#define __predict_true(exp) __builtin_expect((exp), 1)
#define __predict_false(exp) __builtin_expect((exp), 0)
#else
#define __predict_true(exp) (exp)
#define __predict_false(exp) (exp)
#endif
#if __GNUC_PREREQ__(4, 2)
#define __hidden __attribute__((__visibility__("hidden")))
#define __exported __attribute__((__visibility__("default")))
#else
#define __hidden
#define __exported
#endif
/*
* We define this here since <stddef.h>, <sys/queue.h>, and <sys/types.h>
* require it.
*/
#if __GNUC_PREREQ__(4, 1)
#define __offsetof(type, field) __builtin_offsetof(type, field)
#else
#ifndef __cplusplus
#define __offsetof(type, field) \
((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field))
#else
#define __offsetof(type, field) \
(__offsetof__ (reinterpret_cast <__size_t> \
(&reinterpret_cast <const volatile char &> \
(static_cast<type *> (0)->field))))
#endif
#endif
#define __rangeof(type, start, end) \
(__offsetof(type, end) - __offsetof(type, start))
/*
* Given the pointer x to the member m of the struct s, return
* a pointer to the containing structure. When using GCC, we first
* assign pointer x to a local variable, to check that its type is
* compatible with member m.
*/
#if __GNUC_PREREQ__(3, 1)
#define __containerof(x, s, m) ({ \
const volatile __typeof(((s *)0)->m) *__x = (x); \
__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
})
#else
#define __containerof(x, s, m) \
__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
#endif
/*
* Compiler-dependent macros to declare that functions take printf-like
* or scanf-like arguments. They are null except for versions of gcc
* that are known to support the features properly (old versions of gcc-2
* didn't permit keeping the keywords out of the application namespace).
*/
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __printflike(fmtarg, firstvararg)
#define __scanflike(fmtarg, firstvararg)
#define __format_arg(fmtarg)
#define __strfmonlike(fmtarg, firstvararg)
#define __strftimelike(fmtarg, firstvararg)
#else
#define __printflike(fmtarg, firstvararg) \
__attribute__((__format__ (__printf__, fmtarg, firstvararg)))
#define __scanflike(fmtarg, firstvararg) \
__attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))
#define __strfmonlike(fmtarg, firstvararg) \
__attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
#define __strftimelike(fmtarg, firstvararg) \
__attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
#endif
/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER)
#define __printf0like(fmtarg, firstvararg) \
__attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
#else
#define __printf0like(fmtarg, firstvararg)
#endif
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#ifndef __INTEL_COMPILER
#define __strong_reference(sym,aliassym) \
extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
#endif
#ifdef __STDC__
#define __weak_reference(sym,alias) \
__asm__(".weak " #alias); \
__asm__(".equ " #alias ", " #sym)
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning." #sym); \
__asm__(".asciz \"" msg "\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@" #verid)
#define __sym_default(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@@" #verid)
#else
#define __weak_reference(sym,alias) \
__asm__(".weak alias"); \
__asm__(".equ alias, sym")
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning.sym"); \
__asm__(".asciz \"msg\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver impl, sym@verid")
#define __sym_default(impl,sym,verid) \
__asm__(".symver impl, sym@@verid")
#endif /* __STDC__ */
#endif /* __GNUC__ || __INTEL_COMPILER */
#define __GLOBL1(sym) __asm__(".globl " #sym)
#define __GLOBL(sym) __GLOBL1(sym)
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"")
#else
/*
* The following definition might not work well if used in header files,
* but it should be better than nothing. If you want a "do nothing"
* version, then it should generate some harmless declaration, such as:
* #define __IDSTRING(name,string) struct __hack
*/
#define __IDSTRING(name,string) static const char name[] __unused = string
#endif
/*
* Embed the rcs id of a source file in the resulting library. Note that in
* more recent ELF binutils, we use .ident allowing the ID to be stripped.
* Usage:
* __FBSDID("$FreeBSD$");
*/
#ifndef __FBSDID
#if !defined(lint) && !defined(STRIP_FBSDID)
#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s)
#else
#define __FBSDID(s) struct __hack
#endif
#endif
#ifndef __RCSID
#ifndef NO__RCSID
#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s)
#else
#define __RCSID(s) struct __hack
#endif
#endif
#ifndef __RCSID_SOURCE
#ifndef NO__RCSID_SOURCE
#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s)
#else
#define __RCSID_SOURCE(s) struct __hack
#endif
#endif
#ifndef __SCCSID
#ifndef NO__SCCSID
#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s)
#else
#define __SCCSID(s) struct __hack
#endif
#endif
#ifndef __COPYRIGHT
#ifndef NO__COPYRIGHT
#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s)
#else
#define __COPYRIGHT(s) struct __hack
#endif
#endif
#ifndef __DECONST
#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var))
#endif
#ifndef __DEVOLATILE
#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var))
#endif
#ifndef __DEQUALIFY
#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var))
#endif
/*-
* The following definitions are an extension of the behavior originally
* implemented in <sys/_posix.h>, but with a different level of granularity.
* POSIX.1 requires that the macros we test be defined before any standard
* header file is included.
*
* Here's a quick run-down of the versions:
* defined(_POSIX_SOURCE) 1003.1-1988
* _POSIX_C_SOURCE == 1 1003.1-1990
* _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option
* _POSIX_C_SOURCE == 199309 1003.1b-1993
* _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995,
* and the omnibus ISO/IEC 9945-1: 1996
* _POSIX_C_SOURCE == 200112 1003.1-2001
* _POSIX_C_SOURCE == 200809 1003.1-2008
*
* In addition, the X/Open Portability Guide, which is now the Single UNIX
* Specification, defines a feature-test macro which indicates the version of
* that specification, and which subsumes _POSIX_C_SOURCE.
*
* Our macros begin with two underscores to avoid namespace screwage.
*/
/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */
#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1
#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */
#define _POSIX_C_SOURCE 199009
#endif
/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */
#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 199209
#endif
/* Deal with various X/Open Portability Guides and Single UNIX Spec. */
#ifdef _XOPEN_SOURCE
#if _XOPEN_SOURCE - 0 >= 700
#define __XSI_VISIBLE 700
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200809
#elif _XOPEN_SOURCE - 0 >= 600
#define __XSI_VISIBLE 600
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200112
#elif _XOPEN_SOURCE - 0 >= 500
#define __XSI_VISIBLE 500
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 199506
#endif
#endif
/*
* Deal with all versions of POSIX. The ordering relative to the tests above is
* important.
*/
#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE)
#define _POSIX_C_SOURCE 198808
#endif
#ifdef _POSIX_C_SOURCE
#if _POSIX_C_SOURCE >= 200809
#define __POSIX_VISIBLE 200809
#define __ISO_C_VISIBLE 1999
#elif _POSIX_C_SOURCE >= 200112
#define __POSIX_VISIBLE 200112
#define __ISO_C_VISIBLE 1999
#elif _POSIX_C_SOURCE >= 199506
#define __POSIX_VISIBLE 199506
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199309
#define __POSIX_VISIBLE 199309
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199209
#define __POSIX_VISIBLE 199209
#define __ISO_C_VISIBLE 1990
#elif _POSIX_C_SOURCE >= 199009
#define __POSIX_VISIBLE 199009
#define __ISO_C_VISIBLE 1990
#else
#define __POSIX_VISIBLE 198808
#define __ISO_C_VISIBLE 0
#endif /* _POSIX_C_SOURCE */
#else
/*-
* Deal with _ANSI_SOURCE:
* If it is defined, and no other compilation environment is explicitly
* requested, then define our internal feature-test macros to zero. This
* makes no difference to the preprocessor (undefined symbols in preprocessing
* expressions are defined to have value zero), but makes it more convenient for
* a test program to print out the values.
*
* If a program mistakenly defines _ANSI_SOURCE and some other macro such as
* _POSIX_C_SOURCE, we will assume that it wants the broader compilation
* environment (and in fact we will never get here).
*/
#if defined(_ANSI_SOURCE) /* Hide almost everything. */
#define __POSIX_VISIBLE 0
#define __XSI_VISIBLE 0
#define __BSD_VISIBLE 0
#define __ISO_C_VISIBLE 1990
#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */
#define __POSIX_VISIBLE 0
#define __XSI_VISIBLE 0
#define __BSD_VISIBLE 0
#define __ISO_C_VISIBLE 1999
#else /* Default environment: show everything. */
#define __POSIX_VISIBLE 200809
#define __XSI_VISIBLE 700
#define __BSD_VISIBLE 1
#define __ISO_C_VISIBLE 1999
#endif
#endif
#ifndef __has_feature
#define __has_feature(x) 0
#endif
#ifndef __has_include
#define __has_include(x) 0
#endif
#ifndef __has_builtin
#define __has_builtin(x) 0
#endif
#if defined(__mips) || defined(__powerpc64__) || defined(__arm__)
#define __NO_TLS 1
#endif
#endif /* !_SYS_CDEFS_H_ */

65
IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.ld.S Normal file
View File

@@ -0,0 +1,65 @@
/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Vector)
MEMORY {
RAM (rwxa): ORIGIN = 0xEB200000, LENGTH = 0x000C0000
}
SECTIONS
{
. = 0xEB200000;
ASSERT(. == ALIGN(4096),
"CR7 dummy rtos address is not aligned on a page boundary.")
ro . : {
__RO_START__ = .;
*rtos.o(.text*)
*rtos_main.o(.text*)
. = NEXT(32768);
*(.text*)
*(.rodata*)
__RO_END_UNALIGNED__ = .;
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(4096);
. = NEXT(16384);
__RO_END__ = .;
} >RAM
.data . : {
__DATA_START__ = .;
*(.data*)
__DATA_END__ = .;
} >RAM
stacks (NOLOAD) : ALIGN(16) {
__STACKS_START__ = .;
KEEP(*(tzfw_normal_stacks))
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address must be 16-byte aligned.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
__BSS_SIZE__ = SIZEOF(.bss);
ASSERT(. <= 0xEB2FE800, "CR7 dummy rtos has exceeded its limit.")
}

224
IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#define DRAM_BASE (0x40000000)
#define SYSRAM_BASE (0xE6300000)
#define DTCM_BASE (0xEB020000)
#define STACK_BASE_ABT (DTCM_BASE | 0x7080)
#define STACK_BASE_UND (DTCM_BASE | 0x7100)
#define STACK_BASE_FIQ (DTCM_BASE | 0x7180)
#define STACK_BASE_IRQ (DTCM_BASE | 0x7200)
#define STACK_BASE_SVC (DTCM_BASE | 0x8000)
.global Vector
.global Start
.local rtos_stacks
/*****************************************************************************
* Vector table
*****************************************************************************/
.align 5
Vector:
b Start /* Reset */
b Undef /* Undefined Instruction */
b SWI /* Supervisor Call */
b PAbort /* Prefetch Abort */
b DAbort /* Data Abort */
nop /* Not used */
b IRQ /* IRQ interrupt */
b FIQ /* FIQ interrupt */
/*****************************************************************************
* Reset Hander
*****************************************************************************/
Start:
/* initialize registers*/
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11, #0
mov r12, #0
mov lr, #0
/* CR7_CONFIGURE_MPU */
;# region 0: all memory with r/w access for everyone
MOV r0,#0
MCR p15,0,r0,c6,c2,0 ;# region number
MOV r0,#0x0 ;# base address
MCR p15,0,r0,c6,c1,0 ;# D-side base addr
MCR p15,0,r0,c6,c1,1 ;# I-side base addr
MOV r0,#0x3E|0x1 ;# 4GB, all memory
MCR p15,0,r0,c6,c1,2 ;# D-side size & enable
MCR p15,0,r0,c6,c1,3 ;# I-side size & enable
LDR r0,=(0x300|0x00B|0x004) ;# 0x00B
MCR p15,0,r0,c6,c1,4 ;# D-side access control
MCR p15,0,r0,c6,c1,5 ;# I-side access control
;# region 1: Peripheral (0xE0000000~0xFFFFFFFF)
MOV r0,#1
MCR p15,0,r0,c6,c2,0 ;# region number
MOV r0,#0xE0000000 ;# base address
MCR p15,0,r0,c6,c1,0 ;# D-side base addr
MCR p15,0,r0,c6,c1,1 ;# I-side base addr
MOV r0,#0x38 | 0x1 ;# 512MB, all memory
MCR p15,0,r0,c6,c1,2 ;# D-side size & enable
MCR p15,0,r0,c6,c1,3 ;# I-side size & enable
LDR r0,=0x300|0x001|0x004 ;# 0x001
MCR p15,0,r0,c6,c1,4 ;# D-side access control
MCR p15,0,r0,c6,c1,5 ;# I-side access control
;# region 2: SecureRAM (0xEB200000)
MOV r0,#2
MCR p15,0,r0,c6,c2,0 ;# region number
;# LDR r0, =0xE6300000 ;# base address
LDR r0, =0xEB200000 ;# base address
MCR p15,0,r0,c6,c1,0 ;# D-side base addr
MCR p15,0,r0,c6,c1,1 ;# I-side base addr
;# MOV r0,#REGION_SIZE_512KB | 0x1 ; 512KB, all memory
MOV r0,#0x26 | 0x1 ;# 1MB, all memory
MCR p15,0,r0,c6,c1,2 ;# D-side size & enable
MCR p15,0,r0,c6,c1,3 ;# I-side size & enable
LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B
MCR p15,0,r0,c6,c1,4 ;# D-side access control
MCR p15,0,r0,c6,c1,5 ;# I-side access control
;# region 3: TCM (0xEB000000)
MOV r0,#3
MCR p15,0,r0,c6,c2,0 ;# region number
LDR r0, =0xEB000000 ;# base address
MCR p15,0,r0,c6,c1,0 ;# D-side base addr
MCR p15,0,r0,c6,c1,1 ;# I-side base addr
MOV r0,#0x1E | 0x1 ;# 64KB, all memory
MCR p15,0,r0,c6,c1,2 ;# D-side size & enable
MCR p15,0,r0,c6,c1,3 ;# I-side size & enable
LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B
MCR p15,0,r0,c6,c1,4 ;# D-side access control
MCR p15,0,r0,c6,c1,5 ;# I-side access control
;# region 4: SecureROM (0xEB100000)
MOV r0,#4
MCR p15,0,r0,c6,c2,0 ;# region number
LDR r0, =0xEB100000 ;# base address
MCR p15,0,r0,c6,c1,0 ;# D-side base addr
MCR p15,0,r0,c6,c1,1 ;# I-side base addr
MOV r0,#0x22 | 0x1 ;# 256KB, all memory
MCR p15,0,r0,c6,c1,2 ;# D-side size & enable
MCR p15,0,r0,c6,c1,3 ;# I-side size & enable
LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B
MCR p15,0,r0,c6,c1,4 ;# D-side access control
MCR p15,0,r0,c6,c1,5 ;# I-side access control
;#CR7_SET_MPU_ON
MRC p15, 0, r0, c1, c0, 0
ORR r0, r0, #0x00000001
DSB
MCR p15, 0, r0, c1, c0, 0
ISB
LDR PC, =STACK_INIT
STACK_INIT:
/* stack initialize */
ldr r0, =__STACKS_END__
msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */
mov sp, r0 /* STACK_BASE_ABT */
msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */
sub r0, r0, #0x80 /* STACK_BASE_UND */
mov sp, r0
msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */
sub r0, r0, #0x80 /* STACK_BASE_FIQ */
mov sp, r0
msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */
sub r0, r0, #0x80 /* STACK_BASE_IRQ */
mov sp, r0
msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */
sub r0, r0, #0x80 /* STACK_BASE_SVC */
mov sp, r0
/* Loader Main */
BL rtos_main
NO_BOOT:
nop
1:
wfe
b 1b
/*****************************************************************************
* Exception Handers
*****************************************************************************/
/* Undefined Instruction */
Undef:
nop
1:
wfe
b 1b
/* Supervisor Call */
SWI:
nop
1:
wfe
b 1b
/* Prefetch Abort */
PAbort:
nop
1:
wfe
b 1b
/* Data Abort */
DAbort:
nop
1:
wfe
b 1b
/* IRQ interrupt */
IRQ:
nop
1:
wfe
b 1b
/* FIQ interrupt */
FIQ:
nop
1:
wfe
b 1b
/*****************************************************************************
* Define stack
*****************************************************************************/
.section tzfw_normal_stacks, "aw"
.align 6
rtos_stacks:
.space 4 * 1024
.end

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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
#include <stdint.h>
#include "scif.h"
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
/************************************************************************************************/
/* Unions */
/************************************************************************************************/
/************************************************************************************************/
/* Structs */
/************************************************************************************************/
/************************************************************************************************/
/* Globals */
/************************************************************************************************/
/************************************************************************************************/
/* Macros */
/************************************************************************************************/
#define MIDR_PN_SHIFT (0x4U)
#define MIDR_PN_MASK (0X0FFFU)
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
#define MIDR_CR7 (0x0C17U << MIDR_PN_SHIFT)
#define RCAR_PRR (0xFFF00044U) /* Product register */
#define RCAR_PRODUCT_MASK (0x00007F00U)
#define RCAR_CUT_MASK (0x000000FFU)
#define RCAR_PRODUCT_H3 (0x00004F00U)
#define RCAR_PRODUCT_M3 (0x00005200U)
#define RCAR_CUT_ES10 (0x00000000U)
#define RCAR_CUT_ES11 (0x00000001U)
#define RCAR_MAJOR_MASK (0x000000F0U)
#define RCAR_MINOR_MASK (0x0000000FU)
#define RCAR_PRODUCT_SHIFT (8U)
#define RCAR_MAJOR_SHIFT (4U)
#define RCAR_MINOR_SHIFT (0U)
#define RCAR_MAJOR_OFFSET (1U)
/************************************************************************************************/
/* Prototypes */
/************************************************************************************************/
uint32_t rtos_main(void);
uint32_t rtos_main(void)
{
volatile uint32_t i;
for (i = 0; i < 0x00300000U; i++) {
};
PutStr(" ",1);
PutStr("Dummy RTOS Program",1);
PutStr("Dummy RTOS Program boot end",1);
return 0U;
}

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build_message.c

318
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/Makefile Normal file
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# ******************************************************************************
# * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
# *
# * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
# *
# * This software is provided as reference/sample code under the license
# * agreement between Renesas Electronics Corporation and licensee (the
# * "License Agreement") and shall be treated as specified in the License
# * Agreement.
# * These instructions, statements, and software are the confidential
# * information of Renesas Electronics Corporation. They must be used and
# * modified solely for the purpose for which it was furnished by Renesas
# * Electronics Corporation. All or part of these instructions, statements and
# * software must not be reproduced nor disclosed to any third party in any
# * form, unless permitted by the License Agreement.
# *
# * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
# * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
# * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
# * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
# * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# * DAMAGE.
# ******************************************************************************
# ******************************************************************************
# * DESCRIPTION : makefile for Loader
# ******************************************************************************
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude
OUTDIR := build
#output file name
FILE_NAME = icumxa_loader
FILE_NAME_SA0 = bootparam_sa0
FILE_NAME_SA6 = cert_header_sa6
OUTPUT_FILE = $(FILE_NAME).elf
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf
#object file name
OBJ_FILE = common/mem_io/mem_io.o \
common/log/log.o \
common/log/scif.o \
common/timer/micro_wait.o \
image_load/image_load.o \
ip/axi-bus_edcint/edcinten.o \
ip/ip_control.o \
ip/cpg/cpg.o \
ip/pfc/pfc.o \
ip/qos/qos.o \
ip/dma/dma.o \
ip/rpc/rpc.o \
ip/mfis/mfis.o \
ip/wdt/wdt.o \
protect/acc_prot.o \
protect/lifec/acc_prot_lifec.o \
protect/memory/acc_prot_memory.o\
loader/loader_main.o \
loader/loader.o \
loader/cpu_on.o \
remap/remap.o \
rom_api/rom_api.o
OBJ_FILE_SA0 = tools/dummy_create/sa0.o
OBJ_FILE_SA6 = tools/dummy_create/sa6.o
#linker script name
MEMORY_DEF = loader/icumxa_loader.ld
MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld
MEMORY_DEF_SA6 = tools/dummy_create/sa6.ld
###################################################
# Debug build
DEBUG:=0
# Process DEBUG flag
$(eval $(call assert_boolean,DEBUG))
$(eval $(call add_define,DEBUG))
ifeq (${DEBUG},0)
$(eval $(call add_define,NDEBUG))
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Ogeneral
else
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Odebug
endif
# Process RCAR_SECURE_BOOT flag
ifndef RCAR_SECURE_BOOT
RCAR_SECURE_BOOT := 1
endif
$(eval $(call add_define,RCAR_SECURE_BOOT))
# Process LOG_LEVEL
ifndef LOG_LEVEL
LOG_LEVEL := 2
endif
$(eval $(call add_define,LOG_LEVEL))
# Process ACC_PROT_ENABLE flag
ifndef ACC_PROT_ENABLE
ACC_PROT_ENABLE := 1
endif
$(eval $(call add_define,ACC_PROT_ENABLE))
# Process RCAR_DRAM_SPLIT flag
ifndef RCAR_DRAM_SPLIT
RCAR_DRAM_SPLIT := 0
endif
$(eval $(call add_define,RCAR_DRAM_SPLIT))
# Process RCAR_DRAM_LPDDR4_MEMCONF flag
ifndef RCAR_DRAM_LPDDR4_MEMCONF
RCAR_DRAM_LPDDR4_MEMCONF :=1
endif
$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
# Process RCAR_DRAM_CHANNEL flag
ifndef RCAR_DRAM_CHANNEL
RCAR_DRAM_CHANNEL :=1
endif
$(eval $(call add_define,RCAR_DRAM_CHANNEL))
# Process RCAR_REWT_TRAINING flag
ifndef RCAR_REWT_TRAINING
RCAR_REWT_TRAINING := 1
endif
$(eval $(call add_define,RCAR_REWT_TRAINING))
# Process RCAR_DDR_REG_CHECK flag
ifndef RCAR_DDR_REG_CHECK
RCAR_DDR_REG_CHECK :=0
endif
$(eval $(call add_define,RCAR_DDR_REG_CHECK))
###################################################
# pass SecureMonitor parametor
###################################################
# Process CA53_PROG1_SMONI flag
ifndef CA53_PROG1_IS_SMONI
CA53_PROG1_IS_SMONI := 1
endif
$(eval $(call add_define,CA53_PROG1_IS_SMONI))
ifeq (${CA53_PROG1_IS_SMONI},1)
# STag_Smoni_EntrypointInfo parametor
ifndef CA53_PROG2_ATTR
CA53_PROG2_ATTR := 0x00000001
endif
ifndef CA53_PROG2_PC
CA53_PROG2_PC := 0x0000000050000000
endif
ifndef CA53_PROG2_SPSR
CA53_PROG2_SPSR := 0x00000000000003C5
endif
ifndef CA53_PROG2_ARG0
CA53_PROG2_ARG0 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG1
CA53_PROG2_ARG1 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG2
CA53_PROG2_ARG2 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG3
CA53_PROG2_ARG3 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG4
CA53_PROG2_ARG4 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG5
CA53_PROG2_ARG5 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG6
CA53_PROG2_ARG6 := 0x0000000000000000
endif
ifndef CA53_PROG2_ARG7
CA53_PROG2_ARG7 := 0x0000000000000000
endif
$(eval $(call add_define,SMONI_ATTR))
$(eval $(call add_define,CA53_PROG2_ATTR))
$(eval $(call add_define,CA53_PROG2_PC))
$(eval $(call add_define,CA53_PROG2_SPSR))
$(eval $(call add_define,CA53_PROG2_ARG0))
$(eval $(call add_define,CA53_PROG2_ARG1))
$(eval $(call add_define,CA53_PROG2_ARG2))
$(eval $(call add_define,CA53_PROG2_ARG3))
$(eval $(call add_define,CA53_PROG2_ARG4))
$(eval $(call add_define,CA53_PROG2_ARG5))
$(eval $(call add_define,CA53_PROG2_ARG6))
$(eval $(call add_define,CA53_PROG2_ARG7))
endif
include ip/ddr/ddr.mk
###################################################
OUTDIR_REL := $(OUTDIR)/release
OUTDIR_OBJ := $(OUTDIR)/obj
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA6 := $(OBJ_FILE_SA6:%.o=$(OUTDIR_OBJ)/%.o)
CC = cxrh850
AS = cxrh850
LD = cxrh850
OC = gsrec
OD = gdump
ASFLAGS += -asm="-preprocess_assembly_files" \
-asm="-nostartfiles" \
-D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -nostartfiles \
-c99 \
$(INCLUDE_DIR) $(DEFINES)
#-nostdlib
LDFLAGS = -nostartfiles
#LDFLAGS += -llib8bit_s32.a -llib8bit_u16.a
#LDFLAGS += -v -llibansi.a -llibarch.a -llibstartup.a
#-nostdlib
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c
@$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
@$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
-T $(MEMORY_DEF) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
$(LDFLAGS) \
-map=$(OUTDIR_REL)/$(FILE_NAME).map
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
@$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
@$(LD) $(OBJ_FILE_SA0) \
-T $(MEMORY_DEF_SA0) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin)
$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
@$(LD) $(OBJ_FILE_SA6) \
-T $(MEMORY_DEF_SA6) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA6).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) > $(OUTDIR_REL)/$(FILE_NAME_SA6).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA6:%.elf=%.bin)
###################################################
# Compile
###################################################
$(OUTDIR_OBJ)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(CC) $(CFLAGS) -o $@ -c $<
$(OUTDIR_OBJ)/%.o:%.S
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(AS) $(ASFLAGS) -o $@ -c $<
.PHONY: clean
clean:
@rm -rf $(OUTDIR)

84
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/log.c Normal file
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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver
******************************************************************************/
/******************************************************************************
* @file log.c
* - Version : 0.01
* @brief Log driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.07.2020 0.01 First Release
*****************************************************************************/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <log.h>
#include <scif.h>
#define VSPRINTF_OK (0)
void local_printf(const char *fmt, ...)
{
va_list ap;
static char s_buffer[1024];
int32_t num;
uint32_t loop;
/* Convert all arguments to one string */
va_start(ap, fmt);
num = vsprintf(s_buffer, fmt, ap);
va_end(ap);
/* String output */
if (VSPRINTF_OK <= num)
{
for (loop = 0U; loop < num; loop++)
{
(void)console_putc((uint8_t)s_buffer[loop]);
/* If the outputted character is LF, output CR */
if (s_buffer[loop] == '\n')
{
(void)console_putc((uint8_t)'\r');
}
}
}
else
{
while(1)
{
/* loop due to error detection. */
}
}
}
/* End of function local_printf(const char *fmt, ...) */

191
IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/scif.c Normal file
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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver
******************************************************************************/
/******************************************************************************
* @file scif.c
* - Version : 0.01
* @brief 1. Initial setting of SCIF.
* 2. Log output function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.07.2020 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <cpg.h>
#include <cpg_register.h>
#include <pfc.h>
#include <pfc_register.h>
#include <scif_register.h>
#include <rcar_def.h>
#include <scif.h>
#include <mem_io.h>
#include <micro_wait.h>
/* Define */
#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U)
#define SCIF_SCSCR_CKE_MASK (uint16_t)((uint16_t)3U << 0U)
#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN)
#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U)
#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U)
#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U)
#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN)
#define SCIF_SCFCR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCSMR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U)
#define SCIF_SCBRR_INIT_DATA (SCIF_SCBRR_115200BPS)
#define SCIF_SCBRR_HW_INIT (uint8_t)(0xFFU)
#define CPG_MSTPSR2_SCIF0 (((uint32_t)1U) << 7U)
#define CPG_MSTPSR2_SCIF0_ENABLE (((uint32_t)0U) << 7U)
#define GPSR4_SDA2 ((uint32_t)1U << 5U)
#define GPSR4_SCL2 ((uint32_t)1U << 4U)
#define IPSR_24 ((uint32_t)4U << 24U)
#define IPSR_20 ((uint32_t)4U << 20U)
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00000030U) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR4_SDA2 | GPSR4_SCL2) /* SCIF0/HSCIF0_B RX/TX */
#define PFC_IPSR_SCIF_MASK (uint32_t)(0x0FF00000U) /* SCIF0 RX/TX */
#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_24 | IPSR_20) /* SCIF0 RX/TX */
static void scif0_module_start(void);
static void scif0_pfc_init(void);
static void scif0_console_init(void);
static void scif0_module_start(void)
{
uint32_t reg;
reg = mem_read32(CPG_MSTPSR2);
/* If supply of clock to SCIF0 is stopped */
if ((CPG_MSTPSR2_SCIF0 & reg) != CPG_MSTPSR2_SCIF0_ENABLE) {
/* Supply of clock to SCIF0 is start */
mem_write32((uintptr_t)CPG_CPGWPR, CPG_MSTPSR2_SCIF0); /* write protect */
cpg_reg_write(CPG_SCMSTPCR2, CPG_MSTPSR2, ~(CPG_MSTPSR2_SCIF0));
}
}
/* End of function scif0_module_start(void) */
static void scif0_pfc_init(void)
{
uint32_t reg;
/* Set RX / TX of SCIF 0. */
reg = mem_read32(PFC_IPSR7);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_SCIF_VAL;
pfc_reg_write(PFC_IPSR7, reg);
reg = mem_read32(PFC_GPSR4);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR4, reg);
}
/* End of function scif0_pfc_init(void) */
static void scif0_console_init(void)
{
volatile uint16_t reg;
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
mem_write16(SCIF_SCFCR, SCIF_SCFCR_RESET_FIFO);
/* clear ORER bit */
mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
mem_write16(SCIF_SCSMR, SCIF_SCSMR_INIT_DATA);
/* Pclk(66MHz)/1, 115.2kBps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
mem_write16(SCIF_SCBRR, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
mem_write16(SCIF_SCFCR, SCIF_SCFCR_INIT_DATA);
/* enable TE, RE; SC_CLK=no output */
mem_write16(SCIF_SCSCR, SCIF_SCSCR_INIT_DATA);
}
/* End of function scif0_console_init(void) */
void scif_init(void)
{
scif0_module_start();
scif0_pfc_init();
scif0_console_init();
}
/* End of function scif_init(void) */
void scif_release(void)
{
/* set HW initial value */
mem_write16(SCIF_SCFCR, SCIF_SCFCR_INIT_DATA);
mem_write16(SCIF_SCBRR, SCIF_SCBRR_HW_INIT);
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
}
/* End of function scif_release(void) */
void console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR, reg);
}
/* End of function console_putc(uint8_t outchar) */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : memory access driver
******************************************************************************/
/******************************************************************************
* @file mem_io.c
* - Version : 0.01
* @brief Memory access driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.07.2020 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <mem_io.h>
void mem_write8(uintptr_t addr, uint8_t data)
{
*(volatile uint8_t*)addr = data;
}
/* End of function mem_write8(uintptr_t addr, uint8_t data) */
uint8_t mem_read8(uintptr_t addr)
{
return (*(volatile uint8_t*)addr);
}
/* End of function mem_read8(uintptr_t addr) */
void mem_write16(uintptr_t addr, uint16_t data)
{
*(volatile uint16_t*)addr = data;
}
/* End of function mem_write16(uintptr_t addr, uint16_t data) */
uint16_t mem_read16(uintptr_t addr)
{
return (*(volatile uint16_t*)addr);
}
/* End of function mem_read16(uintptr_t addr) */
void mem_write32(uintptr_t addr, uint32_t data)
{
*(volatile uint32_t*)addr = data;
}
/* End of function mem_write32(uintptr_t addr, uint32_t data) */
uint32_t mem_read32(uintptr_t addr)
{
return (*(volatile uint32_t*)addr);
}
/* End of function mem_read32(uintptr_t addr) */
void mem_write64(uintptr_t addr, uint64_t data)
{
*(volatile uint64_t*)addr = data;
}
/* End of function mem_write64(uintptr_t addr, uint64_t data) */
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
}
/* End of function mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver
******************************************************************************/
/******************************************************************************
* @file micro_wait.c
* - Version : 0.01
* @brief Wait of micro second
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.07.2020 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
#include <mem_io.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (0xFFFEEA14U)
#define INTCR_RF (uint16_t)((uint16_t)1U << 12U)
#define INTCR_RF_NO_REQ (uint16_t)((uint16_t)0U << 12U)
#define OSTM0_BASE (0xFFFEE000U)
#define OSTM0CMP (OSTM0_BASE)
#define OSTM0CNT (OSTM0_BASE + 0x0004U)
#define OSTM0TE (OSTM0_BASE + 0x0010U)
#define OSTM0TS (OSTM0_BASE + 0x0014U)
#define OSTM0TT (OSTM0_BASE + 0x0018U)
#define OSTM0CTL (OSTM0_BASE + 0x0020U)
#define OSTM0EMU (OSTM0_BASE + 0x0024U)
#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */
#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */
#define OSTM0TE_TE (uint8_t)(0x01U) /* b0:1: Counter enabled */
#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */
void micro_wait(uint32_t count_us)
{
uint32_t val;
uint16_t reg;
if (count_us != 0U)
{
/* When the timer count is an argument that exceeds 0xFFFFFFFF */
if(MAX_MICRO_WAIT < count_us)
{
count_us = MAX_MICRO_WAIT;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
/* timer start */
mem_write8(OSTM0TT, OSTM0TT_TT);
mem_write32(OSTM0CMP, val);
mem_write8(OSTM0CTL, OSTM0CTL_MD10);
mem_write8(OSTM0TS, OSTM0TS_TS);
while (1)
{
reg = mem_read16(INTICUOSTM0);
if ((reg & (INTCR_RF)) != INTCR_RF_NO_REQ)
{
/* timer stop */
reg = (reg & (uint16_t)(~(INTCR_RF)));
mem_write16(INTICUOSTM0, reg);
mem_write8(OSTM0TT, OSTM0TT_TT);
break;
}
}
}
}
/* End of function micro_wait(uint32_t count_us) */

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IPL/SDK/v3h/src/V3H_ICUMXA_Loader/image_load/image_load.c Normal file
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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file image_load.c
* - Version : 0.01
* @brief Access protection setting driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 03.07.2020 0.01 First Release
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <image_load.h>
#include <dma.h>
#include <remap.h>
#include <scif.h>
#include <mem_io.h>
#include <log.h>
#include <rom_api.h>
#define KEY_SIZE_FLG_MSK (0x00000003U)
#define KEY_SIZE_BIT_SHIFT (21U)
#define CERT_INFO_FLG_OFFSET (0x0000000CU)
#define KEY_SIZE_3072 (0x00000001U)
#define KEY_SIZE_2048 (0x00000000U)
#define NUM_OF_ALWAYS_LOAD_IMAGE (2U)
#define WORD_TO_BYTE (4U)
#define ERROR_PARAM (0U)
#define NOT_OVERLAP_FLAG (0U)
#define OVERLAP_FLAG (1U)
static void check_load_area(uint32_t dst, uint32_t src, uint32_t len);
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uintptr_t *dest_addr);
void load_key_cert(void)
{
uint32_t phys_dst;
phys_dst = remap_get_phys_addr(KEY_CERT_DEST_ADDR);
/* Load key cert */
load_start(phys_dst, RTSRAM_BASE + KEY_CERT_SRC_OFFSET, KEY_CERT_SIZE);
NOTICE(
"======== key cert info ========\n"
"destination address:0x%08x\n"
"physical destination address:0x%08x\n"
"source address:0x%08x\n"
"size:0x%08x\n", KEY_CERT_DEST_ADDR, phys_dst,
RTSRAM_BASE + KEY_CERT_SRC_OFFSET, KEY_CERT_SIZE);
/* End loading key cert */
load_end();
}
/* End of function load_key_cert(void) */
uint32_t load_content_cert(void)
{
uint32_t load_num;
uint32_t phys_dst;
uint32_t loop;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(CONTENT_CERT_DEST_ADDR);
/* Load content cert header */
load_start(phys_dst, FLASH_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE);
NOTICE(
"======== content cert info ========\n"
"destination address:0x%08x\n"
"physical destination address:0x%08x\n"
"source address:0x%08x\n"
"size:0x%08x\n", CONTENT_CERT_DEST_ADDR, phys_dst,
FLASH_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE);
/* End loading cert header */
load_end();
load_num = mem_read32(CONTENT_CERT_DEST_ADDR);
/* Check number of image load.
In case of number of image load is 0, error of transfer parameter.
In case of number of image loads is higher than 8,
the transfer parameter error. */
if ((load_num == 0U) || (load_num > CA53_MAX_IMAGE)) {
ERROR("Content cert info 'load image num' fault.\n");
ERROR("load image num = %d\n",load_num);
panic;
}
/* Load content cert of all images. */
for(loop = 0; loop < (NUM_OF_ALWAYS_LOAD_IMAGE + load_num); loop++)
{
load_start((phys_dst + CONTENT_CERT_DST_OFFSET(loop)),
(FLASH_CONTENT_CERT_ADDR + CONTENT_CERT_SRC_OFFSET(loop)),
CONTENT_CERT_DST_SIZE);
/* End loading content cert */
load_end();
}
NOTICE(
"======== content cert ========\n"
"address:0x%08x size:0x%08x\n",
(CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE),
(CONTENT_CERT_DST_SIZE * (NUM_OF_ALWAYS_LOAD_IMAGE + load_num)));
return load_num;
}
/* End of function load_content_cert(void) */
uint32_t load_image(uint32_t cert_addr, uint32_t flash_src_offset,
const char *name)
{
uint32_t load_addr;
uint32_t flash_image_addr;
uint32_t size;
/* Get transfer parameter of image from a content certificate. */
flash_image_addr = (FLASH_BASE + mem_read32(flash_src_offset));
get_info_from_cert(cert_addr, &size, &load_addr);
NOTICE("======== %s image load info ========\n"
"load address \t= 0x%08x\n" "image size \t= 0x%08x\n"
"source address \t= 0x%08x\n",
name, load_addr, size, flash_image_addr);
/* Check transfer range of image. */
check_load_area(load_addr, flash_image_addr, size);
/* Image load start. */
load_start(load_addr, flash_image_addr, size);
return load_addr;
}
/* End of function load_image(uint32_t cert_addr, uint32_t flash_src_offset, const char *name) */
static void check_load_area(uint32_t dst, uint32_t src, uint32_t len)
{
uint32_t src_end;
uint32_t dst_end;
uint32_t overlap;
uint32_t loop;
static uint32_t s_num = 0U;
/* The memory range of destination. */
const ADDRESS_RANGE add_list[] = {
[TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END},
[TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END}
};
static ADDRESS_RANGE s_placed_image[MAX_PLACED] = {
[0] = {IPL_TOP, IPL_END}, /* Overwrite after RTOS range check. */
[1] = {0U,0U},
[2] = {0U,0U},
[3] = {0U,0U},
[4] = {0U,0U},
[5] = {0U,0U},
[6] = {0U,0U},
[7] = {0U,0U},
[8] = {0U,0U},
[9] = {0U,0U}
};
/* Check image size */
if (len == 0U)
{
ERROR("image size error\n");
panic;
}
/* Check whether source is overflow */
if (src > (UINT32_MAX - len))
{
ERROR("1:overflow is occurred at source\n");
ERROR("1:source address = 0x%x image size = 0x%x\n", src, len);
panic;
} else {
src_end = src + len - 1U;
}
if (src_end < src)
{
ERROR("2:overflow is occurred at source\n");
ERROR("2:source address = 0x%x image size = 0x%x\n", src, len);
panic;
}
/* Check whether destination is overflow */
if (dst > (UINT32_MAX - len))
{
ERROR("1:overflow is occurred at destination\n");
ERROR("1:destination address = 0x%x image size = 0x%x\n", dst,
len);
panic;
}
else
{
dst_end = dst + len - 1U;
}
if (dst_end < dst)
{
ERROR("2:overflow is occurred at destination\n");
ERROR("2:destination address = 0x%x image size = 0x%x\n", dst,
len);
panic;
}
/* Check source address range. */
if ((src < FLASH_BASE) || (FLASH_END < src_end))
{
ERROR("check load area (source address)\n");
ERROR("source address = 0x%x image size = 0x%x\n", src, len);
panic;
}
/* Check destination address range. */
if ((add_list[1].topadd <= dst)
&& (dst_end <= add_list[1].endadd))
{
/* check RT-SRAM */
}
else if ((add_list[0].topadd <= dst)
&& (dst_end <= add_list[0].endadd))
{
/* check SDRAM */
}
else
{
ERROR("check_load_area (destination address)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst,
len);
panic;
}
/* Check there are no overlaps the image that will be loaded and
the images that have already loaded. */
overlap = NOT_OVERLAP_FLAG;
loop = 0U;
do
{
/* check overlap */
if ((dst >= s_placed_image[loop].topadd)
&& (dst <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst_end >= s_placed_image[loop].topadd)
&& (dst_end <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst < s_placed_image[loop].topadd)
&& (s_placed_image[loop].endadd < dst_end))
{
overlap = OVERLAP_FLAG;
}
else
{
loop++;
}
} while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG));
/* Check the overlap flag.
Parameter error if overwrite occurred.
Otherwise, add parameters of the image to be loaded into
Placed_image. */
if (overlap == NOT_OVERLAP_FLAG) {
s_placed_image[s_num].topadd = dst;
s_placed_image[s_num].endadd = dst_end;
INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num,
placed_image[s_num].topadd, placed_image[s_num].endadd);
s_num++;
} else {
ERROR("check_load_area (overlap)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst,
len);
ERROR("overlapped image is [%x]\n", loop);
ERROR("top address = 0x%x end address = 0x%x\n",
s_placed_image[loop].topadd, s_placed_image[loop].endadd);
panic;
}
}
/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uintptr_t *dest_addr)
{
uint32_t val;
uint32_t certInfo1;
uintptr_t pSize;
uintptr_t pDestL;
/* Get key length of content certificate. */
val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET);
certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK;
/* Get the transfer address and transfer size from
the certificate in accordance with the key length. */
if (KEY_SIZE_3072 == certInfo1) { /* key size = 3072 */
pSize = cert_addr + CERT_INFO_SIZE_OFFSET1;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET1;
*dest_addr = (uintptr_t)mem_read32(pDestL);
}
else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET;
*dest_addr = (uintptr_t)mem_read32(pDestL);
}
else
{
*size = ERROR_PARAM;
*dest_addr = ERROR_PARAM;
}
}
/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uintptr_t *dest_addr) */

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IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot.h Normal file
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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Access Protection header
******************************************************************************/
#ifndef ACC_PROT_H_
#define ACC_PROT_H_
/* Prototype */
void acc_prot_init(void);
#endif /* ACC_PROT_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : LifeC Access Protection header
******************************************************************************/
#ifndef ACC_PROT_LIFEC_H__
#define ACC_PROT_LIFEC_H__
#include <stdint.h>
typedef struct {
uintptr_t address;
uint32_t value;
} LIFEC_SETTING_TABLE;
void acc_prot_lifec(void);
#define LIFEC_GROUP3 (3U)
#define LIFEC_GROUP2 (2U)
#define LIFEC_GROUP1 (1U)
#define LIFEC_GROUP0 (0U)
#define LIFEC_PUBLIC (0U)
#define LIFEC_REG_TGT(RegNo, Bits) (((uint32_t)(RegNo) << 16U) | (uint32_t)(Bits))
#define LIFEC_TGT_M_ICUMX LIFEC_REG_TGT(3U, 13U)
void lifec_set_master_grp(uint32_t target, uint32_t sec_grp, uint32_t safe_grp);
#endif /* ACC_PROT_LIFEC_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory Access Protection header
******************************************************************************/
#ifndef ACC_PROT_MEMORY_H_
#define ACC_PROT_MEMORY_H_
#include <stdint.h>
#include <remap_register.h>
#define SECDIVnD_BASE (0xFFE90000U)
#define SECDIVnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a)))
#define SECCTRnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a)) + 0x0040U)
#define SPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0500U)/* 0xE6784500U */
#define SPTDIVCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define SPTCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)
#define DPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0400U)/* 0xE6784400U */
#define DPTDIVCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define DPTCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)
#define PROT_GRP0_R_ (uint8_t)(1U << 7U)
#define PROT_GRP0__W (uint8_t)(1U << 3U)
#define PROT_GRP0_RW (PROT_GRP0_R | PROT_GRP0_W)
#define PROT_GRP1_R_ (uint8_t)(1U << 6U)
#define PROT_GRP1__W (uint8_t)(1U << 2U)
#define PROT_GRP1_RW (PROT_GRP1_R | PROT_GRP1_W)
#define PROT_GRP2_R_ (uint8_t)(1U << 5U)
#define PROT_GRP2__W (uint8_t)(1U << 1U)
#define PROT_GRP2_RW (PROT_GRP2_R | PROT_GRP2_W)
#define PROT_GRP3_R_ (uint8_t)(1U << 4U)
#define PROT_GRP3__W (uint8_t)(1U << 0U)
#define PROT_GRP3_RW (PROT_GRP3_R | PROT_GRP3_W)
#define PROT_GRP_ALL (PROT_GRP0__W | PROT_GRP1__W | PROT_GRP2__W | PROT_GRP3__W)
/* 3210 */
#define R_NNNN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NNNY (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ )
#define R_NNYN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP0_R_)
#define R_NNYY (PROT_GRP3_R_ | PROT_GRP2_R_ )
#define R_NYNN (PROT_GRP3_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NYNY (PROT_GRP3_R_ | PROT_GRP1_R_ )
#define R_NYYN (PROT_GRP3_R_ | PROT_GRP0_R_)
#define R_NYYY (PROT_GRP3_R_ )
#define R_YNNN ( PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YNNY ( PROT_GRP2_R_ | PROT_GRP1_R_ | )
#define R_YNYN ( PROT_GRP2_R_ | PROT_GRP0_R_)
#define R_YNYY ( PROT_GRP2_R_ )
#define R_YYNN ( PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YYNY ( PROT_GRP1_R_ )
#define R_YYYN ( PROT_GRP0_R_)
#define R_YYYY ( 0U )
/* 3210 */
#define W_NNNN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_NNNY (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W )
#define W_NNYN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP0__W)
#define W_NNYY (PROT_GRP3__W | PROT_GRP2__W )
#define W_NYNN (PROT_GRP3__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_NYNY (PROT_GRP3__W | PROT_GRP1__W )
#define W_NYYN (PROT_GRP3__W | PROT_GRP0__W)
#define W_NYYY (PROT_GRP3__W )
#define W_YNNN ( PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_YNNY ( PROT_GRP2__W | PROT_GRP1__W | )
#define W_YNYN ( PROT_GRP2__W | PROT_GRP0__W)
#define W_YNYY ( PROT_GRP2__W )
#define W_YYNN ( PROT_GRP1__W | PROT_GRP0__W)
#define W_YYNY ( PROT_GRP1__W )
#define W_YYYN ( PROT_GRP0__W)
#define W_YYYY ( 0U )
#define RT_SRAM_ADDR_END (0x000FF000U)
#define SYSTEM_RAM_ADDR_END (0xFFFFF000U)
#define DRAM_ADDR_END (0x0000002FFFFF0000ULL)
typedef struct {
uint8_t reg_sec;
uint8_t reg_saf;
uint8_t acc_sec;
uint8_t acc_saf;
}RAM_GROUP;
typedef struct {
uint32_t addr_off; /* RT_SRAM_PROT[0] is must be 0x00000000 */
RAM_GROUP prot;
}RT_SRAM_PROT;
typedef struct {
uint32_t addr; /* SYSTEM_RAM_PROT[0] is must be 0xE6300000 */
RAM_GROUP prot;
}SYSTEM_RAM_PROT;
typedef struct {
uint64_t addr; /* DRAM_PROT[0] is must be 0x00000040_00000000 */
RAM_GROUP prot;
}DRAM_PROT;
void acc_prot_rt_sram(void);
void acc_prot_system_ram(void);
void acc_prot_dram(void);
#endif /* ACC_PROT_LIFEC_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AXI-Bus register header
******************************************************************************/
#ifndef AXI_REGISTER_H_
#define AXI_REGISTER_H_
#include <remap_register.h>
/* AXI base address */
#define AXI_BASE (BASE_AXI_ADDR)
/* SDRAM protection */
#define DPTDIVCR0 (AXI_BASE + 0x4400U) /* AXI dram protected area division 0 */
#define DPTDIVCR1 (AXI_BASE + 0x4404U) /* AXI dram protected area division 1 */
#define DPTDIVCR2 (AXI_BASE + 0x4408U) /* AXI dram protected area division 2 */
#define DPTDIVCR3 (AXI_BASE + 0x440CU) /* AXI dram protected area division 3 */
#define DPTDIVCR4 (AXI_BASE + 0x4410U) /* AXI dram protected area division 4 */
#define DPTDIVCR5 (AXI_BASE + 0x4414U) /* AXI dram protected area division 5 */
#define DPTDIVCR6 (AXI_BASE + 0x4418U) /* AXI dram protected area division 6 */
#define DPTDIVCR7 (AXI_BASE + 0x441CU) /* AXI dram protected area division 7 */
#define DPTDIVCR8 (AXI_BASE + 0x4420U) /* AXI dram protected area division 8 */
#define DPTDIVCR9 (AXI_BASE + 0x4424U) /* AXI dram protected area division 9 */
#define DPTDIVCR10 (AXI_BASE + 0x4428U) /* AXI dram protected area division 10 */
#define DPTDIVCR11 (AXI_BASE + 0x442CU) /* AXI dram protected area division 11 */
#define DPTDIVCR12 (AXI_BASE + 0x4430U) /* AXI dram protected area division 12 */
#define DPTDIVCR13 (AXI_BASE + 0x4434U) /* AXI dram protected area division 13 */
#define DPTDIVCR14 (AXI_BASE + 0x4438U) /* AXI dram protected area division 14 */
#define DPTCR0 (AXI_BASE + 0x4440U) /* AXI dram protected area setting 0 */
#define DPTCR1 (AXI_BASE + 0x4444U) /* AXI dram protected area setting 1 */
#define DPTCR2 (AXI_BASE + 0x4448U) /* AXI dram protected area setting 2 */
#define DPTCR3 (AXI_BASE + 0x444CU) /* AXI dram protected area setting 3 */
#define DPTCR4 (AXI_BASE + 0x4450U) /* AXI dram protected area setting 4 */
#define DPTCR5 (AXI_BASE + 0x4454U) /* AXI dram protected area setting 5 */
#define DPTCR6 (AXI_BASE + 0x4458U) /* AXI dram protected area setting 6 */
#define DPTCR7 (AXI_BASE + 0x445CU) /* AXI dram protected area setting 7 */
#define DPTCR8 (AXI_BASE + 0x4460U) /* AXI dram protected area setting 8 */
#define DPTCR9 (AXI_BASE + 0x4464U) /* AXI dram protected area setting 9 */
#define DPTCR10 (AXI_BASE + 0x4468U) /* AXI dram protected area setting 10 */
#define DPTCR11 (AXI_BASE + 0x446CU) /* AXI dram protected area setting 11 */
#define DPTCR12 (AXI_BASE + 0x4470U) /* AXI dram protected area setting 12 */
#define DPTCR13 (AXI_BASE + 0x4474U) /* AXI dram protected area setting 13 */
#define DPTCR14 (AXI_BASE + 0x4478U) /* AXI dram protected area setting 14 */
#define DPTCR15 (AXI_BASE + 0x447CU) /* AXI dram protected area setting 15 */
/* System RAM protection */
#define SPTDIVCR0 (AXI_BASE + 0x4500U) /* AXI system ram protected area division 0 */
#define SPTDIVCR1 (AXI_BASE + 0x4504U) /* AXI system ram protected area division 1 */
#define SPTDIVCR2 (AXI_BASE + 0x4508U) /* AXI system ram protected area division 2 */
#define SPTDIVCR3 (AXI_BASE + 0x450CU) /* AXI system ram protected area division 3 */
#define SPTDIVCR4 (AXI_BASE + 0x4510U) /* AXI system ram protected area division 4 */
#define SPTDIVCR5 (AXI_BASE + 0x4514U) /* AXI system ram protected area division 5 */
#define SPTDIVCR6 (AXI_BASE + 0x4518U) /* AXI system ram protected area division 6 */
#define SPTDIVCR7 (AXI_BASE + 0x451CU) /* AXI system ram protected area division 7 */
#define SPTDIVCR8 (AXI_BASE + 0x4520U) /* AXI system ram protected area division 8 */
#define SPTDIVCR9 (AXI_BASE + 0x4524U) /* AXI system ram protected area division 9 */
#define SPTDIVCR10 (AXI_BASE + 0x4528U) /* AXI system ram protected area division 10 */
#define SPTDIVCR11 (AXI_BASE + 0x452CU) /* AXI system ram protected area division 11 */
#define SPTDIVCR12 (AXI_BASE + 0x4530U) /* AXI system ram protected area division 12 */
#define SPTDIVCR13 (AXI_BASE + 0x4534U) /* AXI system ram protected area division 13 */
#define SPTDIVCR14 (AXI_BASE + 0x4538U) /* AXI system ram protected area division 14 */
#define SPTCR0 (AXI_BASE + 0x4540U) /* AXI system ram protected area setting 0 */
#define SPTCR1 (AXI_BASE + 0x4544U) /* AXI system ram protected area setting 1 */
#define SPTCR2 (AXI_BASE + 0x4548U) /* AXI system ram protected area setting 2 */
#define SPTCR3 (AXI_BASE + 0x454CU) /* AXI system ram protected area setting 3 */
#define SPTCR4 (AXI_BASE + 0x4550U) /* AXI system ram protected area setting 4 */
#define SPTCR5 (AXI_BASE + 0x4554U) /* AXI system ram protected area setting 5 */
#define SPTCR6 (AXI_BASE + 0x4558U) /* AXI system ram protected area setting 6 */
#define SPTCR7 (AXI_BASE + 0x455CU) /* AXI system ram protected area setting 7 */
#define SPTCR8 (AXI_BASE + 0x4560U) /* AXI system ram protected area setting 8 */
#define SPTCR9 (AXI_BASE + 0x4564U) /* AXI system ram protected area setting 9 */
#define SPTCR10 (AXI_BASE + 0x4568U) /* AXI system ram protected area setting 10 */
#define SPTCR11 (AXI_BASE + 0x456CU) /* AXI system ram protected area setting 11 */
#define SPTCR12 (AXI_BASE + 0x4570U) /* AXI system ram protected area setting 12 */
#define SPTCR13 (AXI_BASE + 0x4574U) /* AXI system ram protected area setting 13 */
#define SPTCR14 (AXI_BASE + 0x4578U) /* AXI system ram protected area setting 14 */
#define SPTCR15 (AXI_BASE + 0x457CU) /* AXI system ram protected area setting 15 */
#define EDCINTEN0 (0xFF840040U) /* EDC Interrupt Enable Register 0 */
#define EDCINTEN1 (0xFF840044U) /* EDC Interrupt Enable Register 1 */
#define EDCINTEN2 (0xFF840048U) /* EDC Interrupt Enable Register 2 */
#define EDCINTEN3 (0xFF84004CU) /* EDC Interrupt Enable Register 3 */
#define EDCINTEN5 (0xFF8401C0U) /* EDC Interrupt Enable Register 5 */
#define EDCINTEN6 (0xFF8401C4U) /* EDC Interrupt Enable Register 6 */
#define EDCINTEN7 (0xFF8401C8U) /* EDC Interrupt Enable Register 8 */
#define EDC_CFG (0xFFE90110U) /* EDC Error control Register(RT-SRAM) V3H_2 */
#endif /* AXI_REGISTER_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG driver header
******************************************************************************/
#ifndef CPG_H_
#define CPG_H_
#include <stdint.h>
/* Prototype */
void cpg_init(void);
void cpg_release(void);
void cpg_reg_write(uintptr_t mstpcr, uintptr_t mstpsr, uint32_t data);
#endif /* CPG_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG register header
******************************************************************************/
#ifndef CPG_REGISTER_H__
#define CPG_REGISTER_H__
#include <remap_register.h>
/* CPG base address */
/* 0xE6150000 */
#define CPG_BASE (BASE_CPG_ADDR)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
/* CPG write protect control */
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) /* Module stop status register 0 */
#define CPG_MSTPSR1 (CPG_BASE + 0x0038U) /* Module stop status register 1 */
#define CPG_MSTPSR2 (CPG_BASE + 0x0040U) /* Module stop status register 2 */
#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* Module stop status register 3 */
#define CPG_MSTPSR4 (CPG_BASE + 0x004CU) /* Module stop status register 4 */
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) /* Module stop status register 5 */
#define CPG_MSTPSR6 (CPG_BASE + 0x01C0U) /* Module stop status register 6 */
#define CPG_MSTPSR7 (CPG_BASE + 0x01C4U) /* Module stop status register 7 */
#define CPG_MSTPSR8 (CPG_BASE + 0x09A0U) /* Module stop status register 8 */
#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) /* Module stop status register 9 */
#define CPG_MSTPSR10 (CPG_BASE + 0x09A8U) /* Module stop status register 10 */
#define CPG_MSTPSR11 (CPG_BASE + 0x09ACU) /* Module stop status register 11 */
/* CPG (Realtime) registers */
#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) /* Realtime Module Stop Control Register 0 */
#define CPG_RMSTPCR1 (CPG_BASE + 0x0114U) /* Realtime Module Stop Control Register 1 */
#define CPG_RMSTPCR2 (CPG_BASE + 0x0118U) /* Realtime Module Stop Control Register 2 */
#define CPG_RMSTPCR3 (CPG_BASE + 0x011CU) /* Realtime Module Stop Control Register 3 */
#define CPG_RMSTPCR4 (CPG_BASE + 0x0120U) /* Realtime Module Stop Control Register 4 */
#define CPG_RMSTPCR5 (CPG_BASE + 0x0124U) /* Realtime Module Stop Control Register 5 */
#define CPG_RMSTPCR6 (CPG_BASE + 0x0128U) /* Realtime Module Stop Control Register 6 */
#define CPG_RMSTPCR7 (CPG_BASE + 0x012CU) /* Realtime Module Stop Control Register 7 */
#define CPG_RMSTPCR8 (CPG_BASE + 0x0980U) /* Realtime Module Stop Control Register 8 */
#define CPG_RMSTPCR9 (CPG_BASE + 0x0984U) /* Realtime Module Stop Control Register 9 */
#define CPG_RMSTPCR10 (CPG_BASE + 0x0988U) /* Realtime Module Stop Control Register 10 */
#define CPG_RMSTPCR11 (CPG_BASE + 0x098CU) /* Realtime Module Stop Control Register 11 */
/* CPG (System) registers */
#define CPG_SMSTPCR0 (CPG_BASE + 0x0130U) /* System Module Stop Control Register 0 */
#define CPG_SMSTPCR1 (CPG_BASE + 0x0134U) /* System Module Stop Control Register 1 */
#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) /* System Module Stop Control Register 2 */
#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) /* System Module Stop Control Register 3 */
#define CPG_SMSTPCR4 (CPG_BASE + 0x0140U) /* System Module Stop Control Register 4 */
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) /* System Module Stop Control Register 5 */
#define CPG_SMSTPCR6 (CPG_BASE + 0x0148U) /* System Module Stop Control Register 6 */
#define CPG_SMSTPCR7 (CPG_BASE + 0x014CU) /* System Module Stop Control Register 7 */
#define CPG_SMSTPCR8 (CPG_BASE + 0x0990U) /* System Module Stop Control Register 8 */
#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) /* System Module Stop Control Register 9 */
#define CPG_SMSTPCR10 (CPG_BASE + 0x0998U) /* System Module Stop Control Register 10 */
#define CPG_SMSTPCR11 (CPG_BASE + 0x099CU) /* System Module Stop Control Register 11 */
/* CPG (SECURITY) registers */
#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U) /* Secure Module Stop Control Register 0 */
#define CPG_SCMSTPCR1 (CPG_BASE + 0x0B24U) /* Secure Module Stop Control Register 1 */
#define CPG_SCMSTPCR2 (CPG_BASE + 0x0B28U) /* Secure Module Stop Control Register 2 */
#define CPG_SCMSTPCR3 (CPG_BASE + 0x0B2CU) /* Secure Module Stop Control Register 3 */
#define CPG_SCMSTPCR4 (CPG_BASE + 0x0B30U) /* Secure Module Stop Control Register 4 */
#define CPG_SCMSTPCR5 (CPG_BASE + 0x0B34U) /* Secure Module Stop Control Register 5 */
#define CPG_SCMSTPCR6 (CPG_BASE + 0x0B38U) /* Secure Module Stop Control Register 6 */
#define CPG_SCMSTPCR7 (CPG_BASE + 0x0B3CU) /* Secure Module Stop Control Register 7 */
#define CPG_SCMSTPCR8 (CPG_BASE + 0x0B40U) /* Secure Module Stop Control Register 8 */
#define CPG_SCMSTPCR9 (CPG_BASE + 0x0B44U) /* Secure Module Stop Control Register 9 */
#define CPG_SCMSTPCR10 (CPG_BASE + 0x0B48U) /* Secure Module Stop Control Register 10 */
#define CPG_SCMSTPCR11 (CPG_BASE + 0x0B4CU) /* Secure Module Stop Control Register 11 */
/* CPG (SAFETY) registers */
#define CPG_SAMSTPCR0 (CPG_BASE + 0x0C20U) /* Safety Module Stop Control Register 0 */
#define CPG_SAMSTPCR1 (CPG_BASE + 0x0C24U) /* Safety Module Stop Control Register 1 */
#define CPG_SAMSTPCR2 (CPG_BASE + 0x0C28U) /* Safety Module Stop Control Register 2 */
#define CPG_SAMSTPCR3 (CPG_BASE + 0x0C2CU) /* Safety Module Stop Control Register 3 */
#define CPG_SAMSTPCR4 (CPG_BASE + 0x0C30U) /* Safety Module Stop Control Register 4 */
#define CPG_SAMSTPCR5 (CPG_BASE + 0x0C34U) /* Safety Module Stop Control Register 5 */
#define CPG_SAMSTPCR6 (CPG_BASE + 0x0C38U) /* Safety Module Stop Control Register 6 */
#define CPG_SAMSTPCR7 (CPG_BASE + 0x0C3CU) /* Safety Module Stop Control Register 7 */
#define CPG_SAMSTPCR8 (CPG_BASE + 0x0C40U) /* Safety Module Stop Control Register 8 */
#define CPG_SAMSTPCR9 (CPG_BASE + 0x0C44U) /* Safety Module Stop Control Register 9 */
#define CPG_SAMSTPCR10 (CPG_BASE + 0x0C48U) /* Safety Module Stop Control Register 10 */
#define CPG_SAMSTPCR11 (CPG_BASE + 0x0C4CU) /* Safety Module Stop Control Register 11 */
#define CPG_SRSTCLR2 (CPG_BASE + 0x0948U) /* Software Reset Clearing Register 2 */
/* APMU */
#define APMU_CA53WUPCR (CPG_BASE + 0x1010U) /* Wake-up control register for A53 */
#define APMU_CR7PSTR (CPG_BASE + 0x3040U) /* Wake-up control register for A53 */
/* IMP core */
#define ASTPOFFR (CPG_BASE + 0x0278U) /* Automatic Module clock stop function off register */
#endif /* CPG_REGISTER_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Power management driver header
******************************************************************************/
#ifndef CPU_ON_H__
#define CPU_ON_H__
#define RCAR_PWR_TARGET_CR7 (0U)
#define RCAR_PWR_TARGET_CA53 (1U)
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
void arm_cpu_on(uint32_t target, uint32_t boot_addr);
#endif /* CPU_ON_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA driver header
******************************************************************************/
#ifndef DMA_DRIVER_H__
#define DMA_DRIVER_H__
#include <stdint.h>
#define DMACH (0U)
#define BIT21 (1U << 21U)
void dma_init(void);
void load_start(uint32_t dst, uint32_t src, uint32_t len);
void load_end(void);
void dma_release(void);
#endif /* DMA_DRIVER_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA register header
******************************************************************************/
#ifndef DMA_REGISTER_H_
#define DMA_REGISTER_H_
#include <remap_register.h>
#define DMACH (0U)
#define BIT21 (1U << 21U)
/* RT-DMAC0(foe RPC) */
#define RTDMA_BASE (BASE_RTDMA_ADDR)
#define DMA_RDMOR (RTDMA_BASE + 0x0060U) /* DMA operation register */
#define DMA_RDMSEC (RTDMA_BASE + 0x0030U)
#define DMA_RDMCHCLR (RTDMA_BASE + 0x0080U) /* DMA channel clear register */
#define DMA_RDMSAR(a) (RTDMA_BASE + 0x8000U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMDAR(a) (RTDMA_BASE + 0x8004U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMTCR(a) (RTDMA_BASE + 0x8008U + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMCHCR(a) (RTDMA_BASE + 0x800CU + ((uint32_t)(a) * 0x0080U))
#define DMA_RDMRS(a) (RTDMA_BASE + 0x8040U + ((uint32_t)(a) * 0x0080U))
#endif /* DMA_REGISTER_H_ */

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/*******************************************************************************
* Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : EDC's control header
******************************************************************************/
#ifndef EDCINTEN_H_
#define EDCINTEN_H_
/* Prototype */
void edc_init(void);
#endif /* EDCINTEN_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function header
******************************************************************************/
#ifndef LOAD_IMAGE_H_
#define LOAD_IMAGE_H_
/* define */
/* Flash address */
#define FLASH_BASE (0x08000000U)
#define FLASH_SIZE (0x04000000U)
#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U)
/* DRAM address */
#define DRAM_BASE (0x40000000U)
#define DRAM_SIZE (0x80000000U)
#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
/* RT-SRAM */
#define RTSRAM_BASE (0xEB200000U)
#define RTSRAM_SIZE ((1024U-18U)*1024U)
#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
/* ICUMXA Loader */
#define IPL_TOP (0xEB2D8000U)
#define IPL_END (0xEB2FFFFFU)
/* Flash address of content certificate */
#define CONTENT_CERT_SA (6U) /* Content Cert SA6 */
#define SA_SIZE (0x00040000U)
#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA6 offset */
/* Certificate logical address */
extern char __ghsbegin_key_load[];
extern char __ghsbegin_cert_load[];
#define KEY_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_key_load[0])
#define CONTENT_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_cert_load[0])
/* Certificate size */
#define KEY_CERT_SRC_OFFSET (0x00000F00U)
#define KEY_CERT_SIZE (0x00000400U) /* Key cert size */
#define CONTENT_CERT_INFO_SIZE (0x00000400U) /* CA53 program num */
#define CONTENT_CERT_SRC_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_SEC_SIZE)) /* content cert src offsett */
#define CONTENT_CERT_DST_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_DST_SIZE)) /* content cert dst offset */
#define CONTENT_CERT_SEC_SIZE (0x00000800U) /* content cert src size */
#define CONTENT_CERT_DST_SIZE (0x00000400U) /* content cert dst size */
/* Load ID */
#define SECURE_FW_ID (0U)
#define RTOS_ID (1U)
#define CA53_PROGRAM_ID (2U)
/* Number of Max loading image */
#define CA53_MAX_IMAGE (8U) /* CA53 program MAX image num */
#define MAX_PLACED (10U)
/* Cert Info Source Address Offset */
#define SRC_ADDR_OFFSET(x) (((uint32_t)(x) * 0x10U) + 0x08U)
#define TARGET_MEM_DRAM (0U)
#define TARGET_MEM_RTSRAM (1U)
/* get info from cert address offset */
#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
/* struct */
/* load address range */
typedef struct {
uint32_t topadd;
uint32_t endadd;
} ADDRESS_RANGE;
/* load info */
typedef struct{
const char *name; /* store load image name */
uint32_t boot_addr; /* store boot address of image */
uint32_t cert_addr; /* store content cert address */
uint32_t src_addr; /* store source address */
} LOAD_INFO;
/* Prototype */
void load_key_cert(void);
uint32_t load_content_cert(void);
uint32_t load_image(uint32_t cert_addr, uint32_t flash_src_offset,
const char *name);
#endif /* LOAD_IMAGE_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : IP's control header
******************************************************************************/
#ifndef IP_CONTROL_H_
#define IP_CONTROL_H_
/* Prototype */
void ip_init(void);
void ip_release(void);
#endif /* IP_CONTROL_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : LifeC register header
******************************************************************************/
#ifndef LIFEC_REGISTER_H__
#define LIFEC_REGISTER_H__
#include <remap_register.h>
/* LIFEC0 (SECURITY) registers */
/* LIFEC0 (SECURITY) base address */
#define LIFEC_SEC_BASE (BASE_LIFEC_ADDR)
/* Security attribute setting for master ports */
#define LIFEC_SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
/* Security attribute setting for slave ports 0 */
#define LIFEC_SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
/* Security attribute setting for slave ports 1 */
#define LIFEC_SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
/* Security attribute setting for slave ports 2 */
#define LIFEC_SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
/* Security attribute setting for slave ports 3 */
#define LIFEC_SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
/* Security attribute setting for slave ports 4 */
#define LIFEC_SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
/* Security attribute setting for slave ports 5 */
#define LIFEC_SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
/* Security attribute setting for slave ports 6 */
#define LIFEC_SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
/* Security attribute setting for slave ports 7 */
#define LIFEC_SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
/* Security attribute setting for slave ports 8 */
#define LIFEC_SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
/* Security attribute setting for slave ports 9 */
#define LIFEC_SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
/* Security attribute setting for slave ports 10 */
#define LIFEC_SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
/* Security attribute setting for slave ports 11 */
#define LIFEC_SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
/* Security attribute setting for slave ports 12 */
#define LIFEC_SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
/* Security attribute setting for slave ports 13 */
#define LIFEC_SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
/* Security attribute setting for slave ports 14 */
#define LIFEC_SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
/* Security attribute setting for slave ports 15 */
#define LIFEC_SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
/* Security group 0 attribute setting for master ports 0 */
#define LIFEC_SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
/* Security group 1 attribute setting for master ports 0 */
#define LIFEC_SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
/* Security group 0 attribute setting for master ports 1 */
#define LIFEC_SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
/* Security group 1 attribute setting for master ports 1 */
#define LIFEC_SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
/* Security group 0 attribute setting for master ports 2 */
#define LIFEC_SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
/* Security group 1 attribute setting for master ports 2 */
#define LIFEC_SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
/* Security group 0 attribute setting for master ports 3 */
#define LIFEC_SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
/* Security group 1 attribute setting for master ports 3 */
#define LIFEC_SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
/* Security group 0 attribute setting for slave ports 0 */
#define LIFEC_SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
/* Security group 1 attribute setting for slave ports 0 */
#define LIFEC_SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
/* Security group 0 attribute setting for slave ports 1 */
#define LIFEC_SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
/* Security group 1 attribute setting for slave ports 1 */
#define LIFEC_SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
/* Security group 0 attribute setting for slave ports 2 */
#define LIFEC_SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
/* Security group 1 attribute setting for slave ports 2 */
#define LIFEC_SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
/* Security group 0 attribute setting for slave ports 3 */
#define LIFEC_SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
/* Security group 1 attribute setting for slave ports 3 */
#define LIFEC_SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
/* Security group 0 attribute setting for slave ports 4 */
#define LIFEC_SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
/* Security group 1 attribute setting for slave ports 4 */
#define LIFEC_SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
/* Security group 0 attribute setting for slave ports 5 */
#define LIFEC_SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
/* Security group 1 attribute setting for slave ports 5 */
#define LIFEC_SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
/* Security group 0 attribute setting for slave ports 6 */
#define LIFEC_SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
/* Security group 1 attribute setting for slave ports 6 */
#define LIFEC_SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
/* Security group 0 attribute setting for slave ports 7 */
#define LIFEC_SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
/* Security group 1 attribute setting for slave ports 7 */
#define LIFEC_SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
/* Security group 0 attribute setting for slave ports 8 */
#define LIFEC_SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
/* Security group 1 attribute setting for slave ports 8 */
#define LIFEC_SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
/* Security group 0 attribute setting for slave ports 9 */
#define LIFEC_SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
/* Security group 1 attribute setting for slave ports 9 */
#define LIFEC_SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
/* Security group 0 attribute setting for slave ports 10 */
#define LIFEC_SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
/* Security group 1 attribute setting for slave ports 10 */
#define LIFEC_SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
/* Security group 0 attribute setting for slave ports 11 */
#define LIFEC_SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
/* Security group 1 attribute setting for slave ports 11 */
#define LIFEC_SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
/* Security group 0 attribute setting for slave ports 12 */
#define LIFEC_SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
/* Security group 1 attribute setting for slave ports 12 */
#define LIFEC_SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
/* Security group 0 attribute setting for slave ports 13 */
#define LIFEC_SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
/* Security group 1 attribute setting for slave ports 13 */
#define LIFEC_SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
/* Security group 0 attribute setting for slave ports 14 */
#define LIFEC_SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
/* Security group 1 attribute setting for slave ports 14 */
#define LIFEC_SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
/* Security group 0 attribute setting for slave ports 15 */
#define LIFEC_SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
/* Security group 1 attribute setting for slave ports 15 */
#define LIFEC_SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
/* Security write protection attribute setting for slave ports 0 */
#define LIFEC_SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
/* Security write protection attribute setting for slave ports 1 */
#define LIFEC_SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
/* Security write protection attribute setting for slave ports 2 */
#define LIFEC_SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
/* Security write protection attribute setting for slave ports 3 */
#define LIFEC_SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
/* Security write protection attribute setting for slave ports 4 */
#define LIFEC_SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
/* Security write protection attribute setting for slave ports 5 */
#define LIFEC_SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
/* Security write protection attribute setting for slave ports 6 */
#define LIFEC_SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
/* Security write protection attribute setting for slave ports 7 */
#define LIFEC_SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
/* Security write protection attribute setting for slave ports 8 */
#define LIFEC_SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
/* Security write protection attribute setting for slave ports 9 */
#define LIFEC_SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
/* Security write protection attribute setting for slave ports 10 */
#define LIFEC_SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
/* Security write protection attribute setting for slave ports 11 */
#define LIFEC_SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
/* Security write protection attribute setting for slave ports 12 */
#define LIFEC_SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
/* Security write protection attribute setting for slave ports 13 */
#define LIFEC_SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
/* Security write protection attribute setting for slave ports 14 */
#define LIFEC_SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
/* Security write protection attribute setting for slave ports 15 */
#define LIFEC_SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
/* LIFEC1 (SAFETY) registers */
/* LIFEC1 (SAFETY) base address */
#define LIFEC_SAFE_BASE (LIFEC_SEC_BASE + 0x00010000U)
/* Safety group 0 attribute setting for master ports 0 */
#define LIFEC_SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
/* Safety group 1 attribute setting for master ports 0 */
#define LIFEC_SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
/* Safety group 0 attribute setting for master ports 1 */
#define LIFEC_SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
/* Safety group 1 attribute setting for master ports 1 */
#define LIFEC_SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
/* Safety group 0 attribute setting for master ports 2 */
#define LIFEC_SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
/* Safety group 1 attribute setting for master ports 2 */
#define LIFEC_SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
/* Safety group 0 attribute setting for master ports 3 */
#define LIFEC_SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
/* Safety group 1 attribute setting for master ports 3 */
#define LIFEC_SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
/* Safety group 0 attribute setting for slave ports 0 */
#define LIFEC_SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
/* Safety group 1 attribute setting for slave ports 0 */
#define LIFEC_SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
/* Safety group 0 attribute setting for slave ports 1 */
#define LIFEC_SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
/* Safety group 1 attribute setting for slave ports 1 */
#define LIFEC_SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
/* Safety group 0 attribute setting for slave ports 2 */
#define LIFEC_SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
/* Safety group 1 attribute setting for slave ports 2 */
#define LIFEC_SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
/* Safety group 0 attribute setting for slave ports 3 */
#define LIFEC_SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
/* Safety group 1 attribute setting for slave ports 3 */
#define LIFEC_SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
/* Safety group 0 attribute setting for slave ports 4 */
#define LIFEC_SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
/* Safety group 1 attribute setting for slave ports 4 */
#define LIFEC_SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
/* Safety group 0 attribute setting for slave ports 5 */
#define LIFEC_SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
/* Safety group 1 attribute setting for slave ports 5 */
#define LIFEC_SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
/* Safety group 0 attribute setting for slave ports 6 */
#define LIFEC_SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
/* Safety group 1 attribute setting for slave ports 6 */
#define LIFEC_SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
/* Safety group 0 attribute setting for slave ports 7 */
#define LIFEC_SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
/* Safety group 1 attribute setting for slave ports 7 */
#define LIFEC_SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
/* Safety group 0 attribute setting for slave ports 8 */
#define LIFEC_SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
/* Safety group 1 attribute setting for slave ports 8 */
#define LIFEC_SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
/* Safety group 0 attribute setting for slave ports 9 */
#define LIFEC_SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
/* Safety group 1 attribute setting for slave ports 9 */
#define LIFEC_SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
/* Safety group 0 attribute setting for slave ports 10 */
#define LIFEC_SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
/* Safety group 1 attribute setting for slave ports 10 */
#define LIFEC_SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
/* Safety group 0 attribute setting for slave ports 11 */
#define LIFEC_SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
/* Safety group 1 attribute setting for slave ports 11 */
#define LIFEC_SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
/* Safety group 0 attribute setting for slave ports 12 */
#define LIFEC_SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
/* Safety group 1 attribute setting for slave ports 12 */
#define LIFEC_SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
/* Safety group 0 attribute setting for slave ports 13 */
#define LIFEC_SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
/* Safety group 1 attribute setting for slave ports 13 */
#define LIFEC_SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
/* Safety group 0 attribute setting for slave ports 14 */
#define LIFEC_SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
/* Safety group 1 attribute setting for slave ports 14 */
#define LIFEC_SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
/* Safety group 0 attribute setting for slave ports 15 */
#define LIFEC_SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
/* Safety group 1 attribute setting for slave ports 15 */
#define LIFEC_SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
/* Safety write protection attribute setting for slave ports 0 */
#define LIFEC_SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
/* Safety write protection attribute setting for slave ports 1 */
#define LIFEC_SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
/* Safety write protection attribute setting for slave ports 2 */
#define LIFEC_SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
/* Safety write protection attribute setting for slave ports 3 */
#define LIFEC_SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
/* Safety write protection attribute setting for slave ports 4 */
#define LIFEC_SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
/* Safety write protection attribute setting for slave ports 5 */
#define LIFEC_SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
/* Safety write protection attribute setting for slave ports 6 */
#define LIFEC_SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
/* Safety write protection attribute setting for slave ports 7 */
#define LIFEC_SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
/* Safety write protection attribute setting for slave ports 8 */
#define LIFEC_SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
/* Safety write protection attribute setting for slave ports 9 */
#define LIFEC_SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
/* Safety write protection attribute setting for slave ports 10 */
#define LIFEC_SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
/* Safety write protection attribute setting for slave ports 11 */
#define LIFEC_SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
/* Safety write protection attribute setting for slave ports 12 */
#define LIFEC_SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
/* Safety write protection attribute setting for slave ports 13 */
#define LIFEC_SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
/* Safety write protection attribute setting for slave ports 14 */
#define LIFEC_SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
/* Safety write protection attribute setting for slave ports 15 */
#define LIFEC_SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTER_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main header
******************************************************************************/
#ifndef LOADER_MAIN_H_
#define LOADER_MAIN_H_
/* define */
#define IPL_VERSION "2.0.5"
/* Global */
extern const char build_message[];
/* prototype */
uint32_t loader_main(void);
#endif /* LOAD_MAIN_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver header
******************************************************************************/
#ifndef LOG_H__
#define LOG_H__
#include <stdint.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) local_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) local_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) local_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) local_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) local_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#define panic \
do { \
local_printf("P:%s\n", __func__); \
while(1){} \
} while (0)
#define FORCE(...) local_printf(__VA_ARGS__)
void local_printf(const char *fmt, ...);
#endif /* LOG_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory access driver header
******************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
/* Prototype */
void mem_write8(uintptr_t addr, uint8_t data);
uint8_t mem_read8(uintptr_t addr);
void mem_write16(uintptr_t addr, uint16_t data);
uint16_t mem_read16(uintptr_t addr);
void mem_write32(uintptr_t addr, uint32_t data);
uint32_t mem_read32(uintptr_t addr);
void mem_write64(uintptr_t addr, uint64_t data);
void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set);
#if defined(__RH850G3K__)
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif
#endif /* MEM_IO_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS driver header
******************************************************************************/
#ifndef MFIS_H__
#define MFIS_H__
#include <stdint.h>
#define MFIS_PROT_CODEVALUE (0xACCE0000U)
#define MFISWPCNTR_WPD_BIT (((uint32_t)1U) << 0U)
typedef struct {
uintptr_t address;
uint32_t value;
} MFIS_SETTING_TABLE;
void mfis_init(void);
#endif /* MFIS_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS register header
******************************************************************************/
#ifndef MFIS_REGISTER_H_
#define MFIS_REGISTER_H_
#include <remap_register.h>
/* MFIS */
#define MFIS_BASE (BASE_MFIS_ADDR)
#define MFIS_MFIERRCTLR0 (MFIS_BASE + 0x0200U)
#define MFIS_MFIERRCTLR1 (MFIS_BASE + 0x0204U)
#define MFIS_MFIERRCTLR2 (MFIS_BASE + 0x0208U)
#define MFIS_MFIERRCTLR3 (MFIS_BASE + 0x020CU)
#define MFIS_MFIERRCTLR4 (MFIS_BASE + 0x0210U)
#define MFIS_MFIERRCTLR5 (MFIS_BASE + 0x0214U)
#define MFIS_MFIERRCTLR6 (MFIS_BASE + 0x0218U)
#define MFIS_MFIERRCTLR7 (MFIS_BASE + 0x0260U)
#define MFIS_MFIERRCTLR8 (MFIS_BASE + 0x026CU)
#define MFIS_MFIERRCTLR9 (MFIS_BASE + 0x0804U)
#define MFIS_MFIERRCTLR10 (MFIS_BASE + 0x0808U)
#define MFIS_MFIERRCTLR11 (MFIS_BASE + 0x080CU)
#define MFIS_MFIERRCTLR12 (MFIS_BASE + 0x0908U)
#define MFIS_MFIERRCTLR13 (MFIS_BASE + 0x0918U)
#define MFIS_MFIERRTGTR0 (MFIS_BASE + 0x0280U)
#define MFIS_MFIERRTGTR1 (MFIS_BASE + 0x0284U)
#define MFIS_MFIERRTGTR2 (MFIS_BASE + 0x0288U)
#define MFIS_MFIERRTGTR3 (MFIS_BASE + 0x028CU)
#define MFIS_MFIERRTGTR4 (MFIS_BASE + 0x0290U)
#define MFIS_MFIERRTGTR5 (MFIS_BASE + 0x0294U)
#define MFIS_MFIERRTGTR6 (MFIS_BASE + 0x025CU)
#define MFIS_MFIERRTGTR7 (MFIS_BASE + 0x0268U)
#define MFIS_MFIERRTGTR8 (MFIS_BASE + 0x0274U)
#define MFIS_MFIERRTGTR9 (MFIS_BASE + 0x081CU)
#define MFIS_MFIERRTGTR10 (MFIS_BASE + 0x0820U)
#define MFIS_MFIERRTGTR11 (MFIS_BASE + 0x0824U)
#define MFIS_MFIERRTGTR12 (MFIS_BASE + 0x0910U)
#define MFIS_MFIERRTGTR13 (MFIS_BASE + 0x0920U)
#define MFIS_MFISBTSTSR (MFIS_BASE + 0x0604U)
#define MFIS_MFIEXTRQMSKCNTR (MFIS_BASE + 0x08A0U)
#define MFIS_MFISWPCNTR (MFIS_BASE + 0x0900U)
#define MFIS_MFISWACNTR (MFIS_BASE + 0x0904U)
#endif /* MFIS_REGISTER_H_ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver header
******************************************************************************/
#ifndef MICRO_WAIT_H_
#define MICRO_WAIT_H_
#include <stdint.h>
/* Define */
/* Prototype */
void micro_wait(uint32_t count_us);
#endif /* MICRO_WAIT_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC driver header
******************************************************************************/
#ifndef PFC_H__
#define PFC_H__
#include <stdint.h>
void pfc_init(void);
void pfc_reg_write(uintptr_t addr, uint32_t data);
#endif /* PFC_H__ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC register header
******************************************************************************/
#ifndef PFC_REGISTER_H__
#define PFC_REGISTER_H__
#include <remap_register.h>
/* GPIO base address */
/* 0xE6050000 */
#define GPIO_BASE (BASE_GPIO_ADDR)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
/* Pin functon base address */
/* 0xE6060000 */
#define PFC_BASE (BASE_PFC_ADDR)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IOCTRL0 (PFC_BASE + 0x0300U)
#define PFC_IOCTRL1 (PFC_BASE + 0x0304U)
#define PFC_IOCTRL2 (PFC_BASE + 0x0308U)
#define PFC_IOCTRL3 (PFC_BASE + 0x030CU)
#define PFC_IOCTRL4 (PFC_BASE + 0x0310U)
#define PFC_IOCTRL5 (PFC_BASE + 0x0314U)
#define PFC_IOCTRL6 (PFC_BASE + 0x0318U)
#define PFC_IOCTRL7 (PFC_BASE + 0x031CU)
#define PFC_IOCTRL8 (PFC_BASE + 0x0320U)
#define PFC_IOCTRL9 (PFC_BASE + 0x0324U)
#define PFC_IOCTRL10 (PFC_BASE + 0x0328U)
#define PFC_IOCTRL11 (PFC_BASE + 0x032CU)
#define PFC_IOCTRL12 (PFC_BASE + 0x0330U)
#define PFC_IOCTRL13 (PFC_BASE + 0x0334U)
#define PFC_IOCTRL14 (PFC_BASE + 0x0338U)
#define PFC_IOCTRL15 (PFC_BASE + 0x033CU)
#define PFC_IOCTRL16 (PFC_BASE + 0x0340U)
#define PFC_IOCTRL17 (PFC_BASE + 0x0344U)
#define PFC_IOCTRL18 (PFC_BASE + 0x0348U)
#define PFC_IOCTRL19 (PFC_BASE + 0x034CU)
#define PFC_IOCTRL30 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
#define PFC_IOCTRL32 (PFC_BASE + 0x0388U)
#define PFC_IOCTRL33 (PFC_BASE + 0x038CU)
#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#endif /* PFC_REGISTER_H__ */

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/*******************************************************************************
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS driver header
******************************************************************************/
#ifndef QOS_INIT_H_
#define QOS_INIT_H_
extern void qos_init(void);
#endif /* QOS_INIT_H_ */

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/*******************************************************************************
* Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS MSTAT table header
******************************************************************************/
#ifndef QOS_MSTAT_H_
#define QOS_MSTAT_H_
typedef struct{
uint16_t offset;
uint64_t mstat_fix;
uint64_t mstat_be;
} QOS_MSTAT_SETTING_TABLE;
const QOS_MSTAT_SETTING_TABLE mstat_v2_tbl[] = {
{0x0278U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0298U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0320U, 0x000C04080000FFFFULL, 0x0000000000000000ULL},
{0x0328U, 0x000C04080000FFFFULL, 0x0000000000000000ULL}
};
const QOS_MSTAT_SETTING_TABLE mstat_tbl[] = {
{0x0000U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0008U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0010U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0018U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL},
{0x0020U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0028U, 0x000C04320000FFFFULL, 0x0000000000000000ULL},
{0x0030U, 0x001004040000FFFFULL, 0x0000000000000000ULL},
{0x0038U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0040U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0048U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0050U, 0x001004280000FFFFULL, 0x0000000000000000ULL},
{0x0058U, 0x001004280000FFFFULL, 0x0000000000000000ULL},
{0x0060U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0068U, 0x001404300000FFFFULL, 0x0000000000000000ULL},
{0x0070U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0078U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0080U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0088U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0090U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x0098U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x00A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00A8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00B0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00B8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00C0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00C8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00D0U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x00D8U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL},
{0x00E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x00E8U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL},
{0x00F0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x00F8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0100U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0108U, 0x000C04010000FFFFULL, 0x0000000000000000ULL},
{0x0110U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0118U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0120U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL},
{0x0128U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0130U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0138U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0140U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL},
{0x0148U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL},
{0x0150U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL},
{0x0158U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0160U, 0x001404280000FFFFULL, 0x0000000000000000ULL},
{0x0168U, 0x001404280000FFFFULL, 0x0000000000000000ULL},
{0x0170U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0178U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0180U, 0x001408280000FFFFULL, 0x0000000000000000ULL},
{0x0188U, 0x000C08200000FFFFULL, 0x0000000000000000ULL},
{0x0190U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x0198U, 0x001004140000FFFFULL, 0x0000000000000000ULL},
{0x01A0U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01A8U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01B0U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x01B8U, 0x000C00000000FFFFULL, 0x0000000000000000ULL},
{0x01C0U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x01C8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01D0U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01D8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01E0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x01E8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x01F0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x01F8U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0200U, 0x001004080000FFFFULL, 0x0000000000000000ULL},
{0x0208U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x0210U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0218U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL},
{0x0220U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0228U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0230U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x0238U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0240U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0248U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0250U, 0x000000000000FFFFULL, 0x0000000000000000ULL},
{0x0258U, 0x001400000000FFFFULL, 0x0000000000000000ULL},
{0x0260U, 0x001400000000FFFFULL, 0x0000000000000000ULL},
{0x0268U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0270U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0278U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x0280U, 0x000C04010000FFFFULL, 0x00100080063FFC01ULL},
{0x0288U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0290U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x0298U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x02A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL},
{0x02A8U, 0x000C04010000FFFFULL, 0x00100060063FFC01ULL},
{0x02B0U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL},
{0x02B8U, 0x001404010000FFFFULL, 0x0000000000000000ULL},
{0x02C0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02C8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02D0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02D8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02E0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL},
{0x02E8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x02F0U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x02F8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0300U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0308U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL},
{0x0310U, 0x000000000000FFFFULL, 0x00100100063FFC01ULL},
{0x0318U, 0x001404010000FFFFULL, 0x0000000000000000ULL}
};
#endif /* QOS_MSTAT_H_ */

146
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/*******************************************************************************
* Copyright (c) 2019-2021 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS Write Training table header
******************************************************************************/
#ifndef QOS_QOSWT_H_
#define QOS_QOSWT_H_
typedef struct{
uint16_t offset;
uint64_t qoswt_fix;
uint64_t qoswt_be;
} QOS_QOSWT_SETTING_TABLE;
const QOS_QOSWT_SETTING_TABLE qoswt_tbl[] = {
{0x0800U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0808U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0810U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0818U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0820U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0828U, 0x000C04320000FFFFULL, 0x0000000000000000ULL},
{0x0830U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0838U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0840U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0848U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0850U, 0x001004200000FFFFULL, 0x0000000000000000ULL},
{0x0858U, 0x001004200000FFFFULL, 0x0000000000000000ULL},
{0x0860U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0868U, 0x001404300000C010ULL, 0x0000000000000000ULL},
{0x0870U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0878U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0880U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0888U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0890U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0898U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08A0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
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{0x08C0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
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{0x08D0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
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{0x08E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x08E8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08F0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x08F8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0900U, 0x0000000000000000ULL, 0x0000000000000000ULL},
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{0x0910U, 0x0000000000000000ULL, 0x0000000000000000ULL},
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{0x0950U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0958U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0960U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0968U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0970U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0978U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
{0x0980U, 0x001404200000FFFFULL, 0x0000000000000000ULL},
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{0x0998U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09A0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09A8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09B0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09B8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09C0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09C8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09D0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09D8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09E0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09E8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09F0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x09F8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A00U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A08U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A10U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A18U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A20U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A28U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A30U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A38U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL},
{0x0A40U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A48U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A50U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A58U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A60U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A68U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A70U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A78U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A80U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A88U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A90U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0A98U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AA0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AA8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AB0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AB8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AC0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AC8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AD0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AD8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AE0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AE8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AF0U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0AF8U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B00U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B08U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B10U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B18U, 0x0000000000000000ULL, 0x0000000000000000ULL},
{0x0B20U, 0x0000000000000000ULL, 0x0000000000000000ULL}, /* Ver.2.x only */
{0x0B28U, 0x0000000000000000ULL, 0x0000000000000000ULL} /* Ver.2.x only */
};
#endif /* QOS_QOSWT_H_ */

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