add IPL

IPL/Customer/Mobis/ca76_loader/memory_cx_ipl.def

@@ -0,0 +1,62 @@
+MEMORY {
+	RAM  (rwxa): ORIGIN = 0x41D00000, LENGTH = 0x000F8000
+	MMU_CPU0   : ORIGIN = 0x41DF8000, LENGTH = 16K
+	SHARED_RAM  (rwa):  ORIGIN = 0x41C00000, LENGTH = 0x0000C000
+	SHARED_SDRAM  (rwa):  ORIGIN = 0x41E00000, LENGTH = 0x00200000
+}
+
+SECTIONS
+{
+	.text : {
+		__RO_START__ = .;
+		*(.text*)
+		*(.rodata*)
+		. = NEXT(64);
+		__RO_END__ = .;
+	} > RAM
+
+	.data : {
+		__DATA_START__ = .;
+		 *(.data)
+		. = NEXT(64);
+		__DATA_END__ = .;
+	} > RAM
+
+	__DATA_SIZE__ = SIZEOF(.data);
+
+	.bss.SHARED_TOP : {
+		__SHARED_TOP_START__ = .;
+		*(.bss.SHARED_TOP)
+		*(.bss.SHARED_LCS)
+		*(.bss.SHARED_CMAC)
+		*(.bss.SHARED_HASH)
+		. = NEXT(0x00200000);
+		__SHARED__END__ = .;
+	} > SHARED_SDRAM
+
+	.SHARED_RAM : {
+		__FWRAM_START__ = .;
+		. += 0;
+		. = NEXT(0x0000C000);
+		__FWRAM_END__ = .;
+	} > SHARED_RAM
+
+	.bss : {
+		__BSS_START__ = .;
+		 *(.bss)
+		 *(COMMON)
+		 . = NEXT(64);
+		__BSS_END__ = .;
+	} > RAM
+
+	stacks (NOLOAD) : ALIGN(64) {
+		__STACKS_START__ = .;
+		KEEP(*(writer_stack))
+		__STACKS_END__ = .;
+	} > RAM
+
+	__BSS_SIZE__ = SIZEOF(.bss);
+}
+
+	MMU_BASE_CPU0    = ORIGIN(MMU_CPU0);
+