add IPL
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288
IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s
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288
IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s
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/**********************************************************/
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/* Sample program : Debug ARM Assembly Program */
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/* File Name : d_armasm.s */
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/* Copyright (C) Renesas Electronics Corp. 2015. */
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/**********************************************************/
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.INCLUDE "boot_mon.h"
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.ALIGN 4
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;# uint32_t MonCp15Mpidr(void);
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STARTFUNC MonCp15Mpidr
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MRS X0, VMPIDR_EL2 ;# read Multiprocessor ID register
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RET
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ENDFUNC MonCp15Mpidr
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;# uint32_t MonCp15Midr(void);
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STARTFUNC MonCp15Midr
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MRS X0, VPIDR_EL2 ;# read Processor ID Register
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RET
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ENDFUNC MonCp15Midr
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;# void WriteTCR_EL3( uint64_t data );
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;# data[63:39]=RES0
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;# data[38][37][36][35][34:32]=TBI1,TBI0,AS,RES0,IPS
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;# data[31:30][29:28][27:26][25:24][23][22][21:16]=TG1,SH1,ORGN1,IRGN1,EPD1,A1 ,T1SZ
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;# data[15:14][13:12][11:10][09:08][07][06][05:00]=TG0,SH0,ORGN0,IRGN0,EPD0,RES0,T0SZ
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STARTFUNC WriteTCR_EL3
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MSR TCR_EL3, X0
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RET
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ENDFUNC WriteTCR_EL3
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;# void WriteMAIR_EL3( uint64_t data );
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;# data[63:56][55:48][47:40][39:32]=Attr7,Attr6,Attr5,Attr4
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;# data[31:24][23:16][15: 8][ 7: 0]=Attr3,Attr2,Attr1,Attr0
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STARTFUNC WriteMAIR_EL3
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MSR MAIR_EL3, X0
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RET
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ENDFUNC WriteMAIR_EL3
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;# void WriteTTBR0_EL3( uint64_t data );
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;# data[63:48]=ASID
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;# data[47: 0]=BADDR
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STARTFUNC WriteTTBR0_EL3
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MSR TTBR0_EL3, X0
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RET
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ENDFUNC WriteTTBR0_EL3
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;# void CleaningAndInvalidateICache(void);
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STARTFUNC CleaningAndInvalidateICache
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IC IALLUIS
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ISB SY
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RET
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ENDFUNC CleaningAndInvalidateICache
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;# Refer: DEN0024A_v8_architecture_PG.pdf
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;# void CleaningDCache(void);
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STARTFUNC CleaningDCache
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MRS X0, CLIDR_EL1
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AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
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LSR W3, W3, #23
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CBZ W3, DC_Finished
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MOV W10, #0 // W10 = 2 x cache level
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MOV W8, #1 // W8 = constant 0b1
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DC_Loop1:
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ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
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LSR W1, W0, W2 // extract 3-bit cache type for this level
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AND W1, W1, #0x7
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CMP W1, #2
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B.LT DC_Skip // No data or unified cache at this level
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MSR CSSELR_EL1, X10 // Select this cache level
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ISB // Synchronize change of CSSELR
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MRS X1, CCSIDR_EL1 // Read CCSIDR
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AND W2, W1, #7 // W2 = log2(linelen)-4
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ADD W2, W2, #4 // W2 = log2(linelen)
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UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
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CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
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LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
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LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
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DC_Loop2:
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UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
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LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
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LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
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DC_Loop3:
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ORR W11, W10, W9 // W11 = combine way number and cache number...
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ORR W11, W11, W7 // ... and set number for DC operand
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DC CSW, X11 // Do data cache clean by set and way
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SUBS W7, W7, W17 // Decrement set number
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B.GE DC_Loop3
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SUBS X9, X9, X16 // Decrement way number
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B.GE DC_Loop2
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DC_Skip:
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ADD W10, W10, #2 // Increment 2 x cache level
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CMP W3, W10
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DSB SY // Ensure completion of previous cache maintenance operation
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B.GT DC_Loop1
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DC_Finished:
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DSB SY ;# Add DSB
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ISB ;# Add ISB
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RET
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ENDFUNC CleaningDCache
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;# Refer: DEN0024A_v8_architecture_PG.pdf
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;# uint32_t CleaningAndInvalidateDCache(void);
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STARTFUNC CleaningAndInvalidateDCache
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MRS X0, CLIDR_EL1
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AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
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LSR W3, W3, #23
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CBZ W3, DCI_Finished
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MOV W10, #0 // W10 = 2 x cache level
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MOV W8, #1 // W8 = constant 0b1
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DCI_Loop1:
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ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
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LSR W1, W0, W2 // extract 3-bit cache type for this level
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AND W1, W1, #0x7
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CMP W1, #2
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B.LT DCI_Skip // No data or unified cache at this level
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MSR CSSELR_EL1, X10 // Select this cache level
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ISB // Synchronize change of CSSELR
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MRS X1, CCSIDR_EL1 // Read CCSIDR
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AND W2, W1, #7 // W2 = log2(linelen)-4
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ADD W2, W2, #4 // W2 = log2(linelen)
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UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
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CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
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LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
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LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
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DCI_Loop2:
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UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
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LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
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LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
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DCI_Loop3:
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ORR W11, W10, W9 // W11 = combine way number and cache number...
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ORR W11, W11, W7 // ... and set number for DC operand
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DC CISW, X11 // Do data cache clean and invalidate by set and way
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SUBS W7, W7, W17 // Decrement set number
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B.GE DCI_Loop3
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SUBS X9, X9, X16 // Decrement way number
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B.GE DCI_Loop2
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DCI_Skip:
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ADD W10, W10, #2 // Increment 2 x cache level
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CMP W3, W10
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DSB SY // Ensure completion of previous cache maintenance operation
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B.GT DCI_Loop1
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DCI_Finished:
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DSB SY ;# Add DSB
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ISB ;# Add ISB
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RET
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ENDFUNC CleaningAndInvalidateDCache
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;# void DCacheEnable(void);
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STARTFUNC DCacheEnable
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MOV X20, X30 ;# Save LR data to X20
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BL SetVmsaTable ;# MMU Table setting
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ISB ;# The ISB forces these changes to be seen before the MMU is enabled.
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MRS X0, SCTLR_EL3 ;# Read System Control Register configuration data
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ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
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ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
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DSB SY
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MSR SCTLR_EL3, X0 ;# Write System Control Register configuration data
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ISB ;# The ISB forces these changes to be seen by the next instruction
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MOV X30, X20 ;# Load LR data from X20
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RET
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ENDFUNC DCacheEnable
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;# void DCacheDisable(void);
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STARTFUNC DCacheDisable
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MOV X20, X30 ;# Save LR data to X20
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DSB SY
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ISB ;#
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MRS X0, SCTLR_EL3 ;#
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;# ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
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;# ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
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bic X0, X0, #1 ;# Set [M] bit and disable the MMU.
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bic X0, X0, #4 ;# Set [C] bit and disable the Data Cache.
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DSB SY
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MSR SCTLR_EL3, X0 ;#
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DSB SY
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ISB ;#
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BL CleaningDCache
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BL CleaningAndInvalidateDCache
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DSB SY
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ISB ;#
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MOV X30, X20 ;# Load LR data from X20
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RET
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ENDFUNC DCacheDisable
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STARTFUNC InterruptDisableDAIF
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MRS X0, DAIF ;# Read DAIF
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LDR W2, =0xC0 ;# bit[7]:IRQ mask bit, bit[6]:FIQ mask bit
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ORR X0,X0,X2 ;# => 0:Exception not masked, 1: Exception masked
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MSR DAIF, X0 ;# Write DAIF
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RET
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ENDFUNC InterruptDisableDAIF
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STARTFUNC ReadSCR_EL3
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MRS X0, SCR_EL3 ;# Read SCR_EL3
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RET
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ENDFUNC ReadSCR_EL3
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STARTFUNC InterruptDisableSCR_EL3
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MRS X0, SCR_EL3 ;# Read SCR_EL3
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LDR W2, =0x6 ;# bit[2]:Physical FIQ Routing, bit[1]:Physical IRQ Routing
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BIC X0,X0,X2 ;# => 0:Interrupt not taken, 1: Interrupt are taken
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MSR SCR_EL3, X0 ;# Write SCR_EL3
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RET
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ENDFUNC InterruptDisableSCR_EL3
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STARTFUNC DropToEl1
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MRS X0, HCR_EL2 ;# Read HCR_EL2
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LDR W2, =0x80000000 ;# bit[31]:EL1 is AArch64
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ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL1 is AArch64
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MSR HCR_EL2, X0 ;# Write HCR_EL2
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MRS X0, SCR_EL3 ;# Read SCR_EL3
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LDR W2, =0x400 ;# bit[10]:EL1 is AArch64
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ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL2/1 are AArch64
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MSR SCR_EL3, X0 ;# Write SCR_EL3
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LDR W0, =0x3C5 ;# bit[3:0]:EL1h
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MSR SPSR_EL3, X0 ;# Write SPSR_EL3
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MOV X0, SP
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MSR SP_EL1,X0
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MOV X0, X30
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MSR ELR_EL3,X0
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ERET
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ENDFUNC DropToEl1
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STARTFUNC UpToEl3
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LDR W0, =0x3CD ;# bit[3:0]:EL3h
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MSR SPSR_EL3, X0 ;# Write SPSR_EL3
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MRS X0, SP_EL1 ;# Read SP_EL1
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MOV SP, X0
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;# MOV X0, X30
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;# MRS X0, ELR_EL1 ;# Read ELR_EL1
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;# MSR ELR_EL3,X0
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RET
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ENDFUNC UpToEl3
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STARTFUNC ChangeNonSecure
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MRS X0, SCR_EL3 ;# Read SCR_EL3
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LDR W2, =0x1 ;# bit[0]:Non-secure bit
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;# LDR W2, =0x481 ;# bit[0]:Non-secure bit
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ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
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MSR SCR_EL3, X0 ;# Write SCR_EL3
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RET
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ENDFUNC ChangeNonSecure
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STARTFUNC ChangeSecure
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MRS X0, SCR_EL3 ;# Read SCR_EL3
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LDR W2, =0x0 ;# bit[0]:Non-secure bit
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ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
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MSR SCR_EL3, X0 ;# Write SCR_EL3
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RET
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ENDFUNC ChangeSecure
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;# void SoftDelayAsm(uint32_t count); <20>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>ON<4F>̏ꍇ<CC8F>A2clock<63><6B>1<EFBFBD><31><EFBFBD>\ (AArch64)
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STARTFUNC SoftDelayAsm ;# <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂܂܌<DC82><DC8C>Z<EFBFBD>Ɏg<C98E>p<EFBFBD><70><EFBFBD><EFBFBD>
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SUBS W0, W0, #1 ;# <20>t<EFBFBD><74><EFBFBD>O<EFBFBD><4F><EFBFBD>X<EFBFBD>V<EFBFBD><56><EFBFBD><C282><C28C>Z 1step
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BNE SoftDelayAsm ;# R0==0<>ɂȂ<C982><C882>܂Ń<DC82><C583>[<5B>v 1step
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RET ;# <20>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>ɖ߂<C996>
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ENDFUNC SoftDelayAsm
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.END
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