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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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29
IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.h Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;#RWDT
;#R-CarH3 77. RCLK Watchdog Timer
.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter
.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A
.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B
;#SystemWDT
;#R-CarH3 78. System Watchdog Timer
.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter
.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A
.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B
.EQU PRR , 0xFFF00044 ;#Product Register
.macro STARTFUNC name
.global \name
.func \name
\name:
.endm
.macro ENDFUNC name
.type \name, %function
.endfunc
.endm

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IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
;# W0-W30 : 32bit Register (W30=Link Register)
;# X0-X30 : 64bit Register (X30=Link Register)
;# WZR : 32bit Zero Register
;# XZR : 64bit Zero Register
;# WSP : 32bit Stack Pointer
;# SP : 64bit Stack Pointer
.INCLUDE "boot_mon.h"
.ALIGN 4
;# Initialize registers
Register_init:
LDR X0, =0
LDR X1, =0
LDR X2, =0
LDR X3, =0
LDR X4, =0
LDR X5, =0
LDR X6, =0
LDR X7, =0
LDR X8, =0
LDR X9, =0
LDR X10, =0
LDR X11, =0
LDR X12, =0
LDR X13, =0
LDR X14, =0
LDR X15, =0
LDR X16, =0
LDR X17, =0
LDR X18, =0
LDR X19, =0
LDR X20, =0
LDR X21, =0
LDR X22, =0
LDR X23, =0
LDR X24, =0
LDR X25, =0
LDR X26, =0
LDR X27, =0
LDR X28, =0
LDR X29, =0
LDR X30, =0
Set_EnableRAM:
;# LDR X0, =0xE67F0018
;# LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM
;# STR W1, [X0]
MRS X0, CurrentEL
CMP X0, #0x0000000C
BEQ current_EL3
current_EL1:
;# Loader
LDR x0, =__STACKS_END__
;# MSR SP_EL0,x0
;# MSR SP_EL1,x0
;# MSR SP_EL2,x0
MOV sp,x0
MOV x0, #0x50000000
MSR ELR_EL1,x0
;# MSR ELR_EL2,x0
;# MSR ELR_EL3,x0
MOV x0, #0x03C5
MSR SPSR_EL1,x0
;# MSR SPSR_EL2,x0
;# MSR SPSR_EL3,x0
;# Enable cache
;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1
orr x0, x0, #(0x1 << 12)
orr x0, x0, #(0x1 << 1)
orr x0, x0, #(0x1 << 3)
msr sctlr_el1, x0
isb
b bss_clr
current_EL3:
;# Loader
LDR x0, =__STACKS_END__
;# MSR SP_EL0,x0
;# MSR SP_EL1,x0
;# MSR SP_EL2,x0
MOV sp,x0
MOV x0, #0xE38
MSR SCR_EL3, x0
MOV x0, #0x44100000
;# MSR ELR_EL1,x0
;# MSR ELR_EL2,x0
MSR ELR_EL3,x0
MOV x0, #0x03C5
;# MSR SPSR_EL1,x0
;# MSR SPSR_EL2,x0
MSR SPSR_EL3,x0
;# Board Initialize
.ifdef Area0Boot
Init_set_WDT:
LDR W0, =RWDT_RWTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled
STR W1, [X0]
Init_set_SYSWDT:
LDR W0, =SYSWDT_WTCSRA
LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
STR W1, [X0]
.endif
;# Enable cache
;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el3
orr x0, x0, #(0x1 << 12)
orr x0, x0, #(0x1 << 1)
orr x0, x0, #(0x1 << 3)
msr sctlr_el3, x0
isb
/* clear bss section */
bss_clr:
mov X0, #0x0
ldr X1, =__BSS_START__
ldr X2, =__BSS_SIZE__
bss_loop:
subs X2, X2, #4
bcc bss_end
str W0, [X1, X2]
b bss_loop
bss_end:
.ifdef Area0Boot
/* copy data section */
ldr X0, =__DATA_COPY_START__
ldr X1, =__DATA_START__
ldr X2, =__DATA_SIZE__
data_loop:
subs X2, X2, #4
bcc data_end
ldr W3, [X0, X2]
str W3, [X1, X2]
b data_loop
.endif
data_end:
;# BL InitScif
BL Main
mov X1, #0x50000000
BR X1
.END

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IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.h Normal file
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/*
* Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved.
*/
#ifndef D_ARMASM_H
#define D_ARMASM_H
void DCacheEnable();
void WriteTCR_EL3(uint64_t data);
void WriteMAIR_EL3(uint64_t data);
void WriteTTBR0_EL3(uint64_t data);
#endif /* D_ARMASM_H */

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IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s Normal file
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/**********************************************************/
/* Sample program : Debug ARM Assembly Program */
/* File Name : d_armasm.s */
/* Copyright (C) Renesas Electronics Corp. 2015. */
/**********************************************************/
.INCLUDE "boot_mon.h"
.ALIGN 4
;# uint32_t MonCp15Mpidr(void);
STARTFUNC MonCp15Mpidr
MRS X0, VMPIDR_EL2 ;# read Multiprocessor ID register
RET
ENDFUNC MonCp15Mpidr
;# uint32_t MonCp15Midr(void);
STARTFUNC MonCp15Midr
MRS X0, VPIDR_EL2 ;# read Processor ID Register
RET
ENDFUNC MonCp15Midr
;# void WriteTCR_EL3( uint64_t data );
;# data[63:39]=RES0
;# data[38][37][36][35][34:32]=TBI1,TBI0,AS,RES0,IPS
;# data[31:30][29:28][27:26][25:24][23][22][21:16]=TG1,SH1,ORGN1,IRGN1,EPD1,A1 ,T1SZ
;# data[15:14][13:12][11:10][09:08][07][06][05:00]=TG0,SH0,ORGN0,IRGN0,EPD0,RES0,T0SZ
STARTFUNC WriteTCR_EL3
MSR TCR_EL3, X0
RET
ENDFUNC WriteTCR_EL3
;# void WriteMAIR_EL3( uint64_t data );
;# data[63:56][55:48][47:40][39:32]=Attr7,Attr6,Attr5,Attr4
;# data[31:24][23:16][15: 8][ 7: 0]=Attr3,Attr2,Attr1,Attr0
STARTFUNC WriteMAIR_EL3
MSR MAIR_EL3, X0
RET
ENDFUNC WriteMAIR_EL3
;# void WriteTTBR0_EL3( uint64_t data );
;# data[63:48]=ASID
;# data[47: 0]=BADDR
STARTFUNC WriteTTBR0_EL3
MSR TTBR0_EL3, X0
RET
ENDFUNC WriteTTBR0_EL3
;# void CleaningAndInvalidateICache(void);
STARTFUNC CleaningAndInvalidateICache
IC IALLUIS
ISB SY
RET
ENDFUNC CleaningAndInvalidateICache
;# Refer: DEN0024A_v8_architecture_PG.pdf
;# void CleaningDCache(void);
STARTFUNC CleaningDCache
MRS X0, CLIDR_EL1
AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
LSR W3, W3, #23
CBZ W3, DC_Finished
MOV W10, #0 // W10 = 2 x cache level
MOV W8, #1 // W8 = constant 0b1
DC_Loop1:
ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
LSR W1, W0, W2 // extract 3-bit cache type for this level
AND W1, W1, #0x7
CMP W1, #2
B.LT DC_Skip // No data or unified cache at this level
MSR CSSELR_EL1, X10 // Select this cache level
ISB // Synchronize change of CSSELR
MRS X1, CCSIDR_EL1 // Read CCSIDR
AND W2, W1, #7 // W2 = log2(linelen)-4
ADD W2, W2, #4 // W2 = log2(linelen)
UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
DC_Loop2:
UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
DC_Loop3:
ORR W11, W10, W9 // W11 = combine way number and cache number...
ORR W11, W11, W7 // ... and set number for DC operand
DC CSW, X11 // Do data cache clean by set and way
SUBS W7, W7, W17 // Decrement set number
B.GE DC_Loop3
SUBS X9, X9, X16 // Decrement way number
B.GE DC_Loop2
DC_Skip:
ADD W10, W10, #2 // Increment 2 x cache level
CMP W3, W10
DSB SY // Ensure completion of previous cache maintenance operation
B.GT DC_Loop1
DC_Finished:
DSB SY ;# Add DSB
ISB ;# Add ISB
RET
ENDFUNC CleaningDCache
;# Refer: DEN0024A_v8_architecture_PG.pdf
;# uint32_t CleaningAndInvalidateDCache(void);
STARTFUNC CleaningAndInvalidateDCache
MRS X0, CLIDR_EL1
AND W3, W0, #0x07000000 // Get 2 x Level of Coherence
LSR W3, W3, #23
CBZ W3, DCI_Finished
MOV W10, #0 // W10 = 2 x cache level
MOV W8, #1 // W8 = constant 0b1
DCI_Loop1:
ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level
LSR W1, W0, W2 // extract 3-bit cache type for this level
AND W1, W1, #0x7
CMP W1, #2
B.LT DCI_Skip // No data or unified cache at this level
MSR CSSELR_EL1, X10 // Select this cache level
ISB // Synchronize change of CSSELR
MRS X1, CCSIDR_EL1 // Read CCSIDR
AND W2, W1, #7 // W2 = log2(linelen)-4
ADD W2, W2, #4 // W2 = log2(linelen)
UBFX W4, W1, #3, #10 // W4 = max way number, right aligned
CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand
LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand
LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
DCI_Loop2:
UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand
LSL W17, W8, W2 // W17 = amount to decrement set number per iteration
DCI_Loop3:
ORR W11, W10, W9 // W11 = combine way number and cache number...
ORR W11, W11, W7 // ... and set number for DC operand
DC CISW, X11 // Do data cache clean and invalidate by set and way
SUBS W7, W7, W17 // Decrement set number
B.GE DCI_Loop3
SUBS X9, X9, X16 // Decrement way number
B.GE DCI_Loop2
DCI_Skip:
ADD W10, W10, #2 // Increment 2 x cache level
CMP W3, W10
DSB SY // Ensure completion of previous cache maintenance operation
B.GT DCI_Loop1
DCI_Finished:
DSB SY ;# Add DSB
ISB ;# Add ISB
RET
ENDFUNC CleaningAndInvalidateDCache
;# void DCacheEnable(void);
STARTFUNC DCacheEnable
MOV X20, X30 ;# Save LR data to X20
BL SetVmsaTable ;# MMU Table setting
ISB ;# The ISB forces these changes to be seen before the MMU is enabled.
MRS X0, SCTLR_EL3 ;# Read System Control Register configuration data
ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
DSB SY
MSR SCTLR_EL3, X0 ;# Write System Control Register configuration data
ISB ;# The ISB forces these changes to be seen by the next instruction
MOV X30, X20 ;# Load LR data from X20
RET
ENDFUNC DCacheEnable
;# void DCacheDisable(void);
STARTFUNC DCacheDisable
MOV X20, X30 ;# Save LR data to X20
DSB SY
ISB ;#
MRS X0, SCTLR_EL3 ;#
;# ORR X0, X0, #1 ;# Set [M] bit and enable the MMU.
;# ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache.
bic X0, X0, #1 ;# Set [M] bit and disable the MMU.
bic X0, X0, #4 ;# Set [C] bit and disable the Data Cache.
DSB SY
MSR SCTLR_EL3, X0 ;#
DSB SY
ISB ;#
BL CleaningDCache
BL CleaningAndInvalidateDCache
DSB SY
ISB ;#
MOV X30, X20 ;# Load LR data from X20
RET
ENDFUNC DCacheDisable
STARTFUNC InterruptDisableDAIF
MRS X0, DAIF ;# Read DAIF
LDR W2, =0xC0 ;# bit[7]:IRQ mask bit, bit[6]:FIQ mask bit
ORR X0,X0,X2 ;# => 0:Exception not masked, 1: Exception masked
MSR DAIF, X0 ;# Write DAIF
RET
ENDFUNC InterruptDisableDAIF
STARTFUNC ReadSCR_EL3
MRS X0, SCR_EL3 ;# Read SCR_EL3
RET
ENDFUNC ReadSCR_EL3
STARTFUNC InterruptDisableSCR_EL3
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x6 ;# bit[2]:Physical FIQ Routing, bit[1]:Physical IRQ Routing
BIC X0,X0,X2 ;# => 0:Interrupt not taken, 1: Interrupt are taken
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC InterruptDisableSCR_EL3
STARTFUNC DropToEl1
MRS X0, HCR_EL2 ;# Read HCR_EL2
LDR W2, =0x80000000 ;# bit[31]:EL1 is AArch64
ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL1 is AArch64
MSR HCR_EL2, X0 ;# Write HCR_EL2
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x400 ;# bit[10]:EL1 is AArch64
ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL2/1 are AArch64
MSR SCR_EL3, X0 ;# Write SCR_EL3
LDR W0, =0x3C5 ;# bit[3:0]:EL1h
MSR SPSR_EL3, X0 ;# Write SPSR_EL3
MOV X0, SP
MSR SP_EL1,X0
MOV X0, X30
MSR ELR_EL3,X0
ERET
ENDFUNC DropToEl1
STARTFUNC UpToEl3
LDR W0, =0x3CD ;# bit[3:0]:EL3h
MSR SPSR_EL3, X0 ;# Write SPSR_EL3
MRS X0, SP_EL1 ;# Read SP_EL1
MOV SP, X0
;# MOV X0, X30
;# MRS X0, ELR_EL1 ;# Read ELR_EL1
;# MSR ELR_EL3,X0
RET
ENDFUNC UpToEl3
STARTFUNC ChangeNonSecure
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x1 ;# bit[0]:Non-secure bit
;# LDR W2, =0x481 ;# bit[0]:Non-secure bit
ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC ChangeNonSecure
STARTFUNC ChangeSecure
MRS X0, SCR_EL3 ;# Read SCR_EL3
LDR W2, =0x0 ;# bit[0]:Non-secure bit
ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure
MSR SCR_EL3, X0 ;# Write SCR_EL3
RET
ENDFUNC ChangeSecure
;# void SoftDelayAsm(uint32_t count); <20>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>ON<4F>̏ꍇ<CC8F>A2clock<63><6B>1<EFBFBD><31><EFBFBD>”\ (AArch64)
STARTFUNC SoftDelayAsm ;# <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̂܂܌<DC82><DC8C>Z<EFBFBD>Ɏg<C98E>p<EFBFBD><70><EFBFBD><EFBFBD>
SUBS W0, W0, #1 ;# <20>t<EFBFBD><74><EFBFBD>O<EFBFBD><4F><EFBFBD>X<EFBFBD>V<EFBFBD><56><EFBFBD>‚Œ<C282><C28C>Z 1step
BNE SoftDelayAsm ;# R0==0<>ɂȂ<C982><C882>܂Ń<DC82><C583>[<5B>v 1step
RET ;# <20>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>ɖ߂<C996>
ENDFUNC SoftDelayAsm
.END

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IPL/Customer/Mobis/ca76_loader/AArch64_boot/stack.s Normal file
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/*
* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
*/
.section writer_stack, "aw", %nobits
.align 5
stacks:
.space (8*1024), 0
.end