woody/Tool
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add IPL

Browse Source
This commit is contained in:
woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

103
IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.c Normal file
View File

@@ -0,0 +1,103 @@
/******************************************************************************/
/* Component Name Customer-implement component */
/******************************************************************************/
/* Product : ICU-M Firmware */
/******************************************************************************/
/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */
/******************************************************************************/
/**********************************************************************************
* Include
***********************************************************************************/
#include "renesas_types.h"
#include "user_icumif_api.h"
/**********************************************************************************
* Globals
***********************************************************************************/
extern void flush_dcache_range(uintptr_t addr, uint32_t size);
extern void inv_dcache_range(uintptr_t addr, uint32_t size);
/**********************************************************************************
* Define
***********************************************************************************/
#define D_CACHE_LINE_ADDR_MASK (0xFFFFFFC0U)
#define D_CACHE_LIMIT_ADDR (0xFFFFFFC0U)
#define CR52_CPSR_IRQ_DISABLE_STATUS (0x00000080U)
#define CR52_PEID (0x00000000u)
#define CA_CPU_ID_MASK (0x0000FF00U)
#define CA_CPU_ID_SHIT (8u)
#define CA_CLUSTER_ID_MASK (0x00FF0000U)
#define CA_CLUSTER_ID_SHIT (16u)
/**********************************************************************************
* Function
***********************************************************************************/
void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size)
{
/* do nothing */
}
void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size)
{
/* do nothing */
}
uint32_t USER_ICUMIF_GetMyPEID(void)
{
uint32_t peid;
#if defined(TARGET_CORTEX_A)
uintptr_t mpidr;
#if defined(AARCH64)
__asm volatile ("mrs %0, MPIDR_EL1" : "=r" (mpidr));
#else
__asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
#endif
peid = ((mpidr & CA_CPU_ID_MASK) >> CA_CPU_ID_SHIT) + (((mpidr & CA_CLUSTER_ID_MASK) >> CA_CLUSTER_ID_SHIT) * 2) + CR52_CPU_NUM;
#elif defined(TARGET_DEVICE_S4X)
peid = CR52_PEID;
#else
uintptr_t mpidr;
__asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
peid = ((mpidr & CA_CPU_ID_MASK) >> CA_CPU_ID_SHIT) + (((mpidr & CA_CLUSTER_ID_MASK) >> CA_CLUSTER_ID_SHIT) * 2);
#endif
return (peid);
}
void USER_ICUMIF_GetLock(uintptr_t *p_saved_psw)
{
uintptr_t saved_psw;
saved_psw = *p_saved_psw;
USER_ICUMIF_GET_LOCK(saved_psw);
*p_saved_psw = saved_psw;
}
void USER_ICUMIF_ReleaseLock(uintptr_t saved_psw)
{
USER_ICUMIF_RELEASE_LOCK(saved_psw);
}
static void USER_ICUMIF_SYNC(void)
{
__asm("dmb sy");
__asm("dsb sy");
__asm("isb");
}
void USER_ICUMIF_Sync(void)
{
USER_ICUMIF_SYNC();
}

97
IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.h Normal file
View File

@@ -0,0 +1,97 @@
/******************************************************************************/
/* Component Name Customer-implement component */
/******************************************************************************/
/* Product : ICU-M Firmware */
/******************************************************************************/
/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */
/******************************************************************************/
#ifndef USER_ICUMIF_API_H_
#define USER_ICUMIF_API_H_
/* Bit pattern of current program status register */
#define FIQ_BIT (0x00000040U)
#define IRQ_BIT (0x00000080U)
#define FIQ_DISABLE (0x00000040U)
#define IRQ_DISABLE (0x00000080U)
#if defined(TARGET_DEVICE_S4X)
#define CR52_CPU_NUM (1u)
#define CA_CPU_NUM (8u)
#else /* TARGET_DEVICE_V4H */
#define CR52_CPU_NUM (3u)
#define CA_CPU_NUM (4u)
#endif
void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size);
void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size);
uint32_t USER_ICUMIF_GetMyPEID(void);
void USER_ICUMIF_GetLock(uintptr_t *p_saved_psw);
void USER_ICUMIF_ReleaseLock(uintptr_t saved_psw);
void USER_ICUMIF_Sync(void);
#if defined(TARGET_CORTEX_A) && defined(AARCH64)
#define USER_ICUMIF_GET_LOCK(X) \
do\
{\
__asm ("mrs %0, DAIF" : "=r" (X));\
if ((IRQ_DISABLE != ((X) & IRQ_BIT)) || (FIQ_DISABLE != ((X) & FIQ_BIT)))\
{\
__asm ("msr DAIFSet, #0x3");\
}\
} while (0)
#else
#define USER_ICUMIF_GET_LOCK(X) \
do\
{\
__asm volatile ("mrs %0, cpsr" : "=r" (X));\
if ((IRQ_DISABLE != ((X) & IRQ_BIT)) || (FIQ_DISABLE != ((X) & FIQ_BIT)))\
{\
__asm ("cpsid if");\
}\
} while (0)
#endif
#if defined(TARGET_CORTEX_A) && defined(AARCH64)
#define USER_ICUMIF_RELEASE_LOCK(X) \
do\
{\
if (FIQ_DISABLE != ((X) & FIQ_BIT))\
{\
__asm ("msr DAIFClr, #0x1");\
}\
else\
{\
}\
if (IRQ_DISABLE != ((X) & IRQ_BIT))\
{\
__asm ("msr DAIFClr, #0x2");\
}\
else\
{\
}\
} while (0)
#else
#define USER_ICUMIF_RELEASE_LOCK(X) \
do\
{\
if (FIQ_DISABLE != ((X) & FIQ_BIT))\
{\
__asm ("cpsie f");\
}\
else\
{\
}\
if (IRQ_DISABLE != ((X) & IRQ_BIT))\
{\
__asm ("cpsie i");\
}\
else\
{\
}\
} while (0)
#endif
#endif /* USER_ICUMIF_API_H_ */