add IPL
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/******************************************************************************/
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/* Component Name ICU-M COMM(PE) Driver */
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/******************************************************************************/
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/* Product : ICU-M Firmware */
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/******************************************************************************/
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/*******************************************************************************
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* Copyright(C) 2021-2023 Renesas Electronics Corporation.
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*
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* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
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*
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* These instructions, statements, and programs are the confidential information
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* of Renesas Electronics Corporation. They must be used and modified solely for
|
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* the purpose for which it was furnished by Renesas Electronics Corporation.
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* All part of them must not be reproduced nor disclosed to others in any form,
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* without the prior written permission of Renesas Electronics Corporation.
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*******************************************************************************/
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#if !defined(ICUM_D_COMM_PE_H)
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#define ICUM_D_COMM_PE_H
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/**************************************************************************************/
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/* Global Pointer Variable */
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/**************************************************************************************/
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/*====================================================================================*/
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/* Shared RAM area address */
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/*====================================================================================*/
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extern uint8_t __ghsbegin_start_gRAM_BANK_A[]; /* Start address ( Bank_A ) */
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extern uint8_t __ghsbegin_end_gRAM_BANK_A[]; /* End address + 1 ( Bank_A ) */
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extern uint8_t __ghsbegin_start_gRAM_MEV[]; /* Start addr ( Exclusion ) */
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/**************************************************************************************/
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/* Definition */
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/**************************************************************************************/
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/* ICUMD Command Register */
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#define ICUM_CMDREGICUM_ICU2PES0 (*(volatile uint32_t*)0xE6610010U)
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#define ICUM_CMDREGICUM_ICU2PES1 (*(volatile uint32_t*)0xE6610128U)
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#define ICUM_CMDREGICUM_ICU2PES2 (*(volatile uint32_t*)0xE6610158U)
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#define ICUM_CMDREGICUM_ICU2PES3 (*(volatile uint32_t*)0xE6610188U)
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#define ICUM_CMDREGICUM_ICU2PES4 (*(volatile uint32_t*)0xE66101B8U)
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#define ICUM_CMDREGICUM_ICU2PES5 (*(volatile uint32_t*)0xE66101E8U)
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#define ICUM_CMDREGICUM_ICU2PES6 (*(volatile uint32_t*)0xE6610218U)
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#define ICUM_CMDREGICUM_ICU2PES7 (*(volatile uint32_t*)0xE6610248U)
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#define ICUM_CMDREGICUM_ICU2PES8 (*(volatile uint32_t*)0xE6610278U)
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#define ICUM_CMDREGICUM_PE2ICUS0 (*(volatile uint32_t*)0xE6610014U)
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#define ICUM_CMDREGICUM_PE2ICUS1 (*(volatile uint32_t*)0xE661012CU)
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#define ICUM_CMDREGICUM_PE2ICUS2 (*(volatile uint32_t*)0xE661015CU)
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#define ICUM_CMDREGICUM_PE2ICUS3 (*(volatile uint32_t*)0xE661018CU)
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#define ICUM_CMDREGICUM_PE2ICUS4 (*(volatile uint32_t*)0xE66101BCU)
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#define ICUM_CMDREGICUM_PE2ICUS5 (*(volatile uint32_t*)0xE66101ECU)
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#define ICUM_CMDREGICUM_PE2ICUS6 (*(volatile uint32_t*)0xE661021CU)
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#define ICUM_CMDREGICUM_PE2ICUS7 (*(volatile uint32_t*)0xE661024CU)
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#define ICUM_CMDREGICUM_PE2ICUS8 (*(volatile uint32_t*)0xE661027CU)
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#define ICUM_CMDREGICUM_PE2ICUFS0 (*(volatile uint32_t*)0xE6610044U)
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#define ICUM_CMDREGICUM_PE2ICUFS1 (*(volatile uint32_t*)0xE6610104U)
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#define ICUM_CMDREGICUM_PE2ICUFS2 (*(volatile uint32_t*)0xE6610134U)
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#define ICUM_CMDREGICUM_PE2ICUFS3 (*(volatile uint32_t*)0xE6610164U)
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#define ICUM_CMDREGICUM_PE2ICUFS4 (*(volatile uint32_t*)0xE6610194U)
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#define ICUM_CMDREGICUM_PE2ICUFS5 (*(volatile uint32_t*)0xE66101C4U)
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#define ICUM_CMDREGICUM_PE2ICUFS6 (*(volatile uint32_t*)0xE66101F4U)
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#define ICUM_CMDREGICUM_PE2ICUFS7 (*(volatile uint32_t*)0xE6610224U)
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#define ICUM_CMDREGICUM_PE2ICUFS8 (*(volatile uint32_t*)0xE6610254U)
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#define ICUM_CMDREGICUM_PE2ICUIE0 (*(volatile uint32_t*)0xE661004CU)
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#define ICUM_CMDREGICUM_PE2ICUIE1 (*(volatile uint32_t*)0xE661010CU)
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#define ICUM_CMDREGICUM_PE2ICUIE2 (*(volatile uint32_t*)0xE661013CU)
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#define ICUM_CMDREGICUM_PE2ICUIE3 (*(volatile uint32_t*)0xE661016CU)
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#define ICUM_CMDREGICUM_PE2ICUIE4 (*(volatile uint32_t*)0xE661019CU)
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#define ICUM_CMDREGICUM_PE2ICUIE5 (*(volatile uint32_t*)0xE66101CCU)
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#define ICUM_CMDREGICUM_PE2ICUIE6 (*(volatile uint32_t*)0xE66101FCU)
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#define ICUM_CMDREGICUM_PE2ICUIE7 (*(volatile uint32_t*)0xE661022CU)
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#define ICUM_CMDREGICUM_PE2ICUIE8 (*(volatile uint32_t*)0xE661025CU)
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#define ICUM_CMDREGICUM_ICU2PEF0 (*(volatile uint32_t*)0xE6610050U)
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#define ICUM_CMDREGICUM_ICU2PEF1 (*(volatile uint32_t*)0xE6610110U)
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#define ICUM_CMDREGICUM_ICU2PEF2 (*(volatile uint32_t*)0xE6610140U)
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#define ICUM_CMDREGICUM_ICU2PEF3 (*(volatile uint32_t*)0xE6610170U)
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#define ICUM_CMDREGICUM_ICU2PEF4 (*(volatile uint32_t*)0xE66101A0U)
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#define ICUM_CMDREGICUM_ICU2PEF5 (*(volatile uint32_t*)0xE66101D0U)
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#define ICUM_CMDREGICUM_ICU2PEF6 (*(volatile uint32_t*)0xE6610200U)
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#define ICUM_CMDREGICUM_ICU2PEF7 (*(volatile uint32_t*)0xE6610230U)
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#define ICUM_CMDREGICUM_ICU2PEF8 (*(volatile uint32_t*)0xE6610260U)
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#define ICUM_CMDREGICUM_ICU2PEFC0 (*(volatile uint32_t*)0xE6610058U)
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#define ICUM_CMDREGICUM_ICU2PEFC1 (*(volatile uint32_t*)0xE6610118U)
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#define ICUM_CMDREGICUM_ICU2PEFC2 (*(volatile uint32_t*)0xE6610148U)
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#define ICUM_CMDREGICUM_ICU2PEFC3 (*(volatile uint32_t*)0xE6610178U)
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#define ICUM_CMDREGICUM_ICU2PEFC4 (*(volatile uint32_t*)0xE66101A8U)
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#define ICUM_CMDREGICUM_ICU2PEFC5 (*(volatile uint32_t*)0xE66101D8U)
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#define ICUM_CMDREGICUM_ICU2PEFC6 (*(volatile uint32_t*)0xE6610208U)
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#define ICUM_CMDREGICUM_ICU2PEFC7 (*(volatile uint32_t*)0xE6610238U)
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#define ICUM_CMDREGICUM_ICU2PEFC8 (*(volatile uint32_t*)0xE6610268U)
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#define ICUM_CMDREGICUM_ICU2PEIE0 (*(volatile uint32_t*)0xE661005CU)
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#define ICUM_CMDREGICUM_ICU2PEIE1 (*(volatile uint32_t*)0xE661011CU)
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#define ICUM_CMDREGICUM_ICU2PEIE2 (*(volatile uint32_t*)0xE661014CU)
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#define ICUM_CMDREGICUM_ICU2PEIE3 (*(volatile uint32_t*)0xE661017CU)
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#define ICUM_CMDREGICUM_ICU2PEIE4 (*(volatile uint32_t*)0xE66101ACU)
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#define ICUM_CMDREGICUM_ICU2PEIE5 (*(volatile uint32_t*)0xE66101DCU)
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#define ICUM_CMDREGICUM_ICU2PEIE6 (*(volatile uint32_t*)0xE661020CU)
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#define ICUM_CMDREGICUM_ICU2PEIE7 (*(volatile uint32_t*)0xE661023CU)
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#define ICUM_CMDREGICUM_ICU2PEIE8 (*(volatile uint32_t*)0xE661026CU)
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#define ICUM_CMDREGICUM_ICU2PEIS0 (*(volatile uint32_t*)0xE6610060U)
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#define ICUM_CMDREGICUM_ICU2PEIS1 (*(volatile uint32_t*)0xE6610120U)
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#define ICUM_CMDREGICUM_ICU2PEIS2 (*(volatile uint32_t*)0xE6610150U)
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#define ICUM_CMDREGICUM_ICU2PEIS3 (*(volatile uint32_t*)0xE6610180U)
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#define ICUM_CMDREGICUM_ICU2PEIS4 (*(volatile uint32_t*)0xE66101B0U)
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#define ICUM_CMDREGICUM_ICU2PEIS5 (*(volatile uint32_t*)0xE66101E0U)
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#define ICUM_CMDREGICUM_ICU2PEIS6 (*(volatile uint32_t*)0xE6610210U)
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#define ICUM_CMDREGICUM_ICU2PEIS7 (*(volatile uint32_t*)0xE6610240U)
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#define ICUM_CMDREGICUM_ICU2PEIS8 (*(volatile uint32_t*)0xE6610270U)
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#define ICUM_CMDREGICUM_PE2ICUSFS (*(volatile uint32_t*)0xE6610074U)
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#define ICUM_CMDREGICUM_SEMAPE00 (*(volatile uint32_t*)0xE66100A0U)
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#define ICUM_CMDREGICUM_SEMAPE01 (*(volatile uint32_t*)0xE66100A4U)
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#define ICUM_CMDREGICUM_SEMAPE02 (*(volatile uint32_t*)0xE66100A8U)
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#define ICUM_CMDREGICUM_SEMAPE03 (*(volatile uint32_t*)0xE66100ACU)
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#define ICUM_CMDREGICUM_SEMAPE04 (*(volatile uint32_t*)0xE66100B0U)
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#define ICUM_CMDREGICUM_SEMAPE05 (*(volatile uint32_t*)0xE66100B4U)
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#define ICUM_CMDREGICUM_SEMAPE06 (*(volatile uint32_t*)0xE66100B8U)
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#define ICUM_CMDREGICUM_SEMAPE07 (*(volatile uint32_t*)0xE66100BCU)
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#define ICUM_CMDREGICUM_SEMAPE08 (*(volatile uint32_t*)0xE66100C0U)
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#define ICUM_CMDREGICUM_SEMAPE0A (*(volatile uint32_t*)0xE66100C8U)
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#define ICUM_CMDREGICUM_SEMAPE0B (*(volatile uint32_t*)0xE66100CCU)
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#define ICUM_CMDREGICUM_SEMAPE0C (*(volatile uint32_t*)0xE66100D0U)
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#define ICUM_CMDREGICUM_SEMAPE0D (*(volatile uint32_t*)0xE66100D4U)
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#define ICUM_CMDREGICUM_SEMAPE0E (*(volatile uint32_t*)0xE66100D8U)
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#define ICUM_CMDREGICUM_SEMAPE0F (*(volatile uint32_t*)0xE66100DCU)
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#define ICUM_CMDREGICUM_SEMAPE10 (*(volatile uint32_t*)0xE66100E0U)
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#define ICUM_CMDREGICUM_SEMAPE11 (*(volatile uint32_t*)0xE66100E4U)
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#define ICUM_CMDREGICUM_SEMAPE12 (*(volatile uint32_t*)0xE66100E8U)
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/* Bit position of initialization process execution state ( INIT_PROCESS_TYPE ) */
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#define PE_QUE_INIT (0U) /* PE queue init */
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#define PE_INTC_INIT (4U) /* PE INTC initialization */
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#define PE_ICU2PEI_INIT (8U) /* PE ICU2PEI initialization */
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/* Execution state of initialization process ( INIT_PROCESS_STATUS ) */
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#define INIT_UNPROCESSED (0U)
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#define INIT_PROCESSED (1U)
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/* Mask pattern of service queue address ( QUE_ADDR_MASK_PATTERN ) */
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#define QUE_ADDR_LOWER_24BITS (0x00FFFFFFU)
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#define QUE_ADDR_UPPER_8BITS_VALUE (0xFF000000U)
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/* Destination PE set value of INTICUP interrupt ( INTICUP_PESEL_PATTERN ) */
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#define INTICUP_PESEL_TO_PE0 (0x00000000U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE1 (0x00000001U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE2 (0x00000002U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE3 (0x00000003U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE4 (0x00000004U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE5 (0x00000006U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE6 (0x00000007U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE7 (0x00000008U) /* Set value (bit 3-0) */
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#define INTICUP_PESEL_TO_PE8 (0x00000009U) /* Set value (bit 3-0) */
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/* Mask pattern for non set PESELs */
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#define INTICUP_ICH_MASK (0xFFFFFFF8U)
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/* Bit position of INTICUP interrupt each PE ( INTICUP_BIT_POSITION ) */
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#define INTICUP_EACH_PE_BIT_WIDTH (3U)
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/* PE Identifier value ( PEID_VALUE ) */
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#define PEID_PE0 (0U)
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#define PEID_PE1 (1U)
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#define PEID_PE2 (2U)
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#define PEID_PE3 (3U)
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#define PEID_MASK (0x000000FU)
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/* Bit position of PE status information ( PE2ICUS_BIT_POSITION ) */
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#define INFO_PE_ST_POSITION (24U)
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/* Bit pattern of PE status information ( INFO_PE_ST_BIT_PATTERN ) */
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#define INFO_PE_ST_FACIACCDIS_BIT (0x00000001U)
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#define INFO_PE_ST_FLS_OPRN_BIT (0x00000001U)
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#define INFO_PE_ST_FLS_DF_PRG_BIT (0x00000001U)
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#define INFO_PE_ST_FLS_CF_PRG_BIT (0x00000001U)
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/* Section address information ( SECTION_ADDRESS_INFO ) */
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#define ADDR_START_SHARED_RAM ((uint32_t *)((void *)__ghsbegin_start_gRAM_BANK_A))
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#define ADDR_END_PLUS1_SHARED_RAM ((uint32_t *)((void *)__ghsbegin_end_gRAM_BANK_A))
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#define PE_SEMAPHORE_RES (0x01000000U)
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#define PE_SEMAPHORE_REQ (0x02000000U)
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#define PE_SEMAPHORE_ERR (0x20000000U)
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#define PE_SEMAPHORE_AUTH_MASK (0xC0000000U)
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#define PE_SEMAPHORE_AUTH_FREE (0x00000000U)
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#define PE_SEMAPHORE_AUTH_GET1ST (0x00000000U)
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#define PE_SEMAPHORE_AUTH_GET2ND (0x80000000U)
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#define PE_SEMAPHORE_WAIT (0x0002645CU)
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#define PE_SEMAPHORE_ER_SYSTEM (0x00000001U)
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#define PE_SEMAPHORE_ER_TIMEOUT (0x00000002U)
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#define PE_SEMAPHORE_ON (0x01U)
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#define PE_SEMAPHORE_OFF (0x00U)
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#define PE_SECURE_MODE_PE0 (0x00000001U)
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#define PE_SECURE_MODE_PE5 (0x00000002U)
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#define PE_SECURE_MODE_PE6 (0x00000004U)
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#define PE_SECURE_MODE_PE1 (0x00000008U)
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#define PE_SECURE_MODE_PE2 (0x00000010U)
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#define PE_SECURE_MODE_PE3 (0x00000020U)
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#define PE_SECURE_MODE_PE4 (0x00000040U)
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#define PE_SECURE_MODE_PE7 (0x00000080U)
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#define PE_SECURE_MODE_PE8 (0x00000100U)
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#define PE_SECURE_MODE_BITOFF (0U)
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#define QUEUE_INDEX_FIRST (0x00U)
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#define QUEUE_INDEX_MAX (0xFFU)
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/* Size of service queue area ( SERVICE_QUEUE_AREA_SIZE ) */
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#define SERV_REQUEST_QUEUE_AREA_SIZE (64U)
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#define SERV_RESPONSE_QUEUE_AREA_SIZE (64U)
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#define TOTAL_SERVICE_QUEUE_AREA_SIZE (SERV_REQUEST_QUEUE_AREA_SIZE + SERV_RESPONSE_QUEUE_AREA_SIZE)
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/* Value for checking number of queue requests per VM ( VM_REQ_QUE_CNT_CHECK ) */
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#define VM_REQ_QUE_CNT_CHECK_OK (0U)
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#define VM_REQ_QUE_CNT_CHECK_REACHED (1U)
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/* Value for RAM area check ( CHECK_VALUE ) */
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#define VALUE_FOR_RAM_AREA_CHECK (0xA5A5A5A5U)
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/*====================================================================================*/
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/* Data pattern of alignment check */
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/*====================================================================================*/
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#define ALIGNMENT_64BYTE_CHECK_PATTERN (0x0000003fU) /* 64 byte alignment */
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#define ALIGNMENT_4BYTE_CHECK_PATTERN (0x00000003U) /* 4 byte alignment */
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#define ALIGNMENT_2BYTE_CHECK_PATTERN (0x00000001U) /* 2 byte alignment */
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/**************************************************************************************/
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/* Type definition */
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/**************************************************************************************/
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/* None */
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/**************************************************************************************/
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/* Enumeration */
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/**************************************************************************************/
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/* None */
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/**************************************************************************************/
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/* Structure Definition */
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/**************************************************************************************/
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typedef struct ICUM_COMM_PE_INFO
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{
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volatile uint32_t* p_icu2pes;
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volatile uint32_t* p_pe2icufs;
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volatile uint32_t* p_pe2icuie;
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volatile uint32_t* p_icu2pef;
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volatile uint32_t* p_icu2pefc;
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volatile uint32_t* p_icu2peie;
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volatile uint32_t* p_icu2peis;
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volatile uint32_t* p_semape;
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volatile uint32_t* p_semape_ns;
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uint32_t inticup_pesel_to_pe;
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uint32_t secure_mode_bit;
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} ICUM_COMM_PE_INFO_t;
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/*====================================================================================*/
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||||
/* Union for pointer manipulation */
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/*====================================================================================*/
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typedef union ptr_manip
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{
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void *p_ptr;
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uint32_t *p_uint32_ptr;
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volatile uint32_t *p_vlt_ptr;
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uintptr_t val;
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} ptr_manip_t;
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/***************************************************************************************/
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/* Prototypes */
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/***************************************************************************************/
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static uint32_t d_COMM_PE_GetSemaphore(uint8_t target_pe, uint8_t request);
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static uint32_t d_COMM_PE_FreeSemaphore(uint8_t target_pe, uint8_t response);
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static void d_COMM_PE_VmRequestCountCheck(uint32_t *p_queptr, r_icumif_vm_id_t vm_id, uint32_t *p_chk_result);
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#endif /* ICUM_D_COMM_PE_H */
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@@ -0,0 +1,461 @@
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/******************************************************************************/
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||||
/* Component Name ICU-M Interface Library (ICUMIF) */
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||||
/******************************************************************************/
|
||||
/* Product : ICU-M Firmware */
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||||
/******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Copyright(C) 2021-2023 Renesas Electronics Corporation.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* These instructions, statements, and programs are the confidential information
|
||||
* of Renesas Electronics Corporation. They must be used and modified solely for
|
||||
* the purpose for which it was furnished by Renesas Electronics Corporation.
|
||||
* All part of them must not be reproduced nor disclosed to others in any form,
|
||||
* without the prior written permission of Renesas Electronics Corporation.
|
||||
*******************************************************************************/
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Header files */
|
||||
/**************************************************************************************/
|
||||
#include "r_icumif_api.h"
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||||
#include "r_icumif_pub.h"
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||||
#include "icum_d_comm_pe_pub.h"
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||||
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||||
#include "r_icumif.h"
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||||
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||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0001]:[ICUMFW_UD_L_IF_0001]
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||||
* Function name: R_ICUMIF_Init
|
||||
* Description : Initialize the ICU-M interface library
|
||||
* Arguments : uint32_t *p_request_queue : Pointer to service request queue
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||||
* Return Value : int32_t Library initialization result
|
||||
* 0 : Successful
|
||||
* Negative values : Parameter error
|
||||
***************************************************************************************/
|
||||
int32_t R_ICUMIF_Init(uint32_t *p_request_queue)
|
||||
{
|
||||
int32_t ret_val = R_ICUMIF_ER_OK;
|
||||
uint32_t call_comm_ret;
|
||||
|
||||
/* 1. address check using Cluster RAM area check function */
|
||||
call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_request_queue), (uint32_t)sizeof(uint32_t) * (uint32_t)TOTAL_QUEUE_LENGTH);
|
||||
if (ER_OK == call_comm_ret)
|
||||
{
|
||||
/* 2. Parameter alignment check */
|
||||
if (0U != ((uint32_t)((uintptr_t)p_request_queue) & ALIGNMENT_4BYTE_CHECK_PATTERN))
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 3. Execute COMM(PE) driver initialization to initialize service queue */
|
||||
call_comm_ret = D_COMM_PE_Init(p_request_queue);
|
||||
|
||||
/* 4. According to result of COMM (PE) driver initialization process, */
|
||||
/* execute respective corresponding processes */
|
||||
if (ER_D_COMM_PARAM_NOT_G_RAM == call_comm_ret)
|
||||
{
|
||||
/* 4-1. Parameters other than shared RAM area, process is terminated */
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
else if (ER_D_COMM_QUE_NOT_ACCESS == call_comm_ret)
|
||||
{
|
||||
/* 4-2. */
|
||||
ret_val = R_ICUMIF_ER_SOFTWARE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 5. Execute interrupt enable process to enable interrupts from ICUP */
|
||||
D_COMM_SetInterruptEnable();
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (ER_D_COMM_ALIGN_NG == call_comm_ret)
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 6. */
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
|
||||
/* 7. */
|
||||
return (ret_val);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0002]:[ICUMFW_UD_L_IF_0002]
|
||||
* Function name: R_ICUMIF_ServiceRequest
|
||||
* Description : Requests ICU-M to execute the service
|
||||
* Arguments : r_icumif_isd_t *p_ISD : Pointer to ISD where request parameter is set
|
||||
* Return Value : int32_t Service execution request result
|
||||
* 0 : Successful
|
||||
* Negative values : Parameter error, Interface library uninitialized
|
||||
***************************************************************************************/
|
||||
int32_t R_ICUMIF_ServiceRequest(r_icumif_isd_t *p_ISD)
|
||||
{
|
||||
int32_t ret_val = R_ICUMIF_ER_OK;
|
||||
uint32_t call_comm_ret;
|
||||
|
||||
/* 1. address check using Cluster RAM area check function */
|
||||
call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_ISD), (uint32_t)sizeof(r_icumif_isd_t));
|
||||
if (ER_OK == call_comm_ret)
|
||||
{
|
||||
/* 2. Parameter alignment check */
|
||||
if (0U != ((uint32_t)((uintptr_t)p_ISD) & ALIGNMENT_4BYTE_CHECK_PATTERN))
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 3-1. Set ID of service request PE */
|
||||
p_ISD->requester_id = (r_icumif_requester_id_t)GET_MY_PEID;
|
||||
|
||||
/* 3-2. Set channel of service execution response interrupt */
|
||||
p_ISD->host_int_ch = ICUM_COMM_ICH_FM_SERV_RESPONSE;
|
||||
|
||||
/* 3-3. Set initial state to service processing state */
|
||||
p_ISD->service_result = SERV_NEW_REQUEST;
|
||||
|
||||
/* 4. In order to check whether area indicated by p_ISD exists in RAM, */
|
||||
/* it checks whether service processing state is SERV_NEW_REQUEST */
|
||||
if (SERV_NEW_REQUEST != p_ISD->service_result)
|
||||
{
|
||||
/* Not SERV_NEW_REQUEST, process is terminated */
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 5. Execute interrupt issue process to issue service execution req interrupt */
|
||||
call_comm_ret = D_COMM_TriggerInterruptToICUP(ICUM_COMM_ICH_TO_SERV_REQUEST, p_ISD);
|
||||
|
||||
/* 6. According to result of interrupt issue process, */
|
||||
/* execute respective corresponding processes */
|
||||
switch (call_comm_ret)
|
||||
{
|
||||
case ER_OK:
|
||||
/* 6-1. Do nothing */
|
||||
break;
|
||||
case ER_D_COMM_QUE_FULL:
|
||||
/* 6-2. */
|
||||
p_ISD->req_res_status = R_ICUMIF_REQRES_PE_RES_DEQUE;
|
||||
p_ISD->service_result = SERV_REQUEST_QUEUE_FULL;
|
||||
ret_val = R_ICUMIF_ER_REQ_QUEUE_FULL;
|
||||
break;
|
||||
case ER_D_COMM_QUE_NOT_INIT:
|
||||
/* 6-3. */
|
||||
ret_val = R_ICUMIF_ER_IF_LIB_NOT_INIT;
|
||||
break;
|
||||
case ER_PARAM:
|
||||
case ER_D_COMM_QUE_NOT_ACCESS:
|
||||
default:
|
||||
/* 6-4. */
|
||||
ret_val = R_ICUMIF_ER_SOFTWARE_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (ER_D_COMM_ALIGN_NG == call_comm_ret)
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 7. */
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
|
||||
/* 8. */
|
||||
return (ret_val);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0003]:[ICUMFW_UD_L_IF_0003]
|
||||
* Function name: R_ICUMIF_ServiceResponse
|
||||
* Description : Acquires ISD from service response queue for self PE
|
||||
* Arguments : None
|
||||
* Return Value : int32_t Service response reception process result
|
||||
* 0 : Successful
|
||||
* Negative values : Interface library uninitialized
|
||||
***************************************************************************************/
|
||||
int32_t R_ICUMIF_ServiceResponse(void)
|
||||
{
|
||||
int32_t ret_val = R_ICUMIF_ER_OK;
|
||||
uint32_t call_comm_ret;
|
||||
uint32_t call_comm_ret_isd;
|
||||
uint32_t exist_isd = 1U;
|
||||
r_icumif_isd_t *p_isd;
|
||||
|
||||
/* Repeat process until there is no ISD in service response queue for self PE */
|
||||
while (1U == exist_isd)
|
||||
{
|
||||
/* 1. Acquires ISD from service response queue for self PE */
|
||||
call_comm_ret = D_COMM_GetResponseISD(&p_isd);
|
||||
|
||||
/* 2. According to result of acquires ISD, */
|
||||
/* execute respective corresponding processes */
|
||||
switch (call_comm_ret)
|
||||
{
|
||||
case ER_OK:
|
||||
case ER_D_COMM_EXIST_ISD:
|
||||
/* 3-1. address check using Cluster RAM area check function */
|
||||
call_comm_ret_isd = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_isd), (uint32_t)sizeof(r_icumif_isd_t));
|
||||
if (ER_OK == call_comm_ret_isd)
|
||||
{
|
||||
/* 3-1-1. For detect that ICU-M could not update ISD, */
|
||||
/* check value of service process state in acquired ISD */
|
||||
if (SERV_NEW_REQUEST == p_isd->service_result)
|
||||
{
|
||||
/* 3-1-1-1. ICU-M could not update ISD */
|
||||
p_isd->service_result = SERV_ISD_NOT_ACCESSIBLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 3-1-1-2. */
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
/* 3-1-2. */
|
||||
if (NULL != p_isd->ptr.p_callbackfunc)
|
||||
{
|
||||
/* 3-1-2-1. If there is registration of callback function, */
|
||||
/* calling callback function */
|
||||
p_isd->ptr.p_callbackfunc(p_isd);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 3-1-2-2. */
|
||||
/* do nothing */
|
||||
}
|
||||
if (ER_OK == call_comm_ret)
|
||||
{
|
||||
exist_isd = 0U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
}
|
||||
else if (ER_D_COMM_ALIGN_NG == call_comm_ret_isd)
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
exist_isd = 0U;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
exist_isd = 0U;
|
||||
}
|
||||
break;
|
||||
case ER_D_COMM_NO_ISD:
|
||||
/* 3-2. No ISD in service response queue, exit from loop process */
|
||||
exist_isd = 0U;
|
||||
break;
|
||||
case ER_D_COMM_QUE_NOT_INIT:
|
||||
/* 3-3. Interface library not initialized */
|
||||
ret_val = R_ICUMIF_ER_IF_LIB_NOT_INIT;
|
||||
exist_isd = 0U;
|
||||
break;
|
||||
case ER_D_COMM_QUE_NOT_ACCESS:
|
||||
default:
|
||||
/* 3-4. Software error */
|
||||
ret_val = R_ICUMIF_ER_SOFTWARE_ERROR;
|
||||
exist_isd = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* 4. Return the service response reception process result */
|
||||
return (ret_val);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0004]:[ICUMFW_UD_L_IF_0004]
|
||||
* Function name: R_ICUMIF_IsServiceCompleted
|
||||
* Description : Check state of service execution requested to ICU-M
|
||||
* Arguments : r_icumif_isd_t *p_ISD : Pointer to ISD that service execution requested
|
||||
* Return Value : int32_t Service execution state
|
||||
* 0 : Service running
|
||||
* Other than 0 : Service execution completion
|
||||
***************************************************************************************/
|
||||
int32_t R_ICUMIF_IsServiceCompleted(r_icumif_isd_t *p_ISD)
|
||||
{
|
||||
int32_t ret_val;
|
||||
uint8_t mem_check = ICUM_COMM_MEMCHECK_OK;
|
||||
uint32_t call_comm_ret;
|
||||
|
||||
/* 1. address check using Cluster RAM area check function */
|
||||
call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_ISD), (uint32_t)sizeof(r_icumif_isd_t));
|
||||
if (ER_OK == call_comm_ret)
|
||||
{
|
||||
/* 2. Parameter alignment check */
|
||||
if (0U != ((uint32_t)((uintptr_t)p_ISD) & ALIGNMENT_4BYTE_CHECK_PATTERN))
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((p_ISD->service_id == SERVICE_01_AES_CMAC) &&
|
||||
((uint32_t)p_ISD->service_priority == R_ICUMIF_SERV_PRIORITY_HIGHEST))
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)D_COMM_GetICUMemCheckErrInfo(&mem_check);
|
||||
}
|
||||
|
||||
if (ICUM_COMM_MEMCHECK_OK == (uint32_t)mem_check)
|
||||
{
|
||||
/* 3. Check service request / response queue transition state in ISD */
|
||||
ret_val = R_ICUMIF_RTN_SERV_RUNNING;
|
||||
|
||||
/* 4. Service execution completion */
|
||||
switch ((uint32_t)p_ISD->req_res_status)
|
||||
{
|
||||
case R_ICUMIF_REQRES_ICUM_RES_ENQUE:
|
||||
if ((uint32_t)p_ISD->res_nointerrupt == R_ICUMIF_REQRES_NOINTERRPUT)
|
||||
{
|
||||
ret_val = R_ICUMIF_RTN_SERV_COMPLETION;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
break;
|
||||
case R_ICUMIF_REQRES_PE_RES_DEQUE:
|
||||
/* 4-1. Check value of service process state in ISD */
|
||||
if (SERV_REQUEST > p_ISD->service_result)
|
||||
{
|
||||
/* 4-1-1. Service execution completion */
|
||||
ret_val = R_ICUMIF_RTN_SERV_COMPLETION;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
break;
|
||||
case R_ICUMIF_REQRES_PE_REQ_ENQUE:
|
||||
if ((uint32_t)p_ISD->req_nointerrupt == R_ICUMIF_REQRES_NOINTERRPUT)
|
||||
{
|
||||
ret_val = R_ICUMIF_RTN_SERV_COMPLETION;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
break;
|
||||
case R_ICUMIF_REQRES_ICUM_REQ_DEQUE:
|
||||
/* 4-2. Service running */
|
||||
/* Initial value */
|
||||
break;
|
||||
default:
|
||||
/* 4-3. */
|
||||
ret_val = R_ICUMIF_ER_SOFTWARE_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (ER_D_COMM_ALIGN_NG == call_comm_ret)
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 5. */
|
||||
ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM;
|
||||
}
|
||||
|
||||
/* 6. */
|
||||
return (ret_val);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0005]:[ICUMFW_UD_L_IF_0005]
|
||||
* Function name: R_ICUMIF_GetStatus
|
||||
* Description : Acquire address value of status information of ICU-M Firmware
|
||||
* Arguments : None
|
||||
* Return Value : r_icumif_sts_t * Address value of ICU-M Firmware status information
|
||||
***************************************************************************************/
|
||||
r_icumif_sts_t *R_ICUMIF_GetStatus(void)
|
||||
{
|
||||
r_icumif_sts_t *p_status;
|
||||
|
||||
/* 1. Acquire address value of status information of ICU-M Firmware */
|
||||
p_status = D_COMM_GetICUStatusAddr();
|
||||
|
||||
/* 2. */
|
||||
return (p_status);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0008]:[ICUMFW_UD_L_IF_0008]
|
||||
* Function name: R_ICUMIF_SetSystemCallBackFunc
|
||||
* Description : Register the function to call back when receiving system interrupt
|
||||
* Arguments : R_ICUMIF_CB_REGIST_t *p_regist_info : Pointer to registration info
|
||||
* Return Value : int32_t Callback registration result
|
||||
* 0 : Successful
|
||||
* Negative values : Parameter error
|
||||
***************************************************************************************/
|
||||
int32_t R_ICUMIF_SetSystemCallBackFunc(R_ICUMIF_CB_REGIST_t *p_regist_info)
|
||||
{
|
||||
int32_t ret_val = R_ICUMIF_ER_OK;
|
||||
uint32_t call_comm_ret;
|
||||
alignment_check_t prm_ptr;
|
||||
|
||||
/* 1. Parameter alignment check ( p_regist_info ) */
|
||||
if (0U != ((uint32_t)((uintptr_t)p_regist_info) & ALIGNMENT_4BYTE_CHECK_PATTERN))
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 2. Parameter alignment check ( callback function address ) */
|
||||
prm_ptr.p_align_check = p_regist_info->p_func_addr;
|
||||
if (0U != (prm_ptr.val_align_check & ALIGNMENT_2BYTE_CHECK_PATTERN))
|
||||
{
|
||||
ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 3. Register the function to call back */
|
||||
call_comm_ret = D_COMM_SetSystemCallBackFunc(p_regist_info);
|
||||
|
||||
/* 4. According to result of callback function regist process, */
|
||||
/* execute respective corresponding processes */
|
||||
switch (call_comm_ret)
|
||||
{
|
||||
case ER_OK:
|
||||
/* 4-1. Do nothing */
|
||||
break;
|
||||
default:
|
||||
/* 4-2. Software error */
|
||||
ret_val = R_ICUMIF_ER_SOFTWARE_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 5. Return callback registration result */
|
||||
return (ret_val);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Function ID : [ICUMFW_CD_L_IF_0010]:[ICUMFW_UD_L_IF_0010]
|
||||
* Function name: R_ICUMIF_IRQ_Handler
|
||||
* Description : Execute interrupt process of ICUP --> PE (INTICUP)
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***************************************************************************************/
|
||||
void R_ICUMIF_IRQ_Handler(void)
|
||||
{
|
||||
D_COMM_IRQ_Handler();
|
||||
}
|
||||
@@ -0,0 +1,60 @@
|
||||
/******************************************************************************/
|
||||
/* Component Name ICU-M Interface Library (ICUMIF) */
|
||||
/******************************************************************************/
|
||||
/* Product : ICU-M Firmware */
|
||||
/******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Copyright(C) 2021-2023 Renesas Electronics Corporation.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* These instructions, statements, and programs are the confidential information
|
||||
* of Renesas Electronics Corporation. They must be used and modified solely for
|
||||
* the purpose for which it was furnished by Renesas Electronics Corporation.
|
||||
* All part of them must not be reproduced nor disclosed to others in any form,
|
||||
* without the prior written permission of Renesas Electronics Corporation.
|
||||
*******************************************************************************/
|
||||
|
||||
#if !defined(R_ICUMIF_H)
|
||||
#define R_ICUMIF_H
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Defines */
|
||||
/**************************************************************************************/
|
||||
|
||||
/*====================================================================================*/
|
||||
/* Data pattern of alignment check */
|
||||
/*====================================================================================*/
|
||||
#define ALIGNMENT_4BYTE_CHECK_PATTERN (0x00000003U) /* 4 byte alignment */
|
||||
#define ALIGNMENT_2BYTE_CHECK_PATTERN (0x00000001U) /* 2 byte alignment */
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Macros */
|
||||
/**************************************************************************************/
|
||||
/* None */
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Type definition */
|
||||
/**************************************************************************************/
|
||||
/* None */
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Enumeration */
|
||||
/**************************************************************************************/
|
||||
/* None */
|
||||
|
||||
/**************************************************************************************/
|
||||
/* Structure Definition */
|
||||
/**************************************************************************************/
|
||||
|
||||
/*====================================================================================*/
|
||||
/* Union for alignment check of pointer value */
|
||||
/*====================================================================================*/
|
||||
typedef union alignment_check
|
||||
{
|
||||
void (*p_align_check)(void);
|
||||
uint32_t val_align_check;
|
||||
} alignment_check_t;
|
||||
|
||||
#endif /* R_ICUMIF_H */
|
||||
|
||||
Reference in New Issue
Block a user