add IPL
This commit is contained in:
387
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S
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387
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S
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@@ -0,0 +1,387 @@
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Image load function
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******************************************************************************/
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/******************************************************************************
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* @file loader_v4h.S
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* - Version : 0.07
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 17.02.2022 0.01 First Release
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* : 09.05.2022 0.02 Removed the last nop instruction
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* : 31.10.2022 0.03 License notation change.
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* : 15.12.2022 0.04 V4H interrupt support.
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* : 28.12.2022 0.05 MPU support.
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* Address acquisition changes in interrupt handlers
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* : 16.02.2023 0.06 Modified instruction to lower case.
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* : 19.12.2024 0.07 Added the process that jump to RTOS#1.
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*****************************************************************************/
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/* SCTLR definitions */
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#define SCTLR_I (1 << 12)
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#define SCTLR_M (1 << 0)
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/* MAIR definitions */
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#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */
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#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
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#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
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#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0)
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#define SUP_EXCEPTION (0x2U)
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#define HYP_EXCEPTION (0x5U)
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#define IRQ_EXCEPTION (0x6U)
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#define FIQ_EXCEPTION (0x7U)
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#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */
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#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
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.global Startup
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.global Vector
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.global dabt_report_exception
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.global pabt_report_exception
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.extern dabort_error
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.extern pabort_error
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.extern Undefined_error
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.extern handler_error
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.align 5
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Vector:
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b Startup /* Reset */
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b Undefined_Handler /* Undefined Instruction */
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b Supervisor_Handler /* Supervisor Call */
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b Prefetch_Handler /* Prefetch Abort */
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b Abort_Handler /* Data Abort */
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b HypTrap_Handler /* Hyp Trap */
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b IRQ_Handler /* IRQ interrupt */
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b FIQ_Handler /* FIQ interrupt */
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/*****************************************************************************
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* Reset Hander
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*****************************************************************************/
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Startup:
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/* initialize registers*/
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/* initialize registers*/
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mov r0, #0
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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mov lr, #0
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ldr r13, =__STACKS_END__
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/* Instruction cache enable */
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mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */
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mrc p15, 0, r1, c1, c0, 0 /* SCTLR */
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bic r0, r0, #SCTLR_M /* M=0 */
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bic r1, r1, #SCTLR_M /* M=0 */
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orr r0, r0, #SCTLR_I /* I=1 */
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orr r1, r1, #SCTLR_I /* I=1 */
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mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
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mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */
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mcr p15, 0, r1, c1, c0, 0 /* SCTLR */
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isb
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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isb
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/* CR52_CONFIGURE_MPU */
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mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */
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mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */
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ldr r0, =MAIR_VAL /* Set MAIR */
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ldr r1, =MAIR_VAL /* Set MAIR */
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mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */
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mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */
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/* region 0: 0x00000000~0x3FFFFFFF */
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ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */
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ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
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mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
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mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
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mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
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/* region 1: 0x40000000~0xBFFFFFFF */
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ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
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mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
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mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
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mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
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/* region 2: 0xC0000000~0xE3FFFFFF */
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ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */
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mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
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mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
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mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
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mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
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/* region 3: 0xE4000000~0xE4FFFFFF */
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ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
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mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
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mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
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mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
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/* region 4: 0xE5000000~0xE62FFFFF */
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ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */
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mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */
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mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */
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mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */
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mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */
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/* region 5: 0xE6300000~0xE632FFFF */
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ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */
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ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */
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mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
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mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
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mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
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mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */
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/* region 6: 0xE6330000~0xE635FFFF */
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ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
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mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
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mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
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mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
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/* region 7: 0xE6360000~0xEB1FFFFF */
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ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */
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mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */
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mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */
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mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */
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mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */
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/* region 8: 0xEB200000~0xEB3FFFFF */
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ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
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mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
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mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
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mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
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/* region 9: 0xEB400000~0xFFFFFFFF */
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ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */
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ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */
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mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */
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mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */
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mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */
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mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */
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/* CR52_SET_MPU_ON */
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mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
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mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
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orr r0, r0, #SCTLR_M /* MPU enable */
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orr r1, r1, #SCTLR_M /* MPU enable */
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mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
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mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
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isb
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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isb
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/* Jump to physical address from mirror address */
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ldr r0, =JUMP_MAIN
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bx r0
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JUMP_MAIN:
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ldr r0, =Vector
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mcr p15, 4, r0, c12, c0, 0 /* HVBAR */
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/* clear bss section */
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mov r0, #0x0
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ldr r1, =__BSS_START__
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ldr r2, =__BSS_SIZE__
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bss_loop:
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subs r2, r2, #4
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bcc bss_end
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str r0, [r1, +r2]
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b bss_loop
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bss_end:
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/* copy data section */
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ldr r0, =__DATA_COPY_START__
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ldr r1, =__DATA_START__
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ldr r2, =__DATA_SIZE__
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data_loop:
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subs r2, r2, #4
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bcc data_end
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ldr r3, [r0, +r2]
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str r3, [r1, +r2]
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b data_loop
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data_end:
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/* Loader Main */
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bl loader_main
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#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
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/* Keep return value from loader_main function (Boot address of RTOS#1) */
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mov r11, r0
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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/* region 0: 0x00000000~0x3FFFFFFF */
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ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */
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ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */
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mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */
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mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */
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mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */
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/* region 1: 0x40000000~0xBFFFFFFF */
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ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */
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ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */
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mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */
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mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */
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mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */
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mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */
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#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
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/* region 2: 0xC0000000~0xE3FFFFFF */
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/* Change MPU setting for RTOS#1. */
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ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */
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||||
ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */
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||||
mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */
|
||||
mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */
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||||
mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */
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||||
mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */
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||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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/* region 3: 0xE4000000~0xE4FFFFFF */
|
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ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */
|
||||
ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */
|
||||
mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */
|
||||
mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */
|
||||
mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */
|
||||
mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */
|
||||
/* region 5: 0xE6300000~0xE632FFFF */
|
||||
ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */
|
||||
ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */
|
||||
mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */
|
||||
mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */
|
||||
mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */
|
||||
mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */
|
||||
/* region 6: 0xE6330000~0xE635FFFF */
|
||||
ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */
|
||||
ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */
|
||||
mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */
|
||||
mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */
|
||||
mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */
|
||||
mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */
|
||||
/* region 8: 0xEB200000~0xEB3FFFFF */
|
||||
ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */
|
||||
ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */
|
||||
mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */
|
||||
mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */
|
||||
mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */
|
||||
mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */
|
||||
|
||||
isb
|
||||
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
|
||||
isb
|
||||
|
||||
/* Instruction cache disable */
|
||||
mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */
|
||||
mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */
|
||||
bic r0, r0, #SCTLR_I /* I=0 */
|
||||
bic r1, r1, #SCTLR_I /* I=0 */
|
||||
mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */
|
||||
mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */
|
||||
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
|
||||
isb
|
||||
|
||||
#if defined(MOBIS_PRK3)
|
||||
/* declare IPL-2nd is finished */
|
||||
ldr r0, =0xEB22FFF4
|
||||
ldr r1, =0xE632FFFF
|
||||
str r1, [r0]
|
||||
#endif
|
||||
#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3))
|
||||
/* Jump to RTOS#1 */
|
||||
bx r11
|
||||
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
|
||||
loader_end:
|
||||
wfi
|
||||
b loader_end
|
||||
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
||||
|
||||
anker:
|
||||
wfi
|
||||
b anker
|
||||
|
||||
/* Undefined Instruction */
|
||||
Undefined_Handler:
|
||||
mrs r0, ELR_hyp
|
||||
b Undefined_error
|
||||
|
||||
/* Supervisor Call */
|
||||
Supervisor_Handler:
|
||||
mov r0, #SUP_EXCEPTION
|
||||
b handler_error
|
||||
|
||||
/* Prefetch Abort */
|
||||
Prefetch_Handler:
|
||||
b pabt_report_exception
|
||||
|
||||
/* Data Abort */
|
||||
Abort_Handler:
|
||||
mrs r0, ELR_hyp
|
||||
b dabt_report_exception
|
||||
|
||||
/* Hyp Trap */
|
||||
HypTrap_Handler:
|
||||
mov r0, #HYP_EXCEPTION
|
||||
b handler_error
|
||||
|
||||
/*IRQ interrupt */
|
||||
IRQ_Handler:
|
||||
mov r0, #IRQ_EXCEPTION
|
||||
b handler_error
|
||||
|
||||
/* FIQ interrupt */
|
||||
FIQ_Handler:
|
||||
mov r0, #FIQ_EXCEPTION
|
||||
b handler_error
|
||||
|
||||
/********************************************************
|
||||
* abort exception
|
||||
********************************************************/
|
||||
dabt_report_exception:
|
||||
mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */
|
||||
mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */
|
||||
b dabort_error
|
||||
|
||||
pabt_report_exception:
|
||||
mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */
|
||||
mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */
|
||||
b pabort_error
|
||||
|
||||
.end
|
||||
Reference in New Issue
Block a user