add IPL
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336
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S
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336
IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Image load function
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******************************************************************************/
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/******************************************************************************
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* @file loader_s4.S
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* - Version : 0.06
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 02.02.2022 0.01 First Release
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* : 27.06.2022 0.02 Remove unused definitions
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* : 02.08.2022 0.03 Support WDT
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* : 31.10.2022 0.04 License notation change.
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* : 14.12.2022 0.05 Support MMU
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* : 17.02.2023 0.06 Modified instruction and General purpose
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* register to lower case.
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*****************************************************************************/
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#include "asm_macros.S"
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/* SCTLR definitions */
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#define SCTLR_M_BIT (1 << 0)
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#define SCTLR_A_BIT (1 << 1)
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#define SCTLR_SA_BIT (1 << 3)
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#define SCTLR_I_BIT (1 << 12)
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#define SCTLR_WXN_BIT (1 << 19)
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#define SCTLR_EE_BIT (1 << 25)
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#define SCTLR_RESET_VAL (SCTLR_SA_BIT)
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#define SCTLR_MMU_ON (SCTLR_M_BIT)
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#define SCTLR_OFF ~(SCTLR_M_BIT | SCTLR_I_BIT | SCTLR_A_BIT)
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/* SCR definitions */
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#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
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#define SCR_TWEDEL_SHIFT (30)
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#define SCR_TWEDEL_MASK (0xf)
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#define SCR_AMVOFFEN_BIT (1 << 35)
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#define SCR_TWEDEn_BIT (1 << 29)
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#define SCR_ECVEN_BIT (1 << 28)
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#define SCR_FGTEN_BIT (1 << 27)
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#define SCR_ATA_BIT (1 << 26)
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#define SCR_FIEN_BIT (1 << 21)
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#define SCR_EEL2_BIT (1 << 18)
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#define SCR_API_BIT (1 << 17)
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#define SCR_APK_BIT (1 << 16)
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#define SCR_TERR_BIT (1 << 15)
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#define SCR_TWE_BIT (1 << 13)
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#define SCR_TWI_BIT (1 << 12)
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#define SCR_ST_BIT (1 << 11)
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#define SCR_RW_BIT (1 << 10)
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#define SCR_SIF_BIT (1 << 9)
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#define SCR_HCE_BIT (1 << 8)
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#define SCR_SMD_BIT (1 << 7)
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#define SCR_EA_BIT (1 << 3)
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#define SCR_FIQ_BIT (1 << 2)
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#define SCR_IRQ_BIT (1 << 1)
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#define SCR_NS_BIT (1 << 0)
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#define SCR_VALID_BIT_MASK (0x2f8f)
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#define SCR_RESET_VAL SCR_RES1_BITS
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/* CPSR/SPSR definitions */
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#define DAIF_FIQ_BIT (1 << 0)
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#define DAIF_IRQ_BIT (1 << 1)
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#define DAIF_ABT_BIT (1 << 2)
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#define DAIF_DBG_BIT (1 << 3)
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#define SPSR_DAIF_SHIFT (6)
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#define SPSR_DAIF_MASK (0xf)
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#define SPSR_AIF_SHIFT (6)
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#define SPSR_AIF_MASK (0x7)
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#define SPSR_E_SHIFT (9)
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#define SPSR_E_MASK (0x1)
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#define SPSR_E_LITTLE (0x0)
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#define SPSR_E_BIG (0x1)
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#define SPSR_T_SHIFT (5)
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#define SPSR_T_MASK (0x1)
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#define SPSR_T_ARM (0x0)
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#define SPSR_T_THUMB (0x1)
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#define SPSR_M_SHIFT (4)
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#define SPSR_M_MASK (0x1)
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#define SPSR_M_AARCH64 (0x0)
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#define SPSR_M_AARCH32 (0x1)
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#define SPSR_EL_SHIFT (2)
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#define SPSR_EL_WIDTH (2)
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/* TCR definitions */
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#define TCR_BIT31_RES1 (1 << 31)
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#define TCR_BIT23_RES1 (1 << 23)
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#define TCR_PS (0 << 16)
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#define TCR_TG0 (0 << 14)
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#define TCR_SH0 (3 << 12)
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#define TCR_ORGN0 (3 << 10)
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#define TCR_IRGN0 (3 << 8)
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#define TCR_T0SZ (32 << 0)
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#define TCR_VAL \
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(TCR_BIT31_RES1 | TCR_BIT23_RES1 | TCR_PS | TCR_TG0 | TCR_SH0 | TCR_ORGN0 | TCR_IRGN0 | TCR_T0SZ)
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/* MAIR definitions */
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#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */
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#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */
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#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */
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#define MAIR_ATTR3 (0x00 << 24)
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#define MAIR_ATTR4 (0x00 << 32)
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#define MAIR_ATTR5 (0x00 << 40)
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#define MAIR_ATTR6 (0x00 << 48)
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#define MAIR_ATTR7 (0x00 << 56)
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#define MAIR_VAL \
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(MAIR_ATTR7 | MAIR_ATTR6 | MAIR_ATTR5 | MAIR_ATTR4 | MAIR_ATTR3 | MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0)
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#define MAIR_INIT_VAL (0x44E048E000098AA4)
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#define BIT_64Cx(nr) (1 << (nr))
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#define SPSR_SSBS_BIT_AARCH64 BIT_64Cx(12)
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#define SPSR_SSBS_BIT_AARCH32 BIT_64Cx(23)
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#define DISABLE_ALL_EXCEPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
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#define MODE_RW_SHIFT (0x4)
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#define MODE_SP_MASK (0x1)
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#define MODE_SP_SHIFT (0x0)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL3 (0x3)
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#define MODE_RW_64 (0x0)
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#define MODE_SP_ELX (0x1)
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#define SPSR_64 (((MODE_RW_64 << MODE_RW_SHIFT) | \
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((MODE_EL3 & MODE_EL_MASK) << MODE_EL_SHIFT) | \
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((MODE_SP_ELX & MODE_SP_MASK) << MODE_SP_SHIFT) | \
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((DISABLE_ALL_EXCEPTIONS & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
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(~(SPSR_SSBS_BIT_AARCH64)))
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.global Startup
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/*****************************************************************************
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* Reset Hander
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*****************************************************************************/
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Startup:
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/* initialize registers*/
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ldr x0, =0
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ldr x1, =0
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ldr x2, =0
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ldr x3, =0
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ldr x4, =0
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ldr x5, =0
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ldr x6, =0
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ldr x7, =0
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ldr x8, =0
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ldr x9, =0
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ldr x10, =0
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ldr x11, =0
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ldr x12, =0
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ldr x13, =0
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ldr x14, =0
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ldr x15, =0
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ldr x16, =0
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ldr x17, =0
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ldr x18, =0
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ldr x19, =0
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ldr x20, =0
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ldr x21, =0
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ldr x22, =0
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ldr x23, =0
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ldr x24, =0
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ldr x25, =0
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ldr x26, =0
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ldr x27, =0
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ldr x28, =0
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ldr x29, =0
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ldr x30, =0
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ldr x0, =__STACKS_END__
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mrs x1, sctlr_el3
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mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
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| SCTLR_SA_BIT | SCTLR_A_BIT))
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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mrs x1, scr_el3
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mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | SCR_FIQ_BIT ) \
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& ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
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orr x0, x0, x1
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msr scr_el3, x0
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/* ---------------------------------------------------------------------
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* Set the exception vectors.
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* ---------------------------------------------------------------------
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*/
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adr x0, loader_exceptions
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msr vbar_el3, x0
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isb
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msr daifclr, #(DAIF_ABT_BIT | DAIF_FIQ_BIT)
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/* ---------------------------------------------------------------------
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* Set the MMU table.
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* ---------------------------------------------------------------------
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*/
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ldr x0 ,=TCR_VAL
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msr tcr_el3, x0
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ldr x0, =MAIR_VAL
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msr mair_el3, x0
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ldr x0, =g_loader_level1_table
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msr ttbr0_el3, x0
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/* ---------------------------------------------------------------------
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* Enable MMU.
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* ---------------------------------------------------------------------
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*/
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isb
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tlbi alle3
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isb
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mrs x0, sctlr_el3
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ldr x1 ,=SCTLR_MMU_ON
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orr x0, x0, x1
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msr sctlr_el3, x0
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dsb sy
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isb
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tlbi alle3
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isb
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/* clear bss section */
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mov x0, #0x0
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ldr x1, =__BSS_START__
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ldr x2, =__BSS_SIZE__
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bss_loop:
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subs x2, x2, #4
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bcc bss_end
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str w0, [x1, x2]
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b bss_loop
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bss_end:
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/* copy data section */
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ldr x0, =__DATA_COPY_START__
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ldr x1, =__DATA_START__
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ldr x2, =__DATA_SIZE__
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data_loop:
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subs x2, x2, #4
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bcc data_end
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ldr w3, [x0, x2]
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str w3, [x1, x2]
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b data_loop
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data_end:
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msr spsel, #0
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ldr x0, =__STACKS_END__
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mov sp, x0
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bl loader_main
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msr elr_el3, x0
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mov x0, #SPSR_64
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msr spsr_el3, x0
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/* ---------------------------------------------------------------------
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* Disable MMU.
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* ---------------------------------------------------------------------
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*/
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mrs x0, sctlr_el3
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ldr x1 ,=SCTLR_OFF
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and x0, x0, x1
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msr sctlr_el3, x0
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dsb sy
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isb
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tlbi alle3
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ic iallu
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/* ---------------------------------------------------------------------
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* Set initial value.
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* ---------------------------------------------------------------------
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*/
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msr ttbr0_el3, xzr
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ldr x0, =MAIR_INIT_VAL
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msr mair_el3, x0
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msr tcr_el3, xzr
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msr vbar_el3, xzr
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isb
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eret
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.end
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