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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM
#define BOOT_INIT_DRAM
extern uint32_t R_DRAM_Init(void);
#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U)
void r_set_pi_rdlvl_interval(void);
#endif
#define INITDRAM_OK (0)
#define INITDRAM_NG (0xFFFFFFFFU)
#define INITDRAM_ERR_I (0xFFFFFFFFU)
#endif /* BOOT_INIT_DRAM */

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk Normal file
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#
# Copyright (c) 2015-2023, Renesas Electronics Corporation All rights reserved.
#
ifeq (${LSI},V4H)
OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram.o
OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram_config.o
else ifeq (${LSI},V4M)
OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram.o
OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram_config.o
endif
OBJ_FILE += ip/ddr/dram_sub_func.o

36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#include <stdint.h>
#include "dram_sub_func.h"
void R_DRAM_Get_Boot_Status(uint32_t *status)
{
*status = DRAM_BOOT_STATUS_COLD;
}
uint32_t R_DRAM_Update_Boot_Status(uint32_t status)
{
uint32_t ret = 0U;
return ret;
}

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef DRAM_SUB_FUNC
#define DRAM_SUB_FUNC
#define DRAM_BOOT_STATUS_COLD (0U)
#define DRAM_BOOT_STATUS_WARM (1U)
void R_DRAM_Get_Boot_Status(uint32_t *status);
uint32_t R_DRAM_Update_Boot_Status(uint32_t status);
#endif /* DRAM_SUB_FUNC_H_ */

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c Normal file
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194
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#include <stdint.h>
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#else
#include "mem_io.h"
#include "log.h"
#endif
#include "boot_init_dram_config.h"
#include "boot_init_dram_regdef.h"
/*******************************************************************************
* PLEASE SET board number or board judge function
******************************************************************************/
// #define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t r_board_judge(void);
uint32_t r_boardcnf_get_brd_type(void)
{
return r_board_judge();
}
#else /* BOARD_JUDGE_AUTO */
uint32_t r_boardcnf_get_brd_type(void)
{
return (2);
}
#endif /* BOARD_JUDGE_AUTO */
/**
* RENESAS WHITE HAWK BOARD EXAMPLE
* @par TraceID Cover_SW_UD:Cover_HW_DD
* V4H-LPDDR5-DDR-SW-UD-01-02:V4H-LPDDR5-DDR-HW-DD-01-04-01
* @param[in] brd Argument for dummy read
* @param[in] clk The pointer which indicate the clock frequency
* @param[in] div The pointer which indicate the clock frequency division
* @details judged by md14/md13\n
* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0)
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1)
*/
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
{
uint32_t md;
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
switch (md)
{
case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */
case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */
case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */
case 0x3U : *clk = 100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */
default : /* nop */ break;
}
(void)brd;
}
/*******************************************************************************
* DDR MBPS TARGET
* PLEASE DEFINE HOW TO JUDGE DDR BPS
******************************************************************************/
/**
* DDRxxxx (judge by md19, md17) : Mbps
* @par TraceID Cover_SW_UD:Cover_HW_DD
* V4H-LPDDR5-DDR-SW-UD-01-03:V4H-LPDDR5-DDR-HW-DD-01-04-02
* @param[in] brd Argument for dummy read
* @param[in] mbps The pointer which indicate the ddr frequency
* @param[in] div The pointer which indicate the ddr frequency division
* @details SSCG enable / disable for PLL1 (judge by md37/md36)
* According to Bit[17] of RST_MODEMR0 and Bit[5:4] of RST_MODEMR1,
* determine the value of ddr mbps and mbps division.
*/
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg)
{
uint32_t md;
uint32_t product;
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
md = (md | (md >> 1)) & 0x03U;
*sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U;
product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
if (product == 0x01U)
{
/* V4H-5 */
switch (md)
{
case 0x0U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
case 0x1U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
case 0x2U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
}
else if (product == 0x02U)
{
/* V4H-3 */
switch (md)
{
case 0x0U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
case 0x1U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
case 0x2U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
}
else
{
/* V4H-7 */
switch (*sscg)
{
case 0x0U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
default : /* nop */ break;
}
break;
case 0x1U :
switch (md)
{
case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
default : /* nop */ break;
}
break;
case 0x2U : /* Not supported */
NOTICE("This MD37/MD36 value is invalid!!\n");panic;
case 0x3U :
switch (md)
{
case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
default : /* nop */ break;
}
break;
default :
/* nop */
break;
}
}
(void)brd;
}
#ifdef BOARD_JUDGE_AUTO
/*******************************************************************************
* SAMPLE board detect function
******************************************************************************/
/**
* Select the setting parameters about the Spieder board you use.
* @par TraceID Cover_SW_UD:Cover_HW_DD
* V4H-LPDDR5-DDR-SW-UD-10:V4H-LPDDR5-DDR-HW-DD-01-03-02
* @return uint32_t Selected table index, this is sample value 0.
* @details Pass the return value from the r_board_judge function.
* In case that "BOARD_JUDGE_AUTO" is not defined, Another process will be called.\n\n
*/
static uint32_t r_board_judge(void)
{
uint32_t brd;
brd = 0U; /* white hawk (64Gbit 1rank)*/
return brd;
}
#endif

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_CONFIG
#define BOOT_INIT_DRAM_CONFIG
#include "boot_init_dram_regdef.h"
//! @details DRAM Param setting
#define JS2_DERATE 0U
//! @details Average periodic refresh interval/Average Refresh Interval [ns]
#define DBSC_REFINT 1920U
#ifndef DBSC_REFINTS
//! 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT.
#define DBSC_REFINTS 0U
#endif
//! @details Periodic-WriteDQ/ReadDQ Training Interval [us]
#define PERIODIC_TRAINING_INTERVAL 20000U
/*******************************************************************************
* NUMBER OF BOARD CONFIGRATION
* PLEASE DEFINE
******************************************************************************/
//! @details Add User platform BOARD
#define BOARDNUM 3U
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
uint32_t r_boardcnf_get_brd_type(void);
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg);
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
typedef struct{
/*
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
0x05...0101B: 24Gb dual channel die / 12Gb single channel die
0x06...0110B: 32Gb dual channel die / 16Gb single channel die
0x07...0111B: 24Gb single channel die
0x08...1000B: 32Gb single channel die
0xFF...NO_MEMORY
*/
uint8_t bdcfg_ddr_density[CS_CNT];
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
uint32_t bdcfg_ca_swap;
/* SoC dqsX([1][0]) -> MEM dqsY: */
uint8_t bdcfg_dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
uint32_t bdcfg_dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
uint8_t bdcfg_dm_swap[SLICE_CNT];
/* SoC ckeX([1][0]) -> MEM csY */
uint8_t bdcfg_cs_swap;
}st_boardcnf_ch_t;
typedef struct {
/* ch in use */
uint8_t bdcfg_phyvalid;
/* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */
uint32_t bdcfg_vref_r;
/* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t bdcfg_vref_w;
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t bdcfg_vref_ca;
/* RFM required check : 0x01 = check enable, 0x00 = check disable */
uint8_t bdcfg_rfm_chk;
//! @details Board parameter about channels
st_boardcnf_ch_t ch[4];
}st_boardcnf_t;
static const st_boardcnf_t boardcnfs[BOARDNUM] = {
/*
* boardcnf[0] RENESAS V4H White Hawk (64Gbit 1rank)
*/
{
0x0FU, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x04506132U,
/* bdcfg_dqs_swap */ 0x01U,
/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U },
/* bdcfg_dm_swap[] */ { 0x03U, 0x07U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x02341065U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U },
/* bdcfg_dm_swap[] */ { 0x00U, 0x02U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[2] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x02150643U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U },
/* bdcfg_dm_swap[] */ { 0x03U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[3] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x01546230U,
/* bdcfg_dqs_swap */ 0x01U,
/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U },
/* bdcfg_dm_swap[] */ { 0x00U, 0x03U },
/* bdcfg_cs_swap */ 0x10U
}
}
},
#if 0 // added from v3.33.3, not used
/*
* boardcnf[1] RENESAS V4H White Hawk (64Gbit 2rank)
*/
{
0x0FU, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
/* bdcfg_ca_swap */ 0x04506132U,
/* bdcfg_dqs_swap */ 0x01U,
/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U },
/* bdcfg_dm_swap[] */ { 0x03U, 0x07U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
/* bdcfg_ca_swap */ 0x02341065U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U },
/* bdcfg_dm_swap[] */ { 0x00U, 0x02U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[2] */ {
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
/* bdcfg_ca_swap */ 0x02150643U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U },
/* bdcfg_dm_swap[] */ { 0x03U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[3] */ {
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
/* bdcfg_ca_swap */ 0x01546230U,
/* bdcfg_dqs_swap */ 0x01U,
/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U },
/* bdcfg_dm_swap[] */ { 0x00U, 0x03U },
/* bdcfg_cs_swap */ 0x10U
}
}
},
#endif
/*
* boardcnf[1] RENESAS V4H (4ch)
*/
{
0x0FU, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[2] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[3] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
}
}
},
/*
* boardcnf[2]MOBIS Proto1 20240717
*/
{
0x0FU, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
/* bdcfg_ca_swap */0x04506132U,
/* bdcfg_dqs_swap */0x01U,
/* bdcfg_dq_swap[] */{ 0x26147085U, 0x12306845U },
/* bdcfg_dm_swap[] */{ 0x03U, 0x07U },
/* bdcfg_cs_swap */0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
/* bdcfg_ca_swap */0x02341065U,
/* bdcfg_dqs_swap */0x10U,
/* bdcfg_dq_swap[] */{ 0x58762314U, 0x71048365U },
/* bdcfg_dm_swap[] */{ 0x00U, 0x02U },
/* bdcfg_cs_swap */0x10U
},
/* ch[2] */ {
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
/* bdcfg_ca_swap */0x02150643U,
/* bdcfg_dqs_swap */0x10U,
/* bdcfg_dq_swap[] */{ 0x58264071U, 0x41207536U },
/* bdcfg_dm_swap[] */{ 0x03U, 0x08U },
/* bdcfg_cs_swap */0x10U
},
/* ch[3] */ {
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
/* bdcfg_ca_swap */0x01546230U,
/* bdcfg_dqs_swap */0x01U,
/* bdcfg_dq_swap[] */{ 0x48761325U, 0x62801745U },
/* bdcfg_dm_swap[] */{ 0x00U, 0x03U },
/* bdcfg_cs_swap */0x10U
}
}
}
};
#endif /* BOOT_INIT_DRAM_CONFIG */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_REGDEF
#define BOOT_INIT_DRAM_REGDEF
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
//! @details The version of DDR code
#define RCAR_DDR_VERSION "rev.1.10"
//! @details The number of channels V4H has
#define DRAM_CH_CNT 0x04U
//! @details The number of slices V4H has
#define SLICE_CNT 0x02U
//! @details The number of chip select V4H has
#define CS_CNT 0x02U
//! @details for pll setting
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
//! @details for ddr density setting
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
//! @details for 16bit value
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */
//! @details Kick bit setting CPG PLL3 division
#define CPG_FRQCRD_KICK_BIT (1U << 31)
//! @details Kick bit to reflect setting CPG PLL3 value
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
//! @details Status bit to check CPG PLL3 works normally
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define CPG_BASE (BASE_CPG_ADDR)
#else
//! @details If this bin is processed by Arm core, address will be "0xE6150000U".
#define CPG_BASE (0xE6150000U)
#endif
//! @details 32-bit readable/writable register
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
//! @details PLL Enable Control Register
#define CPG_PLLECR (CPG_BASE + 0x0820U)
//! @details The register specifies the integer multiplication ratio
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
//! @details The register specifies the fractional multiplication
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
//! @details Functional Safety Reset Check Clear Register
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
//! @details Functional Safety Reset Check Set Register
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
//! @details Functional Safety Reset Check Register A
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
//! @details Software Reset Status Register
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
//! @details Software Reset Clearing Register
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define RST_BASE (BASE_RESET_ADDR)
#else
//! @details If this bin is processed by Arm core, address will be 0xE6160000U.
#define RST_BASE (0xE6160000U)
#endif
//! @details 32-bit read-only register, which is initialized only by POR.
#define RST_MODEMR0 (RST_BASE + 0x0000U)
//! @details 32-bit read-only register, which is initialized only by POR.
#define RST_MODEMR1 (RST_BASE + 0x0004U)
#if defined(__RH850G3K__)
#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR)
#else
#define OTP_MEM_1_BASE (0xE61BF000U)
#endif
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_30 (0x00000020U) /* ver 3.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#else
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif
//! @details DBSC4 System Configuration Register 0
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
//! @details DBSC4 System Configuration Register 1(for DFI domain)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
//! @details DBSC4 System Configuration Register 1(for AXI domain)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
//! @details DBSC4 System Configuration Register 2
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
//! @details PHY type Configuration Register
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
//! @details PHY type Configuration Register 2A
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
//! @details Memory Type register (for DFI domain)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
//! @details Memory Type register (for AXI domain)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
//! @details SDRAM Configuration setting Register (for DFI domain)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
//! @details SDRAM Configuration setting Register (for AXI domain)
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
//! @details DBSC System Register 0(For DFI Domain)
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
//! @details DBSC System Register 0(For AXI Domain)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
//! @details SDRAM Access Enable Register
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
//! @details Auto-Refresh Enable Register
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
//! @details Manual Command-Issuing Register
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
//! @details Operation Complition Waiting Register
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
//! @details SDRAM Operation Setting Register(for DFI domain)
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
//! @details SDRAM Operation Setting Register(for AXI domain)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
//! @details Refresh Configuration Register 1
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
//! @details Refresh Configuration Register 2
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
//! @details SDRAM Callibration Configuration Register
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
//! @details DBI Configuration Register
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
//! @details DFI PHY Master Control Register
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
//! @details DFI Control Update Configuration Register
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
//! @details CAM Unit Operation Setting Register
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
//! @details Read/Write Scheduling Setting Register 1
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
//! @details Data Transfer Cycle Setting
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
//! @details SDRAM Timing Register X
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
//! @details Multirank Operation Setting Register x
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
//! @details DFI Status Interface Input Regiser
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details DFI Status Interface Output Regiser
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Control Register 02
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Lock register
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit register address
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit register access
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Registers Mask for channel
#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Status Register0 ch
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Status Register1 ch
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details Interval Setting for scheduler
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
//! @details Interval Setting for scheduler
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#endif /* BOOT_INIT_DRAM_REGDEF */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef DDR_REGDEF
#define DDR_REGDEF
#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U
#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x10011006U
#define PHY_VREF_INITIAL_STEPSIZE 0x1808100DU
#define PHY_RDLVL_BEST_THRSHLD 0x0004100EU
#define PHY_RDLVL_VREF_OUTLIER 0x1003100EU
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1005102CU
#define PHY_CALVL_VREF_DRIVING_SLICE 0x18011030U
#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A1038U
#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A1038U
#define PHY_WRLVL_STATUS_OBS 0x001C1039U
#define PHY_WRLVL_ERROR_OBS 0x0010103BU
#define PHY_GTLVL_STATUS_OBS 0x0012103DU
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x1009103EU
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x0009103FU
#define PHY_WDQLVL_STATUS_OBS 0x00201043U
#define PHY_DATA_DC_CAL_START 0x1801104DU
#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x1001104EU
#define PHY_REGULATOR_EN_CNT 0x18061050U
#define PHY_VREF_INITIAL_START_POINT 0x00091055U
#define PHY_VREF_INITIAL_STOP_POINT 0x10091055U
#define PHY_VREF_TRAINING_CTRL 0x00021056U
#define PHY_RDDQ0_SLAVE_DELAY 0x0009105DU
#define PHY_RDDQ1_SLAVE_DELAY 0x1009105DU
#define PHY_RDDQ2_SLAVE_DELAY 0x0009105EU
#define PHY_RDDQ3_SLAVE_DELAY 0x1009105EU
#define PHY_RDDQ4_SLAVE_DELAY 0x0009105FU
#define PHY_RDDQ5_SLAVE_DELAY 0x1009105FU
#define PHY_RDDQ6_SLAVE_DELAY 0x00091060U
#define PHY_RDDQ7_SLAVE_DELAY 0x10091060U
#define PHY_RDDM_SLAVE_DELAY 0x00091061U
#define PHY_RX_CAL_ALL_DLY 0x18061061U
#define PHY_RX_PCLK_CLK_SEL 0x00031062U
#define PHY_DATA_DC_CAL_CLK_SEL 0x18031063U
#define PHY_PAD_VREF_CTRL_DQ 0x000E1067U
#define PHY_PER_CS_TRAINING_EN 0x00011068U
#define PHY_RDDATA_EN_TSEL_DLY 0x18051069U
#define PHY_RDDATA_EN_OE_DLY 0x0005106AU
#define PHY_RPTR_UPDATE 0x1004106CU
#define PHY_WRLVL_RESP_WAIT_CNT 0x0806106DU
#define PHY_RDLVL_DLY_STEP 0x08041070U
#define PHY_RDLVL_MAX_EDGE 0x00091071U
#define PHY_RDDATA_EN_DLY 0x10051076U
#define PHY_DQ_DM_SWIZZLE0 0x00201077U
#define PHY_DQ_DM_SWIZZLE1 0x00041078U
#define PHY_CLK_WRDQS_SLAVE_DELAY 0x0009107EU
#define PHY_WRITE_PATH_LAT_DEC 0x1001107EU
#define PHY_RDDQS_GATE_SLAVE_DELAY 0x00091088U
#define PHY_RDDQS_LATENCY_ADJUST 0x10051088U
#define PHY_WRITE_PATH_LAT_ADD 0x18031088U
#define PHY_WRITE_PATH_LAT_FRAC 0x00081089U
#define PHY_GTLVL_LAT_ADJ_START 0x0005108AU
#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U
#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U
#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U
#define PHY_ADR_CALVL_OBS1 0x0020120AU
#define PHY_ADR_CALVL_OBS2 0x0020120BU
#define PHY_ADR_CALVL_DLY_STEP 0x00041210U
#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U
#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U
#define PHY_CSLVL_OBS1 0x00201221U
#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU
#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U
#define PHY_FREQ_SEL_INDEX 0x10021301U
#define SC_PHY_MANUAL_UPDATE 0x18011304U
#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U
#define PHY_CAL_MODE_0 0x000D132CU
#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU
#define PHY_DATA_BYTE_ORDER_SEL 0x0020133EU
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x10031348U
#define PHY_PLL_CTRL 0x000E134BU
#define PHY_PLL_CTRL_8X 0x100E134BU
#define PHY_CAL_CLK_SELECT_0 0x00031360U
#define SC_PHY_WCK_CALC 0x1801101AU
#define PI_START 0x00010800U
#define PI_TRAIN_ALL_FREQ_REQ 0x18010802U
#define PI_CS_MAP 0x08020813U
#define PI_WRLVL_REQ 0x1001081CU
#define PI_WRLVL_CS_SW 0x1802081CU
#define PI_RDLVL_REQ 0x18010824U
#define PI_RDLVL_GATE_REQ 0x00010825U
#define PI_RDLVL_CS_SW 0x08020825U
#define PI_DRAMDCA_FLIP_MASK 0x0802083BU
#define PI_DRAMDCA_LVL_REQ 0x1001083DU
#define PI_DCMLVL_CS_SW 0x1802083DU
#define PI_WRDCM_LVL_EN_F1 0x0002083FU
#define PI_DRAMDCA_LVL_EN_F1 0x0802083FU
#define PI_WRDCM_LVL_EN_F2 0x1802083FU
#define PI_DRAMDCA_LVL_EN_F2 0x00020840U
#define PI_TCKCKEL_F2 0x1804089DU
#define PI_INT_STATUS 0x00200900U
#define PI_INT_ACK_0 0x00200902U
#define PI_INT_ACK_1 0x00030903U
#define PI_ADDR_MUX_0 0x00030910U
#define PI_ADDR_MUX_1 0x08030910U
#define PI_ADDR_MUX_2 0x10030910U
#define PI_ADDR_MUX_3 0x18030910U
#define PI_ADDR_MUX_4 0x00030911U
#define PI_ADDR_MUX_5 0x08030911U
#define PI_ADDR_MUX_6 0x10030911U
#define PI_DATA_BYTE_SWAP_EN 0x18010911U
#define PI_DATA_BYTE_SWAP_SLICE0 0x00010912U
#define PI_DATA_BYTE_SWAP_SLICE1 0x08010912U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00080964U
#define PI_WRLAT_F2 0x1007096AU
#define PI_TWCKENL_WR_ADJ_F2 0x1806096AU
#define PI_TWCKENL_RD_ADJ_F2 0x0006096BU
#define PI_TWCKPRE_STATIC_F2 0x0806096BU
#define PI_TWCKPRE_TOGGLE_RD_F2 0x1806096BU
#define PI_TWCKENL_FS_ADJ_F2 0x0006096CU
#define PI_CASLAT_F2 0x0807096CU
#define PI_TRFC_F2 0x000A0971U
#define PI_TREF_F2 0x00140972U
#define PI_TDFI_WRLVL_WW_F0 0x000A0974U
#define PI_TDFI_WRLVL_WW_F1 0x000A0975U
#define PI_WRLVL_EN_F2 0x18020975U
#define PI_TDFI_WRLVL_WW_F2 0x000A0976U
#define PI_WRLVL_WCKOFF_F2 0x10080976U
#define PI_RDLVL_EN_F2 0x1802097AU
#define PI_RDLVL_GATE_EN_F2 0x0002097BU
#define PI_RDLVL_VREF_EN_F0 0x1004097BU
#define PI_RDLVL_VREF_EN_F1 0x0004097DU
#define PI_RDLVL_VREF_EN_F2 0x1004097EU
#define PI_RDLAT_ADJ_F2 0x00090981U
#define PI_WRLAT_ADJ_F2 0x00070982U
#define PI_TDFI_CALVL_CC_F2 0x000A0985U
#define PI_TDFI_CALVL_CAPTURE_F2 0x100A0985U
#define PI_CALVL_EN_F2 0x10020986U
#define PI_TCAENT_F2 0x000E0989U
#define PI_TVREF_SHORT_F2 0x000A098FU
#define PI_TVREF_LONG_F2 0x100A098FU
#define PI_TVRCG_ENABLE_F2 0x000A0990U
#define PI_TVRCG_DISABLE_F2 0x100A0990U
#define PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00070991U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x08070991U
#define PI_CALVL_VREF_INITIAL_START_POINT_F1 0x18070991U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00070992U
#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070992U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070992U
#define PI_TDFI_CALVL_STROBE_F2 0x08040995U
#define PI_TXP_F2 0x10050995U
#define PI_TMRWCKEL_F2 0x18080995U
#define PI_TCKEHDQS_F2 0x1006099DU
#define PI_TFC_F2 0x000A099EU
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100709A0U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180709A0U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000709A4U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080709A4U
#define PI_TDFI_WDQLVL_WR_F2 0x000A09A6U
#define PI_TDFI_WDQLVL_RW_F2 0x100A09A6U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x000709A7U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x080709A7U
#define PI_WDQLVL_EN_F2 0x180209A7U
#define PI_MBIST_RDLAT_ADJ_F2 0x080909A8U
#define PI_MBIST_TWCKENL_RD_ADJ_F2 0x180609A8U
#define PI_TRTP_F2 0x180809B3U
#define PI_TRP_F2 0x000809B4U
#define PI_TRCD_F2 0x080809B4U
#define PI_TWTR_S_F2 0x180609B4U
#define PI_TWTR_L_F2 0x000609B5U
#define PI_TWTR_F2 0x100609B5U
#define PI_TWR_F2 0x180809B5U
#define PI_TRAS_MIN_F2 0x100909B6U
#define PI_TDQSCK_MAX_F2 0x000409B7U
#define PI_TSR_F2 0x100809B7U
#define PI_TMRD_F2 0x180809B7U
#define PI_TDFI_CTRLUPD_MAX_F2 0x001509BCU
#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x002009BDU
#define PI_TINIT_F2 0x001809CCU
#define PI_TINIT1_F2 0x001809CDU
#define PI_TINIT3_F2 0x001809CEU
#define PI_TINIT4_F2 0x001809CFU
#define PI_TINIT5_F2 0x001809D0U
#define PI_TXSNR_F2 0x001009D1U
#define PI_TZQCAL_F2 0x100C09D6U
#define PI_TZQLAT_F2 0x000709D7U
#define PI_ZQRESET_F2 0x100C09D8U
#define PI_TDQ72DQ_F2 0x100A09DDU
#define PI_TCBTRTW_F2 0x000609DEU
#define PI_MC_TRFC_F2 0x000A09E1U
#define PI_CKE_MUX_0 0x000309E6U
#define PI_CKE_MUX_1 0x080309E6U
#define PI_SEQ_DEC_SW_CS 0x00020A4EU
#define PI_SW_SEQ_START 0x10010A4EU
#define PI_SW_SEQ_0 0x001B0BF1U
#define PI_SW_SEQ_1 0x001B0BF2U
#define PI_DFS_ENTRY_SEQ_0 0x001D0BFBU
#define PI_DFS_INITIALIZATION_SEQ_1 0x001D0C24U
#define PI_DFS_INITIALIZATION_SEQ_9 0x001D0C2CU
#define PI_DFS_INITIALIZATION_SEQ_10 0x001D0C2DU
#define PI_SEQ_WAIT_16_F2 0x00180C77U
#define PI_SEQ_WAIT_17_F2 0x00180C7AU
#define PI_SEQ_WAIT_18_F2 0x00180C7DU
#define PI_SEQ_WAIT_19_F2 0x00180C80U
#define PI_SEQ_WAIT_20_F2 0x00180C83U
#define PI_SEQ_WAIT_21_F2 0x00180C86U
#define PI_SEQ_WAIT_22_F2 0x00180C89U
#define PI_SEQ_WAIT_23_F2 0x00180C8CU
#define PI_SEQ_WAIT_24_F2 0x00180C8FU
#define PI_SEQ_WAIT_25_F2 0x00180C92U
#define PI_SEQ_WAIT_26_F2 0x00180C95U
#define PI_SEQ_WAIT_30_F2 0x00180CA1U
#define PI_DARRAY3_0_CS0_F0 0x00080D0BU
#define PI_DARRAY3_1_CS0_F0 0x08080D0BU
#define PI_DARRAY3_0_CS0_F1 0x00080D15U
#define PI_DARRAY3_1_CS0_F1 0x08080D15U
#define PI_DARRAY3_0_CS0_F2 0x00080D1FU
#define PI_DARRAY3_1_CS0_F2 0x08080D1FU
#define PI_DARRAY3_4_CS0_F2 0x00080D20U
#define PI_DARRAY3_20_CS0_F2 0x00080D24U
#define PI_DARRAY3_0_CS1_F0 0x00080D29U
#define PI_DARRAY3_1_CS1_F0 0x08080D29U
#define PI_DARRAY3_0_CS1_F1 0x00080D33U
#define PI_DARRAY3_1_CS1_F1 0x08080D33U
#define PI_DARRAY3_0_CS1_F2 0x00080D3DU
#define PI_DARRAY3_1_CS1_F2 0x08080D3DU
#define PI_DARRAY3_4_CS1_F2 0x00080D3EU
#define PI_DARRAY3_20_CS1_F2 0x00080D42U
#define PI_DLL_RST 0x00010941U
#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU
#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU
#define PI_RDLVL_TRAIN_SEQ_1 0x001B0C42U
#define PI_RDLVL_TRAIN_SEQ_2 0x001B0C43U
#define PI_RDLVL_TRAIN_SEQ_3 0x001B0C44U
#define PI_RDLVL_TRAIN_SEQ_4 0x001B0C45U
#define PI_RDLVL_TRAIN_SEQ_5 0x001B0C46U
#define PI_WDQLVL_VREF_EN 0x0804089EU
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 0x001B0868U
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 0x001B0869U
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 0x001B086AU
#define PHY_PER_CS_TRAINING_INDEX 0x18011006U
#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008108CU
#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021075U
#define PI_WDQLVL_PERIODIC 0x000108A0U
#define PHY_MEAS_DLY_STEP_ENABLE 0x08061076U
#define PI_RDLVL_PERIODIC 0x0801082EU
#define PI_LONG_COUNT_MASK 0x1005090FU
#define PI_WDQLVL_INTERVAL 0x001008A4U
#define PI_RDLVL_INTERVAL 0x08100835U
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)
#endif /* DDR_REGDEF */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC initialize function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4h.c
* - Version : 0.06
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 09.08.2022 0.01 First Release
* : 16.11.2022 0.02 Change ecc_enable to ecc_sdram_enable
* : 04.04.2023 0.03 Removed stdio.h and string.h.
* : 20.09.2023 0.04 Update the ecc_sdram_enable function according to HWSAN rev0.82.
* : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 27.01.2025 0.06 Remove unused functions.
*****************************************************************************/
#include <stdint.h>
#if (ECC_ENABLE == 1)
#include "ecc_enable_v4h.h"
#include "ecm_enable_v4h.h"
#include "mem_io.h"
#include "v4h/lpddr5/boot_init_dram_regdef.h"
/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
void ecc_sdram_enable(void)
{
NOTICE("ECC for DRAM is enable.\n");
uint32_t ecm_tmp;
/* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
mem_write32(DB0SYSCNT0, 0x00001234U);
mem_write32(DB1SYSCNT0, 0x00001234U);
mem_write32(DB0SYSCNT0A, 0x00001234U);
mem_write32(DB1SYSCNT0A, 0x00001234U);
/* (A) Setting ECM */
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 3, 1 of ECMERRTGTR0 to 0 and bit 3, 1 of ECMERRCTLR0 to 1. */
ecm_tmp = mem_read32(ECMERRTGTR0);
ecm_tmp &= ~(0xAU);
ecm_write(ECMERRTGTR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRCTLR0);
ecm_tmp |= (0xAU);
ecm_write(ECMERRCTLR0, ecm_tmp);
/* (B) Setting ECC protection area */
/* Set the bottom row address of the ECC protection area */
mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
mem_write32(DB1FSDRAMECCAREA00, ECC_PROT_SIZE10);
/* (C) Initialization for DRAM */
mem_write32(DBSC_DB0ACEN, 0x00000000U);
mem_write32(DBSC_DB1ACEN, 0x00000000U);
/*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
mem_write32(DB0FSCONF00A, 0x0U);
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
mem_write32(DB0FSCTRL01A, 0x01U);
/*** Initialization for DRAM connected to DBS1 Initialize RANK0 in according with the following procedure.***/
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB1FSCONF00A[1:0]. */
mem_write32(DB1FSCONF00A, 0x0U);
/* [Step2] Set the start row address of the initialization area in DB1FSCONF01A[31:0]. */
mem_write32(DB1FSCONF01A, START_ECC_INIT_AREA10);
/* [Step3] Set the end row address of the initialization area in DB1FSCONF02A[31:0]. */
mem_write32(DB1FSCONF02A, END_ECC_INIT_AREA10);
/* [Step4] Set 0x1 to DB1FSCTRL01A[0] to start initialization. */
mem_write32(DB1FSCTRL01A, 0x01U);
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
/* [Step5] When DB1FSSTAT01A[0] is set to 0x1, DBS1/RANK0 initialization is complete.*/
NOTICE("DRAM rank 0 of DBSC0/1 is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB0FSSTAT01A);
ecm_tmp &= mem_read32(DB1FSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* (D) Setting ECC protection enable */
/* Enable ECC protection for dbs0/rank0 by setting 0x1 in DB0FSCONFAXI0[8]. */
ecm_tmp = mem_read32(DB0FSCONFAXI0);
ecm_tmp |= (0x1U << 8U);
mem_write32(DB0FSCONFAXI0, ecm_tmp);
/* Enable ECC protection for dbs1/rank0 by setting 0x1 in DB1FSCONFAXI0[8]. */
ecm_tmp = mem_read32(DB1FSCONFAXI0);
ecm_tmp |= (0x1U << 8U);
mem_write32(DB1FSCONFAXI0, ecm_tmp);
/* (E) System RAM initialization */
NOTICE("System RAM of DBSC0 is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB0FSSTAT00A);
} while (ecm_tmp != 0x1U);
NOTICE("System RAM of DBSC1 is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB1FSSTAT00A);
} while (ecm_tmp != 0x1U);
/* (F) Setting for ECC error interrupt */
/* (1) Set the ECC error interrupt for read data. */
mem_write32(DB0FSINTENB02A, 0xFF00U);
mem_write32(DB1FSINTENB02A, 0xFF00U);
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
ecm_tmp = mem_read32(DB0FSINTENB02A);
ecm_tmp |= 0xFF000000U;
mem_write32(DB0FSINTENB02A, ecm_tmp);
ecm_tmp = mem_read32(DB1FSINTENB02A);
ecm_tmp |= 0xFF000000U;
mem_write32(DB1FSINTENB02A, ecm_tmp);
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
mem_write32(DB1FSINTENB04A, 0xFFFFFFFFU);
/* Lock the ECM registers */
ecm_lock();
/* Enable the write protect of ECM registers */
mem_write32(DBSC_DB0ACEN, 0x00000001U);
mem_write32(DBSC_DB1ACEN, 0x00000001U);
/* Enable the access protect for DBSC registers */
mem_write32(DB0SYSCNT0, 0x00000000U);
mem_write32(DB1SYSCNT0, 0x00000000U);
mem_write32(DB0SYSCNT0A, 0x00000000U);
mem_write32(DB1SYSCNT0A, 0x00000000U);
}
#endif /* ECC_ENABLE == 1 */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
/* DBSC registers */
#if defined(__RH850G3K__)
#include "remap_register.h"
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#if (ECC_ENABLE == 1)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif /* ECC_ENABLE == 1 */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#if (ECC_ENABLE == 1)
void ecc_sdram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U)
#endif /* ECC_ENABLE == 1 */
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#if (ECC_ENABLE == 1)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U)
#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0xCCCCU)
#define ECC_PROT_SIZE01 (0xCCCCU)
#define ECC_PROT_SIZE10 (0xCCCCU)
#define ECC_PROT_SIZE11 (0xCCCCU)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x0000CCCBU)
#define END_ECC_INIT_AREA10 (0x0000CCCBU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x0000CCCBU)
#define END_ECC_INIT_AREA11 (0x0000CCCBU)
/*********** Other settings cannot be changed ***************/
#endif /* ECC_ENABLE == 1 */
#endif/* ECC_PROTECT */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4h.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4h.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
#include "ecc_enable_v4h.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define ECM_ERR_REG_MAX (40U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_error_enable(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250000U, 0xFFFFF00FU}, /* ECMERRCTLR0 */
[1] = {0xE6250004U, 0xFFF8C000U}, /* ECMERRCTLR1 */
[2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xE6250014U, 0xFFFFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
[7] = {0xE625001CU, 0x6F980FFFU}, /* ECMERRCTLR7 */
[8] = {0xE6250020U, 0xFFF00000U}, /* ECMERRCTLR8 */
[9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
[10] = {0xE6250028U, 0x557D554FU}, /* ECMERRCTLR10 */
[11] = {0xE625002CU, 0xFFFC1555U}, /* ECMERRCTLR11 */
[12] = {0xE6250030U, 0x5557FFFFU}, /* ECMERRCTLR12 */
[13] = {0xE6250034U, 0x00000055U}, /* ECMERRCTLR13 */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[14] = {0xE6250040U, 0x3FFFFFFFU}, /* ECMERRCTLR16 */
[15] = {0xE6250044U, 0x2FFF8CE0U}, /* ECMERRCTLR17 */
[16] = {0xE6250048U, 0x0EC03FFFU}, /* ECMERRCTLR18 */
[17] = {0xE625004CU, 0xFFFFFFF9U}, /* ECMERRCTLR19 */
[18] = {0xE6250050U, 0xFE66667EU}, /* ECMERRCTLR20 */
[19] = {0xE6250054U, 0xBFE3BE0FU}, /* ECMERRCTLR21 */
[20] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
[21] = {0xE625005CU, 0x7EF3C008U}, /* ECMERRCTLR23 */
[22] = {0xE6250060U, 0x7FFE8ADBU}, /* ECMERRCTLR24 */
[23] = {0xE6250064U, 0xCF807FFFU}, /* ECMERRCTLR25 */
[24] = {0xE6250068U, 0x7EF3C008U}, /* ECMERRCTLR26 */
[25] = {0xE625006CU, 0x7FFE8ADBU}, /* ECMERRCTLR27 */
[26] = {0xE6250070U, 0xCF807FFFU}, /* ECMERRCTLR28 */
[27] = {0xE6250074U, 0x0073C008U}, /* ECMERRCTLR29 */
[28] = {0xE6250078U, 0x7FE68A9BU}, /* ECMERRCTLR30 */
[29] = {0xE625007CU, 0x8C007E00U}, /* ECMERRCTLR31 */
[30] = {0xE6250080U, 0xCFFFFFFFU}, /* ECMERRCTLR32 */
[31] = {0xE6250084U, 0x0FFFFFFFU}, /* ECMERRCTLR33 */
[32] = {0xE6250088U, 0x000003FFU}, /* ECMERRCTLR34 */
[33] = {0xE625008CU, 0xFFFFFFC0U}, /* ECMERRCTLR35 */
[34] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[35] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
[36] = {0xE625009CU, 0x1FFF0000U}, /* ECMERRCTLR39 */
[37] = {0xE62500A0U, 0x1FFC7FFFU}, /* ECMERRCTLR40 */
[38] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
[39] = {0xE62500A8U, 0x3FBFFDFFU}, /* ECMERRCTLR42 */
};
#if (ECMERRTGTR_INTC == 1)
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250200U, 0xFFFFF00FU}, /* ECMERRTGTR0 */
[1] = {0xE6250204U, 0xFFF8C000U}, /* ECMERRTGTR1 */
[2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xE6250214U, 0xFFFFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
[7] = {0xE625021CU, 0x6F980FFFU}, /* ECMERRTGTR7 */
[8] = {0xE6250220U, 0xFFF00000U}, /* ECMERRTGTR8 */
[9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
[10] = {0xE6250228U, 0x557D554FU}, /* ECMERRTGTR10 */
[11] = {0xE625022CU, 0xFFFC1555U}, /* ECMERRTGTR11 */
[12] = {0xE6250230U, 0x5557FFFFU}, /* ECMERRTGTR12 */
[13] = {0xE6250234U, 0x00000055U}, /* ECMERRTGTR13 */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[14] = {0xE6250240U, 0x3FFFFFFFU}, /* ECMERRTGTR16 */
[15] = {0xE6250244U, 0x2FFF8CE0U}, /* ECMERRTGTR17 */
[16] = {0xE6250248U, 0x0EC03FFFU}, /* ECMERRTGTR18 */
[17] = {0xE625024CU, 0xFFFFFFF9U}, /* ECMERRTGTR19 */
[18] = {0xE6250250U, 0xFE66667EU}, /* ECMERRTGTR20 */
[19] = {0xE6250254U, 0xBFE3BE0FU}, /* ECMERRTGTR21 */
[20] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
[21] = {0xE625025CU, 0x7EF3C008U}, /* ECMERRTGTR23 */
[22] = {0xE6250260U, 0x7FFE8ADBU}, /* ECMERRTGTR24 */
[23] = {0xE6250264U, 0xCF807FFFU}, /* ECMERRTGTR25 */
[24] = {0xE6250268U, 0x7EF3C008U}, /* ECMERRTGTR26 */
[25] = {0xE625026CU, 0x7FFE8ADBU}, /* ECMERRTGTR27 */
[26] = {0xE6250270U, 0xCF807FFFU}, /* ECMERRTGTR28 */
[27] = {0xE6250274U, 0x0073C008U}, /* ECMERRTGTR29 */
[28] = {0xE6250278U, 0x7FE68A9BU}, /* ECMERRTGTR30 */
[29] = {0xE625027CU, 0x8C007E00U}, /* ECMERRTGTR31 */
[30] = {0xE6250280U, 0xCFFFFFFFU}, /* ECMERRTGTR32 */
[31] = {0xE6250284U, 0x0FFFFFFFU}, /* ECMERRTGTR33 */
[32] = {0xE6250288U, 0x000003FFU}, /* ECMERRTGTR34 */
[33] = {0xE625028CU, 0xFFFFFFC0U}, /* ECMERRTGTR35 */
[34] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[35] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
[36] = {0xE625029CU, 0x1FFF0000U}, /* ECMERRTGTR39 */
[37] = {0xE62502A0U, 0x1FFC7FFFU}, /* ECMERRTGTR40 */
[38] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
[39] = {0xE62502A8U, 0x3FBFFDFFU}, /* ECMERRTGTR42 */
};
#elif (ECMERRTGTR_INTC == 0)
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
[1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
[2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
[3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
[4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
[5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
[6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
[7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
[8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
[9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
[10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
[11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
[12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
[13] = {0xE6250234U, 0x00000000U}, /* ECMERRTGTR13 */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[14] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
[15] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
[16] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
[17] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
[18] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
[19] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
[20] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
[21] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
[22] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
[23] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
[24] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
[25] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
[26] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
[27] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
[28] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
[29] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
[30] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
[31] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
[32] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
[33] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
[34] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[35] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
[36] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
[37] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
[38] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
[39] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
};
#endif /* ECMERRTGTR_INTC == 1 */
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR register setting.\n");
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
{
/* Set ECMERRCTLR registers. */
reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
reg |= ecmerrctlr_tbl[loop].value;
ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_tbl[loop].phys_addr),
ecmerrctlr_tbl[loop].value);
}
NOTICE("ECMERRTGTR register setting.\n");
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
{
/* Set ECMERRTGTR registers. */
reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
reg |= ecmerrtgtr_tbl[loop].value;
ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
ecmerrtgtr_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_error_enable(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE
#define ECM_ENABLE
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_error_enable(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE */

1753
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h Normal file
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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c Normal file
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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#include <stdint.h>
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#else
#include "mem_io.h"
#include "log.h"
#endif
#include "boot_init_dram_regdef.h"
#include "boot_init_dram_config.h"
/*******************************************************************************
* PLEASE SET board number or board judge function
******************************************************************************/
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t r_board_judge(void);
uint32_t r_boardcnf_get_brd_type(void)
{
return r_board_judge();
}
#else /* BOARD_JUDGE_AUTO */
uint32_t r_boardcnf_get_brd_type(void)
{
return (0);
}
#endif /* BOARD_JUDGE_AUTO */
/*******************************************************************************
* EXTAL CLOCK DEFINITION
* PLEASE DEFINE HOW TO JUDGE BORAD CLK
******************************************************************************/
/*
* RENESAS GRAY HAWK BOARD EXAMPLE
* judge by md14/md13
*
* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0)
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1)
*/
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
{
uint32_t md;
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
switch (md)
{
case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */
case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */
case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */
case 0x3U : *clk =100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */
default : /* Nothing */ break;
}
(void)brd;
}
/*******************************************************************************
* DDR MBPS TARGET
* PLEASE DEFINE HOW TO JUDGE DDR BPS
******************************************************************************/
/*
DDRxxxx (judge by md19,17) : Mbps
SSCG enable / disable for PLL1 (judge by md18/md37/md36)
*/
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en)
{
uint32_t md;
uint32_t product;
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
md = (md | (md >> 1)) & 0x03U;
*sscg = ((mmio_read_32(RST_MODEMR0) >> 16) & 0x04U) | ((mmio_read_32(RST_MODEMR1) >> 4) & 0x03U);
product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
if (product == 0x01U)
{
/* V4M-5 */
switch (md)
{
case 0x0U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
case 0x1U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
case 0x2U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
}
else if (product == 0x02U)
{
/* V4M-3 */
switch (md)
{
case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
}
else if (product == 0x04U)
{
/* V4M-2 */
switch (md)
{
case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
}
else
{
/* V4M-7 */
switch (*sscg)
{
case 0x0U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x1U :
switch (md)
{
case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x2U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x3U :
switch (md)
{
case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x4U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x5U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x6U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
case 0x7U :
switch (md)
{
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
default : /* Nothing */ break;
}
break;
default :
/* Nothing */
break;
}/* Setting of SSCG */
} /* (product == 0x01U) */
(void)brd;
}
#ifdef BOARD_JUDGE_AUTO
/*******************************************************************************
* SAMPLE board detect function
******************************************************************************/
static uint32_t r_board_judge(void)
{
uint32_t brd;
brd = 0U; /* gray hawk (64Gbit 2rank) */
return brd;
}
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_CONFIG_H_
#define BOOT_INIT_DRAM_CONFIG_H_
/*******************************************************************************
* DRAM Param setting
******************************************************************************/
#define JS2_DERATE 0U
#define DBSC_REFINT 1920U /* Average periodic refresh interval/Average Refresh Interval [ns] */
#ifndef DBSC_REFINTS
#define DBSC_REFINTS 0U /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
#endif
#define PERIODIC_TRAINING_INTERVAL 20000U /* Periodic-WriteDQ/ReadDQ Training Interval [us] */
/*******************************************************************************
* NUMBER OF BOARD CONFIGURATION
* PLEASE DEFINE
******************************************************************************/
#define BOARDNUM 2U /* Add User platform BOARD */
/*******************************************************************************
* Prototypes
******************************************************************************/
uint32_t r_boardcnf_get_brd_type(void);
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en);
/*******************************************************************************
* BOARD CONFIGURATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
typedef struct
{
/*
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
0x05...0101B: 24Gb dual channel die / 12Gb single channel die
0x06...0110B: 32Gb dual channel die / 16Gb single channel die
0x07...0111B: 24Gb single channel die
0x08...1000B: 32Gb single channel die
0xFF...NO_MEMORY
*/
uint8_t bdcfg_ddr_density[CS_CNT];
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
uint32_t bdcfg_ca_swap;
/* SoC dqsX([1][0]) -> MEM dqsY: */
uint8_t bdcfg_dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
uint32_t bdcfg_dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
uint8_t bdcfg_dm_swap[SLICE_CNT];
/* SoC ckeX([1][0]) -> MEM csY */
uint8_t bdcfg_cs_swap;
} st_boardcnf_ch_t;
typedef struct
{
/* ch in use */
uint8_t bdcfg_phyvalid;
/* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */
uint32_t bdcfg_vref_r;
/* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t bdcfg_vref_w;
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t bdcfg_vref_ca;
/* RFM required check : 0x01 = check enable, 0x00 = check disable */
uint8_t bdcfg_rfm_chk;
st_boardcnf_ch_t ch[2];
} st_boardcnf_t;
static const st_boardcnf_t boardcnfs[BOARDNUM] = {
/*
* boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank)
*/
{
0x03U, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
/* bdcfg_ca_swap */ 0x06235104U,
/* bdcfg_dqs_swap */ 0x01U,
/* bdcfg_dq_swap[] */ { 0x43061257U, 0x30721685U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x04U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
/* bdcfg_ca_swap */ 0x04012653U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x58147026U, 0x70132685U },
/* bdcfg_dm_swap[] */ { 0x03U, 0x04U },
/* bdcfg_cs_swap */ 0x10U
}
}
},
/*
* boardcnf[1] RENESAS V4M (2ch)
*/
{
0x03U, /* bdcfg_phyvalid */
0x00000000U, /* bdcfg_vref_r */
0x0000U, /* bdcfg_vref_w */
0x0000U, /* bdcfg_vref_ca */
0x01U, /* bdcfg_rfm_chk */
{
/* ch[0] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
},
/* ch[1] */ {
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
/* bdcfg_ca_swap */ 0x06543210U,
/* bdcfg_dqs_swap */ 0x10U,
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
/* bdcfg_cs_swap */ 0x10U
}
}
}
};
#endif /* BOOT_INIT_DRAM_CONFIG_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_REGDEF_H_
#define BOOT_INIT_DRAM_REGDEF_H_
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.1.00"
#define DRAM_CH_CNT 0x02U
#define SLICE_CNT 0x02U
#define CS_CNT 0x02U
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
#if defined(__RH850G3K__)
#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR)
#else
#define OTP_MEM_1_BASE (0xE61BF000U)
#endif
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4M DBSC0 clk_dbsc region */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4M DBSC0 clk_axim region */
#else
#define DBSC_D_BASE (0xE67A4000U) /* forV4M DBSC0 clk_dbsc region */
#define DBSC_A_BASE (0xE6790000U) /* forV4M DBSC0 clk_axim region */
#endif
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x0804U)
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#endif /* BOOT_INIT_DRAM_REGDEF_H_ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef DDR_REGDEF_H_
#define DDR_REGDEF_H_
#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U
#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011006U
#define PHY_PER_CS_TRAINING_INDEX 0x00011007U
#define PHY_VREF_INITIAL_STEPSIZE 0x1808100EU
#define PHY_RDLVL_BEST_THRSHLD 0x0004100FU
#define PHY_RDLVL_VREF_OUTLIER 0x1003100FU
#define SC_PHY_WCK_CALC 0x1801101BU
#define PHY_WRLVL_PER_START 0x00071020U
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x08051022U
#define PHY_CALVL_VREF_DRIVING_SLICE 0x08011026U
#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A102DU
#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A102DU
#define PHY_WRLVL_STATUS_OBS 0x001C102EU
#define PHY_WRLVL_ERROR_OBS 0x00021030U
#define PHY_GTLVL_STATUS_OBS 0x00121032U
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x10091033U
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00091034U
#define PHY_WDQLVL_STATUS_OBS 0x00201038U
#define PHY_DATA_DC_CAL_START 0x08011041U
#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011042U
#define PHY_REGULATOR_EN_CNT 0x00061044U
#define PHY_VREF_INITIAL_START_POINT 0x00091048U
#define PHY_VREF_INITIAL_STOP_POINT 0x10091048U
#define PHY_VREF_TRAINING_CTRL 0x00021049U
#define PHY_RDDQ0_SLAVE_DELAY 0x00091050U
#define PHY_RDDQ1_SLAVE_DELAY 0x10091050U
#define PHY_RDDQ2_SLAVE_DELAY 0x00091051U
#define PHY_RDDQ3_SLAVE_DELAY 0x10091051U
#define PHY_RDDQ4_SLAVE_DELAY 0x00091052U
#define PHY_RDDQ5_SLAVE_DELAY 0x10091052U
#define PHY_RDDQ6_SLAVE_DELAY 0x00091053U
#define PHY_RDDQ7_SLAVE_DELAY 0x10091053U
#define PHY_RDDM_SLAVE_DELAY 0x00091054U
#define PHY_RX_CAL_ALL_DLY 0x18061054U
#define PHY_RX_PCLK_CLK_SEL 0x00031055U
#define PHY_DATA_DC_CAL_CLK_SEL 0x08031055U
#define PHY_PAD_VREF_CTRL_DQ 0x100E1058U
#define PHY_PER_CS_TRAINING_EN 0x10011059U
#define PHY_RDDATA_EN_TSEL_DLY 0x0805105BU
#define PHY_RDDATA_EN_OE_DLY 0x1005105BU
#define PHY_RPTR_UPDATE 0x0804105EU
#define PHY_WRLVL_RESP_WAIT_CNT 0x0006105FU
#define PHY_RDLVL_DLY_STEP 0x08041062U
#define PHY_RDLVL_MAX_EDGE 0x00091063U
#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021068U
#define PHY_RDDATA_EN_DLY 0x10051069U
#define PHY_DQ_DM_SWIZZLE0 0x0020106AU
#define PHY_DQ_DM_SWIZZLE1 0x0004106BU
#define PHY_CLK_WRDQS_SLAVE_DELAY 0x00091071U
#define PHY_WRITE_PATH_LAT_DEC 0x10011071U
#define PHY_RDDQS_LATENCY_ADJUST 0x1005107BU
#define PHY_WRITE_PATH_LAT_ADD 0x1803107BU
#define PHY_WRITE_PATH_LAT_FRAC 0x0008107CU
#define PHY_GTLVL_LAT_ADJ_START 0x0005107DU
#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008107FU
#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U
#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U
#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U
#define PHY_ADR_CALVL_OBS1 0x0020120AU
#define PHY_ADR_CALVL_OBS2 0x0020120BU
#define PHY_ADR_CALVL_DLY_STEP 0x00041210U
#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U
#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U
#define PHY_CSLVL_OBS1 0x00201221U
#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE 0x1008122DU
#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU
#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U
#define PHY_FREQ_SEL_INDEX 0x10021301U
#define SC_PHY_MANUAL_UPDATE 0x18011304U
#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U
#define PHY_TCKSRE_WAIT 0x1004131FU
#define PHY_CAL_MODE_0 0x000D132CU
#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU
#define PHY_DATA_BYTE_ORDER_SEL 0x0020133FU
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x1003134AU
#define PHY_PLL_CTRL 0x000E134DU
#define PHY_PLL_CTRL_8X 0x100E134DU
#define PHY_CAL_CLK_SELECT_0 0x00031361U
#define PI_START 0x00010800U
#define PI_TRAIN_ALL_FREQ_REQ 0x18010804U
#define PI_FREQ_MAP 0x0020080DU
#define PI_INIT_WORK_FREQ 0x0005080EU
#define PI_CS_MAP 0x08020815U
#define PI_WRLVL_REQ 0x0801081FU
#define PI_WRLVL_CS_SW 0x1002081FU
#define PI_RDLVL_REQ 0x10010827U
#define PI_RDLVL_GATE_REQ 0x18010827U
#define PI_RDLVL_CS_SW 0x00020828U
#define PI_RDLVL_PERIODIC 0x08010831U
#define PI_RDLVL_INTERVAL 0x08100838U
#define PI_DRAMDCA_FLIP_MASK 0x0802083EU
#define PI_DRAMDCA_LVL_REQ 0x10010840U
#define PI_DCMLVL_CS_SW 0x18020840U
#define PI_WRDCM_LVL_EN_F1 0x00020842U
#define PI_DRAMDCA_LVL_EN_F1 0x08020842U
#define PI_WRDCM_LVL_EN_F2 0x18020842U
#define PI_DRAMDCA_LVL_EN_F2 0x00020843U
#define PI_TCKCKEL_F2 0x18040851U
#define PI_WDQLVL_VREF_EN 0x08040852U
#define PI_WDQLVL_PERIODIC 0x00010854U
#define PI_WDQLVL_INTERVAL 0x00100858U
#define PI_INT_STATUS 0x002008B7U
#define PI_INT_ACK_0 0x002008B9U
#define PI_INT_ACK_1 0x000108BAU
#define PI_LONG_COUNT_MASK 0x100508BCU
#define PI_ADDRESS_MUX_0 0x000308BDU
#define PI_ADDRESS_MUX_1 0x080308BDU
#define PI_ADDRESS_MUX_2 0x100308BDU
#define PI_ADDRESS_MUX_3 0x180308BDU
#define PI_ADDRESS_MUX_4 0x000308BEU
#define PI_ADDRESS_MUX_5 0x080308BEU
#define PI_ADDRESS_MUX_6 0x100308BEU
#define PI_DATA_BYTE_SWAP_EN 0x180108BEU
#define PI_DATA_BYTE_SWAP_SLICE0 0x000108BFU
#define PI_DATA_BYTE_SWAP_SLICE1 0x080108BFU
#define PI_PWRUP_SREFRESH_EXIT 0x100108C2U
#define PI_DLL_RST 0x000108C6U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x000808E8U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x000808E9U
#define PI_WRLAT_F1 0x100708EDU
#define PI_TWCKENL_RD_ADJ_F1 0x000608EEU
#define PI_TWCKPRE_STATIC_F1 0x080608EEU
#define PI_TWCKPRE_TOGGLE_RD_F1 0x180608EEU
#define PI_WCK_ACTIVE_WR_F1 0x000708EFU
#define PI_WCK_ACTIVE_RD_F1 0x080708EFU
#define PI_CASLAT_F1 0x180708EFU
#define PI_WRLAT_F2 0x000708F0U
#define PI_TWCKENL_WR_ADJ_F2 0x080608F0U
#define PI_TWCKENL_RD_ADJ_F2 0x100608F0U
#define PI_TWCKPRE_STATIC_F2 0x180608F0U
#define PI_TWCKPRE_TOGGLE_RD_F2 0x080608F1U
#define PI_WCK_ACTIVE_WR_F2 0x100708F1U
#define PI_WCK_ACTIVE_RD_F2 0x180708F1U
#define PI_TWCKENL_FS_ADJ_F2 0x000608F2U
#define PI_CASLAT_F2 0x080708F2U
#define PI_TRFC_F1 0x000A08F4U
#define PI_TREF_F1 0x001408F5U
#define PI_TRFC_F2 0x000A08F6U
#define PI_TREF_F2 0x001408F7U
#define PI_WRLVL_EN_F1 0x000208FAU
#define PI_TDFI_WRLVL_WW_F1 0x080A08FAU
#define PI_WRLVL_EN_F2 0x000208FBU
#define PI_TDFI_WRLVL_WW_F2 0x080A08FBU
#define PI_WRLVL_WCKOFF_F2 0x180808FBU
#define PI_RDLVL_EN_F1 0x100208FFU
#define PI_RDLVL_GATE_EN_F1 0x180208FFU
#define PI_RDLVL_EN_F2 0x00020900U
#define PI_RDLVL_GATE_EN_F2 0x08020900U
#define PI_RDLVL_VREF_EN_F0 0x18040900U
#define PI_RDLVL_RDDQ_EN_F1 0x00040902U
#define PI_RDLVL_VREF_EN_F1 0x08040902U
#define PI_RDLVL_VREF_EN_F2 0x18040903U
#define PI_RDLAT_ADJ_F1 0x10090905U
#define PI_RDLAT_ADJ_F2 0x00090906U
#define PI_WRLAT_ADJ_F1 0x18070906U
#define PI_WRLAT_ADJ_F2 0x00070907U
#define PI_TDFI_CALVL_CC_F1 0x000A0909U
#define PI_TDFI_CALVL_CAPTURE_F1 0x100A0909U
#define PI_TDFI_CALVL_CC_F2 0x000A090AU
#define PI_TDFI_CALVL_CAPTURE_F2 0x100A090AU
#define PI_CALVL_EN_F1 0x0802090BU
#define PI_CALVL_EN_F2 0x1002090BU
#define PI_TCAENT_F1 0x000E090DU
#define PI_TCAENT_F2 0x000E090EU
#define PI_TVREF_LONG_F1 0x000A0912U
#define PI_TVRCG_ENABLE_F1 0x100A0912U
#define PI_TVRCG_DISABLE_F1 0x000A0913U
#define PI_TVREF_LONG_F2 0x100A0914U
#define PI_TVRCG_ENABLE_F2 0x000A0915U
#define PI_TVRCG_DISABLE_F2 0x100A0915U
#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070917U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070917U
#define PI_TDFI_CALVL_STROBE_F2 0x0804091AU
#define PI_TXP_F2 0x1005091AU
#define PI_TMRWCKEL_F2 0x1808091AU
#define PI_TCKEHDQS_F1 0x10060921U
#define PI_TFC_F1 0x000A0922U
#define PI_TCKEHDQS_F2 0x10060922U
#define PI_TFC_F2 0x000A0923U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x10070925U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x18070925U
#define PI_TDFI_WDQLVL_WR_F1 0x080A0928U
#define PI_TDFI_WDQLVL_RW_F1 0x000A0929U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x10070929U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x18070929U
#define PI_WDQLVL_EN_F1 0x0802092AU
#define PI_WDQLVL_RDLAT_ADJ_F1 0x0009092BU
#define PI_WDQLVL_WRLAT_ADJ_F1 0x1009092BU
#define PI_WDQLVL_TWCKENL_RD_ADJ_F1 0x0006092CU
#define PI_TDFI_WDQLVL_WR_F2 0x080A092CU
#define PI_TDFI_WDQLVL_RW_F2 0x000A092DU
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x1007092DU
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x1807092DU
#define PI_WDQLVL_EN_F2 0x0802092EU
#define PI_WDQLVL_RDLAT_ADJ_F2 0x0009092FU
#define PI_WDQLVL_WRLAT_ADJ_F2 0x1009092FU
#define PI_WDQLVL_TWCKENL_RD_ADJ_F2 0x00060930U
#define PI_TRTP_F1 0x18080936U
#define PI_TRP_F1 0x00080937U
#define PI_TRCD_F1 0x08080937U
#define PI_TWTR_S_F1 0x18060937U
#define PI_TWTR_L_F1 0x00060938U
#define PI_TWTR_F1 0x10060938U
#define PI_TWR_F1 0x18080938U
#define PI_TRAS_MAX_F1 0x00100939U
#define PI_TRAS_MIN_F1 0x10090939U
#define PI_TSR_F1 0x1008093AU
#define PI_TRTP_F2 0x0808093BU
#define PI_TRP_F2 0x1008093BU
#define PI_TRCD_F2 0x1808093BU
#define PI_TWTR_S_F2 0x0806093CU
#define PI_TWTR_L_F2 0x1006093CU
#define PI_TWTR_F2 0x0006093DU
#define PI_TWR_F2 0x0808093DU
#define PI_TRAS_MAX_F2 0x1010093DU
#define PI_TRAS_MIN_F2 0x0009093EU
#define PI_TDQSCK_MAX_F2 0x1004093EU
#define PI_TSR_F2 0x0008093FU
#define PI_TMRD_F2 0x0808093FU
#define PI_TDFI_CTRLUPD_MAX_F1 0x00150942U
#define PI_TDFI_CTRLUPD_INTERVAL_F1 0x00200943U
#define PI_TDFI_CTRLUPD_MAX_F2 0x00150944U
#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x00200945U
#define PI_TXSR_F1 0x10100946U
#define PI_TXSR_F2 0x00100947U
#define PI_TINIT_F1 0x0018094EU
#define PI_TINIT1_F1 0x0018094FU
#define PI_TINIT3_F1 0x00180950U
#define PI_TINIT4_F1 0x00180951U
#define PI_TINIT5_F1 0x00180952U
#define PI_TXSNR_F1 0x00100953U
#define PI_TINIT_F2 0x00180954U
#define PI_TINIT1_F2 0x00180955U
#define PI_TINIT3_F2 0x00180956U
#define PI_TINIT4_F2 0x00180957U
#define PI_TINIT5_F2 0x00180958U
#define PI_TXSNR_F2 0x00100959U
#define PI_TZQCAL_F1 0x100C095CU
#define PI_TZQLAT_F1 0x0007095DU
#define PI_TZQCAL_F2 0x100C095EU
#define PI_TZQLAT_F2 0x0007095FU
#define PI_ZQRESET_F1 0x000C0960U
#define PI_ZQRESET_F2 0x100C0960U
#define PI_TDQ72DQ_F1 0x000A0964U
#define PI_TCBTRTW_F1 0x10060964U
#define PI_TDQ72DQ_F2 0x100A0965U
#define PI_TCBTRTW_F2 0x00060966U
#define PI_MC_TRFC_F1 0x100A0968U
#define PI_MC_TRFC_F2 0x000A0969U
#define PI_TDFI_WCK_STOP_F1 0x0808096EU
#define PI_TDFI_WCK_STOP_F2 0x1808096EU
#define PI_CKE_MUX_0 0x1802096FU
#define PI_CKE_MUX_1 0x00020970U
#define PI_SEQ_DEC_SW_CS 0x0002097BU
#define PI_SW_SEQ_START 0x1001097BU
#define PI_SEQ_ARRAY_29 0x001D09C9U
#define PI_SEQ_ARRAY_64 0x001D09ECU
#define PI_SEQ_ARRAY_65 0x001D09EDU
#define PI_SEQ_ARRAY_66 0x001D09EEU
#define PI_SEQ_ARRAY_67 0x001D09EFU
#define PI_SEQ_ARRAY_68 0x001D09F0U
#define PI_SEQ_ARRAY_69 0x001D09F1U
#define PI_SEQ_ARRAY_70 0x001D09F2U
#define PI_SEQ_ARRAY_71 0x001D09F3U
#define PI_SEQ_ARRAY_72 0x001D09F4U
#define PI_SEQ_ARRAY_81 0x001D09FDU
#define PI_SEQ_ARRAY_82 0x001D09FEU
#define PI_SEQ_ARRAY_333 0x001B0AF9U
#define PI_SEQ_ARRAY_334 0x001B0AFAU
#define PI_SEQ_ARRAY_335 0x001B0AFBU
#define PI_SEQ_ARRAY_349 0x001B0B09U
#define PI_SEQ_ARRAY_350 0x001B0B0AU
#define PI_RDLVL_TRAIN_SEQ_1 0x001B0B9EU
#define PI_RDLVL_TRAIN_SEQ_2 0x001B0B9FU
#define PI_RDLVL_TRAIN_SEQ_3 0x001B0BA0U
#define PI_RDLVL_TRAIN_SEQ_4 0x001B0BA1U
#define PI_RDLVL_TRAIN_SEQ_5 0x001B0BA2U
#define PI_SEQ_WAIT_16_F1 0x00180BD2U
#define PI_SEQ_WAIT_16_F2 0x00180BD3U
#define PI_SEQ_WAIT_17_F1 0x00180BD5U
#define PI_SEQ_WAIT_17_F2 0x00180BD6U
#define PI_SEQ_WAIT_18_F2 0x00180BD9U
#define PI_SEQ_WAIT_19_F1 0x00180BDBU
#define PI_SEQ_WAIT_19_F2 0x00180BDCU
#define PI_SEQ_WAIT_20_F1 0x00180BDEU
#define PI_SEQ_WAIT_20_F2 0x00180BDFU
#define PI_SEQ_WAIT_21_F1 0x00180BE1U
#define PI_SEQ_WAIT_21_F2 0x00180BE2U
#define PI_SEQ_WAIT_22_F1 0x00180BE4U
#define PI_SEQ_WAIT_22_F2 0x00180BE5U
#define PI_SEQ_WAIT_23_F1 0x00180BE7U
#define PI_SEQ_WAIT_23_F2 0x00180BE8U
#define PI_SEQ_WAIT_24_F1 0x00180BEAU
#define PI_SEQ_WAIT_24_F2 0x00180BEBU
#define PI_SEQ_WAIT_25_F1 0x00180BEDU
#define PI_SEQ_WAIT_25_F2 0x00180BEEU
#define PI_SEQ_WAIT_26_F1 0x00180BF0U
#define PI_SEQ_WAIT_26_F2 0x00180BF1U
#define PI_SEQ_WAIT_27_F2 0x00180BF4U
#define PI_SEQ_WAIT_31_F1 0x00180BFFU
#define PI_SEQ_WAIT_31_F2 0x00180C00U
#define PI_WP_GAP_0_F1 0x100F0C0DU
#define PI_WP_GAP_0_F2 0x000F0C0EU
#define PI_RP_GAP_0_F1 0x000F0C0FU
#define PI_RP_GAP_0_F2 0x100F0C0FU
#define PI_WR_GAP_S_0_F1 0x100F0C10U
#define PI_WR_GAP_S_0_F2 0x000F0C11U
#define PI_WR_GAP_L_0_F1 0x000F0C12U
#define PI_WR_GAP_L_0_F2 0x100F0C12U
#define PI_RW_GAP_0_F1 0x100F0C13U
#define PI_RW_GAP_0_F2 0x000F0C14U
#define PI_WP_GAP_1_F1 0x000F0C1BU
#define PI_WP_GAP_1_F2 0x100F0C1BU
#define PI_RP_GAP_1_F1 0x100F0C1CU
#define PI_RP_GAP_1_F2 0x000F0C1DU
#define PI_WR_GAP_S_1_F1 0x000F0C1EU
#define PI_WR_GAP_S_1_F2 0x100F0C1EU
#define PI_WR_GAP_L_1_F1 0x100F0C1FU
#define PI_WR_GAP_L_1_F2 0x000F0C20U
#define PI_RW_GAP_1_F1 0x000F0C21U
#define PI_RW_GAP_1_F2 0x100F0C21U
#define PI_WP_GAP_2_F1 0x100F0C28U
#define PI_WP_GAP_2_F2 0x000F0C29U
#define PI_RP_GAP_2_F1 0x000F0C2AU
#define PI_RP_GAP_2_F2 0x100F0C2AU
#define PI_WR_GAP_S_2_F1 0x100F0C2BU
#define PI_WR_GAP_S_2_F2 0x000F0C2CU
#define PI_WR_GAP_L_2_F1 0x000F0C2DU
#define PI_WR_GAP_L_2_F2 0x100F0C2DU
#define PI_RW_GAP_2_F1 0x100F0C2EU
#define PI_RW_GAP_2_F2 0x000F0C2FU
#define PI_WP_GAP_3_F1 0x000F0C36U
#define PI_WP_GAP_3_F2 0x100F0C36U
#define PI_RP_GAP_3_F1 0x100F0C37U
#define PI_RP_GAP_3_F2 0x000F0C38U
#define PI_WR_GAP_S_3_F1 0x000F0C39U
#define PI_WR_GAP_S_3_F2 0x100F0C39U
#define PI_WR_GAP_L_3_F1 0x100F0C3AU
#define PI_WR_GAP_L_3_F2 0x000F0C3BU
#define PI_RW_GAP_3_F1 0x000F0C3CU
#define PI_RW_GAP_3_F2 0x100F0C3CU
#define PI_DARRAY3_0_CS0_F0 0x00080C9DU
#define PI_DARRAY3_1_CS0_F0 0x08080C9DU
#define PI_DARRAY3_0_CS0_F1 0x00080CA7U
#define PI_DARRAY3_1_CS0_F1 0x08080CA7U
#define PI_DARRAY3_0_CS0_F2 0x00080CB1U
#define PI_DARRAY3_1_CS0_F2 0x08080CB1U
#define PI_DARRAY3_2_CS0_F2 0x10080CB1U
#define PI_DARRAY3_20_CS0_F2 0x00080CB6U
#define PI_DARRAY3_0_CS1_F0 0x00080CBBU
#define PI_DARRAY3_1_CS1_F0 0x08080CBBU
#define PI_DARRAY3_0_CS1_F1 0x00080CC5U
#define PI_DARRAY3_1_CS1_F1 0x08080CC5U
#define PI_DARRAY3_0_CS1_F2 0x00080CCFU
#define PI_DARRAY3_1_CS1_F2 0x08080CCFU
#define PI_DARRAY3_2_CS1_F2 0x10080CCFU
#define PI_DARRAY3_20_CS1_F2 0x00080CD4U
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)
#endif /* DDR_REGDEF_H_ */

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IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c Normal file
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/*******************************************************************************
* Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC initialize function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4m.c
* - Version : 0.05
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
* : 21.08.2023 0.02 Update the ecc setting according to HW SAN rev0.82.
* : 08.04.2024 0.03 Update the ecc register setting.
* : 13.06.2024 0.04 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 27.01.2025 0.05 Add ECM setting process.
* Remove unused functions.
*****************************************************************************/
#include <stdint.h>
#if (ECC_ENABLE == 1)
#include "ecc_enable_v4m.h"
#include "ecm_enable_v4m.h"
#include "mem_io.h"
#include "v4m/lpddr5/boot_init_dram_regdef.h"
/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
void ecc_sdram_enable(void)
{
NOTICE("ECC for DRAM is enable.\n");
uint32_t ecm_tmp;
/* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
mem_write32(DB0SYSCNT0, 0x00001234U);
mem_write32(DB0SYSCNT0A, 0x00001234U);
/* (A) Setting ECM */
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 1 of ECMERRTGTR0 to 0 and bit 1 of ECMERRCTLR0 to 1. */
ecm_tmp = mem_read32(ECMERRTGTR0);
ecm_tmp &= ~(0x2U);
ecm_write(ECMERRTGTR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRCTLR0);
ecm_tmp |= (0x2U);
ecm_write(ECMERRCTLR0, ecm_tmp);
/* (B) Setting ECC protection area */
/* Set the bottom row address of the ECC protection area */
mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
mem_write32(DB0FSDRAMECCAREA01, ECC_PROT_SIZE01);
/* (C) Initialization for DRAM */
mem_write32(DBSC_DB0ACEN, 0x00000000U);
/*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
mem_write32(DB0FSCONF00A, 0x0U);
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
mem_write32(DB0FSCTRL01A, 0x01U);
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
NOTICE("DRAM rank 0 of DBSC0 is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB0FSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/*** If DRAM is connected to RANK1, Initialize RANK1 by the following procedure ***/
/* [Step1] Specify RANK1 as the initialization target. Set 0x1 to DB0FSCONF00A[1:0]. */
mem_write32(DB0FSCONF00A, 0x1U);
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA01);
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA01);
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
mem_write32(DB0FSCTRL01A, 0x01U);
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
NOTICE("DRAM rank 1 of DBSC0 is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB0FSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* (D) Setting ECC protection enable */
ecm_tmp = mem_read32(DB0FSCONFAXI0);
ecm_tmp |= (0x3U << 8U);
mem_write32(DB0FSCONFAXI0, ecm_tmp);
/* (E) System RAM initialization */
/* Read DB0FSSTAT00A and wait until its value changes to 0x1. */
/* When DB0FSSTAT00A changes to 0x1, the System RAM area initialization is complete of dbs0 */
NOTICE("System RAM is initializing.......\n");
do
{
ecm_tmp = 0x01U;
ecm_tmp &= mem_read32(DB0FSSTAT00A);
} while (ecm_tmp != 0x1U);
/* (F) Setting for ECC error interrupt */
/* (1) Set the ECC error interrupt for read data */
mem_write32(DB0FSINTENB02A, 0xFF00U);
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
ecm_tmp = mem_read32(DB0FSINTENB02A);
ecm_tmp |= 0xFF000000U;
mem_write32(DB0FSINTENB02A, ecm_tmp);
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
/* Lock the ECM registers */
ecm_lock();
/* Enable the write protect of ECM registers */
mem_write32(DBSC_DB0ACEN, 0x00000001U);
/* Enable the access protect for DBSC registers */
mem_write32(DB0SYSCNT0, 0x00000000U);
mem_write32(DB0SYSCNT0A, 0x00000000U);
}
#endif /* ECC_ENABLE == 1 */

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/*******************************************************************************
* Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
/* DBSC registers */
#if defined(__RH850G3K__)
#include "remap_register.h"
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#if (ECC_ENABLE == 1)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif /* ECC_ENABLE == 1 */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#if (ECC_ENABLE == 1)
void ecc_sdram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U)
#endif /* ECC_ENABLE == 1 */
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#if (ECC_ENABLE == 1)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U)
#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0xCCCCU)
#define ECC_PROT_SIZE01 (0xCCCCU)
#define ECC_PROT_SIZE10 (0xCCCCU)
#define ECC_PROT_SIZE11 (0xCCCCU)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x0000CCCBU)
#define END_ECC_INIT_AREA10 (0x0000CCCBU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x0000CCCBU)
#define END_ECC_INIT_AREA11 (0x0000CCCBU)
/*********** Other settings cannot be changed ***************/
#endif /* ECC_ENABLE == 1 */
#endif/* ECC_PROTECT */

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/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4m.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4m.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
#include "ecc_enable_v4m.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define ECM_ERR_REG_MAX (39U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_error_enable(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250000U, 0xFFFFF003U}, /* ECMERRCTLR0 */
[1] = {0xE6250004U, 0xA7F8C000U}, /* ECMERRCTLR1 */
[2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xE6250014U, 0x8FFFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
[7] = {0xE625001CU, 0x68980FFFU}, /* ECMERRCTLR7 */
[8] = {0xE6250020U, 0x60A00000U}, /* ECMERRCTLR8 */
[9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
[10] = {0xE6250028U, 0x557D554CU}, /* ECMERRCTLR10 */
[11] = {0xE625002CU, 0xFF3C1555U}, /* ECMERRCTLR11 */
[12] = {0xE6250030U, 0x0003FFFFU}, /* ECMERRCTLR12 */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[13] = {0xE6250040U, 0x33F03FFFU}, /* ECMERRCTLR16 */
[14] = {0xE6250044U, 0x2DFF9CE0U}, /* ECMERRCTLR17 */
[15] = {0xE6250048U, 0x0CC037FFU}, /* ECMERRCTLR18 */
[16] = {0xE625004CU, 0xFFFFFF31U}, /* ECMERRCTLR19 */
[17] = {0xE6250050U, 0xFE60067EU}, /* ECMERRCTLR20 */
[18] = {0xE6250054U, 0xBF61820FU}, /* ECMERRCTLR21 */
[19] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
[20] = {0xE625005CU, 0x7E90C008U}, /* ECMERRCTLR23 */
[21] = {0xE6250060U, 0x7E788AD9U}, /* ECMERRCTLR24 */
[22] = {0xE6250064U, 0xC7807AB7U}, /* ECMERRCTLR25 */
[23] = {0xE6250068U, 0x7E90C008U}, /* ECMERRCTLR26 */
[24] = {0xE625006CU, 0x7E788AD9U}, /* ECMERRCTLR27 */
[25] = {0xE6250070U, 0xC7807AB7U}, /* ECMERRCTLR28 */
[26] = {0xE6250074U, 0x0010C008U}, /* ECMERRCTLR29 */
[27] = {0xE6250078U, 0x7E608A99U}, /* ECMERRCTLR30 */
[28] = {0xE625007CU, 0x84007A00U}, /* ECMERRCTLR31 */
[29] = {0xE6250080U, 0xDFFFFFFFU}, /* ECMERRCTLR32 */
[30] = {0xE6250084U, 0x1FFFFFFFU}, /* ECMERRCTLR33 */
[31] = {0xE6250088U, 0x0000001FU}, /* ECMERRCTLR34 */
[32] = {0xE625008CU, 0xA3BEEA80U}, /* ECMERRCTLR35 */
[33] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[34] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
[35] = {0xE625009CU, 0x19FF0000U}, /* ECMERRCTLR39 */
[36] = {0xE62500A0U, 0x0000601EU}, /* ECMERRCTLR40 */
[37] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
[38] = {0xE62500A8U, 0x0000000FU}, /* ECMERRCTLR42 */
};
#if (ECMERRTGTR_INTC == 1)
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250200U, 0xFFFFF003U}, /* ECMERRTGTR0 */
[1] = {0xE6250204U, 0xA7F8C000U}, /* ECMERRTGTR1 */
[2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xE6250214U, 0x8FFFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
[7] = {0xE625021CU, 0x68980FFFU}, /* ECMERRTGTR7 */
[8] = {0xE6250220U, 0x60A00000U}, /* ECMERRTGTR8 */
[9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
[10] = {0xE6250228U, 0x557D554CU}, /* ECMERRTGTR10 */
[11] = {0xE625022CU, 0xFF3C1555U}, /* ECMERRTGTR11 */
[12] = {0xE6250230U, 0x0003FFFFU}, /* ECMERRTGTR12 */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[13] = {0xE6250240U, 0x33F03FFFU}, /* ECMERRTGTR16 */
[14] = {0xE6250244U, 0x2DFF9CE0U}, /* ECMERRTGTR17 */
[15] = {0xE6250248U, 0x0CC037FFU}, /* ECMERRTGTR18 */
[16] = {0xE625024CU, 0xFFFFFF31U}, /* ECMERRTGTR19 */
[17] = {0xE6250250U, 0xFE60067EU}, /* ECMERRTGTR20 */
[18] = {0xE6250254U, 0xBF61820FU}, /* ECMERRTGTR21 */
[19] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
[20] = {0xE625025CU, 0x7E90C008U}, /* ECMERRTGTR23 */
[21] = {0xE6250260U, 0x7E788AD9U}, /* ECMERRTGTR24 */
[22] = {0xE6250264U, 0xC7807AB7U}, /* ECMERRTGTR25 */
[23] = {0xE6250268U, 0x7E90C008U}, /* ECMERRTGTR26 */
[24] = {0xE625026CU, 0x7E788AD9U}, /* ECMERRTGTR27 */
[25] = {0xE6250270U, 0xC7807AB7U}, /* ECMERRTGTR28 */
[26] = {0xE6250274U, 0x0010C008U}, /* ECMERRTGTR29 */
[27] = {0xE6250278U, 0x7E608A99U}, /* ECMERRTGTR30 */
[28] = {0xE625027CU, 0x84007A00U}, /* ECMERRTGTR31 */
[29] = {0xE6250280U, 0xDFFFFFFFU}, /* ECMERRTGTR32 */
[30] = {0xE6250284U, 0x1FFFFFFFU}, /* ECMERRTGTR33 */
[31] = {0xE6250288U, 0x0000001FU}, /* ECMERRTGTR34 */
[32] = {0xE625028CU, 0xA3BEEA80U}, /* ECMERRTGTR35 */
[33] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[34] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
[35] = {0xE625029CU, 0x19FF0000U}, /* ECMERRTGTR39 */
[36] = {0xE62502A0U, 0x0000601EU}, /* ECMERRTGTR40 */
[37] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
[38] = {0xE62502A8U, 0x0000000FU}, /* ECMERRTGTR42 */
};
#elif (ECMERRTGTR_INTC == 0)
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
[0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
[1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
[2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
[3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
[4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
[5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
[6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
[7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
[8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
[9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
[10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
[11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
[12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[13] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
[14] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
[15] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
[16] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
[17] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
[18] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
[19] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
[20] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
[21] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
[22] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
[23] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
[24] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
[25] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
[26] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
[27] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
[28] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
[29] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
[30] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
[31] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
[32] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
[33] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[34] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
[35] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
[36] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
[37] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
[38] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
};
#endif /* ECMERRTGTR_INTC == 1 */
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR register setting.\n");
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
{
/* Set ECMERRCTLR registers. */
reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
reg |= ecmerrctlr_tbl[loop].value;
ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_tbl[loop].phys_addr),
ecmerrctlr_tbl[loop].value);
}
NOTICE("ECMERRTGTR register setting.\n");
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
{
/* Set ECMERRTGTR registers. */
reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
reg |= ecmerrtgtr_tbl[loop].value;
ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
ecmerrtgtr_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_error_enable(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

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/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE
#define ECM_ENABLE
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_error_enable(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE */

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