add IPL
This commit is contained in:
36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h
Normal file
36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM
|
||||
#define BOOT_INIT_DRAM
|
||||
|
||||
extern uint32_t R_DRAM_Init(void);
|
||||
#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U)
|
||||
void r_set_pi_rdlvl_interval(void);
|
||||
#endif
|
||||
|
||||
#define INITDRAM_OK (0)
|
||||
#define INITDRAM_NG (0xFFFFFFFFU)
|
||||
#define INITDRAM_ERR_I (0xFFFFFFFFU)
|
||||
|
||||
#endif /* BOOT_INIT_DRAM */
|
||||
12
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk
Normal file
12
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk
Normal file
@@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright (c) 2015-2023, Renesas Electronics Corporation All rights reserved.
|
||||
#
|
||||
|
||||
ifeq (${LSI},V4H)
|
||||
OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram.o
|
||||
OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram_config.o
|
||||
else ifeq (${LSI},V4M)
|
||||
OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram.o
|
||||
OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram_config.o
|
||||
endif
|
||||
OBJ_FILE += ip/ddr/dram_sub_func.o
|
||||
36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c
Normal file
36
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c
Normal file
@@ -0,0 +1,36 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "dram_sub_func.h"
|
||||
|
||||
void R_DRAM_Get_Boot_Status(uint32_t *status)
|
||||
{
|
||||
*status = DRAM_BOOT_STATUS_COLD;
|
||||
}
|
||||
|
||||
uint32_t R_DRAM_Update_Boot_Status(uint32_t status)
|
||||
{
|
||||
uint32_t ret = 0U;
|
||||
return ret;
|
||||
}
|
||||
33
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h
Normal file
33
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef DRAM_SUB_FUNC
|
||||
#define DRAM_SUB_FUNC
|
||||
|
||||
#define DRAM_BOOT_STATUS_COLD (0U)
|
||||
#define DRAM_BOOT_STATUS_WARM (1U)
|
||||
|
||||
void R_DRAM_Get_Boot_Status(uint32_t *status);
|
||||
uint32_t R_DRAM_Update_Boot_Status(uint32_t status);
|
||||
|
||||
#endif /* DRAM_SUB_FUNC_H_ */
|
||||
4613
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c
Normal file
4613
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,194 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#else
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#endif
|
||||
#include "boot_init_dram_config.h"
|
||||
#include "boot_init_dram_regdef.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PLEASE SET board number or board judge function
|
||||
******************************************************************************/
|
||||
// #define BOARD_JUDGE_AUTO
|
||||
#ifdef BOARD_JUDGE_AUTO
|
||||
static uint32_t r_board_judge(void);
|
||||
uint32_t r_boardcnf_get_brd_type(void)
|
||||
{
|
||||
return r_board_judge();
|
||||
}
|
||||
#else /* BOARD_JUDGE_AUTO */
|
||||
uint32_t r_boardcnf_get_brd_type(void)
|
||||
{
|
||||
return (2);
|
||||
}
|
||||
#endif /* BOARD_JUDGE_AUTO */
|
||||
|
||||
/**
|
||||
* RENESAS WHITE HAWK BOARD EXAMPLE
|
||||
* @par TraceID Cover_SW_UD:Cover_HW_DD
|
||||
* V4H-LPDDR5-DDR-SW-UD-01-02:V4H-LPDDR5-DDR-HW-DD-01-04-01
|
||||
* @param[in] brd Argument for dummy read
|
||||
* @param[in] clk The pointer which indicate the clock frequency
|
||||
* @param[in] div The pointer which indicate the clock frequency division
|
||||
* @details judged by md14/md13\n
|
||||
* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0)
|
||||
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
|
||||
* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1)
|
||||
*/
|
||||
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
|
||||
{
|
||||
uint32_t md;
|
||||
|
||||
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */
|
||||
case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */
|
||||
case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */
|
||||
case 0x3U : *clk = 100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */
|
||||
default : /* nop */ break;
|
||||
}
|
||||
(void)brd;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* DDR MBPS TARGET
|
||||
* PLEASE DEFINE HOW TO JUDGE DDR BPS
|
||||
******************************************************************************/
|
||||
/**
|
||||
* DDRxxxx (judge by md19, md17) : Mbps
|
||||
* @par TraceID Cover_SW_UD:Cover_HW_DD
|
||||
* V4H-LPDDR5-DDR-SW-UD-01-03:V4H-LPDDR5-DDR-HW-DD-01-04-02
|
||||
* @param[in] brd Argument for dummy read
|
||||
* @param[in] mbps The pointer which indicate the ddr frequency
|
||||
* @param[in] div The pointer which indicate the ddr frequency division
|
||||
* @details SSCG enable / disable for PLL1 (judge by md37/md36)
|
||||
* According to Bit[17] of RST_MODEMR0 and Bit[5:4] of RST_MODEMR1,
|
||||
* determine the value of ddr mbps and mbps division.
|
||||
*/
|
||||
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg)
|
||||
{
|
||||
uint32_t md;
|
||||
uint32_t product;
|
||||
|
||||
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
|
||||
md = (md | (md >> 1)) & 0x03U;
|
||||
*sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U;
|
||||
product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
|
||||
|
||||
if (product == 0x01U)
|
||||
{
|
||||
/* V4H-5 */
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
|
||||
case 0x1U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
|
||||
case 0x2U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
}
|
||||
else if (product == 0x02U)
|
||||
{
|
||||
/* V4H-3 */
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
case 0x1U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
case 0x2U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* V4H-7 */
|
||||
switch (*sscg)
|
||||
{
|
||||
case 0x0U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
default : /* nop */ break;
|
||||
}
|
||||
break;
|
||||
case 0x1U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
default : /* nop */ break;
|
||||
}
|
||||
break;
|
||||
case 0x2U : /* Not supported */
|
||||
NOTICE("This MD37/MD36 value is invalid!!\n");panic;
|
||||
case 0x3U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */
|
||||
default : /* nop */ break;
|
||||
}
|
||||
break;
|
||||
default :
|
||||
/* nop */
|
||||
break;
|
||||
}
|
||||
}
|
||||
(void)brd;
|
||||
}
|
||||
|
||||
#ifdef BOARD_JUDGE_AUTO
|
||||
/*******************************************************************************
|
||||
* SAMPLE board detect function
|
||||
******************************************************************************/
|
||||
/**
|
||||
* Select the setting parameters about the Spieder board you use.
|
||||
* @par TraceID Cover_SW_UD:Cover_HW_DD
|
||||
* V4H-LPDDR5-DDR-SW-UD-10:V4H-LPDDR5-DDR-HW-DD-01-03-02
|
||||
* @return uint32_t Selected table index, this is sample value 0.
|
||||
* @details Pass the return value from the r_board_judge function.
|
||||
* In case that "BOARD_JUDGE_AUTO" is not defined, Another process will be called.\n\n
|
||||
*/
|
||||
static uint32_t r_board_judge(void)
|
||||
{
|
||||
uint32_t brd;
|
||||
|
||||
brd = 0U; /* white hawk (64Gbit 1rank)*/
|
||||
|
||||
return brd;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,282 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_CONFIG
|
||||
#define BOOT_INIT_DRAM_CONFIG
|
||||
|
||||
#include "boot_init_dram_regdef.h"
|
||||
|
||||
//! @details DRAM Param setting
|
||||
#define JS2_DERATE 0U
|
||||
//! @details Average periodic refresh interval/Average Refresh Interval [ns]
|
||||
#define DBSC_REFINT 1920U
|
||||
#ifndef DBSC_REFINTS
|
||||
//! 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT.
|
||||
#define DBSC_REFINTS 0U
|
||||
#endif
|
||||
//! @details Periodic-WriteDQ/ReadDQ Training Interval [us]
|
||||
#define PERIODIC_TRAINING_INTERVAL 20000U
|
||||
|
||||
/*******************************************************************************
|
||||
* NUMBER OF BOARD CONFIGRATION
|
||||
* PLEASE DEFINE
|
||||
******************************************************************************/
|
||||
//! @details Add User platform BOARD
|
||||
#define BOARDNUM 3U
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD CONFIGRATION
|
||||
* PLEASE DEFINE boardcnfs[]
|
||||
******************************************************************************/
|
||||
uint32_t r_boardcnf_get_brd_type(void);
|
||||
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
|
||||
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg);
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD CONFIGRATION
|
||||
* PLEASE DEFINE boardcnfs[]
|
||||
******************************************************************************/
|
||||
typedef struct{
|
||||
/*
|
||||
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
|
||||
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
|
||||
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
|
||||
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
|
||||
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
|
||||
0x05...0101B: 24Gb dual channel die / 12Gb single channel die
|
||||
0x06...0110B: 32Gb dual channel die / 16Gb single channel die
|
||||
0x07...0111B: 24Gb single channel die
|
||||
0x08...1000B: 32Gb single channel die
|
||||
0xFF...NO_MEMORY
|
||||
*/
|
||||
uint8_t bdcfg_ddr_density[CS_CNT];
|
||||
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
|
||||
uint32_t bdcfg_ca_swap;
|
||||
/* SoC dqsX([1][0]) -> MEM dqsY: */
|
||||
uint8_t bdcfg_dqs_swap;
|
||||
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
|
||||
uint32_t bdcfg_dq_swap[SLICE_CNT];
|
||||
/* SoC dm -> MEM dqY/dm: (8 means DM) */
|
||||
uint8_t bdcfg_dm_swap[SLICE_CNT];
|
||||
/* SoC ckeX([1][0]) -> MEM csY */
|
||||
uint8_t bdcfg_cs_swap;
|
||||
}st_boardcnf_ch_t;
|
||||
|
||||
typedef struct {
|
||||
|
||||
/* ch in use */
|
||||
uint8_t bdcfg_phyvalid;
|
||||
/* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */
|
||||
uint32_t bdcfg_vref_r;
|
||||
/* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
|
||||
uint16_t bdcfg_vref_w;
|
||||
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
|
||||
uint16_t bdcfg_vref_ca;
|
||||
/* RFM required check : 0x01 = check enable, 0x00 = check disable */
|
||||
uint8_t bdcfg_rfm_chk;
|
||||
//! @details Board parameter about channels
|
||||
st_boardcnf_ch_t ch[4];
|
||||
}st_boardcnf_t;
|
||||
|
||||
static const st_boardcnf_t boardcnfs[BOARDNUM] = {
|
||||
/*
|
||||
* boardcnf[0] RENESAS V4H White Hawk (64Gbit 1rank)
|
||||
*/
|
||||
{
|
||||
0x0FU, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x04506132U,
|
||||
/* bdcfg_dqs_swap */ 0x01U,
|
||||
/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U },
|
||||
/* bdcfg_dm_swap[] */ { 0x03U, 0x07U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x02341065U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U },
|
||||
/* bdcfg_dm_swap[] */ { 0x00U, 0x02U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[2] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x02150643U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U },
|
||||
/* bdcfg_dm_swap[] */ { 0x03U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[3] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x01546230U,
|
||||
/* bdcfg_dqs_swap */ 0x01U,
|
||||
/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U },
|
||||
/* bdcfg_dm_swap[] */ { 0x00U, 0x03U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
}
|
||||
}
|
||||
},
|
||||
#if 0 // added from v3.33.3, not used
|
||||
/*
|
||||
* boardcnf[1] RENESAS V4H White Hawk (64Gbit 2rank)
|
||||
*/
|
||||
{
|
||||
0x0FU, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
|
||||
/* bdcfg_ca_swap */ 0x04506132U,
|
||||
/* bdcfg_dqs_swap */ 0x01U,
|
||||
/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U },
|
||||
/* bdcfg_dm_swap[] */ { 0x03U, 0x07U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
|
||||
/* bdcfg_ca_swap */ 0x02341065U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U },
|
||||
/* bdcfg_dm_swap[] */ { 0x00U, 0x02U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[2] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
|
||||
/* bdcfg_ca_swap */ 0x02150643U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U },
|
||||
/* bdcfg_dm_swap[] */ { 0x03U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[3] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x04U, 0x04U },
|
||||
/* bdcfg_ca_swap */ 0x01546230U,
|
||||
/* bdcfg_dqs_swap */ 0x01U,
|
||||
/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U },
|
||||
/* bdcfg_dm_swap[] */ { 0x00U, 0x03U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
}
|
||||
}
|
||||
},
|
||||
#endif
|
||||
/*
|
||||
* boardcnf[1] RENESAS V4H (4ch)
|
||||
*/
|
||||
{
|
||||
0x0FU, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[2] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[3] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
}
|
||||
}
|
||||
},
|
||||
/*
|
||||
* boardcnf[2]MOBIS Proto1 20240717
|
||||
*/
|
||||
{
|
||||
0x0FU, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */0x04506132U,
|
||||
/* bdcfg_dqs_swap */0x01U,
|
||||
/* bdcfg_dq_swap[] */{ 0x26147085U, 0x12306845U },
|
||||
/* bdcfg_dm_swap[] */{ 0x03U, 0x07U },
|
||||
/* bdcfg_cs_swap */0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */0x02341065U,
|
||||
/* bdcfg_dqs_swap */0x10U,
|
||||
/* bdcfg_dq_swap[] */{ 0x58762314U, 0x71048365U },
|
||||
/* bdcfg_dm_swap[] */{ 0x00U, 0x02U },
|
||||
/* bdcfg_cs_swap */0x10U
|
||||
},
|
||||
/* ch[2] */ {
|
||||
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */0x02150643U,
|
||||
/* bdcfg_dqs_swap */0x10U,
|
||||
/* bdcfg_dq_swap[] */{ 0x58264071U, 0x41207536U },
|
||||
/* bdcfg_dm_swap[] */{ 0x03U, 0x08U },
|
||||
/* bdcfg_cs_swap */0x10U
|
||||
},
|
||||
/* ch[3] */ {
|
||||
/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU },
|
||||
/* bdcfg_ca_swap */0x01546230U,
|
||||
/* bdcfg_dqs_swap */0x01U,
|
||||
/* bdcfg_dq_swap[] */{ 0x48761325U, 0x62801745U },
|
||||
/* bdcfg_dm_swap[] */{ 0x00U, 0x03U },
|
||||
/* bdcfg_cs_swap */0x10U
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
};
|
||||
#endif /* BOOT_INIT_DRAM_CONFIG */
|
||||
@@ -0,0 +1,203 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_REGDEF
|
||||
#define BOOT_INIT_DRAM_REGDEF
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#include "remap_register.h"
|
||||
#endif
|
||||
|
||||
//! @details The version of DDR code
|
||||
#define RCAR_DDR_VERSION "rev.1.10"
|
||||
//! @details The number of channels V4H has
|
||||
#define DRAM_CH_CNT 0x04U
|
||||
//! @details The number of slices V4H has
|
||||
#define SLICE_CNT 0x02U
|
||||
//! @details The number of chip select V4H has
|
||||
#define CS_CNT 0x02U
|
||||
|
||||
//! @details for pll setting
|
||||
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
|
||||
|
||||
//! @details for ddr density setting
|
||||
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
|
||||
//! @details for 16bit value
|
||||
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */
|
||||
|
||||
//! @details Kick bit setting CPG PLL3 division
|
||||
#define CPG_FRQCRD_KICK_BIT (1U << 31)
|
||||
//! @details Kick bit to reflect setting CPG PLL3 value
|
||||
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
|
||||
//! @details Status bit to check CPG PLL3 works normally
|
||||
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
//! @details If this bin is processed by RH850G3K, address will be remapped.
|
||||
#define CPG_BASE (BASE_CPG_ADDR)
|
||||
#else
|
||||
//! @details If this bin is processed by Arm core, address will be "0xE6150000U".
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#endif
|
||||
//! @details 32-bit readable/writable register
|
||||
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
|
||||
//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency
|
||||
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
|
||||
//! @details PLL Enable Control Register
|
||||
#define CPG_PLLECR (CPG_BASE + 0x0820U)
|
||||
//! @details The register specifies the integer multiplication ratio
|
||||
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
|
||||
//! @details The register specifies the fractional multiplication
|
||||
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
|
||||
//! @details Functional Safety Reset Check Clear Register
|
||||
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
|
||||
//! @details Functional Safety Reset Check Set Register
|
||||
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
|
||||
//! @details Functional Safety Reset Check Register A
|
||||
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
|
||||
//! @details Software Reset Status Register
|
||||
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
|
||||
//! @details Software Reset Clearing Register
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
//! @details If this bin is processed by RH850G3K, address will be remapped.
|
||||
#define RST_BASE (BASE_RESET_ADDR)
|
||||
#else
|
||||
//! @details If this bin is processed by Arm core, address will be 0xE6160000U.
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#endif
|
||||
//! @details 32-bit read-only register, which is initialized only by POR.
|
||||
#define RST_MODEMR0 (RST_BASE + 0x0000U)
|
||||
//! @details 32-bit read-only register, which is initialized only by POR.
|
||||
#define RST_MODEMR1 (RST_BASE + 0x0004U)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR)
|
||||
#else
|
||||
#define OTP_MEM_1_BASE (0xE61BF000U)
|
||||
#endif
|
||||
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
|
||||
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
|
||||
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
|
||||
|
||||
#define PRR_PRODUCT_30 (0x00000020U) /* ver 3.0 */
|
||||
|
||||
/* DBSC registers */
|
||||
#if defined(__RH850G3K__)
|
||||
//! @details If this bin is processed by RH850G3K, address will be remapped.
|
||||
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#else
|
||||
//! @details If this bin is processed by RH850G3K, address will be remapped.
|
||||
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#endif
|
||||
//! @details DBSC4 System Configuration Register 0
|
||||
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
|
||||
//! @details DBSC4 System Configuration Register 1(for DFI domain)
|
||||
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
|
||||
//! @details DBSC4 System Configuration Register 1(for AXI domain)
|
||||
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
|
||||
//! @details DBSC4 System Configuration Register 2
|
||||
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
|
||||
//! @details PHY type Configuration Register
|
||||
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
|
||||
//! @details PHY type Configuration Register 2A
|
||||
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
|
||||
//! @details Memory Type register (for DFI domain)
|
||||
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
|
||||
//! @details Memory Type register (for AXI domain)
|
||||
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
|
||||
//! @details SDRAM Configuration setting Register (for DFI domain)
|
||||
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
|
||||
//! @details SDRAM Configuration setting Register (for AXI domain)
|
||||
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
|
||||
//! @details DBSC System Register 0(For DFI Domain)
|
||||
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
|
||||
//! @details DBSC System Register 0(For AXI Domain)
|
||||
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
|
||||
//! @details SDRAM Access Enable Register
|
||||
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
|
||||
//! @details Auto-Refresh Enable Register
|
||||
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
|
||||
//! @details Manual Command-Issuing Register
|
||||
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
|
||||
//! @details Operation Complition Waiting Register
|
||||
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
|
||||
//! @details SDRAM Operation Setting Register(for DFI domain)
|
||||
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
|
||||
//! @details SDRAM Operation Setting Register(for AXI domain)
|
||||
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
|
||||
//! @details Refresh Configuration Register 1
|
||||
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
|
||||
//! @details Refresh Configuration Register 2
|
||||
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
|
||||
//! @details SDRAM Callibration Configuration Register
|
||||
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
|
||||
//! @details DBI Configuration Register
|
||||
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
|
||||
//! @details DFI PHY Master Control Register
|
||||
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
|
||||
//! @details DFI Control Update Configuration Register
|
||||
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
|
||||
//! @details CAM Unit Operation Setting Register
|
||||
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
|
||||
//! @details Read/Write Scheduling Setting Register 1
|
||||
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
|
||||
//! @details Data Transfer Cycle Setting
|
||||
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
|
||||
//! @details SDRAM Timing Register X
|
||||
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
|
||||
//! @details Multirank Operation Setting Register x
|
||||
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
|
||||
//! @details DFI Status Interface Input Regiser
|
||||
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details DFI Status Interface Output Regiser
|
||||
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Unit Control Register 02
|
||||
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Unit Lock register
|
||||
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Unit register address
|
||||
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Unit register access
|
||||
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Unit Registers Mask for channel
|
||||
#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Status Register0 ch
|
||||
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details PHY Status Register1 ch
|
||||
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
//! @details Interval Setting for scheduler
|
||||
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
|
||||
//! @details Interval Setting for scheduler
|
||||
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF */
|
||||
269
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h
Normal file
269
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h
Normal file
@@ -0,0 +1,269 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef DDR_REGDEF
|
||||
#define DDR_REGDEF
|
||||
|
||||
#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U
|
||||
#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x10011006U
|
||||
#define PHY_VREF_INITIAL_STEPSIZE 0x1808100DU
|
||||
#define PHY_RDLVL_BEST_THRSHLD 0x0004100EU
|
||||
#define PHY_RDLVL_VREF_OUTLIER 0x1003100EU
|
||||
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1005102CU
|
||||
#define PHY_CALVL_VREF_DRIVING_SLICE 0x18011030U
|
||||
#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A1038U
|
||||
#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A1038U
|
||||
#define PHY_WRLVL_STATUS_OBS 0x001C1039U
|
||||
#define PHY_WRLVL_ERROR_OBS 0x0010103BU
|
||||
#define PHY_GTLVL_STATUS_OBS 0x0012103DU
|
||||
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x1009103EU
|
||||
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x0009103FU
|
||||
#define PHY_WDQLVL_STATUS_OBS 0x00201043U
|
||||
#define PHY_DATA_DC_CAL_START 0x1801104DU
|
||||
#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x1001104EU
|
||||
#define PHY_REGULATOR_EN_CNT 0x18061050U
|
||||
#define PHY_VREF_INITIAL_START_POINT 0x00091055U
|
||||
#define PHY_VREF_INITIAL_STOP_POINT 0x10091055U
|
||||
#define PHY_VREF_TRAINING_CTRL 0x00021056U
|
||||
#define PHY_RDDQ0_SLAVE_DELAY 0x0009105DU
|
||||
#define PHY_RDDQ1_SLAVE_DELAY 0x1009105DU
|
||||
#define PHY_RDDQ2_SLAVE_DELAY 0x0009105EU
|
||||
#define PHY_RDDQ3_SLAVE_DELAY 0x1009105EU
|
||||
#define PHY_RDDQ4_SLAVE_DELAY 0x0009105FU
|
||||
#define PHY_RDDQ5_SLAVE_DELAY 0x1009105FU
|
||||
#define PHY_RDDQ6_SLAVE_DELAY 0x00091060U
|
||||
#define PHY_RDDQ7_SLAVE_DELAY 0x10091060U
|
||||
#define PHY_RDDM_SLAVE_DELAY 0x00091061U
|
||||
#define PHY_RX_CAL_ALL_DLY 0x18061061U
|
||||
#define PHY_RX_PCLK_CLK_SEL 0x00031062U
|
||||
#define PHY_DATA_DC_CAL_CLK_SEL 0x18031063U
|
||||
#define PHY_PAD_VREF_CTRL_DQ 0x000E1067U
|
||||
#define PHY_PER_CS_TRAINING_EN 0x00011068U
|
||||
#define PHY_RDDATA_EN_TSEL_DLY 0x18051069U
|
||||
#define PHY_RDDATA_EN_OE_DLY 0x0005106AU
|
||||
#define PHY_RPTR_UPDATE 0x1004106CU
|
||||
#define PHY_WRLVL_RESP_WAIT_CNT 0x0806106DU
|
||||
#define PHY_RDLVL_DLY_STEP 0x08041070U
|
||||
#define PHY_RDLVL_MAX_EDGE 0x00091071U
|
||||
#define PHY_RDDATA_EN_DLY 0x10051076U
|
||||
#define PHY_DQ_DM_SWIZZLE0 0x00201077U
|
||||
#define PHY_DQ_DM_SWIZZLE1 0x00041078U
|
||||
#define PHY_CLK_WRDQS_SLAVE_DELAY 0x0009107EU
|
||||
#define PHY_WRITE_PATH_LAT_DEC 0x1001107EU
|
||||
#define PHY_RDDQS_GATE_SLAVE_DELAY 0x00091088U
|
||||
#define PHY_RDDQS_LATENCY_ADJUST 0x10051088U
|
||||
#define PHY_WRITE_PATH_LAT_ADD 0x18031088U
|
||||
#define PHY_WRITE_PATH_LAT_FRAC 0x00081089U
|
||||
#define PHY_GTLVL_LAT_ADJ_START 0x0005108AU
|
||||
#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U
|
||||
#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U
|
||||
#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U
|
||||
#define PHY_ADR_CALVL_OBS1 0x0020120AU
|
||||
#define PHY_ADR_CALVL_OBS2 0x0020120BU
|
||||
#define PHY_ADR_CALVL_DLY_STEP 0x00041210U
|
||||
#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U
|
||||
#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U
|
||||
#define PHY_CSLVL_OBS1 0x00201221U
|
||||
#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU
|
||||
#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U
|
||||
#define PHY_FREQ_SEL_INDEX 0x10021301U
|
||||
#define SC_PHY_MANUAL_UPDATE 0x18011304U
|
||||
#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U
|
||||
#define PHY_CAL_MODE_0 0x000D132CU
|
||||
#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU
|
||||
#define PHY_DATA_BYTE_ORDER_SEL 0x0020133EU
|
||||
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x10031348U
|
||||
#define PHY_PLL_CTRL 0x000E134BU
|
||||
#define PHY_PLL_CTRL_8X 0x100E134BU
|
||||
#define PHY_CAL_CLK_SELECT_0 0x00031360U
|
||||
#define SC_PHY_WCK_CALC 0x1801101AU
|
||||
#define PI_START 0x00010800U
|
||||
#define PI_TRAIN_ALL_FREQ_REQ 0x18010802U
|
||||
#define PI_CS_MAP 0x08020813U
|
||||
#define PI_WRLVL_REQ 0x1001081CU
|
||||
#define PI_WRLVL_CS_SW 0x1802081CU
|
||||
#define PI_RDLVL_REQ 0x18010824U
|
||||
#define PI_RDLVL_GATE_REQ 0x00010825U
|
||||
#define PI_RDLVL_CS_SW 0x08020825U
|
||||
#define PI_DRAMDCA_FLIP_MASK 0x0802083BU
|
||||
#define PI_DRAMDCA_LVL_REQ 0x1001083DU
|
||||
#define PI_DCMLVL_CS_SW 0x1802083DU
|
||||
#define PI_WRDCM_LVL_EN_F1 0x0002083FU
|
||||
#define PI_DRAMDCA_LVL_EN_F1 0x0802083FU
|
||||
#define PI_WRDCM_LVL_EN_F2 0x1802083FU
|
||||
#define PI_DRAMDCA_LVL_EN_F2 0x00020840U
|
||||
#define PI_TCKCKEL_F2 0x1804089DU
|
||||
#define PI_INT_STATUS 0x00200900U
|
||||
#define PI_INT_ACK_0 0x00200902U
|
||||
#define PI_INT_ACK_1 0x00030903U
|
||||
#define PI_ADDR_MUX_0 0x00030910U
|
||||
#define PI_ADDR_MUX_1 0x08030910U
|
||||
#define PI_ADDR_MUX_2 0x10030910U
|
||||
#define PI_ADDR_MUX_3 0x18030910U
|
||||
#define PI_ADDR_MUX_4 0x00030911U
|
||||
#define PI_ADDR_MUX_5 0x08030911U
|
||||
#define PI_ADDR_MUX_6 0x10030911U
|
||||
#define PI_DATA_BYTE_SWAP_EN 0x18010911U
|
||||
#define PI_DATA_BYTE_SWAP_SLICE0 0x00010912U
|
||||
#define PI_DATA_BYTE_SWAP_SLICE1 0x08010912U
|
||||
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00080964U
|
||||
#define PI_WRLAT_F2 0x1007096AU
|
||||
#define PI_TWCKENL_WR_ADJ_F2 0x1806096AU
|
||||
#define PI_TWCKENL_RD_ADJ_F2 0x0006096BU
|
||||
#define PI_TWCKPRE_STATIC_F2 0x0806096BU
|
||||
#define PI_TWCKPRE_TOGGLE_RD_F2 0x1806096BU
|
||||
#define PI_TWCKENL_FS_ADJ_F2 0x0006096CU
|
||||
#define PI_CASLAT_F2 0x0807096CU
|
||||
#define PI_TRFC_F2 0x000A0971U
|
||||
#define PI_TREF_F2 0x00140972U
|
||||
#define PI_TDFI_WRLVL_WW_F0 0x000A0974U
|
||||
#define PI_TDFI_WRLVL_WW_F1 0x000A0975U
|
||||
#define PI_WRLVL_EN_F2 0x18020975U
|
||||
#define PI_TDFI_WRLVL_WW_F2 0x000A0976U
|
||||
#define PI_WRLVL_WCKOFF_F2 0x10080976U
|
||||
#define PI_RDLVL_EN_F2 0x1802097AU
|
||||
#define PI_RDLVL_GATE_EN_F2 0x0002097BU
|
||||
#define PI_RDLVL_VREF_EN_F0 0x1004097BU
|
||||
#define PI_RDLVL_VREF_EN_F1 0x0004097DU
|
||||
#define PI_RDLVL_VREF_EN_F2 0x1004097EU
|
||||
#define PI_RDLAT_ADJ_F2 0x00090981U
|
||||
#define PI_WRLAT_ADJ_F2 0x00070982U
|
||||
#define PI_TDFI_CALVL_CC_F2 0x000A0985U
|
||||
#define PI_TDFI_CALVL_CAPTURE_F2 0x100A0985U
|
||||
#define PI_CALVL_EN_F2 0x10020986U
|
||||
#define PI_TCAENT_F2 0x000E0989U
|
||||
#define PI_TVREF_SHORT_F2 0x000A098FU
|
||||
#define PI_TVREF_LONG_F2 0x100A098FU
|
||||
#define PI_TVRCG_ENABLE_F2 0x000A0990U
|
||||
#define PI_TVRCG_DISABLE_F2 0x100A0990U
|
||||
#define PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00070991U
|
||||
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x08070991U
|
||||
#define PI_CALVL_VREF_INITIAL_START_POINT_F1 0x18070991U
|
||||
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00070992U
|
||||
#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070992U
|
||||
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070992U
|
||||
#define PI_TDFI_CALVL_STROBE_F2 0x08040995U
|
||||
#define PI_TXP_F2 0x10050995U
|
||||
#define PI_TMRWCKEL_F2 0x18080995U
|
||||
#define PI_TCKEHDQS_F2 0x1006099DU
|
||||
#define PI_TFC_F2 0x000A099EU
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100709A0U
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180709A0U
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000709A4U
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080709A4U
|
||||
#define PI_TDFI_WDQLVL_WR_F2 0x000A09A6U
|
||||
#define PI_TDFI_WDQLVL_RW_F2 0x100A09A6U
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x000709A7U
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x080709A7U
|
||||
#define PI_WDQLVL_EN_F2 0x180209A7U
|
||||
#define PI_MBIST_RDLAT_ADJ_F2 0x080909A8U
|
||||
#define PI_MBIST_TWCKENL_RD_ADJ_F2 0x180609A8U
|
||||
#define PI_TRTP_F2 0x180809B3U
|
||||
#define PI_TRP_F2 0x000809B4U
|
||||
#define PI_TRCD_F2 0x080809B4U
|
||||
#define PI_TWTR_S_F2 0x180609B4U
|
||||
#define PI_TWTR_L_F2 0x000609B5U
|
||||
#define PI_TWTR_F2 0x100609B5U
|
||||
#define PI_TWR_F2 0x180809B5U
|
||||
#define PI_TRAS_MIN_F2 0x100909B6U
|
||||
#define PI_TDQSCK_MAX_F2 0x000409B7U
|
||||
#define PI_TSR_F2 0x100809B7U
|
||||
#define PI_TMRD_F2 0x180809B7U
|
||||
#define PI_TDFI_CTRLUPD_MAX_F2 0x001509BCU
|
||||
#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x002009BDU
|
||||
#define PI_TINIT_F2 0x001809CCU
|
||||
#define PI_TINIT1_F2 0x001809CDU
|
||||
#define PI_TINIT3_F2 0x001809CEU
|
||||
#define PI_TINIT4_F2 0x001809CFU
|
||||
#define PI_TINIT5_F2 0x001809D0U
|
||||
#define PI_TXSNR_F2 0x001009D1U
|
||||
#define PI_TZQCAL_F2 0x100C09D6U
|
||||
#define PI_TZQLAT_F2 0x000709D7U
|
||||
#define PI_ZQRESET_F2 0x100C09D8U
|
||||
#define PI_TDQ72DQ_F2 0x100A09DDU
|
||||
#define PI_TCBTRTW_F2 0x000609DEU
|
||||
#define PI_MC_TRFC_F2 0x000A09E1U
|
||||
#define PI_CKE_MUX_0 0x000309E6U
|
||||
#define PI_CKE_MUX_1 0x080309E6U
|
||||
#define PI_SEQ_DEC_SW_CS 0x00020A4EU
|
||||
#define PI_SW_SEQ_START 0x10010A4EU
|
||||
#define PI_SW_SEQ_0 0x001B0BF1U
|
||||
#define PI_SW_SEQ_1 0x001B0BF2U
|
||||
#define PI_DFS_ENTRY_SEQ_0 0x001D0BFBU
|
||||
#define PI_DFS_INITIALIZATION_SEQ_1 0x001D0C24U
|
||||
#define PI_DFS_INITIALIZATION_SEQ_9 0x001D0C2CU
|
||||
#define PI_DFS_INITIALIZATION_SEQ_10 0x001D0C2DU
|
||||
#define PI_SEQ_WAIT_16_F2 0x00180C77U
|
||||
#define PI_SEQ_WAIT_17_F2 0x00180C7AU
|
||||
#define PI_SEQ_WAIT_18_F2 0x00180C7DU
|
||||
#define PI_SEQ_WAIT_19_F2 0x00180C80U
|
||||
#define PI_SEQ_WAIT_20_F2 0x00180C83U
|
||||
#define PI_SEQ_WAIT_21_F2 0x00180C86U
|
||||
#define PI_SEQ_WAIT_22_F2 0x00180C89U
|
||||
#define PI_SEQ_WAIT_23_F2 0x00180C8CU
|
||||
#define PI_SEQ_WAIT_24_F2 0x00180C8FU
|
||||
#define PI_SEQ_WAIT_25_F2 0x00180C92U
|
||||
#define PI_SEQ_WAIT_26_F2 0x00180C95U
|
||||
#define PI_SEQ_WAIT_30_F2 0x00180CA1U
|
||||
#define PI_DARRAY3_0_CS0_F0 0x00080D0BU
|
||||
#define PI_DARRAY3_1_CS0_F0 0x08080D0BU
|
||||
#define PI_DARRAY3_0_CS0_F1 0x00080D15U
|
||||
#define PI_DARRAY3_1_CS0_F1 0x08080D15U
|
||||
#define PI_DARRAY3_0_CS0_F2 0x00080D1FU
|
||||
#define PI_DARRAY3_1_CS0_F2 0x08080D1FU
|
||||
#define PI_DARRAY3_4_CS0_F2 0x00080D20U
|
||||
#define PI_DARRAY3_20_CS0_F2 0x00080D24U
|
||||
#define PI_DARRAY3_0_CS1_F0 0x00080D29U
|
||||
#define PI_DARRAY3_1_CS1_F0 0x08080D29U
|
||||
#define PI_DARRAY3_0_CS1_F1 0x00080D33U
|
||||
#define PI_DARRAY3_1_CS1_F1 0x08080D33U
|
||||
#define PI_DARRAY3_0_CS1_F2 0x00080D3DU
|
||||
#define PI_DARRAY3_1_CS1_F2 0x08080D3DU
|
||||
#define PI_DARRAY3_4_CS1_F2 0x00080D3EU
|
||||
#define PI_DARRAY3_20_CS1_F2 0x00080D42U
|
||||
#define PI_DLL_RST 0x00010941U
|
||||
#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU
|
||||
#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU
|
||||
#define PI_RDLVL_TRAIN_SEQ_1 0x001B0C42U
|
||||
#define PI_RDLVL_TRAIN_SEQ_2 0x001B0C43U
|
||||
#define PI_RDLVL_TRAIN_SEQ_3 0x001B0C44U
|
||||
#define PI_RDLVL_TRAIN_SEQ_4 0x001B0C45U
|
||||
#define PI_RDLVL_TRAIN_SEQ_5 0x001B0C46U
|
||||
#define PI_WDQLVL_VREF_EN 0x0804089EU
|
||||
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 0x001B0868U
|
||||
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 0x001B0869U
|
||||
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 0x001B086AU
|
||||
#define PHY_PER_CS_TRAINING_INDEX 0x18011006U
|
||||
#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008108CU
|
||||
#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021075U
|
||||
#define PI_WDQLVL_PERIODIC 0x000108A0U
|
||||
#define PHY_MEAS_DLY_STEP_ENABLE 0x08061076U
|
||||
#define PI_RDLVL_PERIODIC 0x0801082EU
|
||||
#define PI_LONG_COUNT_MASK 0x1005090FU
|
||||
#define PI_WDQLVL_INTERVAL 0x001008A4U
|
||||
#define PI_RDLVL_INTERVAL 0x08100835U
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)
|
||||
|
||||
#endif /* DDR_REGDEF */
|
||||
@@ -0,0 +1,183 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECC initialize function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ecc_enable_v4h.c
|
||||
* - Version : 0.06
|
||||
* @brief Enable setting process of ECC for DRAM.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 09.08.2022 0.01 First Release
|
||||
* : 16.11.2022 0.02 Change ecc_enable to ecc_sdram_enable
|
||||
* : 04.04.2023 0.03 Removed stdio.h and string.h.
|
||||
* : 20.09.2023 0.04 Update the ecc_sdram_enable function according to HWSAN rev0.82.
|
||||
* : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise
|
||||
* : the ecm_lock()/ecm_unlock() process.
|
||||
* : 27.01.2025 0.06 Remove unused functions.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#if (ECC_ENABLE == 1)
|
||||
#include "ecc_enable_v4h.h"
|
||||
#include "ecm_enable_v4h.h"
|
||||
#include "mem_io.h"
|
||||
#include "v4h/lpddr5/boot_init_dram_regdef.h"
|
||||
|
||||
/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
|
||||
void ecc_sdram_enable(void)
|
||||
{
|
||||
NOTICE("ECC for DRAM is enable.\n");
|
||||
|
||||
uint32_t ecm_tmp;
|
||||
|
||||
/* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
|
||||
After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
|
||||
mem_write32(DB0SYSCNT0, 0x00001234U);
|
||||
mem_write32(DB1SYSCNT0, 0x00001234U);
|
||||
mem_write32(DB0SYSCNT0A, 0x00001234U);
|
||||
mem_write32(DB1SYSCNT0A, 0x00001234U);
|
||||
|
||||
/* (A) Setting ECM */
|
||||
/* Unlock the write protect of ECM registers */
|
||||
ecm_unlock();
|
||||
|
||||
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
|
||||
to inform the external device of the error via the ERROROUT# pin. */
|
||||
/* Set bit 3, 1 of ECMERRTGTR0 to 0 and bit 3, 1 of ECMERRCTLR0 to 1. */
|
||||
ecm_tmp = mem_read32(ECMERRTGTR0);
|
||||
ecm_tmp &= ~(0xAU);
|
||||
ecm_write(ECMERRTGTR0, ecm_tmp);
|
||||
|
||||
ecm_tmp = mem_read32(ECMERRCTLR0);
|
||||
ecm_tmp |= (0xAU);
|
||||
ecm_write(ECMERRCTLR0, ecm_tmp);
|
||||
|
||||
/* (B) Setting ECC protection area */
|
||||
/* Set the bottom row address of the ECC protection area */
|
||||
mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
|
||||
mem_write32(DB1FSDRAMECCAREA00, ECC_PROT_SIZE10);
|
||||
|
||||
/* (C) Initialization for DRAM */
|
||||
mem_write32(DBSC_DB0ACEN, 0x00000000U);
|
||||
mem_write32(DBSC_DB1ACEN, 0x00000000U);
|
||||
|
||||
/*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
|
||||
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
|
||||
mem_write32(DB0FSCONF00A, 0x0U);
|
||||
|
||||
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
|
||||
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
|
||||
|
||||
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
|
||||
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
|
||||
|
||||
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
|
||||
mem_write32(DB0FSCTRL01A, 0x01U);
|
||||
|
||||
/*** Initialization for DRAM connected to DBS1 Initialize RANK0 in according with the following procedure.***/
|
||||
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB1FSCONF00A[1:0]. */
|
||||
mem_write32(DB1FSCONF00A, 0x0U);
|
||||
|
||||
/* [Step2] Set the start row address of the initialization area in DB1FSCONF01A[31:0]. */
|
||||
mem_write32(DB1FSCONF01A, START_ECC_INIT_AREA10);
|
||||
|
||||
/* [Step3] Set the end row address of the initialization area in DB1FSCONF02A[31:0]. */
|
||||
mem_write32(DB1FSCONF02A, END_ECC_INIT_AREA10);
|
||||
|
||||
/* [Step4] Set 0x1 to DB1FSCTRL01A[0] to start initialization. */
|
||||
mem_write32(DB1FSCTRL01A, 0x01U);
|
||||
|
||||
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
|
||||
/* [Step5] When DB1FSSTAT01A[0] is set to 0x1, DBS1/RANK0 initialization is complete.*/
|
||||
NOTICE("DRAM rank 0 of DBSC0/1 is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB0FSSTAT01A);
|
||||
ecm_tmp &= mem_read32(DB1FSSTAT01A);
|
||||
} while ((ecm_tmp & 0x01U) != 0x01U);
|
||||
|
||||
/* (D) Setting ECC protection enable */
|
||||
/* Enable ECC protection for dbs0/rank0 by setting 0x1 in DB0FSCONFAXI0[8]. */
|
||||
ecm_tmp = mem_read32(DB0FSCONFAXI0);
|
||||
ecm_tmp |= (0x1U << 8U);
|
||||
mem_write32(DB0FSCONFAXI0, ecm_tmp);
|
||||
|
||||
/* Enable ECC protection for dbs1/rank0 by setting 0x1 in DB1FSCONFAXI0[8]. */
|
||||
ecm_tmp = mem_read32(DB1FSCONFAXI0);
|
||||
ecm_tmp |= (0x1U << 8U);
|
||||
mem_write32(DB1FSCONFAXI0, ecm_tmp);
|
||||
|
||||
/* (E) System RAM initialization */
|
||||
NOTICE("System RAM of DBSC0 is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB0FSSTAT00A);
|
||||
} while (ecm_tmp != 0x1U);
|
||||
|
||||
NOTICE("System RAM of DBSC1 is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB1FSSTAT00A);
|
||||
} while (ecm_tmp != 0x1U);
|
||||
|
||||
/* (F) Setting for ECC error interrupt */
|
||||
/* (1) Set the ECC error interrupt for read data. */
|
||||
mem_write32(DB0FSINTENB02A, 0xFF00U);
|
||||
mem_write32(DB1FSINTENB02A, 0xFF00U);
|
||||
|
||||
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
|
||||
ecm_tmp = mem_read32(DB0FSINTENB02A);
|
||||
ecm_tmp |= 0xFF000000U;
|
||||
mem_write32(DB0FSINTENB02A, ecm_tmp);
|
||||
ecm_tmp = mem_read32(DB1FSINTENB02A);
|
||||
ecm_tmp |= 0xFF000000U;
|
||||
mem_write32(DB1FSINTENB02A, ecm_tmp);
|
||||
|
||||
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
|
||||
mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
|
||||
mem_write32(DB1FSINTENB04A, 0xFFFFFFFFU);
|
||||
|
||||
/* Lock the ECM registers */
|
||||
ecm_lock();
|
||||
|
||||
/* Enable the write protect of ECM registers */
|
||||
mem_write32(DBSC_DB0ACEN, 0x00000001U);
|
||||
mem_write32(DBSC_DB1ACEN, 0x00000001U);
|
||||
|
||||
/* Enable the access protect for DBSC registers */
|
||||
mem_write32(DB0SYSCNT0, 0x00000000U);
|
||||
mem_write32(DB1SYSCNT0, 0x00000000U);
|
||||
mem_write32(DB0SYSCNT0A, 0x00000000U);
|
||||
mem_write32(DB1SYSCNT0A, 0x00000000U);
|
||||
}
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECC driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef ECC_PROTECT
|
||||
#define ECC_PROTECT
|
||||
/* DBSC registers */
|
||||
#if defined(__RH850G3K__)
|
||||
#include "remap_register.h"
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#define ECM_BASE (BASE_ECC_ADDR)
|
||||
#else
|
||||
#if (ECC_ENABLE == 1)
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
#define ECM_BASE (0xE6250000U)
|
||||
#endif/* defined(__RH850G3K__) */
|
||||
|
||||
#if (ECC_ENABLE == 1)
|
||||
void ecc_sdram_enable(void);
|
||||
|
||||
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
|
||||
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
|
||||
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
|
||||
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
|
||||
|
||||
#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U)
|
||||
#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U)
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
#define ECMWACNTR (ECM_BASE + 0x0A04U)
|
||||
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
|
||||
#if (ECC_ENABLE == 1)
|
||||
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
|
||||
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
|
||||
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
|
||||
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
|
||||
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
|
||||
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
|
||||
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
|
||||
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
|
||||
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
|
||||
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
|
||||
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
|
||||
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
|
||||
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
|
||||
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
|
||||
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
|
||||
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
|
||||
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
|
||||
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
|
||||
|
||||
#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U)
|
||||
#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U)
|
||||
#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U)
|
||||
#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U)
|
||||
|
||||
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
|
||||
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
|
||||
|
||||
/********************* Set by the user *********************/
|
||||
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
|
||||
#define ECC_PROT_SIZE00 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE01 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE10 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE11 (0xCCCCU)
|
||||
|
||||
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
|
||||
#define START_ECC_INIT_AREA00 (0x00000000U)
|
||||
#define START_ECC_INIT_AREA10 (0x00000000U)
|
||||
#define END_ECC_INIT_AREA00 (0x0000CCCBU)
|
||||
#define END_ECC_INIT_AREA10 (0x0000CCCBU)
|
||||
|
||||
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
|
||||
#define START_ECC_INIT_AREA01 (0x00000000U)
|
||||
#define START_ECC_INIT_AREA11 (0x00000000U)
|
||||
#define END_ECC_INIT_AREA01 (0x0000CCCBU)
|
||||
#define END_ECC_INIT_AREA11 (0x0000CCCBU)
|
||||
/*********** Other settings cannot be changed ***************/
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
#endif/* ECC_PROTECT */
|
||||
@@ -0,0 +1,260 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECM initialize function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ecm_enable_v4h.c
|
||||
* - Version : 0.01
|
||||
* @brief ECM setting.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 29.01.2025 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ecm_enable_v4h.h"
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
#include "log.h"
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
#include "ecc_enable_v4h.h"
|
||||
#include "mem_io.h"
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
#define ECM_ERR_REG_MAX (40U)
|
||||
|
||||
typedef struct{
|
||||
uint32_t phys_addr; /* Physical address of ECM registers. */
|
||||
uint32_t value; /* Setting value of ECM registers. */
|
||||
} ECM_ERROR_TABLE;
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
void ecm_unlock(void)
|
||||
{
|
||||
mem_write32(ECMWPCNTR, 0xACCE0001U);
|
||||
}
|
||||
|
||||
void ecm_write(uint32_t adr, uint32_t val)
|
||||
{
|
||||
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
|
||||
mem_write32(adr, val);
|
||||
}
|
||||
|
||||
void ecm_lock(void)
|
||||
{
|
||||
mem_write32(ECMWPCNTR, 0xACCE0000U);
|
||||
}
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
void ecm_error_enable(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t loop;
|
||||
|
||||
const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250000U, 0xFFFFF00FU}, /* ECMERRCTLR0 */
|
||||
[1] = {0xE6250004U, 0xFFF8C000U}, /* ECMERRCTLR1 */
|
||||
[2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
|
||||
[3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
|
||||
[4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
|
||||
[5] = {0xE6250014U, 0xFFFFFFFFU}, /* ECMERRCTLR5 */
|
||||
[6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
|
||||
[7] = {0xE625001CU, 0x6F980FFFU}, /* ECMERRCTLR7 */
|
||||
[8] = {0xE6250020U, 0xFFF00000U}, /* ECMERRCTLR8 */
|
||||
[9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
|
||||
[10] = {0xE6250028U, 0x557D554FU}, /* ECMERRCTLR10 */
|
||||
[11] = {0xE625002CU, 0xFFFC1555U}, /* ECMERRCTLR11 */
|
||||
[12] = {0xE6250030U, 0x5557FFFFU}, /* ECMERRCTLR12 */
|
||||
[13] = {0xE6250034U, 0x00000055U}, /* ECMERRCTLR13 */
|
||||
/* Skip ECMERRCTLR14 setting */
|
||||
/* Skip ECMERRCTLR15 setting */
|
||||
[14] = {0xE6250040U, 0x3FFFFFFFU}, /* ECMERRCTLR16 */
|
||||
[15] = {0xE6250044U, 0x2FFF8CE0U}, /* ECMERRCTLR17 */
|
||||
[16] = {0xE6250048U, 0x0EC03FFFU}, /* ECMERRCTLR18 */
|
||||
[17] = {0xE625004CU, 0xFFFFFFF9U}, /* ECMERRCTLR19 */
|
||||
[18] = {0xE6250050U, 0xFE66667EU}, /* ECMERRCTLR20 */
|
||||
[19] = {0xE6250054U, 0xBFE3BE0FU}, /* ECMERRCTLR21 */
|
||||
[20] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
|
||||
[21] = {0xE625005CU, 0x7EF3C008U}, /* ECMERRCTLR23 */
|
||||
[22] = {0xE6250060U, 0x7FFE8ADBU}, /* ECMERRCTLR24 */
|
||||
[23] = {0xE6250064U, 0xCF807FFFU}, /* ECMERRCTLR25 */
|
||||
[24] = {0xE6250068U, 0x7EF3C008U}, /* ECMERRCTLR26 */
|
||||
[25] = {0xE625006CU, 0x7FFE8ADBU}, /* ECMERRCTLR27 */
|
||||
[26] = {0xE6250070U, 0xCF807FFFU}, /* ECMERRCTLR28 */
|
||||
[27] = {0xE6250074U, 0x0073C008U}, /* ECMERRCTLR29 */
|
||||
[28] = {0xE6250078U, 0x7FE68A9BU}, /* ECMERRCTLR30 */
|
||||
[29] = {0xE625007CU, 0x8C007E00U}, /* ECMERRCTLR31 */
|
||||
[30] = {0xE6250080U, 0xCFFFFFFFU}, /* ECMERRCTLR32 */
|
||||
[31] = {0xE6250084U, 0x0FFFFFFFU}, /* ECMERRCTLR33 */
|
||||
[32] = {0xE6250088U, 0x000003FFU}, /* ECMERRCTLR34 */
|
||||
[33] = {0xE625008CU, 0xFFFFFFC0U}, /* ECMERRCTLR35 */
|
||||
[34] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
|
||||
/* Skip ECMERRCTLR37 setting */
|
||||
[35] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
|
||||
[36] = {0xE625009CU, 0x1FFF0000U}, /* ECMERRCTLR39 */
|
||||
[37] = {0xE62500A0U, 0x1FFC7FFFU}, /* ECMERRCTLR40 */
|
||||
[38] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
|
||||
[39] = {0xE62500A8U, 0x3FBFFDFFU}, /* ECMERRCTLR42 */
|
||||
};
|
||||
|
||||
#if (ECMERRTGTR_INTC == 1)
|
||||
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250200U, 0xFFFFF00FU}, /* ECMERRTGTR0 */
|
||||
[1] = {0xE6250204U, 0xFFF8C000U}, /* ECMERRTGTR1 */
|
||||
[2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
|
||||
[3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
|
||||
[4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
|
||||
[5] = {0xE6250214U, 0xFFFFFFFFU}, /* ECMERRTGTR5 */
|
||||
[6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
|
||||
[7] = {0xE625021CU, 0x6F980FFFU}, /* ECMERRTGTR7 */
|
||||
[8] = {0xE6250220U, 0xFFF00000U}, /* ECMERRTGTR8 */
|
||||
[9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
|
||||
[10] = {0xE6250228U, 0x557D554FU}, /* ECMERRTGTR10 */
|
||||
[11] = {0xE625022CU, 0xFFFC1555U}, /* ECMERRTGTR11 */
|
||||
[12] = {0xE6250230U, 0x5557FFFFU}, /* ECMERRTGTR12 */
|
||||
[13] = {0xE6250234U, 0x00000055U}, /* ECMERRTGTR13 */
|
||||
/* Skip ECMERRTGTR14 setting */
|
||||
/* Skip ECMERRTGTR15 setting */
|
||||
[14] = {0xE6250240U, 0x3FFFFFFFU}, /* ECMERRTGTR16 */
|
||||
[15] = {0xE6250244U, 0x2FFF8CE0U}, /* ECMERRTGTR17 */
|
||||
[16] = {0xE6250248U, 0x0EC03FFFU}, /* ECMERRTGTR18 */
|
||||
[17] = {0xE625024CU, 0xFFFFFFF9U}, /* ECMERRTGTR19 */
|
||||
[18] = {0xE6250250U, 0xFE66667EU}, /* ECMERRTGTR20 */
|
||||
[19] = {0xE6250254U, 0xBFE3BE0FU}, /* ECMERRTGTR21 */
|
||||
[20] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
|
||||
[21] = {0xE625025CU, 0x7EF3C008U}, /* ECMERRTGTR23 */
|
||||
[22] = {0xE6250260U, 0x7FFE8ADBU}, /* ECMERRTGTR24 */
|
||||
[23] = {0xE6250264U, 0xCF807FFFU}, /* ECMERRTGTR25 */
|
||||
[24] = {0xE6250268U, 0x7EF3C008U}, /* ECMERRTGTR26 */
|
||||
[25] = {0xE625026CU, 0x7FFE8ADBU}, /* ECMERRTGTR27 */
|
||||
[26] = {0xE6250270U, 0xCF807FFFU}, /* ECMERRTGTR28 */
|
||||
[27] = {0xE6250274U, 0x0073C008U}, /* ECMERRTGTR29 */
|
||||
[28] = {0xE6250278U, 0x7FE68A9BU}, /* ECMERRTGTR30 */
|
||||
[29] = {0xE625027CU, 0x8C007E00U}, /* ECMERRTGTR31 */
|
||||
[30] = {0xE6250280U, 0xCFFFFFFFU}, /* ECMERRTGTR32 */
|
||||
[31] = {0xE6250284U, 0x0FFFFFFFU}, /* ECMERRTGTR33 */
|
||||
[32] = {0xE6250288U, 0x000003FFU}, /* ECMERRTGTR34 */
|
||||
[33] = {0xE625028CU, 0xFFFFFFC0U}, /* ECMERRTGTR35 */
|
||||
[34] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
|
||||
/* Skip ECMERRTGTR37 setting */
|
||||
[35] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
|
||||
[36] = {0xE625029CU, 0x1FFF0000U}, /* ECMERRTGTR39 */
|
||||
[37] = {0xE62502A0U, 0x1FFC7FFFU}, /* ECMERRTGTR40 */
|
||||
[38] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
|
||||
[39] = {0xE62502A8U, 0x3FBFFDFFU}, /* ECMERRTGTR42 */
|
||||
};
|
||||
#elif (ECMERRTGTR_INTC == 0)
|
||||
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
|
||||
[1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
|
||||
[2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
|
||||
[3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
|
||||
[4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
|
||||
[5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
|
||||
[6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
|
||||
[7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
|
||||
[8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
|
||||
[9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
|
||||
[10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
|
||||
[11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
|
||||
[12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
|
||||
[13] = {0xE6250234U, 0x00000000U}, /* ECMERRTGTR13 */
|
||||
/* Skip ECMERRTGTR14 setting */
|
||||
/* Skip ECMERRTGTR15 setting */
|
||||
[14] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
|
||||
[15] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
|
||||
[16] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
|
||||
[17] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
|
||||
[18] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
|
||||
[19] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
|
||||
[20] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
|
||||
[21] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
|
||||
[22] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
|
||||
[23] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
|
||||
[24] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
|
||||
[25] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
|
||||
[26] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
|
||||
[27] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
|
||||
[28] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
|
||||
[29] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
|
||||
[30] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
|
||||
[31] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
|
||||
[32] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
|
||||
[33] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
|
||||
[34] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
|
||||
/* Skip ECMERRTGTR37 setting */
|
||||
[35] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
|
||||
[36] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
|
||||
[37] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
|
||||
[38] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
|
||||
[39] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
|
||||
};
|
||||
#endif /* ECMERRTGTR_INTC == 1 */
|
||||
|
||||
/* Unlock the write protect of ECM registers */
|
||||
ecm_unlock();
|
||||
|
||||
NOTICE("ECMERRCTLR register setting.\n");
|
||||
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
|
||||
{
|
||||
/* Set ECMERRCTLR registers. */
|
||||
reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
|
||||
reg |= ecmerrctlr_tbl[loop].value;
|
||||
ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
|
||||
|
||||
INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
|
||||
loop,
|
||||
ecmerrctlr_tbl[loop].phys_addr,
|
||||
mem_read32(ecmerrctlr_tbl[loop].phys_addr),
|
||||
ecmerrctlr_tbl[loop].value);
|
||||
}
|
||||
|
||||
NOTICE("ECMERRTGTR register setting.\n");
|
||||
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
|
||||
{
|
||||
/* Set ECMERRTGTR registers. */
|
||||
reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
|
||||
reg |= ecmerrtgtr_tbl[loop].value;
|
||||
ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
|
||||
|
||||
INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
|
||||
loop,
|
||||
ecmerrtgtr_tbl[loop].phys_addr,
|
||||
mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
|
||||
ecmerrtgtr_tbl[loop].value);
|
||||
}
|
||||
|
||||
/* Lock the ECM registers */
|
||||
ecm_lock();
|
||||
}
|
||||
/* End of function ecm_error_enable(void) */
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECM driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef ECM_ENABLE
|
||||
#define ECM_ENABLE
|
||||
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
void ecm_unlock(void);
|
||||
void ecm_write(uint32_t adr, uint32_t val);
|
||||
void ecm_lock(void);
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
void ecm_error_enable(void);
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
#endif/* ECM_ENABLE */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
4542
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c
Normal file
4542
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#else
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#endif
|
||||
#include "boot_init_dram_regdef.h"
|
||||
#include "boot_init_dram_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PLEASE SET board number or board judge function
|
||||
******************************************************************************/
|
||||
#define BOARD_JUDGE_AUTO
|
||||
#ifdef BOARD_JUDGE_AUTO
|
||||
static uint32_t r_board_judge(void);
|
||||
uint32_t r_boardcnf_get_brd_type(void)
|
||||
{
|
||||
return r_board_judge();
|
||||
}
|
||||
#else /* BOARD_JUDGE_AUTO */
|
||||
uint32_t r_boardcnf_get_brd_type(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
#endif /* BOARD_JUDGE_AUTO */
|
||||
|
||||
/*******************************************************************************
|
||||
* EXTAL CLOCK DEFINITION
|
||||
* PLEASE DEFINE HOW TO JUDGE BORAD CLK
|
||||
******************************************************************************/
|
||||
/*
|
||||
* RENESAS GRAY HAWK BOARD EXAMPLE
|
||||
* judge by md14/md13
|
||||
*
|
||||
* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0)
|
||||
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
|
||||
* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1)
|
||||
*/
|
||||
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div)
|
||||
{
|
||||
uint32_t md;
|
||||
|
||||
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U;
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */
|
||||
case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */
|
||||
case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */
|
||||
case 0x3U : *clk =100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
(void)brd;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* DDR MBPS TARGET
|
||||
* PLEASE DEFINE HOW TO JUDGE DDR BPS
|
||||
******************************************************************************/
|
||||
/*
|
||||
DDRxxxx (judge by md19,17) : Mbps
|
||||
SSCG enable / disable for PLL1 (judge by md18/md37/md36)
|
||||
*/
|
||||
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en)
|
||||
{
|
||||
uint32_t md;
|
||||
uint32_t product;
|
||||
|
||||
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U;
|
||||
md = (md | (md >> 1)) & 0x03U;
|
||||
*sscg = ((mmio_read_32(RST_MODEMR0) >> 16) & 0x04U) | ((mmio_read_32(RST_MODEMR1) >> 4) & 0x03U);
|
||||
product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
|
||||
|
||||
if (product == 0x01U)
|
||||
{
|
||||
/* V4M-5 */
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
|
||||
case 0x1U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
|
||||
case 0x2U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
}
|
||||
else if (product == 0x02U)
|
||||
{
|
||||
/* V4M-3 */
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
}
|
||||
else if (product == 0x04U)
|
||||
{
|
||||
/* V4M-2 */
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* V4M-7 */
|
||||
switch (*sscg)
|
||||
{
|
||||
case 0x0U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x1U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x2U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x3U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x4U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x5U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x6U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
case 0x7U :
|
||||
switch (md)
|
||||
{
|
||||
case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */
|
||||
case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */
|
||||
case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */
|
||||
case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */
|
||||
default : /* Nothing */ break;
|
||||
}
|
||||
break;
|
||||
default :
|
||||
/* Nothing */
|
||||
break;
|
||||
}/* Setting of SSCG */
|
||||
} /* (product == 0x01U) */
|
||||
|
||||
(void)brd;
|
||||
}
|
||||
|
||||
#ifdef BOARD_JUDGE_AUTO
|
||||
/*******************************************************************************
|
||||
* SAMPLE board detect function
|
||||
******************************************************************************/
|
||||
static uint32_t r_board_judge(void)
|
||||
{
|
||||
uint32_t brd;
|
||||
|
||||
brd = 0U; /* gray hawk (64Gbit 2rank) */
|
||||
|
||||
return brd;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,156 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_CONFIG_H_
|
||||
#define BOOT_INIT_DRAM_CONFIG_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* DRAM Param setting
|
||||
******************************************************************************/
|
||||
#define JS2_DERATE 0U
|
||||
#define DBSC_REFINT 1920U /* Average periodic refresh interval/Average Refresh Interval [ns] */
|
||||
#ifndef DBSC_REFINTS
|
||||
#define DBSC_REFINTS 0U /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
|
||||
#endif
|
||||
#define PERIODIC_TRAINING_INTERVAL 20000U /* Periodic-WriteDQ/ReadDQ Training Interval [us] */
|
||||
|
||||
/*******************************************************************************
|
||||
* NUMBER OF BOARD CONFIGURATION
|
||||
* PLEASE DEFINE
|
||||
******************************************************************************/
|
||||
#define BOARDNUM 2U /* Add User platform BOARD */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
uint32_t r_boardcnf_get_brd_type(void);
|
||||
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
|
||||
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en);
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD CONFIGURATION
|
||||
* PLEASE DEFINE boardcnfs[]
|
||||
******************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/*
|
||||
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
|
||||
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
|
||||
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
|
||||
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
|
||||
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
|
||||
0x05...0101B: 24Gb dual channel die / 12Gb single channel die
|
||||
0x06...0110B: 32Gb dual channel die / 16Gb single channel die
|
||||
0x07...0111B: 24Gb single channel die
|
||||
0x08...1000B: 32Gb single channel die
|
||||
0xFF...NO_MEMORY
|
||||
*/
|
||||
uint8_t bdcfg_ddr_density[CS_CNT];
|
||||
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
|
||||
uint32_t bdcfg_ca_swap;
|
||||
/* SoC dqsX([1][0]) -> MEM dqsY: */
|
||||
uint8_t bdcfg_dqs_swap;
|
||||
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
|
||||
uint32_t bdcfg_dq_swap[SLICE_CNT];
|
||||
/* SoC dm -> MEM dqY/dm: (8 means DM) */
|
||||
uint8_t bdcfg_dm_swap[SLICE_CNT];
|
||||
/* SoC ckeX([1][0]) -> MEM csY */
|
||||
uint8_t bdcfg_cs_swap;
|
||||
} st_boardcnf_ch_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* ch in use */
|
||||
uint8_t bdcfg_phyvalid;
|
||||
/* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */
|
||||
uint32_t bdcfg_vref_r;
|
||||
/* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
|
||||
uint16_t bdcfg_vref_w;
|
||||
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
|
||||
uint16_t bdcfg_vref_ca;
|
||||
/* RFM required check : 0x01 = check enable, 0x00 = check disable */
|
||||
uint8_t bdcfg_rfm_chk;
|
||||
|
||||
st_boardcnf_ch_t ch[2];
|
||||
} st_boardcnf_t;
|
||||
|
||||
static const st_boardcnf_t boardcnfs[BOARDNUM] = {
|
||||
/*
|
||||
* boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank)
|
||||
*/
|
||||
{
|
||||
0x03U, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
|
||||
/* bdcfg_ca_swap */ 0x06235104U,
|
||||
/* bdcfg_dqs_swap */ 0x01U,
|
||||
/* bdcfg_dq_swap[] */ { 0x43061257U, 0x30721685U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x04U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
|
||||
/* bdcfg_ca_swap */ 0x04012653U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x58147026U, 0x70132685U },
|
||||
/* bdcfg_dm_swap[] */ { 0x03U, 0x04U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
}
|
||||
}
|
||||
},
|
||||
/*
|
||||
* boardcnf[1] RENESAS V4M (2ch)
|
||||
*/
|
||||
{
|
||||
0x03U, /* bdcfg_phyvalid */
|
||||
0x00000000U, /* bdcfg_vref_r */
|
||||
0x0000U, /* bdcfg_vref_w */
|
||||
0x0000U, /* bdcfg_vref_ca */
|
||||
0x01U, /* bdcfg_rfm_chk */
|
||||
{
|
||||
/* ch[0] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
},
|
||||
/* ch[1] */ {
|
||||
/* bdcfg_ddr_density[] */ { 0x06U, 0x06U },
|
||||
/* bdcfg_ca_swap */ 0x06543210U,
|
||||
/* bdcfg_dqs_swap */ 0x10U,
|
||||
/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U },
|
||||
/* bdcfg_dm_swap[] */ { 0x08U, 0x08U },
|
||||
/* bdcfg_cs_swap */ 0x10U
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_CONFIG_H_ */
|
||||
@@ -0,0 +1,165 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_REGDEF_H_
|
||||
#define BOOT_INIT_DRAM_REGDEF_H_
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#include "remap_register.h"
|
||||
#endif
|
||||
|
||||
#define RCAR_DDR_VERSION "rev.1.00"
|
||||
#define DRAM_CH_CNT 0x02U
|
||||
#define SLICE_CNT 0x02U
|
||||
#define CS_CNT 0x02U
|
||||
|
||||
/* for pll setting */
|
||||
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
|
||||
|
||||
/* for ddr density setting */
|
||||
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
|
||||
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */
|
||||
|
||||
/* system registers : CPG */
|
||||
#define CPG_FRQCRD_KICK_BIT (1U << 31)
|
||||
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
|
||||
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define CPG_BASE (BASE_CPG_ADDR)
|
||||
#else
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#endif
|
||||
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
|
||||
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
|
||||
#define CPG_PLLECR (CPG_BASE + 0x0820U)
|
||||
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
|
||||
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
|
||||
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
|
||||
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
|
||||
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
|
||||
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define RST_BASE (BASE_RESET_ADDR)
|
||||
#else
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#endif
|
||||
#define RST_MODEMR0 (RST_BASE + 0x0000U)
|
||||
#define RST_MODEMR1 (RST_BASE + 0x0004U)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR)
|
||||
#else
|
||||
#define OTP_MEM_1_BASE (0xE61BF000U)
|
||||
#endif
|
||||
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
|
||||
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
|
||||
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
|
||||
|
||||
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
|
||||
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
|
||||
|
||||
/* DBSC registers */
|
||||
#if defined(__RH850G3K__)
|
||||
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4M DBSC0 clk_dbsc region */
|
||||
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4M DBSC0 clk_axim region */
|
||||
#else
|
||||
#define DBSC_D_BASE (0xE67A4000U) /* forV4M DBSC0 clk_dbsc region */
|
||||
#define DBSC_A_BASE (0xE6790000U) /* forV4M DBSC0 clk_axim region */
|
||||
#endif
|
||||
|
||||
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
|
||||
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
|
||||
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
|
||||
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
|
||||
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
|
||||
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
|
||||
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
|
||||
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
|
||||
|
||||
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
|
||||
|
||||
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
|
||||
|
||||
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
|
||||
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
|
||||
|
||||
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
|
||||
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
|
||||
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
|
||||
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
|
||||
|
||||
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
|
||||
|
||||
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
|
||||
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
|
||||
|
||||
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
|
||||
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
|
||||
|
||||
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
|
||||
|
||||
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
|
||||
|
||||
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
|
||||
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
|
||||
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
|
||||
|
||||
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
|
||||
|
||||
#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x0804U)
|
||||
|
||||
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
|
||||
|
||||
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
|
||||
|
||||
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
|
||||
|
||||
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF_H_ */
|
||||
390
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h
Normal file
390
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h
Normal file
@@ -0,0 +1,390 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef DDR_REGDEF_H_
|
||||
#define DDR_REGDEF_H_
|
||||
|
||||
#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U
|
||||
#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011006U
|
||||
#define PHY_PER_CS_TRAINING_INDEX 0x00011007U
|
||||
#define PHY_VREF_INITIAL_STEPSIZE 0x1808100EU
|
||||
#define PHY_RDLVL_BEST_THRSHLD 0x0004100FU
|
||||
#define PHY_RDLVL_VREF_OUTLIER 0x1003100FU
|
||||
#define SC_PHY_WCK_CALC 0x1801101BU
|
||||
#define PHY_WRLVL_PER_START 0x00071020U
|
||||
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x08051022U
|
||||
#define PHY_CALVL_VREF_DRIVING_SLICE 0x08011026U
|
||||
#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A102DU
|
||||
#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A102DU
|
||||
#define PHY_WRLVL_STATUS_OBS 0x001C102EU
|
||||
#define PHY_WRLVL_ERROR_OBS 0x00021030U
|
||||
#define PHY_GTLVL_STATUS_OBS 0x00121032U
|
||||
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x10091033U
|
||||
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00091034U
|
||||
#define PHY_WDQLVL_STATUS_OBS 0x00201038U
|
||||
#define PHY_DATA_DC_CAL_START 0x08011041U
|
||||
#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011042U
|
||||
#define PHY_REGULATOR_EN_CNT 0x00061044U
|
||||
#define PHY_VREF_INITIAL_START_POINT 0x00091048U
|
||||
#define PHY_VREF_INITIAL_STOP_POINT 0x10091048U
|
||||
#define PHY_VREF_TRAINING_CTRL 0x00021049U
|
||||
#define PHY_RDDQ0_SLAVE_DELAY 0x00091050U
|
||||
#define PHY_RDDQ1_SLAVE_DELAY 0x10091050U
|
||||
#define PHY_RDDQ2_SLAVE_DELAY 0x00091051U
|
||||
#define PHY_RDDQ3_SLAVE_DELAY 0x10091051U
|
||||
#define PHY_RDDQ4_SLAVE_DELAY 0x00091052U
|
||||
#define PHY_RDDQ5_SLAVE_DELAY 0x10091052U
|
||||
#define PHY_RDDQ6_SLAVE_DELAY 0x00091053U
|
||||
#define PHY_RDDQ7_SLAVE_DELAY 0x10091053U
|
||||
#define PHY_RDDM_SLAVE_DELAY 0x00091054U
|
||||
#define PHY_RX_CAL_ALL_DLY 0x18061054U
|
||||
#define PHY_RX_PCLK_CLK_SEL 0x00031055U
|
||||
#define PHY_DATA_DC_CAL_CLK_SEL 0x08031055U
|
||||
#define PHY_PAD_VREF_CTRL_DQ 0x100E1058U
|
||||
#define PHY_PER_CS_TRAINING_EN 0x10011059U
|
||||
#define PHY_RDDATA_EN_TSEL_DLY 0x0805105BU
|
||||
#define PHY_RDDATA_EN_OE_DLY 0x1005105BU
|
||||
#define PHY_RPTR_UPDATE 0x0804105EU
|
||||
#define PHY_WRLVL_RESP_WAIT_CNT 0x0006105FU
|
||||
#define PHY_RDLVL_DLY_STEP 0x08041062U
|
||||
#define PHY_RDLVL_MAX_EDGE 0x00091063U
|
||||
#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021068U
|
||||
#define PHY_RDDATA_EN_DLY 0x10051069U
|
||||
#define PHY_DQ_DM_SWIZZLE0 0x0020106AU
|
||||
#define PHY_DQ_DM_SWIZZLE1 0x0004106BU
|
||||
#define PHY_CLK_WRDQS_SLAVE_DELAY 0x00091071U
|
||||
#define PHY_WRITE_PATH_LAT_DEC 0x10011071U
|
||||
#define PHY_RDDQS_LATENCY_ADJUST 0x1005107BU
|
||||
#define PHY_WRITE_PATH_LAT_ADD 0x1803107BU
|
||||
#define PHY_WRITE_PATH_LAT_FRAC 0x0008107CU
|
||||
#define PHY_GTLVL_LAT_ADJ_START 0x0005107DU
|
||||
#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008107FU
|
||||
#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U
|
||||
#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U
|
||||
#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U
|
||||
#define PHY_ADR_CALVL_OBS1 0x0020120AU
|
||||
#define PHY_ADR_CALVL_OBS2 0x0020120BU
|
||||
#define PHY_ADR_CALVL_DLY_STEP 0x00041210U
|
||||
#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U
|
||||
#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U
|
||||
#define PHY_CSLVL_OBS1 0x00201221U
|
||||
#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE 0x1008122DU
|
||||
#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU
|
||||
#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U
|
||||
#define PHY_FREQ_SEL_INDEX 0x10021301U
|
||||
#define SC_PHY_MANUAL_UPDATE 0x18011304U
|
||||
#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U
|
||||
#define PHY_TCKSRE_WAIT 0x1004131FU
|
||||
#define PHY_CAL_MODE_0 0x000D132CU
|
||||
#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU
|
||||
#define PHY_DATA_BYTE_ORDER_SEL 0x0020133FU
|
||||
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x1003134AU
|
||||
#define PHY_PLL_CTRL 0x000E134DU
|
||||
#define PHY_PLL_CTRL_8X 0x100E134DU
|
||||
#define PHY_CAL_CLK_SELECT_0 0x00031361U
|
||||
|
||||
#define PI_START 0x00010800U
|
||||
#define PI_TRAIN_ALL_FREQ_REQ 0x18010804U
|
||||
#define PI_FREQ_MAP 0x0020080DU
|
||||
#define PI_INIT_WORK_FREQ 0x0005080EU
|
||||
#define PI_CS_MAP 0x08020815U
|
||||
#define PI_WRLVL_REQ 0x0801081FU
|
||||
#define PI_WRLVL_CS_SW 0x1002081FU
|
||||
#define PI_RDLVL_REQ 0x10010827U
|
||||
#define PI_RDLVL_GATE_REQ 0x18010827U
|
||||
#define PI_RDLVL_CS_SW 0x00020828U
|
||||
#define PI_RDLVL_PERIODIC 0x08010831U
|
||||
#define PI_RDLVL_INTERVAL 0x08100838U
|
||||
#define PI_DRAMDCA_FLIP_MASK 0x0802083EU
|
||||
#define PI_DRAMDCA_LVL_REQ 0x10010840U
|
||||
#define PI_DCMLVL_CS_SW 0x18020840U
|
||||
#define PI_WRDCM_LVL_EN_F1 0x00020842U
|
||||
#define PI_DRAMDCA_LVL_EN_F1 0x08020842U
|
||||
#define PI_WRDCM_LVL_EN_F2 0x18020842U
|
||||
#define PI_DRAMDCA_LVL_EN_F2 0x00020843U
|
||||
#define PI_TCKCKEL_F2 0x18040851U
|
||||
#define PI_WDQLVL_VREF_EN 0x08040852U
|
||||
#define PI_WDQLVL_PERIODIC 0x00010854U
|
||||
#define PI_WDQLVL_INTERVAL 0x00100858U
|
||||
#define PI_INT_STATUS 0x002008B7U
|
||||
#define PI_INT_ACK_0 0x002008B9U
|
||||
#define PI_INT_ACK_1 0x000108BAU
|
||||
#define PI_LONG_COUNT_MASK 0x100508BCU
|
||||
#define PI_ADDRESS_MUX_0 0x000308BDU
|
||||
#define PI_ADDRESS_MUX_1 0x080308BDU
|
||||
#define PI_ADDRESS_MUX_2 0x100308BDU
|
||||
#define PI_ADDRESS_MUX_3 0x180308BDU
|
||||
#define PI_ADDRESS_MUX_4 0x000308BEU
|
||||
#define PI_ADDRESS_MUX_5 0x080308BEU
|
||||
#define PI_ADDRESS_MUX_6 0x100308BEU
|
||||
#define PI_DATA_BYTE_SWAP_EN 0x180108BEU
|
||||
#define PI_DATA_BYTE_SWAP_SLICE0 0x000108BFU
|
||||
#define PI_DATA_BYTE_SWAP_SLICE1 0x080108BFU
|
||||
#define PI_PWRUP_SREFRESH_EXIT 0x100108C2U
|
||||
#define PI_DLL_RST 0x000108C6U
|
||||
#define PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x000808E8U
|
||||
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x000808E9U
|
||||
#define PI_WRLAT_F1 0x100708EDU
|
||||
#define PI_TWCKENL_RD_ADJ_F1 0x000608EEU
|
||||
#define PI_TWCKPRE_STATIC_F1 0x080608EEU
|
||||
#define PI_TWCKPRE_TOGGLE_RD_F1 0x180608EEU
|
||||
#define PI_WCK_ACTIVE_WR_F1 0x000708EFU
|
||||
#define PI_WCK_ACTIVE_RD_F1 0x080708EFU
|
||||
#define PI_CASLAT_F1 0x180708EFU
|
||||
#define PI_WRLAT_F2 0x000708F0U
|
||||
#define PI_TWCKENL_WR_ADJ_F2 0x080608F0U
|
||||
#define PI_TWCKENL_RD_ADJ_F2 0x100608F0U
|
||||
#define PI_TWCKPRE_STATIC_F2 0x180608F0U
|
||||
#define PI_TWCKPRE_TOGGLE_RD_F2 0x080608F1U
|
||||
#define PI_WCK_ACTIVE_WR_F2 0x100708F1U
|
||||
#define PI_WCK_ACTIVE_RD_F2 0x180708F1U
|
||||
#define PI_TWCKENL_FS_ADJ_F2 0x000608F2U
|
||||
#define PI_CASLAT_F2 0x080708F2U
|
||||
#define PI_TRFC_F1 0x000A08F4U
|
||||
#define PI_TREF_F1 0x001408F5U
|
||||
#define PI_TRFC_F2 0x000A08F6U
|
||||
#define PI_TREF_F2 0x001408F7U
|
||||
#define PI_WRLVL_EN_F1 0x000208FAU
|
||||
#define PI_TDFI_WRLVL_WW_F1 0x080A08FAU
|
||||
#define PI_WRLVL_EN_F2 0x000208FBU
|
||||
#define PI_TDFI_WRLVL_WW_F2 0x080A08FBU
|
||||
#define PI_WRLVL_WCKOFF_F2 0x180808FBU
|
||||
#define PI_RDLVL_EN_F1 0x100208FFU
|
||||
#define PI_RDLVL_GATE_EN_F1 0x180208FFU
|
||||
#define PI_RDLVL_EN_F2 0x00020900U
|
||||
#define PI_RDLVL_GATE_EN_F2 0x08020900U
|
||||
#define PI_RDLVL_VREF_EN_F0 0x18040900U
|
||||
#define PI_RDLVL_RDDQ_EN_F1 0x00040902U
|
||||
#define PI_RDLVL_VREF_EN_F1 0x08040902U
|
||||
#define PI_RDLVL_VREF_EN_F2 0x18040903U
|
||||
#define PI_RDLAT_ADJ_F1 0x10090905U
|
||||
#define PI_RDLAT_ADJ_F2 0x00090906U
|
||||
#define PI_WRLAT_ADJ_F1 0x18070906U
|
||||
#define PI_WRLAT_ADJ_F2 0x00070907U
|
||||
#define PI_TDFI_CALVL_CC_F1 0x000A0909U
|
||||
#define PI_TDFI_CALVL_CAPTURE_F1 0x100A0909U
|
||||
#define PI_TDFI_CALVL_CC_F2 0x000A090AU
|
||||
#define PI_TDFI_CALVL_CAPTURE_F2 0x100A090AU
|
||||
#define PI_CALVL_EN_F1 0x0802090BU
|
||||
#define PI_CALVL_EN_F2 0x1002090BU
|
||||
#define PI_TCAENT_F1 0x000E090DU
|
||||
#define PI_TCAENT_F2 0x000E090EU
|
||||
#define PI_TVREF_LONG_F1 0x000A0912U
|
||||
#define PI_TVRCG_ENABLE_F1 0x100A0912U
|
||||
#define PI_TVRCG_DISABLE_F1 0x000A0913U
|
||||
#define PI_TVREF_LONG_F2 0x100A0914U
|
||||
#define PI_TVRCG_ENABLE_F2 0x000A0915U
|
||||
#define PI_TVRCG_DISABLE_F2 0x100A0915U
|
||||
#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070917U
|
||||
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070917U
|
||||
#define PI_TDFI_CALVL_STROBE_F2 0x0804091AU
|
||||
#define PI_TXP_F2 0x1005091AU
|
||||
#define PI_TMRWCKEL_F2 0x1808091AU
|
||||
#define PI_TCKEHDQS_F1 0x10060921U
|
||||
#define PI_TFC_F1 0x000A0922U
|
||||
#define PI_TCKEHDQS_F2 0x10060922U
|
||||
#define PI_TFC_F2 0x000A0923U
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x10070925U
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x18070925U
|
||||
#define PI_TDFI_WDQLVL_WR_F1 0x080A0928U
|
||||
#define PI_TDFI_WDQLVL_RW_F1 0x000A0929U
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x10070929U
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x18070929U
|
||||
#define PI_WDQLVL_EN_F1 0x0802092AU
|
||||
#define PI_WDQLVL_RDLAT_ADJ_F1 0x0009092BU
|
||||
#define PI_WDQLVL_WRLAT_ADJ_F1 0x1009092BU
|
||||
#define PI_WDQLVL_TWCKENL_RD_ADJ_F1 0x0006092CU
|
||||
#define PI_TDFI_WDQLVL_WR_F2 0x080A092CU
|
||||
#define PI_TDFI_WDQLVL_RW_F2 0x000A092DU
|
||||
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x1007092DU
|
||||
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x1807092DU
|
||||
#define PI_WDQLVL_EN_F2 0x0802092EU
|
||||
#define PI_WDQLVL_RDLAT_ADJ_F2 0x0009092FU
|
||||
#define PI_WDQLVL_WRLAT_ADJ_F2 0x1009092FU
|
||||
#define PI_WDQLVL_TWCKENL_RD_ADJ_F2 0x00060930U
|
||||
#define PI_TRTP_F1 0x18080936U
|
||||
#define PI_TRP_F1 0x00080937U
|
||||
#define PI_TRCD_F1 0x08080937U
|
||||
#define PI_TWTR_S_F1 0x18060937U
|
||||
#define PI_TWTR_L_F1 0x00060938U
|
||||
#define PI_TWTR_F1 0x10060938U
|
||||
#define PI_TWR_F1 0x18080938U
|
||||
#define PI_TRAS_MAX_F1 0x00100939U
|
||||
#define PI_TRAS_MIN_F1 0x10090939U
|
||||
#define PI_TSR_F1 0x1008093AU
|
||||
#define PI_TRTP_F2 0x0808093BU
|
||||
#define PI_TRP_F2 0x1008093BU
|
||||
#define PI_TRCD_F2 0x1808093BU
|
||||
#define PI_TWTR_S_F2 0x0806093CU
|
||||
#define PI_TWTR_L_F2 0x1006093CU
|
||||
#define PI_TWTR_F2 0x0006093DU
|
||||
#define PI_TWR_F2 0x0808093DU
|
||||
#define PI_TRAS_MAX_F2 0x1010093DU
|
||||
#define PI_TRAS_MIN_F2 0x0009093EU
|
||||
#define PI_TDQSCK_MAX_F2 0x1004093EU
|
||||
#define PI_TSR_F2 0x0008093FU
|
||||
#define PI_TMRD_F2 0x0808093FU
|
||||
#define PI_TDFI_CTRLUPD_MAX_F1 0x00150942U
|
||||
#define PI_TDFI_CTRLUPD_INTERVAL_F1 0x00200943U
|
||||
#define PI_TDFI_CTRLUPD_MAX_F2 0x00150944U
|
||||
#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x00200945U
|
||||
#define PI_TXSR_F1 0x10100946U
|
||||
#define PI_TXSR_F2 0x00100947U
|
||||
#define PI_TINIT_F1 0x0018094EU
|
||||
#define PI_TINIT1_F1 0x0018094FU
|
||||
#define PI_TINIT3_F1 0x00180950U
|
||||
#define PI_TINIT4_F1 0x00180951U
|
||||
#define PI_TINIT5_F1 0x00180952U
|
||||
#define PI_TXSNR_F1 0x00100953U
|
||||
#define PI_TINIT_F2 0x00180954U
|
||||
#define PI_TINIT1_F2 0x00180955U
|
||||
#define PI_TINIT3_F2 0x00180956U
|
||||
#define PI_TINIT4_F2 0x00180957U
|
||||
#define PI_TINIT5_F2 0x00180958U
|
||||
#define PI_TXSNR_F2 0x00100959U
|
||||
#define PI_TZQCAL_F1 0x100C095CU
|
||||
#define PI_TZQLAT_F1 0x0007095DU
|
||||
#define PI_TZQCAL_F2 0x100C095EU
|
||||
#define PI_TZQLAT_F2 0x0007095FU
|
||||
#define PI_ZQRESET_F1 0x000C0960U
|
||||
#define PI_ZQRESET_F2 0x100C0960U
|
||||
#define PI_TDQ72DQ_F1 0x000A0964U
|
||||
#define PI_TCBTRTW_F1 0x10060964U
|
||||
#define PI_TDQ72DQ_F2 0x100A0965U
|
||||
#define PI_TCBTRTW_F2 0x00060966U
|
||||
#define PI_MC_TRFC_F1 0x100A0968U
|
||||
#define PI_MC_TRFC_F2 0x000A0969U
|
||||
#define PI_TDFI_WCK_STOP_F1 0x0808096EU
|
||||
#define PI_TDFI_WCK_STOP_F2 0x1808096EU
|
||||
#define PI_CKE_MUX_0 0x1802096FU
|
||||
#define PI_CKE_MUX_1 0x00020970U
|
||||
#define PI_SEQ_DEC_SW_CS 0x0002097BU
|
||||
#define PI_SW_SEQ_START 0x1001097BU
|
||||
#define PI_SEQ_ARRAY_29 0x001D09C9U
|
||||
#define PI_SEQ_ARRAY_64 0x001D09ECU
|
||||
#define PI_SEQ_ARRAY_65 0x001D09EDU
|
||||
#define PI_SEQ_ARRAY_66 0x001D09EEU
|
||||
#define PI_SEQ_ARRAY_67 0x001D09EFU
|
||||
#define PI_SEQ_ARRAY_68 0x001D09F0U
|
||||
#define PI_SEQ_ARRAY_69 0x001D09F1U
|
||||
#define PI_SEQ_ARRAY_70 0x001D09F2U
|
||||
#define PI_SEQ_ARRAY_71 0x001D09F3U
|
||||
#define PI_SEQ_ARRAY_72 0x001D09F4U
|
||||
#define PI_SEQ_ARRAY_81 0x001D09FDU
|
||||
#define PI_SEQ_ARRAY_82 0x001D09FEU
|
||||
#define PI_SEQ_ARRAY_333 0x001B0AF9U
|
||||
#define PI_SEQ_ARRAY_334 0x001B0AFAU
|
||||
#define PI_SEQ_ARRAY_335 0x001B0AFBU
|
||||
#define PI_SEQ_ARRAY_349 0x001B0B09U
|
||||
#define PI_SEQ_ARRAY_350 0x001B0B0AU
|
||||
#define PI_RDLVL_TRAIN_SEQ_1 0x001B0B9EU
|
||||
#define PI_RDLVL_TRAIN_SEQ_2 0x001B0B9FU
|
||||
#define PI_RDLVL_TRAIN_SEQ_3 0x001B0BA0U
|
||||
#define PI_RDLVL_TRAIN_SEQ_4 0x001B0BA1U
|
||||
#define PI_RDLVL_TRAIN_SEQ_5 0x001B0BA2U
|
||||
#define PI_SEQ_WAIT_16_F1 0x00180BD2U
|
||||
#define PI_SEQ_WAIT_16_F2 0x00180BD3U
|
||||
#define PI_SEQ_WAIT_17_F1 0x00180BD5U
|
||||
#define PI_SEQ_WAIT_17_F2 0x00180BD6U
|
||||
#define PI_SEQ_WAIT_18_F2 0x00180BD9U
|
||||
#define PI_SEQ_WAIT_19_F1 0x00180BDBU
|
||||
#define PI_SEQ_WAIT_19_F2 0x00180BDCU
|
||||
#define PI_SEQ_WAIT_20_F1 0x00180BDEU
|
||||
#define PI_SEQ_WAIT_20_F2 0x00180BDFU
|
||||
#define PI_SEQ_WAIT_21_F1 0x00180BE1U
|
||||
#define PI_SEQ_WAIT_21_F2 0x00180BE2U
|
||||
#define PI_SEQ_WAIT_22_F1 0x00180BE4U
|
||||
#define PI_SEQ_WAIT_22_F2 0x00180BE5U
|
||||
#define PI_SEQ_WAIT_23_F1 0x00180BE7U
|
||||
#define PI_SEQ_WAIT_23_F2 0x00180BE8U
|
||||
#define PI_SEQ_WAIT_24_F1 0x00180BEAU
|
||||
#define PI_SEQ_WAIT_24_F2 0x00180BEBU
|
||||
#define PI_SEQ_WAIT_25_F1 0x00180BEDU
|
||||
#define PI_SEQ_WAIT_25_F2 0x00180BEEU
|
||||
#define PI_SEQ_WAIT_26_F1 0x00180BF0U
|
||||
#define PI_SEQ_WAIT_26_F2 0x00180BF1U
|
||||
#define PI_SEQ_WAIT_27_F2 0x00180BF4U
|
||||
#define PI_SEQ_WAIT_31_F1 0x00180BFFU
|
||||
#define PI_SEQ_WAIT_31_F2 0x00180C00U
|
||||
#define PI_WP_GAP_0_F1 0x100F0C0DU
|
||||
#define PI_WP_GAP_0_F2 0x000F0C0EU
|
||||
#define PI_RP_GAP_0_F1 0x000F0C0FU
|
||||
#define PI_RP_GAP_0_F2 0x100F0C0FU
|
||||
#define PI_WR_GAP_S_0_F1 0x100F0C10U
|
||||
#define PI_WR_GAP_S_0_F2 0x000F0C11U
|
||||
#define PI_WR_GAP_L_0_F1 0x000F0C12U
|
||||
#define PI_WR_GAP_L_0_F2 0x100F0C12U
|
||||
#define PI_RW_GAP_0_F1 0x100F0C13U
|
||||
#define PI_RW_GAP_0_F2 0x000F0C14U
|
||||
#define PI_WP_GAP_1_F1 0x000F0C1BU
|
||||
#define PI_WP_GAP_1_F2 0x100F0C1BU
|
||||
#define PI_RP_GAP_1_F1 0x100F0C1CU
|
||||
#define PI_RP_GAP_1_F2 0x000F0C1DU
|
||||
#define PI_WR_GAP_S_1_F1 0x000F0C1EU
|
||||
#define PI_WR_GAP_S_1_F2 0x100F0C1EU
|
||||
#define PI_WR_GAP_L_1_F1 0x100F0C1FU
|
||||
#define PI_WR_GAP_L_1_F2 0x000F0C20U
|
||||
#define PI_RW_GAP_1_F1 0x000F0C21U
|
||||
#define PI_RW_GAP_1_F2 0x100F0C21U
|
||||
#define PI_WP_GAP_2_F1 0x100F0C28U
|
||||
#define PI_WP_GAP_2_F2 0x000F0C29U
|
||||
#define PI_RP_GAP_2_F1 0x000F0C2AU
|
||||
#define PI_RP_GAP_2_F2 0x100F0C2AU
|
||||
#define PI_WR_GAP_S_2_F1 0x100F0C2BU
|
||||
#define PI_WR_GAP_S_2_F2 0x000F0C2CU
|
||||
#define PI_WR_GAP_L_2_F1 0x000F0C2DU
|
||||
#define PI_WR_GAP_L_2_F2 0x100F0C2DU
|
||||
#define PI_RW_GAP_2_F1 0x100F0C2EU
|
||||
#define PI_RW_GAP_2_F2 0x000F0C2FU
|
||||
#define PI_WP_GAP_3_F1 0x000F0C36U
|
||||
#define PI_WP_GAP_3_F2 0x100F0C36U
|
||||
#define PI_RP_GAP_3_F1 0x100F0C37U
|
||||
#define PI_RP_GAP_3_F2 0x000F0C38U
|
||||
#define PI_WR_GAP_S_3_F1 0x000F0C39U
|
||||
#define PI_WR_GAP_S_3_F2 0x100F0C39U
|
||||
#define PI_WR_GAP_L_3_F1 0x100F0C3AU
|
||||
#define PI_WR_GAP_L_3_F2 0x000F0C3BU
|
||||
#define PI_RW_GAP_3_F1 0x000F0C3CU
|
||||
#define PI_RW_GAP_3_F2 0x100F0C3CU
|
||||
#define PI_DARRAY3_0_CS0_F0 0x00080C9DU
|
||||
#define PI_DARRAY3_1_CS0_F0 0x08080C9DU
|
||||
#define PI_DARRAY3_0_CS0_F1 0x00080CA7U
|
||||
#define PI_DARRAY3_1_CS0_F1 0x08080CA7U
|
||||
#define PI_DARRAY3_0_CS0_F2 0x00080CB1U
|
||||
#define PI_DARRAY3_1_CS0_F2 0x08080CB1U
|
||||
#define PI_DARRAY3_2_CS0_F2 0x10080CB1U
|
||||
#define PI_DARRAY3_20_CS0_F2 0x00080CB6U
|
||||
#define PI_DARRAY3_0_CS1_F0 0x00080CBBU
|
||||
#define PI_DARRAY3_1_CS1_F0 0x08080CBBU
|
||||
#define PI_DARRAY3_0_CS1_F1 0x00080CC5U
|
||||
#define PI_DARRAY3_1_CS1_F1 0x08080CC5U
|
||||
#define PI_DARRAY3_0_CS1_F2 0x00080CCFU
|
||||
#define PI_DARRAY3_1_CS1_F2 0x08080CCFU
|
||||
#define PI_DARRAY3_2_CS1_F2 0x10080CCFU
|
||||
#define PI_DARRAY3_20_CS1_F2 0x00080CD4U
|
||||
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)
|
||||
|
||||
#endif /* DDR_REGDEF_H_ */
|
||||
@@ -0,0 +1,171 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* This software is provided as reference/sample code under the license
|
||||
* agreement between Renesas Electronics Corporation and licensee (the
|
||||
* "License Agreement") and shall be treated as specified in the License
|
||||
* Agreement.
|
||||
* These instructions, statements, and software are the confidential
|
||||
* information of Renesas Electronics Corporation. They must be used and
|
||||
* modified solely for the purpose for which it was furnished by Renesas
|
||||
* Electronics Corporation. All or part of these instructions, statements and
|
||||
* software must not be reproduced nor disclosed to any third party in any
|
||||
* form, unless permitted by the License Agreement.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
|
||||
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECC initialize function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ecc_enable_v4m.c
|
||||
* - Version : 0.05
|
||||
* @brief Enable setting process of ECC for DRAM.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.08.2023 0.01 First Release
|
||||
* : 21.08.2023 0.02 Update the ecc setting according to HW SAN rev0.82.
|
||||
* : 08.04.2024 0.03 Update the ecc register setting.
|
||||
* : 13.06.2024 0.04 Fix register setting for EDC_CFG, and revise
|
||||
* : the ecm_lock()/ecm_unlock() process.
|
||||
* : 27.01.2025 0.05 Add ECM setting process.
|
||||
* Remove unused functions.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#if (ECC_ENABLE == 1)
|
||||
#include "ecc_enable_v4m.h"
|
||||
#include "ecm_enable_v4m.h"
|
||||
#include "mem_io.h"
|
||||
#include "v4m/lpddr5/boot_init_dram_regdef.h"
|
||||
|
||||
/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/
|
||||
void ecc_sdram_enable(void)
|
||||
{
|
||||
NOTICE("ECC for DRAM is enable.\n");
|
||||
|
||||
uint32_t ecm_tmp;
|
||||
|
||||
/* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers.
|
||||
After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */
|
||||
mem_write32(DB0SYSCNT0, 0x00001234U);
|
||||
mem_write32(DB0SYSCNT0A, 0x00001234U);
|
||||
|
||||
/* (A) Setting ECM */
|
||||
/* Unlock the write protect of ECM registers */
|
||||
ecm_unlock();
|
||||
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
|
||||
to inform the external device of the error via the ERROROUT# pin. */
|
||||
/* Set bit 1 of ECMERRTGTR0 to 0 and bit 1 of ECMERRCTLR0 to 1. */
|
||||
ecm_tmp = mem_read32(ECMERRTGTR0);
|
||||
ecm_tmp &= ~(0x2U);
|
||||
ecm_write(ECMERRTGTR0, ecm_tmp);
|
||||
|
||||
ecm_tmp = mem_read32(ECMERRCTLR0);
|
||||
ecm_tmp |= (0x2U);
|
||||
ecm_write(ECMERRCTLR0, ecm_tmp);
|
||||
|
||||
/* (B) Setting ECC protection area */
|
||||
/* Set the bottom row address of the ECC protection area */
|
||||
mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00);
|
||||
mem_write32(DB0FSDRAMECCAREA01, ECC_PROT_SIZE01);
|
||||
|
||||
/* (C) Initialization for DRAM */
|
||||
mem_write32(DBSC_DB0ACEN, 0x00000000U);
|
||||
|
||||
/*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/
|
||||
/* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */
|
||||
mem_write32(DB0FSCONF00A, 0x0U);
|
||||
|
||||
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
|
||||
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00);
|
||||
|
||||
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
|
||||
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00);
|
||||
|
||||
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
|
||||
mem_write32(DB0FSCTRL01A, 0x01U);
|
||||
|
||||
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
|
||||
NOTICE("DRAM rank 0 of DBSC0 is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB0FSSTAT01A);
|
||||
} while ((ecm_tmp & 0x01U) != 0x01U);
|
||||
|
||||
/*** If DRAM is connected to RANK1, Initialize RANK1 by the following procedure ***/
|
||||
/* [Step1] Specify RANK1 as the initialization target. Set 0x1 to DB0FSCONF00A[1:0]. */
|
||||
mem_write32(DB0FSCONF00A, 0x1U);
|
||||
|
||||
/* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */
|
||||
mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA01);
|
||||
|
||||
/* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */
|
||||
mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA01);
|
||||
|
||||
/* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */
|
||||
mem_write32(DB0FSCTRL01A, 0x01U);
|
||||
|
||||
/* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */
|
||||
NOTICE("DRAM rank 1 of DBSC0 is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB0FSSTAT01A);
|
||||
} while ((ecm_tmp & 0x01U) != 0x01U);
|
||||
|
||||
/* (D) Setting ECC protection enable */
|
||||
ecm_tmp = mem_read32(DB0FSCONFAXI0);
|
||||
ecm_tmp |= (0x3U << 8U);
|
||||
mem_write32(DB0FSCONFAXI0, ecm_tmp);
|
||||
|
||||
/* (E) System RAM initialization */
|
||||
/* Read DB0FSSTAT00A and wait until its value changes to 0x1. */
|
||||
/* When DB0FSSTAT00A changes to 0x1, the System RAM area initialization is complete of dbs0 */
|
||||
NOTICE("System RAM is initializing.......\n");
|
||||
do
|
||||
{
|
||||
ecm_tmp = 0x01U;
|
||||
ecm_tmp &= mem_read32(DB0FSSTAT00A);
|
||||
} while (ecm_tmp != 0x1U);
|
||||
|
||||
/* (F) Setting for ECC error interrupt */
|
||||
/* (1) Set the ECC error interrupt for read data */
|
||||
mem_write32(DB0FSINTENB02A, 0xFF00U);
|
||||
|
||||
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
|
||||
ecm_tmp = mem_read32(DB0FSINTENB02A);
|
||||
ecm_tmp |= 0xFF000000U;
|
||||
mem_write32(DB0FSINTENB02A, ecm_tmp);
|
||||
|
||||
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
|
||||
mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU);
|
||||
|
||||
/* Lock the ECM registers */
|
||||
ecm_lock();
|
||||
|
||||
/* Enable the write protect of ECM registers */
|
||||
mem_write32(DBSC_DB0ACEN, 0x00000001U);
|
||||
|
||||
/* Enable the access protect for DBSC registers */
|
||||
mem_write32(DB0SYSCNT0, 0x00000000U);
|
||||
mem_write32(DB0SYSCNT0A, 0x00000000U);
|
||||
}
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* This software is provided as reference/sample code under the license
|
||||
* agreement between Renesas Electronics Corporation and licensee (the
|
||||
* "License Agreement") and shall be treated as specified in the License
|
||||
* Agreement.
|
||||
* These instructions, statements, and software are the confidential
|
||||
* information of Renesas Electronics Corporation. They must be used and
|
||||
* modified solely for the purpose for which it was furnished by Renesas
|
||||
* Electronics Corporation. All or part of these instructions, statements and
|
||||
* software must not be reproduced nor disclosed to any third party in any
|
||||
* form, unless permitted by the License Agreement.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
|
||||
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECC driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef ECC_PROTECT
|
||||
#define ECC_PROTECT
|
||||
/* DBSC registers */
|
||||
#if defined(__RH850G3K__)
|
||||
#include "remap_register.h"
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#define ECM_BASE (BASE_ECC_ADDR)
|
||||
#else
|
||||
#if (ECC_ENABLE == 1)
|
||||
#include "mem_io.h"
|
||||
#include "log.h"
|
||||
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
|
||||
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
#define ECM_BASE (0xE6250000U)
|
||||
#endif/* defined(__RH850G3K__) */
|
||||
|
||||
#if (ECC_ENABLE == 1)
|
||||
void ecc_sdram_enable(void);
|
||||
|
||||
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
|
||||
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
|
||||
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
|
||||
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
|
||||
|
||||
#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U)
|
||||
#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U)
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
#define ECMWACNTR (ECM_BASE + 0x0A04U)
|
||||
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
|
||||
#if (ECC_ENABLE == 1)
|
||||
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
|
||||
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
|
||||
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
|
||||
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
|
||||
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
|
||||
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
|
||||
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
|
||||
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
|
||||
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
|
||||
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
|
||||
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
|
||||
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
|
||||
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
|
||||
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
|
||||
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
|
||||
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
|
||||
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
|
||||
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
|
||||
|
||||
#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U)
|
||||
#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U)
|
||||
#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U)
|
||||
#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U)
|
||||
|
||||
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
|
||||
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
|
||||
|
||||
/********************* Set by the user *********************/
|
||||
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
|
||||
#define ECC_PROT_SIZE00 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE01 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE10 (0xCCCCU)
|
||||
#define ECC_PROT_SIZE11 (0xCCCCU)
|
||||
|
||||
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
|
||||
#define START_ECC_INIT_AREA00 (0x00000000U)
|
||||
#define START_ECC_INIT_AREA10 (0x00000000U)
|
||||
#define END_ECC_INIT_AREA00 (0x0000CCCBU)
|
||||
#define END_ECC_INIT_AREA10 (0x0000CCCBU)
|
||||
|
||||
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
|
||||
#define START_ECC_INIT_AREA01 (0x00000000U)
|
||||
#define START_ECC_INIT_AREA11 (0x00000000U)
|
||||
#define END_ECC_INIT_AREA01 (0x0000CCCBU)
|
||||
#define END_ECC_INIT_AREA11 (0x0000CCCBU)
|
||||
/*********** Other settings cannot be changed ***************/
|
||||
#endif /* ECC_ENABLE == 1 */
|
||||
|
||||
#endif/* ECC_PROTECT */
|
||||
@@ -0,0 +1,265 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* This software is provided as reference/sample code under the license
|
||||
* agreement between Renesas Electronics Corporation and licensee (the
|
||||
* "License Agreement") and shall be treated as specified in the License
|
||||
* Agreement.
|
||||
* These instructions, statements, and software are the confidential
|
||||
* information of Renesas Electronics Corporation. They must be used and
|
||||
* modified solely for the purpose for which it was furnished by Renesas
|
||||
* Electronics Corporation. All or part of these instructions, statements and
|
||||
* software must not be reproduced nor disclosed to any third party in any
|
||||
* form, unless permitted by the License Agreement.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
|
||||
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECM initialize function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ecm_enable_v4m.c
|
||||
* - Version : 0.01
|
||||
* @brief ECM setting.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 29.01.2025 0.01 First Release
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ecm_enable_v4m.h"
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
#include "log.h"
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
#include "ecc_enable_v4m.h"
|
||||
#include "mem_io.h"
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
#define ECM_ERR_REG_MAX (39U)
|
||||
|
||||
typedef struct{
|
||||
uint32_t phys_addr; /* Physical address of ECM registers. */
|
||||
uint32_t value; /* Setting value of ECM registers. */
|
||||
} ECM_ERROR_TABLE;
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
void ecm_unlock(void)
|
||||
{
|
||||
mem_write32(ECMWPCNTR, 0xACCE0001U);
|
||||
}
|
||||
|
||||
void ecm_write(uint32_t adr, uint32_t val)
|
||||
{
|
||||
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
|
||||
mem_write32(adr, val);
|
||||
}
|
||||
|
||||
void ecm_lock(void)
|
||||
{
|
||||
mem_write32(ECMWPCNTR, 0xACCE0000U);
|
||||
}
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
void ecm_error_enable(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t loop;
|
||||
|
||||
const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250000U, 0xFFFFF003U}, /* ECMERRCTLR0 */
|
||||
[1] = {0xE6250004U, 0xA7F8C000U}, /* ECMERRCTLR1 */
|
||||
[2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
|
||||
[3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
|
||||
[4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
|
||||
[5] = {0xE6250014U, 0x8FFFFFFFU}, /* ECMERRCTLR5 */
|
||||
[6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */
|
||||
[7] = {0xE625001CU, 0x68980FFFU}, /* ECMERRCTLR7 */
|
||||
[8] = {0xE6250020U, 0x60A00000U}, /* ECMERRCTLR8 */
|
||||
[9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */
|
||||
[10] = {0xE6250028U, 0x557D554CU}, /* ECMERRCTLR10 */
|
||||
[11] = {0xE625002CU, 0xFF3C1555U}, /* ECMERRCTLR11 */
|
||||
[12] = {0xE6250030U, 0x0003FFFFU}, /* ECMERRCTLR12 */
|
||||
/* Skip ECMERRCTLR13 setting */
|
||||
/* Skip ECMERRCTLR14 setting */
|
||||
/* Skip ECMERRCTLR15 setting */
|
||||
[13] = {0xE6250040U, 0x33F03FFFU}, /* ECMERRCTLR16 */
|
||||
[14] = {0xE6250044U, 0x2DFF9CE0U}, /* ECMERRCTLR17 */
|
||||
[15] = {0xE6250048U, 0x0CC037FFU}, /* ECMERRCTLR18 */
|
||||
[16] = {0xE625004CU, 0xFFFFFF31U}, /* ECMERRCTLR19 */
|
||||
[17] = {0xE6250050U, 0xFE60067EU}, /* ECMERRCTLR20 */
|
||||
[18] = {0xE6250054U, 0xBF61820FU}, /* ECMERRCTLR21 */
|
||||
[19] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */
|
||||
[20] = {0xE625005CU, 0x7E90C008U}, /* ECMERRCTLR23 */
|
||||
[21] = {0xE6250060U, 0x7E788AD9U}, /* ECMERRCTLR24 */
|
||||
[22] = {0xE6250064U, 0xC7807AB7U}, /* ECMERRCTLR25 */
|
||||
[23] = {0xE6250068U, 0x7E90C008U}, /* ECMERRCTLR26 */
|
||||
[24] = {0xE625006CU, 0x7E788AD9U}, /* ECMERRCTLR27 */
|
||||
[25] = {0xE6250070U, 0xC7807AB7U}, /* ECMERRCTLR28 */
|
||||
[26] = {0xE6250074U, 0x0010C008U}, /* ECMERRCTLR29 */
|
||||
[27] = {0xE6250078U, 0x7E608A99U}, /* ECMERRCTLR30 */
|
||||
[28] = {0xE625007CU, 0x84007A00U}, /* ECMERRCTLR31 */
|
||||
[29] = {0xE6250080U, 0xDFFFFFFFU}, /* ECMERRCTLR32 */
|
||||
[30] = {0xE6250084U, 0x1FFFFFFFU}, /* ECMERRCTLR33 */
|
||||
[31] = {0xE6250088U, 0x0000001FU}, /* ECMERRCTLR34 */
|
||||
[32] = {0xE625008CU, 0xA3BEEA80U}, /* ECMERRCTLR35 */
|
||||
[33] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
|
||||
/* Skip ECMERRCTLR37 setting */
|
||||
[34] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */
|
||||
[35] = {0xE625009CU, 0x19FF0000U}, /* ECMERRCTLR39 */
|
||||
[36] = {0xE62500A0U, 0x0000601EU}, /* ECMERRCTLR40 */
|
||||
[37] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */
|
||||
[38] = {0xE62500A8U, 0x0000000FU}, /* ECMERRCTLR42 */
|
||||
};
|
||||
|
||||
#if (ECMERRTGTR_INTC == 1)
|
||||
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250200U, 0xFFFFF003U}, /* ECMERRTGTR0 */
|
||||
[1] = {0xE6250204U, 0xA7F8C000U}, /* ECMERRTGTR1 */
|
||||
[2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
|
||||
[3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
|
||||
[4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
|
||||
[5] = {0xE6250214U, 0x8FFFFFFFU}, /* ECMERRTGTR5 */
|
||||
[6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */
|
||||
[7] = {0xE625021CU, 0x68980FFFU}, /* ECMERRTGTR7 */
|
||||
[8] = {0xE6250220U, 0x60A00000U}, /* ECMERRTGTR8 */
|
||||
[9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */
|
||||
[10] = {0xE6250228U, 0x557D554CU}, /* ECMERRTGTR10 */
|
||||
[11] = {0xE625022CU, 0xFF3C1555U}, /* ECMERRTGTR11 */
|
||||
[12] = {0xE6250230U, 0x0003FFFFU}, /* ECMERRTGTR12 */
|
||||
/* Skip ECMERRTGTR13 setting */
|
||||
/* Skip ECMERRTGTR14 setting */
|
||||
/* Skip ECMERRTGTR15 setting */
|
||||
[13] = {0xE6250240U, 0x33F03FFFU}, /* ECMERRTGTR16 */
|
||||
[14] = {0xE6250244U, 0x2DFF9CE0U}, /* ECMERRTGTR17 */
|
||||
[15] = {0xE6250248U, 0x0CC037FFU}, /* ECMERRTGTR18 */
|
||||
[16] = {0xE625024CU, 0xFFFFFF31U}, /* ECMERRTGTR19 */
|
||||
[17] = {0xE6250250U, 0xFE60067EU}, /* ECMERRTGTR20 */
|
||||
[18] = {0xE6250254U, 0xBF61820FU}, /* ECMERRTGTR21 */
|
||||
[19] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */
|
||||
[20] = {0xE625025CU, 0x7E90C008U}, /* ECMERRTGTR23 */
|
||||
[21] = {0xE6250260U, 0x7E788AD9U}, /* ECMERRTGTR24 */
|
||||
[22] = {0xE6250264U, 0xC7807AB7U}, /* ECMERRTGTR25 */
|
||||
[23] = {0xE6250268U, 0x7E90C008U}, /* ECMERRTGTR26 */
|
||||
[24] = {0xE625026CU, 0x7E788AD9U}, /* ECMERRTGTR27 */
|
||||
[25] = {0xE6250270U, 0xC7807AB7U}, /* ECMERRTGTR28 */
|
||||
[26] = {0xE6250274U, 0x0010C008U}, /* ECMERRTGTR29 */
|
||||
[27] = {0xE6250278U, 0x7E608A99U}, /* ECMERRTGTR30 */
|
||||
[28] = {0xE625027CU, 0x84007A00U}, /* ECMERRTGTR31 */
|
||||
[29] = {0xE6250280U, 0xDFFFFFFFU}, /* ECMERRTGTR32 */
|
||||
[30] = {0xE6250284U, 0x1FFFFFFFU}, /* ECMERRTGTR33 */
|
||||
[31] = {0xE6250288U, 0x0000001FU}, /* ECMERRTGTR34 */
|
||||
[32] = {0xE625028CU, 0xA3BEEA80U}, /* ECMERRTGTR35 */
|
||||
[33] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
|
||||
/* Skip ECMERRTGTR37 setting */
|
||||
[34] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */
|
||||
[35] = {0xE625029CU, 0x19FF0000U}, /* ECMERRTGTR39 */
|
||||
[36] = {0xE62502A0U, 0x0000601EU}, /* ECMERRTGTR40 */
|
||||
[37] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */
|
||||
[38] = {0xE62502A8U, 0x0000000FU}, /* ECMERRTGTR42 */
|
||||
};
|
||||
#elif (ECMERRTGTR_INTC == 0)
|
||||
const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = {
|
||||
[0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */
|
||||
[1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */
|
||||
[2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */
|
||||
[3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */
|
||||
[4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */
|
||||
[5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */
|
||||
[6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */
|
||||
[7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */
|
||||
[8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */
|
||||
[9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */
|
||||
[10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */
|
||||
[11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */
|
||||
[12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */
|
||||
/* Skip ECMERRTGTR13 setting */
|
||||
/* Skip ECMERRTGTR14 setting */
|
||||
/* Skip ECMERRTGTR15 setting */
|
||||
[13] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */
|
||||
[14] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */
|
||||
[15] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */
|
||||
[16] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */
|
||||
[17] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */
|
||||
[18] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */
|
||||
[19] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */
|
||||
[20] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */
|
||||
[21] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */
|
||||
[22] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */
|
||||
[23] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */
|
||||
[24] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */
|
||||
[25] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */
|
||||
[26] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */
|
||||
[27] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */
|
||||
[28] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */
|
||||
[29] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */
|
||||
[30] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */
|
||||
[31] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */
|
||||
[32] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */
|
||||
[33] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */
|
||||
/* Skip ECMERRTGTR37 setting */
|
||||
[34] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */
|
||||
[35] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */
|
||||
[36] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */
|
||||
[37] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */
|
||||
[38] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */
|
||||
};
|
||||
#endif /* ECMERRTGTR_INTC == 1 */
|
||||
|
||||
/* Unlock the write protect of ECM registers */
|
||||
ecm_unlock();
|
||||
|
||||
NOTICE("ECMERRCTLR register setting.\n");
|
||||
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
|
||||
{
|
||||
/* Set ECMERRCTLR registers. */
|
||||
reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr);
|
||||
reg |= ecmerrctlr_tbl[loop].value;
|
||||
ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg);
|
||||
|
||||
INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
|
||||
loop,
|
||||
ecmerrctlr_tbl[loop].phys_addr,
|
||||
mem_read32(ecmerrctlr_tbl[loop].phys_addr),
|
||||
ecmerrctlr_tbl[loop].value);
|
||||
}
|
||||
|
||||
NOTICE("ECMERRTGTR register setting.\n");
|
||||
for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++)
|
||||
{
|
||||
/* Set ECMERRTGTR registers. */
|
||||
reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr);
|
||||
reg |= ecmerrtgtr_tbl[loop].value;
|
||||
ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg);
|
||||
|
||||
INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
|
||||
loop,
|
||||
ecmerrtgtr_tbl[loop].phys_addr,
|
||||
mem_read32(ecmerrtgtr_tbl[loop].phys_addr),
|
||||
ecmerrtgtr_tbl[loop].value);
|
||||
}
|
||||
|
||||
/* Lock the ECM registers */
|
||||
ecm_lock();
|
||||
}
|
||||
/* End of function ecm_error_enable(void) */
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
|
||||
*
|
||||
* This software is provided as reference/sample code under the license
|
||||
* agreement between Renesas Electronics Corporation and licensee (the
|
||||
* "License Agreement") and shall be treated as specified in the License
|
||||
* Agreement.
|
||||
* These instructions, statements, and software are the confidential
|
||||
* information of Renesas Electronics Corporation. They must be used and
|
||||
* modified solely for the purpose for which it was furnished by Renesas
|
||||
* Electronics Corporation. All or part of these instructions, statements and
|
||||
* software must not be reproduced nor disclosed to any third party in any
|
||||
* form, unless permitted by the License Agreement.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
|
||||
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : ECM driver header
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef ECM_ENABLE
|
||||
#define ECM_ENABLE
|
||||
|
||||
#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1))
|
||||
void ecm_unlock(void);
|
||||
void ecm_write(uint32_t adr, uint32_t val);
|
||||
void ecm_lock(void);
|
||||
#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */
|
||||
|
||||
#if (ECM_ERROR_ENABLE == 1)
|
||||
void ecm_error_enable(void);
|
||||
#endif /* ECM_ERROR_ENABLE == 1 */
|
||||
|
||||
#endif/* ECM_ENABLE */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
95
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c
Normal file
95
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c
Normal file
@@ -0,0 +1,95 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc boot
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_boot.c
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 18.03.2022 0.02 Removed unnecessary functions
|
||||
* Removed unnecessary header file inclusions
|
||||
* : 16.06.2022 0.03 Change log output
|
||||
* : 31.10.2022 0.04 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "emmc_boot.h"
|
||||
#include "log.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_def.h"
|
||||
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Definitions */
|
||||
/************************************************************************************************/
|
||||
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Unions */
|
||||
/************************************************************************************************/
|
||||
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Structs */
|
||||
/************************************************************************************************/
|
||||
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Globals */
|
||||
/************************************************************************************************/
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Macros */
|
||||
/************************************************************************************************/
|
||||
|
||||
/************************************************************************************************/
|
||||
/* Prototypes */
|
||||
/************************************************************************************************/
|
||||
|
||||
void emmc_initialize( void )
|
||||
{
|
||||
EMMC_ERROR_CODE result;
|
||||
|
||||
/* eMMC driver initialize */
|
||||
(void)emmc_init(); /* Normal clock mode */
|
||||
|
||||
/* Card power on */
|
||||
(void)emmc_memcard_power(TRUE);
|
||||
|
||||
/* Card mount */
|
||||
result = emmc_mount();
|
||||
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
NOTICE("eMMC initialize error!!\n");
|
||||
panic;
|
||||
}
|
||||
}
|
||||
622
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c
Normal file
622
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c
Normal file
@@ -0,0 +1,622 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc command
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_cmd.c
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 16.06.2022 0.02 Change log output
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_registers.h"
|
||||
#include "emmc_def.h"
|
||||
#include "timer.h"
|
||||
#include "log.h"
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
static void emmc_read_response(uint32_t *response);
|
||||
static void emmc_little_to_big(uint8_t *p, uint32_t value);
|
||||
static void emmc_data_transfer_dma(void);
|
||||
static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask);
|
||||
static void emmc_softreset(void);
|
||||
static void emmc_WaitCmd2Cmd_8Cycle(void);
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
/* execute MMC command.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* * Clock to memory card IF is enabled.
|
||||
* - Post-conditions:<BR>
|
||||
* Requested command is executed successfully
|
||||
*
|
||||
* param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS)
|
||||
* param[in,out] *response Response from the card (virtual address)
|
||||
* return eMMC error code.
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
|
||||
{
|
||||
EMMC_ERROR_CODE rtn_code = EMMC_ERR;
|
||||
HAL_MEMCARD_RESPONSE_TYPE response_type;
|
||||
HAL_MEMCARD_COMMAND_TYPE cmd_type;
|
||||
EMMC_INT_STATE state;
|
||||
|
||||
/* parameter check */
|
||||
if (response == NULL)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
|
||||
return EMMC_ERR_PARAM;
|
||||
}
|
||||
|
||||
/* state check */
|
||||
if (mmc_drv_obj.clock_enable != TRUE)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE);
|
||||
return EMMC_ERR_STATE;
|
||||
}
|
||||
|
||||
if (mmc_drv_obj.state_machine_blocking == TRUE)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR);
|
||||
return EMMC_ERR;
|
||||
}
|
||||
|
||||
state = ESTATE_BEGIN;
|
||||
response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK);
|
||||
cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK);
|
||||
|
||||
/* state machine */
|
||||
while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END))
|
||||
{
|
||||
/* The interrupt factor flag is observed. */
|
||||
(void)emmc_interrupt();
|
||||
|
||||
/* wait interrupt */
|
||||
if (mmc_drv_obj.state_machine_blocking == TRUE)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ESTATE_BEGIN:
|
||||
/* Busy check */
|
||||
if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY);
|
||||
return EMMC_ERR_CARD_BUSY;
|
||||
}
|
||||
|
||||
/* clear register */
|
||||
mem_write32(SD_INFO1, 0x00000000U);
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR);
|
||||
mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0);
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
|
||||
/* fallthrough */
|
||||
|
||||
case ESTATE_ISSUE_CMD:
|
||||
/* ARG */
|
||||
mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg);
|
||||
/* issue cmd */
|
||||
mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw);
|
||||
/* Set driver flag */
|
||||
mmc_drv_obj.state_machine_blocking = TRUE;
|
||||
|
||||
if (response_type == HAL_MEMCARD_RESPONSE_NONE)
|
||||
{
|
||||
state = ESTATE_NON_RESP_CMD;
|
||||
} else {
|
||||
state = ESTATE_RCV_RESP;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case ESTATE_NON_RESP_CMD:
|
||||
/* interrupt disable */
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U);
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
|
||||
|
||||
/* check interrupt */
|
||||
if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
|
||||
{
|
||||
/* error interrupt */
|
||||
rtn_code = EMMC_ERR_INFO2;
|
||||
state = ESTATE_ERROR;
|
||||
} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) {
|
||||
/* not receive expected interrupt */
|
||||
rtn_code = EMMC_ERR_RESPONSE;
|
||||
state = ESTATE_ERROR;
|
||||
} else {
|
||||
emmc_WaitCmd2Cmd_8Cycle();
|
||||
state = ESTATE_END;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_RCV_RESP:
|
||||
/* interrupt disable */
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U);
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
|
||||
|
||||
/* check interrupt */
|
||||
if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
|
||||
{
|
||||
/* error interrupt */
|
||||
rtn_code = EMMC_ERR_INFO2;
|
||||
state = ESTATE_ERROR;
|
||||
break;
|
||||
} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) {
|
||||
/* not receive expected interrupt */
|
||||
rtn_code = EMMC_ERR_RESPONSE;
|
||||
state = ESTATE_ERROR;
|
||||
break;
|
||||
} else {
|
||||
/* nop */
|
||||
}
|
||||
|
||||
/* read response */
|
||||
emmc_read_response(response);
|
||||
|
||||
/* check response */
|
||||
rtn_code = emmc_response_check(response, error_mask);
|
||||
if (rtn_code != EMMC_SUCCESS)
|
||||
{
|
||||
state = ESTATE_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (response_type == HAL_MEMCARD_RESPONSE_R1b)
|
||||
{
|
||||
/* R1b */
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
state = ESTATE_RCV_RESPONSE_BUSY;
|
||||
} else {
|
||||
state = ESTATE_CHECK_RESPONSE_COMPLETE;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_RCV_RESPONSE_BUSY:
|
||||
/* check interrupt */
|
||||
if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
|
||||
{
|
||||
/* error interrupt */
|
||||
rtn_code = EMMC_ERR_INFO2;
|
||||
state = ESTATE_ERROR;
|
||||
break;
|
||||
}
|
||||
/* DAT0 not Busy */
|
||||
if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U)
|
||||
{
|
||||
state = ESTATE_CHECK_RESPONSE_COMPLETE;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_CHECK_RESPONSE_COMPLETE:
|
||||
if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE)
|
||||
{
|
||||
state = ESTATE_DATA_TRANSFER;
|
||||
} else {
|
||||
emmc_WaitCmd2Cmd_8Cycle();
|
||||
state = ESTATE_END;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_DATA_TRANSFER:
|
||||
/* ADTC command */
|
||||
mmc_drv_obj.during_transfer = TRUE;
|
||||
mmc_drv_obj.state_machine_blocking = TRUE;
|
||||
|
||||
if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA)
|
||||
{
|
||||
/* DMA */
|
||||
emmc_data_transfer_dma();
|
||||
} else {
|
||||
/* PIO */
|
||||
/* interrupt enable (FIFO read/write enable) */
|
||||
if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
|
||||
{
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
} else {
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
}
|
||||
}
|
||||
state = ESTATE_DATA_TRANSFER_COMPLETE;
|
||||
break;
|
||||
|
||||
case ESTATE_DATA_TRANSFER_COMPLETE:
|
||||
/* check interrupt */
|
||||
if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U)
|
||||
{
|
||||
/* error interrupt */
|
||||
rtn_code = EMMC_ERR_INFO2;
|
||||
state = ESTATE_TRANSFER_ERROR;
|
||||
break;
|
||||
} else {
|
||||
/* success. nothing to do. */
|
||||
}
|
||||
|
||||
/* DMAC error ? */
|
||||
if (mmc_drv_obj.dma_error_flag == TRUE)
|
||||
{
|
||||
/* Error occurred in DMAC driver. */
|
||||
rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER;
|
||||
state = ESTATE_TRANSFER_ERROR;
|
||||
} else if (mmc_drv_obj.during_dma_transfer == TRUE) {
|
||||
/* DMAC not finished. unknown error */
|
||||
rtn_code = EMMC_ERR;
|
||||
state = ESTATE_TRANSFER_ERROR;
|
||||
} else {
|
||||
mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2);
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
|
||||
mmc_drv_obj.state_machine_blocking = TRUE;
|
||||
|
||||
state = ESTATE_ACCESS_END;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_ACCESS_END:
|
||||
|
||||
/* clear flag */
|
||||
if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode)
|
||||
{
|
||||
mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
|
||||
mem_write32(SD_STOP, 0x00000000U);
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
}
|
||||
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U);
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR);
|
||||
mem_write32(SD_INFO1, 0x00000000U);
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR);
|
||||
|
||||
if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U)
|
||||
{
|
||||
emmc_WaitCmd2Cmd_8Cycle();
|
||||
state = ESTATE_END;
|
||||
} else {
|
||||
state = ESTATE_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTATE_TRANSFER_ERROR:
|
||||
/* The error occurred in the Data transfer. */
|
||||
if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode)
|
||||
{
|
||||
mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
|
||||
mem_write32(SD_STOP, 0x00000000U);
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
}
|
||||
/* fallthrough */
|
||||
|
||||
case ESTATE_ERROR:
|
||||
emmc_softreset();
|
||||
ERROR("%s:0x%x\n",__func__,rtn_code);
|
||||
return rtn_code;
|
||||
|
||||
default:
|
||||
state = ESTATE_END;
|
||||
break;
|
||||
} /* switch (state) */
|
||||
} /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
|
||||
|
||||
/* force terminate */
|
||||
if (mmc_drv_obj.force_terminate == TRUE)
|
||||
{
|
||||
/* timeout timer is expired. Or, PIO data transfer error. */
|
||||
/* Timeout occurred in the DMA transfer. */
|
||||
if (mmc_drv_obj.during_dma_transfer == TRUE)
|
||||
{
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
}
|
||||
emmc_softreset();
|
||||
|
||||
return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
|
||||
}
|
||||
|
||||
/* success */
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** host controller softrest.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param None.
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_softreset(void)
|
||||
{
|
||||
int32_t loop = 10000;
|
||||
int32_t retry = 1000;
|
||||
|
||||
/* flag clear */
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
mmc_drv_obj.force_terminate = FALSE;
|
||||
mmc_drv_obj.dma_error_flag = FALSE;
|
||||
|
||||
/* during operation ? */
|
||||
if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)
|
||||
{
|
||||
/* wait CMDSEQ = 0 */
|
||||
while (loop > 0)
|
||||
{
|
||||
if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U)
|
||||
{
|
||||
break; /* ready */
|
||||
}
|
||||
|
||||
loop--;
|
||||
if ((loop == 0) && (retry > 0))
|
||||
{
|
||||
micro_wait(1000U); /* wait 1ms */
|
||||
loop = 10000;
|
||||
retry--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* reset */
|
||||
mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */
|
||||
mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */
|
||||
|
||||
/* initialize */
|
||||
mem_write32(SD_INFO1, 0x00000000U);
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR);
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
|
||||
|
||||
}
|
||||
|
||||
/** read response
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Called from emmc_exec_cmd().
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] *response Response from the card
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_read_response(uint32_t *response)
|
||||
{
|
||||
|
||||
uint8_t *p = NULL;
|
||||
|
||||
if (response == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* read response */
|
||||
if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH)
|
||||
{
|
||||
/* CSD or CID */
|
||||
p = (uint8_t *)(response);
|
||||
emmc_little_to_big(p, ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U))); /* [127:96] */
|
||||
emmc_little_to_big(p + 4U, ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U))); /* [95:64] */
|
||||
emmc_little_to_big(p + 8U, ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U))); /* [63:32] */
|
||||
emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U)); /* [31:0] */
|
||||
} else {
|
||||
*response = mem_read32(SD_RSP10); /* [39:8] */
|
||||
}
|
||||
}
|
||||
|
||||
/** response check
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Called from emmc_exec_cmd().
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in] *response Response from the card
|
||||
* param[in] error_mask Errors to be checked (for R1/R1b response)
|
||||
* return error code.
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask)
|
||||
{
|
||||
|
||||
HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd)
|
||||
& (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK);
|
||||
|
||||
if (response == NULL)
|
||||
{
|
||||
return EMMC_ERR_PARAM;
|
||||
}
|
||||
|
||||
if (response_type == HAL_MEMCARD_RESPONSE_NONE)
|
||||
{
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/* response check */
|
||||
if (response_type <= HAL_MEMCARD_RESPONSE_R1b)
|
||||
{
|
||||
/* R1 or R1b */
|
||||
mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT);
|
||||
if ((*response & error_mask) != 0U)
|
||||
{
|
||||
return EMMC_ERR_CARD_STATUS_BIT;
|
||||
}
|
||||
} else if (response_type == HAL_MEMCARD_RESPONSE_R4) {
|
||||
/* R4 */
|
||||
if ((*response & EMMC_R4_STATUS) != 0U)
|
||||
{
|
||||
return EMMC_ERR_CARD_STATUS_BIT;
|
||||
}
|
||||
} else {
|
||||
; /* nothing to do. other type does not have status bit */
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** brief converts endian from little to big
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] p destination buffer address.
|
||||
* param[in] value convert data.(little)
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_little_to_big(uint8_t *p, uint32_t value)
|
||||
{
|
||||
if (p == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
p[0] = (uint8_t)(value >> 24U);
|
||||
p[1] = (uint8_t)(value >> 16U);
|
||||
p[2] = (uint8_t)(value >> 8U);
|
||||
p[3] = (uint8_t)value;
|
||||
}
|
||||
|
||||
/** data transfer with DMA.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Called from emmc_exec_cmd().
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return error code.
|
||||
*/
|
||||
static void emmc_data_transfer_dma(void)
|
||||
{
|
||||
mmc_drv_obj.during_dma_transfer = TRUE;
|
||||
mmc_drv_obj.dma_error_flag = FALSE;
|
||||
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U);
|
||||
mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ));
|
||||
|
||||
/* DMAC setting */
|
||||
if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
|
||||
{
|
||||
/* transfer complete interrupt enable when write to eMMC */
|
||||
mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE ));
|
||||
/* When writing to eMMC, set only bit 17 to "0". */
|
||||
mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH0_ENABLE ));
|
||||
/* BUFF --> FIFO */
|
||||
mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */
|
||||
} else {
|
||||
/* transfer complete interrupt enable when read from eMMC */
|
||||
mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE ));
|
||||
/* When reading from eMMC, set only bit 16 to "0". */
|
||||
mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH1_ENABLE ));
|
||||
/* FIFO --> BUFF */
|
||||
mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH1(upstream), 64-bit width */
|
||||
}
|
||||
mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */
|
||||
|
||||
mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */
|
||||
}
|
||||
|
||||
/** wait cmd-cmd 8cycle
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_WaitCmd2Cmd_8Cycle(void)
|
||||
{
|
||||
uint32_t dataL, wait = 0U;
|
||||
|
||||
dataL = mem_read32(SD_CLK_CTRL);
|
||||
dataL &= 0x000000FFU;
|
||||
|
||||
switch (dataL)
|
||||
{
|
||||
case 0xFFU: /* 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x00U: /* 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x01U: /* 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x02U: /* 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x04U: /* 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x08U: /* 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x10U: /* 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x20U: /* 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) */
|
||||
wait = 10U;
|
||||
break;
|
||||
case 0x40U: /* 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) */
|
||||
wait = 20U;
|
||||
break;
|
||||
case 0x80U: /* 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) */
|
||||
wait = 30U;
|
||||
break;
|
||||
default:
|
||||
/* nop */
|
||||
break;
|
||||
}
|
||||
micro_wait(wait);
|
||||
|
||||
}
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
399
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c
Normal file
399
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c
Normal file
@@ -0,0 +1,399 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc initialize
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_init.c
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 22.03.2022 0.02 Removed CPG setting
|
||||
* Added Function End comment
|
||||
* Added header file inclusion
|
||||
* : 24.10.2022 0.03 Add CPG setting to support HS200/400
|
||||
* : 31.10.2022 0.04 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_registers.h"
|
||||
#include "emmc_def.h"
|
||||
#include "mem_io.h"
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
#undef DUMP_EMMC_REGISTERS
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
st_mmc_base mmc_drv_obj;
|
||||
#define CX_IPL_EMMC_DATA (0x41DFF000UL)
|
||||
#define CX_IPL_CSD_DATA (CX_IPL_EMMC_DATA)
|
||||
#define CX_IPL_CID_DATA (CX_IPL_CSD_DATA + EMMC_MAX_CSD_LENGTH)
|
||||
#define CX_IPL_EXT_CSD_DATA (CX_IPL_CID_DATA + EMMC_MAX_CID_LENGTH)
|
||||
volatile uint8_t *default_csd_data = (volatile uint8_t *)CX_IPL_CSD_DATA;
|
||||
volatile uint8_t *default_cid_data = (volatile uint8_t *)CX_IPL_CID_DATA;
|
||||
volatile uint8_t *default_ext_csd_data = (volatile uint8_t *)CX_IPL_EXT_CSD_DATA;
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
static void emmc_drv_init(void);
|
||||
static EMMC_ERROR_CODE emmc_dev_init(void);
|
||||
static EMMC_ERROR_CODE emmc_dev_finalize(void);
|
||||
static void emmc_memset(void *buff, uint8_t data, uint32_t cnt);
|
||||
static EMMC_ERROR_CODE emmc_reset_controller(void);
|
||||
static void emmc_driver_config(void);
|
||||
static void emmc_set_data_timeout(uint32_t data_timeout);
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE)
|
||||
static void dump_buf(const uint8_t *buf, int size)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
if ((i % 16) == 0)
|
||||
{
|
||||
log_printf("\n%x: ", i);
|
||||
}
|
||||
log_printf("%b ", (uint8_t)buf[i]);
|
||||
}
|
||||
log_printf("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_mmc_drv_obj(void)
|
||||
{
|
||||
#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE)
|
||||
NOTICE("[%s:%d] size of mmc_drv_obj %d\n", __func__, __LINE__, sizeof(mmc_drv_obj));
|
||||
NOTICE("CSD data:");
|
||||
dump_buf(mmc_drv_obj.csd_data, sizeof(mmc_drv_obj.csd_data));
|
||||
NOTICE("CID data:");
|
||||
dump_buf(mmc_drv_obj.cid_data, sizeof(mmc_drv_obj.cid_data));
|
||||
NOTICE("ext CSD data:");
|
||||
dump_buf(mmc_drv_obj.ext_csd_data, sizeof(mmc_drv_obj.ext_csd_data));
|
||||
#endif
|
||||
}
|
||||
|
||||
void import_mmc_drv_obj(void)
|
||||
{
|
||||
/* Fill mmc_drv_obj with default values */
|
||||
emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base));
|
||||
|
||||
for(int i=0; i < EMMC_MAX_CID_LENGTH; i++)
|
||||
{
|
||||
mmc_drv_obj.cid_data[i] = default_cid_data[i];
|
||||
}
|
||||
for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++)
|
||||
{
|
||||
mmc_drv_obj.csd_data[i] = default_csd_data[i];
|
||||
}
|
||||
for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++)
|
||||
{
|
||||
mmc_drv_obj.ext_csd_data[i] = default_ext_csd_data[i];
|
||||
}
|
||||
dump_mmc_drv_obj();
|
||||
|
||||
mmc_drv_obj.card_power_enable = TRUE;
|
||||
mmc_drv_obj.clock_enable = TRUE;
|
||||
mmc_drv_obj.initialize = TRUE;
|
||||
mmc_drv_obj.mount = TRUE;
|
||||
mmc_drv_obj.selected = TRUE;
|
||||
}
|
||||
|
||||
void export_mmc_drv_obj(void)
|
||||
{
|
||||
for(int i=0; i < EMMC_MAX_CID_LENGTH; i++)
|
||||
{
|
||||
*((volatile uint8_t *)&default_cid_data[i]) = mmc_drv_obj.cid_data[i];
|
||||
}
|
||||
for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++)
|
||||
{
|
||||
*((volatile uint8_t *)&default_csd_data[i]) = mmc_drv_obj.csd_data[i];
|
||||
}
|
||||
for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++)
|
||||
{
|
||||
*((volatile uint8_t *)&default_ext_csd_data[i]) = mmc_drv_obj.ext_csd_data[i];
|
||||
}
|
||||
|
||||
dump_mmc_drv_obj();
|
||||
}
|
||||
|
||||
/** brief eMMC initialize.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* retval EMMC_SUCCESS successful.
|
||||
* retval EMMC_ERR error from interrupt API.
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_init(void)
|
||||
{
|
||||
/* initialize H/W */
|
||||
(void)emmc_reset_controller();
|
||||
|
||||
/* Configuration */
|
||||
emmc_driver_config();
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** terminate emmc driver
|
||||
*
|
||||
* EMMC H/W and S/W resource is released.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return None.
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_terminate(void)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* H/W finalize */
|
||||
result = emmc_dev_finalize();
|
||||
|
||||
/* driver finalize */
|
||||
emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); /* clear global variable */
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/** Function executes full reset to MMC host controller without taking power out from the memory card.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* Reset MMC host controller without taking power out from the memory card.
|
||||
* Memory card preserves its state.
|
||||
*
|
||||
* return None
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_reset_controller(void)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* initialize mmc driver */
|
||||
emmc_drv_init();
|
||||
|
||||
mmc_drv_obj.base_address = MMC0_SD_BASE;
|
||||
|
||||
/* initialize H/W */
|
||||
result = emmc_dev_init();
|
||||
|
||||
mmc_drv_obj.initialize = TRUE;
|
||||
|
||||
return result;
|
||||
|
||||
}
|
||||
|
||||
/** Configuration eMMC driver
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* initialized eMMC driver.
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return None
|
||||
*/
|
||||
static void emmc_driver_config(void)
|
||||
{
|
||||
/* Read/Write data timeout */
|
||||
emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT);
|
||||
}
|
||||
|
||||
/** Sets data timeout
|
||||
*
|
||||
* Sets the data timeout value for read and write operations.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* initialized eMMC driver.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* After this function is called, the timeout value is set according to argument.
|
||||
*
|
||||
* param[in] time_out The desired timeout value in milliseconds.
|
||||
* return None
|
||||
*/
|
||||
static void emmc_set_data_timeout(uint32_t data_timeout)
|
||||
{
|
||||
mmc_drv_obj.data_timeout = data_timeout;
|
||||
}
|
||||
|
||||
/** eMMC driver initialize. (software)
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_drv_init(void)
|
||||
{
|
||||
/* initialize */
|
||||
emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base));
|
||||
|
||||
mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT;
|
||||
|
||||
mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
|
||||
}
|
||||
|
||||
/** eMMC driver initialize. (H/W)
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* return None.
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_dev_init(void)
|
||||
{
|
||||
/* InitSdCkcr */
|
||||
mem_write32(CPG_CPGWPR, ~(0x00000001U));
|
||||
mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */
|
||||
|
||||
/* MMCIF initialize */
|
||||
mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
|
||||
|
||||
mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */
|
||||
mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */
|
||||
mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** EMMC H/W finalize
|
||||
*
|
||||
* EMMC Host and Card hardware resource is released.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
* return None.
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_dev_finalize(void)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* MMC power off
|
||||
* the power supply of eMMC device is always turning on.
|
||||
* RST_n : Hi --> Low level.
|
||||
*/
|
||||
result = emmc_memcard_power(FALSE);
|
||||
|
||||
mem_write32(SD_INFO1, 0x00000000U);
|
||||
mem_write32(SD_INFO2, 0x00000800U);
|
||||
mem_write32(DM_CM_INFO1, 0x00000000U);
|
||||
mem_write32(DM_CM_INFO2, 0x00000000U);
|
||||
|
||||
mem_write32(SD_CLK_CTRL, 0x00000020U);
|
||||
mem_write32(CC_EXT_MODE, 0x00000000U);
|
||||
mem_write32(SD_STOP, 0x00000000U);
|
||||
mem_write32(SD_SECCNT, 0x00000000U);
|
||||
mem_write32(DM_CM_DTRAN_MODE, 0x00000000U);
|
||||
mem_write32(DM_DTRAN_ADDR, 0x00000000U);
|
||||
mem_write32(SD_OPTION, 0x00000000U);
|
||||
mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/** Set power to memory card IF.
|
||||
* This function control Vcc and Vccq and RST_n.
|
||||
*
|
||||
* attention
|
||||
* CPU cannot control Vcc&Vccq.
|
||||
* The power supply of eMMC device is always turning on.
|
||||
*
|
||||
* param[in] mode TRUE = power on, FALSE = power off
|
||||
*
|
||||
* retval EMMC_SUCCESS powering succeeded
|
||||
* retval EMMC_ERR_CARD_POWER powering failed
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode)
|
||||
{
|
||||
if (mode == TRUE)
|
||||
{
|
||||
/* power on (Vcc&Vccq is always power on) */
|
||||
mmc_drv_obj.card_power_enable = TRUE;
|
||||
} else {
|
||||
/* power off (Vcc&Vccq is always power on) */
|
||||
mmc_drv_obj.card_power_enable = FALSE;
|
||||
mmc_drv_obj.mount = FALSE;
|
||||
mmc_drv_obj.selected = FALSE;
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** memset(). no use C standard library.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] buff pointer to buffer (virtual)
|
||||
* param[in] data fill data.
|
||||
* param[in] cnt fill size (number of bytes)
|
||||
* return None.
|
||||
*/
|
||||
static void emmc_memset(void *buff, uint8_t data, uint32_t cnt)
|
||||
{
|
||||
uint8_t *tmp = NULL;
|
||||
tmp = (uint8_t *)buff;
|
||||
|
||||
if (buff == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
while (cnt > 0U)
|
||||
{
|
||||
*tmp = data;
|
||||
tmp++;
|
||||
cnt--;
|
||||
}
|
||||
}
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
239
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c
Normal file
239
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c
Normal file
@@ -0,0 +1,239 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc interrupt
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_interrupt.c
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 16.06.2022 0.02 Change log output
|
||||
* : 31.10.2022 0.03 License notation change.
|
||||
* : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_registers.h"
|
||||
#include "emmc_def.h"
|
||||
#include "log.h"
|
||||
#include "mem_io.h"
|
||||
#include <stdint.h>
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual);
|
||||
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
|
||||
|
||||
/** emmc driver interrupt service routine.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Must be block emmc driver state machine.
|
||||
* - Post-conditions:<BR>
|
||||
* unblocking emmc driver state machine.
|
||||
*
|
||||
* retval INT_SUCCESS
|
||||
*/
|
||||
uint32_t emmc_interrupt(void)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* SD_INFO */
|
||||
mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1);
|
||||
mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2);
|
||||
|
||||
/* SD_INFO EVENT */
|
||||
mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK);
|
||||
mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK);
|
||||
|
||||
/* ERR_STS */
|
||||
mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1);
|
||||
mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2);
|
||||
|
||||
/* DM_CM_INFO */
|
||||
mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1);
|
||||
mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2);
|
||||
|
||||
/* DM_CM_INFO EVENT */
|
||||
mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK);
|
||||
mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK);
|
||||
|
||||
/* ERR SD_INFO2 */
|
||||
if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U)
|
||||
{
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */
|
||||
mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
}
|
||||
|
||||
/* PIO Transfer */
|
||||
/* BWE/BRE */
|
||||
else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) {
|
||||
/* BWE */
|
||||
if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U)
|
||||
{
|
||||
mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */
|
||||
}
|
||||
/* BRE */
|
||||
else {
|
||||
mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */
|
||||
}
|
||||
|
||||
result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */
|
||||
mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH;
|
||||
mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH;
|
||||
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
/* data transfer error */
|
||||
ERROR("%s:0x%x\n",__func__, result);
|
||||
|
||||
/* Panic */
|
||||
mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */
|
||||
mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */
|
||||
mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */
|
||||
mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */
|
||||
mmc_drv_obj.force_terminate = TRUE;
|
||||
} else {
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
}
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
}
|
||||
|
||||
/* DMA_TRANSFER */
|
||||
/* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */
|
||||
else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) {
|
||||
mem_write32(DM_CM_INFO1, 0x00000000U);
|
||||
mem_write32(DM_CM_INFO2, 0x00000000U);
|
||||
mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */
|
||||
/* DM_CM_INFO2: DMA-ch0 error occured */
|
||||
if (( DM_CM_INFO2_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U)
|
||||
{
|
||||
mmc_drv_obj.dma_error_flag = TRUE;
|
||||
} else {
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
}
|
||||
mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */
|
||||
}
|
||||
/* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
|
||||
else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) {
|
||||
mem_write32(DM_CM_INFO1, 0x00000000U);
|
||||
mem_write32(DM_CM_INFO2, 0x00000000U);
|
||||
mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */
|
||||
/* DM_CM_INFO2: DMA-ch1 error occured */
|
||||
if (( DM_CM_INFO2_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U)
|
||||
{
|
||||
mmc_drv_obj.dma_error_flag = TRUE;
|
||||
} else {
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
}
|
||||
mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */
|
||||
}
|
||||
|
||||
/* Response end */
|
||||
else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) {
|
||||
mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
}
|
||||
/* Access end */
|
||||
else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) {
|
||||
mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
} else {
|
||||
/* nothing to do. */
|
||||
}
|
||||
|
||||
return 0U;
|
||||
}
|
||||
|
||||
/** Data transfer function with PIO (Single sector).
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Called from interrupt service.
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] buff_address_virtual Dest/Src buffer address(virtual).
|
||||
* retval EMMC_SUCCESS successful.
|
||||
* retval EMMC_ERR_PARAM parameter error.
|
||||
* retval EMMC_ERR_STATE state error.
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual)
|
||||
{
|
||||
uint32_t length, i;
|
||||
uint64_t *bufPtrLL;
|
||||
|
||||
if (buff_address_virtual == NULL)
|
||||
{
|
||||
return EMMC_ERR_PARAM;
|
||||
}
|
||||
|
||||
if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U))
|
||||
{
|
||||
return EMMC_ERR_STATE;
|
||||
}
|
||||
|
||||
bufPtrLL = (uint64_t*)buff_address_virtual;
|
||||
length = mmc_drv_obj.remain_size;
|
||||
|
||||
/* data transefer */
|
||||
for (i = 0U; i < (length >> 3U); i++)
|
||||
{
|
||||
/* Write */
|
||||
if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE)
|
||||
{
|
||||
mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */
|
||||
}
|
||||
/* Read */
|
||||
else {
|
||||
*bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */
|
||||
}
|
||||
bufPtrLL++;
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
1592
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_mount.c
Normal file
1592
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_mount.c
Normal file
File diff suppressed because it is too large
Load Diff
94
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c
Normal file
94
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c
Normal file
@@ -0,0 +1,94 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc multi boot
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc multiboot.c
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_def.h"
|
||||
#include "emmc_multiboot.h"
|
||||
#include "types.h"
|
||||
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
uint32_t emmc_check_result(uint32_t result);
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
|
||||
uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize)
|
||||
{
|
||||
EMMC_ERROR_CODE result;
|
||||
uint32_t rtn_val = EMMC_DEV_ERR;
|
||||
|
||||
/* Partition select */
|
||||
result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition);
|
||||
|
||||
if (result == EMMC_SUCCESS)
|
||||
{
|
||||
result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE);
|
||||
}
|
||||
|
||||
/* EMMC_ERROR_CODE -> ROM_XX */
|
||||
rtn_val = emmc_check_result((uint32_t)result);
|
||||
|
||||
return rtn_val;
|
||||
}
|
||||
uint32_t emmc_check_result(uint32_t result)
|
||||
{
|
||||
uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION;
|
||||
|
||||
if (result == EMMC_SUCCESS)
|
||||
{
|
||||
ret = EMMC_DEV_OK;
|
||||
} else if (result == EMMC_ERR) {
|
||||
ret = EMMC_DEV_ERR;
|
||||
} else { /* other */
|
||||
ret = EMMC_DEV_ERR_HW;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
216
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c
Normal file
216
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c
Normal file
@@ -0,0 +1,216 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc read
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_read.c
|
||||
* - Version : 0.04
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 23.03.2022 0.02 Added header file inclusion
|
||||
* : 16.06.2022 0.03 Change log output
|
||||
* : 31.10.2022 0.04 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_registers.h"
|
||||
#include "emmc_def.h"
|
||||
#include "log.h"
|
||||
#include "mem_io.h"
|
||||
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL
|
||||
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
|
||||
|
||||
static inline uint32_t get_min_value(uint32_t a, uint32_t b)
|
||||
{
|
||||
uint32_t ret = a;
|
||||
|
||||
if(b < a)
|
||||
{
|
||||
ret = b;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
/** function of read sector
|
||||
*
|
||||
* This function always use block read.
|
||||
* Single block read is not used.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* MMC card is mounted.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] buff_address_virtual virtual address of read data buffer.
|
||||
* param[in] sector_number data address for MMC device (sector number).
|
||||
* param[in] count number of sector.
|
||||
* param[in] transfermode Mode of data transfer, DMA or not DMA.
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count,
|
||||
uint32_t feature_flags)
|
||||
{
|
||||
uint32_t trans_count;
|
||||
uint32_t remain;
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
HAL_MEMCARD_DATA_TRANSFER_MODE transfermode;
|
||||
|
||||
/* parameter check */
|
||||
if (count == 0U)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
|
||||
return EMMC_ERR_PARAM;
|
||||
}
|
||||
|
||||
/* state check */
|
||||
if (mmc_drv_obj.mount != TRUE)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE);
|
||||
return EMMC_ERR_STATE;
|
||||
}
|
||||
|
||||
/* DMA? */
|
||||
if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U)
|
||||
{
|
||||
transfermode = HAL_MEMCARD_DMA;
|
||||
} else {
|
||||
transfermode = HAL_MEMCARD_NOT_DMA;
|
||||
}
|
||||
|
||||
remain = count;
|
||||
while (remain != 0U)
|
||||
{
|
||||
trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX);
|
||||
result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count);
|
||||
sector_number += trans_count;
|
||||
remain -= trans_count;
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** multiple block read
|
||||
*
|
||||
* Multiple block read with pre-defined block count.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* MMC card is mounted.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in,out] buff_address_virtual virtual address of read data buffer.
|
||||
* param[in] sector_number data address for MMC device (sector number).
|
||||
* param[in] count number of sector. (0x1 - 0xffff)
|
||||
* param[in] transfer_mode Mode of data transfer, DMA or not DMA.
|
||||
*/
|
||||
static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count,
|
||||
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* parameter check */
|
||||
if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U)
|
||||
|| ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA)))
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM);
|
||||
return EMMC_ERR_PARAM;
|
||||
}
|
||||
|
||||
/* CMD23 */
|
||||
emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count);
|
||||
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
mem_write32(SD_SECCNT, count);
|
||||
mem_write32(SD_STOP, 0x00000100U);
|
||||
mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */
|
||||
|
||||
/* CMD18 */
|
||||
emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT,
|
||||
HAL_MEMCARD_READ, transfer_mode);
|
||||
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result; /* CMD18 error code */
|
||||
}
|
||||
|
||||
/* CMD13 */
|
||||
emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U);
|
||||
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
/* ready status check */
|
||||
if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY);
|
||||
return EMMC_ERR_CARD_BUSY;
|
||||
}
|
||||
|
||||
/* state check */
|
||||
if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN)
|
||||
{
|
||||
ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_STATE);
|
||||
return EMMC_ERR_CARD_STATE;
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
305
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c
Normal file
305
IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c
Normal file
@@ -0,0 +1,305 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : emmc utility
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file emmc_utility
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.02.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
|
||||
/* ************************ HEADER (INCLUDE) SECTION *********************** */
|
||||
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_registers.h"
|
||||
#include "emmc_def.h"
|
||||
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
|
||||
|
||||
#define BUSY_SIGNAL (1U << 10U)
|
||||
|
||||
static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] =
|
||||
{
|
||||
0x00000000U, /* CMD0 */
|
||||
0x00000701U, /* CMD1 */
|
||||
0x00000002U, /* CMD2 */
|
||||
0x00000003U, /* CMD3 */
|
||||
0x00000004U, /* CMD4 */
|
||||
0x00000505U, /* CMD5 */
|
||||
0x00000406U, /* CMD6 */
|
||||
0x00000007U, /* CMD7 */
|
||||
0x00001C08U, /* CMD8 */
|
||||
0x00000009U, /* CMD9 */
|
||||
0x0000000AU, /* CMD10 */
|
||||
0x00000000U, /* reserved */
|
||||
0x0000000CU, /* CMD12 */
|
||||
0x0000000DU, /* CMD13 */
|
||||
0x00001C0EU, /* CMD14 */
|
||||
0x0000000FU, /* CMD15 */
|
||||
0x00000010U, /* CMD16 */
|
||||
0x00000011U, /* CMD17 */
|
||||
0x00007C12U, /* CMD18 */
|
||||
0x00000C13U, /* CMD19 */
|
||||
0x00000000U,
|
||||
0x00001C15U, /* CMD21 */
|
||||
0x00000000U,
|
||||
0x00000017U, /* CMD23 */
|
||||
0x00000018U, /* CMD24 */
|
||||
0x00006C19U, /* CMD25 */
|
||||
0x00000C1AU, /* CMD26 */
|
||||
0x0000001BU, /* CMD27 */
|
||||
0x0000001CU, /* CMD28 */
|
||||
0x0000001DU, /* CMD29 */
|
||||
0x0000001EU, /* CMD30 */
|
||||
0x00001C1FU, /* CMD31 */
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000423U, /* CMD35 */
|
||||
0x00000424U, /* CMD36 */
|
||||
0x00000000U,
|
||||
0x00000026U, /* CMD38 */
|
||||
0x00000427U, /* CMD39 */
|
||||
0x00000428U, /* CMD40 : send cmd */
|
||||
0x00000000U,
|
||||
0x0000002AU, /* CMD42 */
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000C31U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00007C35U,
|
||||
0x00006C36U,
|
||||
0x00000037U, /* CMD55 */
|
||||
0x00000038U, /* CMD56 : Read */
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U,
|
||||
0x00000000U
|
||||
};
|
||||
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
|
||||
|
||||
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
||||
|
||||
/* ************************** FUNCTION PROTOTYPES ************************** */
|
||||
|
||||
/* ********************************* CODE ********************************** */
|
||||
|
||||
/** make non-transfer command data
|
||||
*
|
||||
* Response data buffer is automatically selected.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Clock to memory card IF is enabled.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* After this function is called, command can be executed.
|
||||
*
|
||||
* param[in] cmd command information.
|
||||
* param[in] arg command argument
|
||||
* return None.
|
||||
*/
|
||||
void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg)
|
||||
{
|
||||
/* command information */
|
||||
mmc_drv_obj.cmd_info.cmd = cmd;
|
||||
mmc_drv_obj.cmd_info.arg = arg;
|
||||
mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ;
|
||||
mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK];
|
||||
|
||||
/* clear data transfer information */
|
||||
mmc_drv_obj.trans_size = 0U;
|
||||
mmc_drv_obj.remain_size = 0U;
|
||||
mmc_drv_obj.buff_address_virtual = NULL;
|
||||
mmc_drv_obj.buff_address_physical = NULL;
|
||||
|
||||
/* response information */
|
||||
mmc_drv_obj.response_length = 6U;
|
||||
|
||||
switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK))
|
||||
{
|
||||
case HAL_MEMCARD_RESPONSE_NONE:
|
||||
mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
|
||||
mmc_drv_obj.response_length = 0U;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R1:
|
||||
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R1b:
|
||||
mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */
|
||||
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R2:
|
||||
mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
|
||||
mmc_drv_obj.response_length = 17U;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R3:
|
||||
mmc_drv_obj.response = &mmc_drv_obj.r3_ocr;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R4:
|
||||
mmc_drv_obj.response = &mmc_drv_obj.r4_resp;
|
||||
break;
|
||||
case HAL_MEMCARD_RESPONSE_R5:
|
||||
mmc_drv_obj.response = &mmc_drv_obj.r5_resp;
|
||||
break;
|
||||
default:
|
||||
mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/** Making command information for data transfer command.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* None.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* After this function is called, command can be executed.
|
||||
*
|
||||
* param[in] cmd command
|
||||
* param[in] arg command argument
|
||||
* param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address)
|
||||
* Client is responsible of allocation and deallocation of the buffer.
|
||||
* param[in] len transfer length in bytes
|
||||
* param[in] dir direction
|
||||
* param[in] transfer_mode Mode of data transfer, DMA or not DMA.
|
||||
* return None.
|
||||
*/
|
||||
void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */
|
||||
uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
|
||||
{
|
||||
emmc_make_nontrans_cmd(cmd, arg); /* update common information */
|
||||
|
||||
/* for data transfer command */
|
||||
mmc_drv_obj.cmd_info.dir = dir;
|
||||
mmc_drv_obj.buff_address_virtual = buff_address_virtual;
|
||||
mmc_drv_obj.buff_address_physical = buff_address_virtual;
|
||||
mmc_drv_obj.trans_size = len;
|
||||
mmc_drv_obj.remain_size = len;
|
||||
mmc_drv_obj.transfer_mode = transfer_mode;
|
||||
}
|
||||
|
||||
/** Send idle command.
|
||||
* Function execute CMD0.
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* Clock to MMC I/F enabled.
|
||||
*
|
||||
* - Post-conditions:<BR>
|
||||
* Card reset to idle or pre-idle state.
|
||||
*
|
||||
* param[in] arg CMD0 argument.
|
||||
* return error code
|
||||
*/
|
||||
EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg)
|
||||
{
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
/* initialize state */
|
||||
mmc_drv_obj.mount = FALSE;
|
||||
mmc_drv_obj.selected = FALSE;
|
||||
mmc_drv_obj.during_transfer = FALSE;
|
||||
mmc_drv_obj.during_dma_transfer = FALSE;
|
||||
mmc_drv_obj.dma_error_flag = FALSE;
|
||||
mmc_drv_obj.force_terminate = FALSE;
|
||||
mmc_drv_obj.state_machine_blocking = FALSE;
|
||||
|
||||
mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
|
||||
mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */
|
||||
mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE;
|
||||
|
||||
/* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */
|
||||
emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */
|
||||
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
/* change MMC clock(400KHz) */
|
||||
mmc_drv_obj.set_freq = MMC_400KHZ;
|
||||
result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq);
|
||||
if (result != EMMC_SUCCESS)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
return EMMC_SUCCESS;
|
||||
}
|
||||
|
||||
/** get bit field data for 16bytes data(CSD register).
|
||||
*
|
||||
* - Pre-conditions:<BR>
|
||||
* .
|
||||
* - Post-conditions:<BR>
|
||||
* .
|
||||
*
|
||||
* param[in] data 16bytes data.
|
||||
* param[in] top bit number(top). 128>top
|
||||
* param[in] bottom bit number(bottom). (0<=bottom<=top)
|
||||
* return bit field.
|
||||
*/
|
||||
uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
uint32_t index_top = (uint32_t)(15U - (top >> 3U));
|
||||
uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U));
|
||||
|
||||
if (index_top == index_bottom)
|
||||
{
|
||||
value = data[index_top];
|
||||
} else if ((index_top + 1U) == index_bottom) {
|
||||
value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]);
|
||||
} else if ((index_top + 2U) == index_bottom) {
|
||||
value = (uint32_t)(
|
||||
((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]);
|
||||
} else {
|
||||
value = (uint32_t)(
|
||||
((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U)
|
||||
| ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]);
|
||||
}
|
||||
|
||||
value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U));
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/* ******************************** END ************************************ */
|
||||
|
||||
0
IPL/Customer/Mobis/V4H_Cx_Loader/ip/gpio
Normal file
0
IPL/Customer/Mobis/V4H_Cx_Loader/ip/gpio
Normal file
102
IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c
Normal file
102
IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c
Normal file
@@ -0,0 +1,102 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : INTC handler function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file interrupt.c
|
||||
* - Version : 0.05
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 02.08.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
* : 15.12.2022 0.03 V4H interrupt support.
|
||||
* : 27.12.2022 0.04 Change argument of pabort_error.
|
||||
* : 21.08.2023 0.05 Add support for V4M.
|
||||
*****************************************************************************/
|
||||
#include "ip_control.h"
|
||||
#include "log.h"
|
||||
#include "gic.h"
|
||||
#include "swdt.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
void handler_fiq(void)
|
||||
{
|
||||
uint32_t intid = GIC_AcknowledgePending();
|
||||
if (intid == INTC_SPI_SWDT)
|
||||
{
|
||||
swdt_exec();
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("Invalid interrupt occurred.(%d)\n",intid);
|
||||
panic;
|
||||
}
|
||||
}
|
||||
/* End of function handler_fiq(void) */
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar)
|
||||
{
|
||||
|
||||
ERROR("Data abort.\n");
|
||||
ERROR(" Data abort occurrred address : 0x%x\n", occ_add);
|
||||
ERROR(" DFSR:0x%x DFAR:0x%x\n", dfsr, dfar);
|
||||
panic;
|
||||
|
||||
}
|
||||
/* End of function dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfare) */
|
||||
|
||||
void pabort_error(uint32_t ifsr, uint32_t ifar)
|
||||
{
|
||||
|
||||
ERROR("Prefetch abort.\n");
|
||||
ERROR(" IFSR:0x%x IFAR:0x%x\n", ifsr, ifar);
|
||||
panic;
|
||||
}
|
||||
/* End of function pabort_error(uint32_t ifsr, uint32_t ifar) */
|
||||
|
||||
void Undefined_error(uint32_t occ_add)
|
||||
{
|
||||
|
||||
ERROR("Undefined Instruction.\n");
|
||||
ERROR(" Undefined Instruction occurrred address : 0x%x\n", occ_add);
|
||||
panic;
|
||||
}
|
||||
/* End of function Undefined_error(uint32_t occ_add) */
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
void handler_error(uint32_t ex_type)
|
||||
{
|
||||
|
||||
ERROR("Unhandled exception occurred.\n");
|
||||
ERROR(" Exception type = 0x%x.\n", ex_type);
|
||||
panic;
|
||||
}
|
||||
/* End of function handler_error(uint32_t ex_type) */
|
||||
100
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c
Normal file
100
IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c
Normal file
@@ -0,0 +1,100 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : IP's control function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file ip_control.c
|
||||
* - Version : 0.08
|
||||
* @brief Initial setting controller.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 30.11.2021 0.01 First Release
|
||||
* : 18.01.2022 0.02 Changed log output
|
||||
* Supported Generic Timer
|
||||
* : 22.03.2022 0.03 Removed unnecessary header file inclusions
|
||||
* Removed unnecessary functions
|
||||
* : 10.05.2022 0.04 Added function return value judgment
|
||||
* : 16.06.2022 0.05 Change log output
|
||||
* : 02.08.2022 0.06 Added SWDT and GIC
|
||||
* : 31.10.2022 0.07 License notation change.
|
||||
* : 04.09.2023 0.08 Add C4 power domain setting.
|
||||
* : 13.10.2023 0.09 Moved C4 power domain setting to ICUMX IPL.
|
||||
*****************************************************************************/
|
||||
#include <scif.h>
|
||||
#include <ip_control.h>
|
||||
#include <emmc_boot.h>
|
||||
#include <emmc_def.h>
|
||||
#include <timer.h>
|
||||
#include <log.h>
|
||||
#include "gic.h"
|
||||
#include "swdt.h"
|
||||
#if (1 == (MEASURE_TIME))
|
||||
#include <scmt.h>
|
||||
#include <scmt_checkpoint.h>
|
||||
#else
|
||||
#define scmt_wait_ticks(x)
|
||||
#define store_time_checkpoint(x,y)
|
||||
#endif
|
||||
|
||||
void ip_init(void)
|
||||
{
|
||||
scif_init();
|
||||
generic_timer_init();
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
Interrupt_Config();
|
||||
Interrupt_Enable(INTC_SPI_SWDT);
|
||||
swdt_init();
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
#ifndef MOBIS_PRK3
|
||||
emmc_initialize();
|
||||
store_time_checkpoint("emmc_initialize", 0);
|
||||
#endif
|
||||
}
|
||||
/* End of function ip_init(void) */
|
||||
|
||||
void ip_release(void)
|
||||
{
|
||||
#if (BL2_LOAD_ENABLE == BL2_DISABLE)
|
||||
EMMC_ERROR_CODE result = EMMC_ERR;
|
||||
|
||||
result = emmc_terminate();
|
||||
if(EMMC_SUCCESS != result)
|
||||
{
|
||||
ERROR("ip_release error (emmc_terminate).\n");
|
||||
panic;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
swdt_release();
|
||||
Interrupt_Disable(INTC_SPI_SWDT);
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
}
|
||||
/* End of function ip_release(void) */
|
||||
553
IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c
Normal file
553
IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c
Normal file
@@ -0,0 +1,553 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : QoS initialize function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file qos.c
|
||||
* - Version : 0.14
|
||||
* @brief Initial setting process of QoS.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 28.07.2021 0.01 First Release
|
||||
* : 23.05.2022 0.02 Integration of S4 and V4H
|
||||
* Update QoS setting rev.0.02 (for S4)
|
||||
* Update QoS setting rev.0.03 (for V4H)
|
||||
* : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579)
|
||||
* : 19.04.2023 0.04 Update the setting version from v6.1 to v7.0(for V4H).
|
||||
* : 22.05.2023 0.05 Update the setting version from v7.0 to v7.1.1(for V4H).
|
||||
* : 22.05.2023 0.06 Update the setting version from v7.1.1 to v8.0.0(for V4H).
|
||||
* : 08.06.2023 0.07 Update the setting version from v8.0.0 to v8.0.1(for V4H).
|
||||
* : 15.06.2023 0.08 Update the setting version from v8.0.1 to v8.0.2(for V4H).
|
||||
* : 21.08.2023 0.09 Add support for V4M.
|
||||
* : 20.09.2023 0.10 Update the setting version from v9.0.1 to v10.0.0(for V4M).
|
||||
* : 20.09.2023 0.11 Update the setting version from v10.0.0 to v10.1.0(for V4H).
|
||||
* : 11.10.2023 0.12 Update the setting version from v10.1.0 to v10.2.1(for V4H/V4M).
|
||||
* : 17.01.2024 0.13 Update the setting version from v10.1.0 to v11.0.0(for V4H/V4M).
|
||||
* : 05.04.2024 0.14 Update the setting version from v11.0.0 to v12.0.0(for V4H/V4M).
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined(__RH850G3K__)
|
||||
#include <log.h>
|
||||
#include <remap_register.h>
|
||||
#include <remap.h>
|
||||
#else
|
||||
#include <log.h>
|
||||
#include <rcar_register.h>
|
||||
#endif
|
||||
#include <qos.h>
|
||||
#include <mem_io.h>
|
||||
#include <cnf_tbl.h>
|
||||
#include <rcar_def.h>
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define RCAR_QOS_VERSION "base_v6.1"
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#define RCAR_QOS_VERSION "v12.0.0"
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
#define RCAR_DRAM_SPLIT_DISABLE (0U)
|
||||
#define RCAR_DRAM_SPLIT_ENABLE (1U)
|
||||
#define RCAR_REWT_TRAINING_DISABLE (0U)
|
||||
#define RCAR_REWT_TRAINING_ENABLE (1U)
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define AXMM_BASE (BASE_AXMM_ADDR)
|
||||
#else
|
||||
#define AXMM_BASE (0xE6780000U)
|
||||
#endif
|
||||
#define AXMM_MMCR (AXMM_BASE + 0x4300U)
|
||||
#define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U)
|
||||
#define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU)
|
||||
#define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U)
|
||||
#define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U)
|
||||
#define AXMM_TR3CR (AXMM_BASE + 0x5100CU)
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#if defined(__RH850G3K__)
|
||||
#define DBSC_BASE (BASE_DBSC_ADDR)
|
||||
#else
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#endif
|
||||
|
||||
#define DBSC_CH_NUM (1U) /* Number of DBSCx */
|
||||
#define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/
|
||||
#define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/
|
||||
|
||||
#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U)
|
||||
#define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#if defined(__RH850G3K__)
|
||||
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U)
|
||||
#define DBSC_A_BASE (BASE_DBSC_ADDR)
|
||||
#else
|
||||
#define DBSC_D_BASE (0xE67A4000U)
|
||||
#define DBSC_A_BASE (0xE6790000U)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
#define DBSC_CH_NUM (2U) /* ch number of DBSCx */
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
#define DBSC_CH_NUM (1U) /* ch number of DBSCx */
|
||||
#endif
|
||||
|
||||
#define DBSC_A_CH_OFFSET (0x8000U)
|
||||
#define DBSC_D_CH_OFFSET (0x4000U)
|
||||
|
||||
#define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U)
|
||||
#define DBSC_SYSCNT1 (DBSC_A_BASE + 0x0104U)
|
||||
#define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U)
|
||||
#define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U)
|
||||
#define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU)
|
||||
#define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U)
|
||||
|
||||
#define AXMM_TR0CR0 (AXMM_BASE + 0x51000U)
|
||||
#define AXMM_TR1CR0 (AXMM_BASE + 0x51004U)
|
||||
#define AXMM_TR2CR0 (AXMM_BASE + 0x51008U)
|
||||
#define AXMM_TR3CR0 (AXMM_BASE + 0x5100CU)
|
||||
#define AXMM_TR0CR1 (AXMM_BASE + 0x51100U)
|
||||
#define AXMM_TR1CR1 (AXMM_BASE + 0x51104U)
|
||||
#define AXMM_TR2CR1 (AXMM_BASE + 0x51108U)
|
||||
#define AXMM_TR3CR1 (AXMM_BASE + 0x5110CU)
|
||||
#define AXMM_TR0CR2 (AXMM_BASE + 0x51200U)
|
||||
#define AXMM_TR1CR2 (AXMM_BASE + 0x51204U)
|
||||
#define AXMM_TR2CR2 (AXMM_BASE + 0x51208U)
|
||||
#define AXMM_TR3CR2 (AXMM_BASE + 0x5120CU)
|
||||
#define DBSC_FCPRSCTRL (DBSC_A_BASE + 0x0110U)
|
||||
#define ACTEXT_RT0_R (0xFFC50800U)
|
||||
#define ACTEXT_RT0_W (0xFFC51800U)
|
||||
#define ACTEXT_IR0_R (0xFF890800U)
|
||||
#define ACTEXT_IR0_W (0xFF891800U)
|
||||
#define ACTEXT_IR1_R (0xFF892800U)
|
||||
#define ACTEXT_IR1_W (0xFF893800U)
|
||||
#define SI0_RW_MAX (0xF1201110U)
|
||||
#define SI1_RW_MAX (0xF1202110U)
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#define QOS_BASE (BASE_QOS_ADDR)
|
||||
#else
|
||||
#define QOS_BASE (0xE67E0000U)
|
||||
#endif
|
||||
#define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U)
|
||||
#define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U)
|
||||
#define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U)
|
||||
#define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U)
|
||||
#define QOS_SL_INIT (QOS_BASE + 0x00008000U)
|
||||
#define QOS_REF_ARS (QOS_BASE + 0x00008004U)
|
||||
#define QOS_STATQC (QOS_BASE + 0x00008008U)
|
||||
#define QOS_REF_ENBL (QOS_BASE + 0x00008044U)
|
||||
#define QOS_BWG (QOS_BASE + 0x0000804CU)
|
||||
#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U)
|
||||
#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U)
|
||||
#define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U)
|
||||
#define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U)
|
||||
#define QOSWT_WTEN (QOS_BASE + 0x00008030U)
|
||||
#define QOSWT_WTREF (QOS_BASE + 0x00008034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE + 0x00008038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU)
|
||||
#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
#define QOS_RAS (QOS_BASE + 0x00010000U)
|
||||
#define QOS_RAEN (QOS_BASE + 0x00010018U)
|
||||
#define QOS_DANN_LOW (QOS_BASE + 0x00010030U)
|
||||
#define QOS_DANN_HIGH (QOS_BASE + 0x00010034U)
|
||||
#define QOS_DANT (QOS_BASE + 0x00010038U)
|
||||
#define QOS_EMS_LOW (QOS_BASE + 0x00010040U)
|
||||
#define QOS_EMS_HIGH (QOS_BASE + 0x00010044U)
|
||||
#define QOS_FSS (QOS_BASE + 0x00010048U)
|
||||
#define QOS_INSFC (QOS_BASE + 0x00010050U)
|
||||
#define QOS_EARLYR (QOS_BASE + 0x00010060U)
|
||||
#define QOS_RACNT0 (QOS_BASE + 0x00010080U)
|
||||
#define QOS_STATGEN0 (QOS_BASE + 0x00010088U)
|
||||
|
||||
#define CCI_BASE (BASE_CCI_ADDR)
|
||||
#define CCIQOS00 (CCI_BASE + 0xC020U)
|
||||
#define CCIQOS01 (CCI_BASE + 0xC024U)
|
||||
#define CCIQOS10 (CCI_BASE + 0xD000U)
|
||||
#define CCIQOS11 (CCI_BASE + 0xD004U)
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#define CCIQOS12 (CCI_BASE + 0xD008U)
|
||||
#define CCIQOS13 (CCI_BASE + 0xD00CU)
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++)
|
||||
{
|
||||
/* DBSC CAM, Scheduling Setting */
|
||||
mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U);
|
||||
mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U);
|
||||
mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00048218U); /* dbcam0cnf1 */
|
||||
#if ((ECC_ENABLE == 1) && (RCAR_LSI == RCAR_V4H))
|
||||
/* For WA for DBSC5 Hang5 issue. */
|
||||
if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
|
||||
{
|
||||
mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000002C4U); /* dbcam0cnf2 */
|
||||
}
|
||||
else
|
||||
{
|
||||
mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */
|
||||
}
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */
|
||||
#else
|
||||
mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */
|
||||
#endif
|
||||
mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
#if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1))
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */
|
||||
#else
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U);
|
||||
#endif
|
||||
#elif (RCAR_LSI == RCAR_V4H)
|
||||
#if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1))
|
||||
if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
|
||||
{
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */
|
||||
}
|
||||
else if((mem_read32(PRR) & PRR_CUT_MASK) == PRR_PRODUCT_22)
|
||||
{
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U);
|
||||
}
|
||||
else
|
||||
{
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
|
||||
}
|
||||
#elif ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 0))
|
||||
if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
|
||||
{
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */
|
||||
}
|
||||
else
|
||||
{
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
|
||||
}
|
||||
#else
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
|
||||
#endif
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
# if (ECC_ENABLE == 1)
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U);
|
||||
#else
|
||||
mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
|
||||
# endif
|
||||
#endif
|
||||
|
||||
mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */
|
||||
mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */
|
||||
mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */
|
||||
mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU);
|
||||
|
||||
#if (((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) || (RCAR_LSI == RCAR_V4M))
|
||||
mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */
|
||||
#else
|
||||
mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */
|
||||
#endif
|
||||
|
||||
/* DBSC QoS Setting */
|
||||
mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU);
|
||||
mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U);
|
||||
mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
|
||||
mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
|
||||
mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U);
|
||||
mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
|
||||
mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U);
|
||||
mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
|
||||
mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
|
||||
mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U);
|
||||
mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
|
||||
mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
|
||||
mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U);
|
||||
mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U);
|
||||
mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U);
|
||||
mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U);
|
||||
mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U);
|
||||
mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U);
|
||||
mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
|
||||
mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
|
||||
mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U);
|
||||
mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U);
|
||||
mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
|
||||
mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U);
|
||||
mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U);
|
||||
mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U);
|
||||
mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U);
|
||||
mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U);
|
||||
if (loop == 0) /* Target register is only DBSC0 side. */
|
||||
{
|
||||
mem_write32(DBSC_FCPRSCTRL, 0x00000001U);
|
||||
}
|
||||
mem_write32((DBSC_SYSCNT1 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U);
|
||||
mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U);
|
||||
mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U);
|
||||
}
|
||||
}
|
||||
/* End of function dbsc_setting(void) */
|
||||
|
||||
void qos_init(void)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
/* Setting the register of DBSC4 for QoS initialize */
|
||||
dbsc_setting();
|
||||
|
||||
NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION);
|
||||
NOTICE("DRAM refresh interval 1.91 usec\n");
|
||||
|
||||
#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
#if (RCAR_LSI == RCAR_S4)
|
||||
/* Resource Alloc setting */
|
||||
mem_write32(QOS_RAS, 0x00000028U);
|
||||
mem_write32(QOS_DANN_LOW, 0x02020201U);
|
||||
mem_write32(QOS_DANN_HIGH, 0x04040200U);
|
||||
mem_write32(QOS_DANT, 0x00181004U);
|
||||
mem_write32(QOS_EMS_LOW, 0x00000000U);
|
||||
mem_write32(QOS_EMS_HIGH, 0x00000000U);
|
||||
mem_write32(QOS_FSS, 0x0000000AU);
|
||||
mem_write32(QOS_INSFC, 0x030F0001U);
|
||||
mem_write32(QOS_EARLYR, 0x00000000U);
|
||||
mem_write32(QOS_RACNT0, 0x00050003U);
|
||||
mem_write32(QOS_STATGEN0, 0x00000000U);
|
||||
|
||||
/* QoS MSTAT setting */
|
||||
mem_write32(QOS_SL_INIT, 0x00050100U);
|
||||
mem_write32(QOS_REF_ARS, 0x00FB0000U);
|
||||
mem_write32(QOS_REF_ENBL, 0x00000012U);
|
||||
mem_write32(QOS_BWG, 0x00000002U);
|
||||
mem_write32(AXMM_MMCR, 0x00010000U);
|
||||
|
||||
mem_write32(CCIQOS00, 0x08000000);
|
||||
mem_write32(CCIQOS01, 0x08000000);
|
||||
mem_write32(CCIQOS10, 0x00000001);
|
||||
mem_write32(CCIQOS11, 0x00000001);
|
||||
mem_write32(CCIQOS12, 0x00000001);
|
||||
mem_write32(CCIQOS13, 0x00000001);
|
||||
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE)
|
||||
/* Address Split 2ch */
|
||||
mem_write32(AXMM_ADSPLCR0, 0x00000000U);
|
||||
mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU);
|
||||
mem_write32(AXMM_ADSPLCR2, 0x00000000U);
|
||||
mem_write32(AXMM_ADSPLCR3, 0x00000000U);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
mem_write32(CCIQOS00, 0x08000000);
|
||||
mem_write32(CCIQOS01, 0x08000000);
|
||||
if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20)
|
||||
{
|
||||
mem_write32(CCIQOS10, 0x00000001U);
|
||||
mem_write32(CCIQOS11, 0x00000001U);
|
||||
}
|
||||
else
|
||||
{
|
||||
mem_write32(CCIQOS10, 0x00000000U);
|
||||
mem_write32(CCIQOS11, 0x00000000U);
|
||||
}
|
||||
#endif
|
||||
/* Resource Alloc setting */
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
mem_write32(QOS_RAS, 0x00000048U);
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
mem_write32(QOS_RAS, 0x00000030U);
|
||||
#endif
|
||||
mem_write32(QOS_DANN_LOW, 0x02020201U);
|
||||
mem_write32(QOS_DANN_HIGH, 0x04040200U);
|
||||
mem_write32(QOS_DANT, 0x00181008U);
|
||||
mem_write32(QOS_EMS_LOW, 0x00000000U);
|
||||
mem_write32(QOS_EMS_HIGH, 0x00000000U);
|
||||
mem_write32(QOS_FSS, 0x0000000AU);
|
||||
mem_write32(QOS_INSFC, 0x030F0001U);
|
||||
mem_write32(QOS_EARLYR, 0x00000000U);
|
||||
mem_write32(QOS_RACNT0, 0x00050003U);
|
||||
mem_write32(QOS_STATGEN0, 0x00000000U);
|
||||
|
||||
/* QoS MSTAT setting */
|
||||
mem_write32(QOS_SL_INIT, 0x00070120U);
|
||||
mem_write32(QOS_REF_ARS, 0x011B0000U);
|
||||
mem_write32(QOS_REF_ENBL, 0x00000012U);
|
||||
mem_write32(QOS_BWG, 0x00000004U);
|
||||
#if ((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1))
|
||||
if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21)
|
||||
{
|
||||
mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */
|
||||
}
|
||||
else
|
||||
{
|
||||
mem_write32(AXMM_MMCR, 0x00010000U); /* OTLINT-5579: V4H DBSC WA3 */
|
||||
}
|
||||
#elif (RCAR_LSI == RCAR_V4M)
|
||||
mem_write32(AXMM_MMCR, 0x00010000U);
|
||||
#else
|
||||
mem_write32(AXMM_MMCR, 0x00010000U);
|
||||
#endif
|
||||
mem_write32(ACTEXT_RT0_R, 0x00000003U);
|
||||
mem_write32(ACTEXT_RT0_W, 0x00000003U);
|
||||
mem_write32(ACTEXT_IR0_R, 0x00000003U);
|
||||
mem_write32(ACTEXT_IR0_W, 0x00000003U);
|
||||
mem_write32(ACTEXT_IR1_R, 0x00000003U);
|
||||
mem_write32(ACTEXT_IR1_W, 0x00000003U);
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
mem_write32(AXMM_TR3CR, 0x00010000U);
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4M)
|
||||
mem_write32(AXMM_TR0CR0, 0x00000000U);
|
||||
mem_write32(AXMM_TR1CR0, 0x00000000U);
|
||||
mem_write32(AXMM_TR2CR0, 0x00000000U);
|
||||
mem_write32(AXMM_TR3CR0, 0x00000000U);
|
||||
mem_write32(AXMM_TR0CR1, 0x70707070U);
|
||||
mem_write32(AXMM_TR1CR1, 0x70707070U);
|
||||
mem_write32(AXMM_TR2CR1, 0x70707070U);
|
||||
mem_write32(AXMM_TR3CR1, 0x70707070U);
|
||||
mem_write32(AXMM_TR0CR2, 0x70707070U);
|
||||
mem_write32(AXMM_TR1CR2, 0x70707070U);
|
||||
mem_write32(AXMM_TR2CR2, 0x70707070U);
|
||||
mem_write32(AXMM_TR3CR2, 0x70707070U);
|
||||
#endif
|
||||
|
||||
|
||||
#if (RCAR_LSI == RCAR_V4H)
|
||||
if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20)
|
||||
{
|
||||
/* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */
|
||||
mem_write32(SI0_RW_MAX, 0x00000038U);
|
||||
mem_write32(SI1_RW_MAX, 0x00000038U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_LSI == RCAR_S4 */
|
||||
|
||||
for (i = 0U; i < QOS_TBL_MAX; i++)
|
||||
{
|
||||
mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix);
|
||||
mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix);
|
||||
mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be);
|
||||
mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be);
|
||||
}
|
||||
|
||||
#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < QOS_TBL_MAX; i++)
|
||||
{
|
||||
mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix);
|
||||
mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix);
|
||||
mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be);
|
||||
mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be);
|
||||
}
|
||||
#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
/* QoS SRAM setting */
|
||||
mem_write32(QOS_RAEN, 0x00000001U);
|
||||
#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
mem_write32(QOSWT_WTREF, 0x02080208U);
|
||||
mem_write32(QOSWT_WTSET0, 0x0D90050FU);
|
||||
mem_write32(QOSWT_WTSET1, 0x0D90050FU);
|
||||
mem_write32(QOSWT_WTEN, 0x00000001U);
|
||||
#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
mem_write32(QOS_STATQC, 0x00000101U);
|
||||
}
|
||||
/* End of function qos_init(void) */
|
||||
81
IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c
Normal file
81
IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c
Normal file
@@ -0,0 +1,81 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : RT-VRAM driver
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file RTVRAM.c
|
||||
* - Version : 0.03
|
||||
* @brief RT-VRAM driver.
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 17.11.2021 0.01 First Release
|
||||
* : 03.12.2021 0.02 remove Cache flush.
|
||||
* : 06.01.2022 0.03 Static analysis support
|
||||
*****************************************************************************/
|
||||
|
||||
#if defined(__RH850G3K__)
|
||||
#include <ram_def.h>
|
||||
#else
|
||||
#include <rcar_register.h>
|
||||
#endif
|
||||
#include <rtvram.h>
|
||||
#include <mem_io.h>
|
||||
#include <log.h>
|
||||
#include <inline_asm.h>
|
||||
|
||||
#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1U << 8U)
|
||||
#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6U << 0U)
|
||||
|
||||
#define RTVRAM_EXT_MODE_EXT (1U << 0U)
|
||||
|
||||
#define RTVRAM_VBUF_NUM (7U)
|
||||
|
||||
#define RTVRAM_EXTEND_ENABLE (1U)
|
||||
|
||||
void rtvram_extendmode(void)
|
||||
{
|
||||
#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE)
|
||||
uint32_t reg;
|
||||
uint32_t loop;
|
||||
|
||||
/* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
|
||||
for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++)
|
||||
{
|
||||
mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U));
|
||||
}
|
||||
|
||||
reg = mem_read32(RTVRAM_VBUF_CFG);
|
||||
reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); /* Cache Mode: 8-way, VBF size: 28M */
|
||||
mem_write32(RTVRAM_VBUF_CFG, reg);
|
||||
|
||||
/* Set at the end */
|
||||
mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */
|
||||
|
||||
syncm();
|
||||
#endif
|
||||
}
|
||||
/* End of function rtvram_extendmode(void) */
|
||||
123
IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c
Normal file
123
IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c
Normal file
@@ -0,0 +1,123 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* DESCRIPTION : Watchdog Timer function
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* @file swdt.c
|
||||
* - Version : 0.02
|
||||
* @brief
|
||||
* .
|
||||
*****************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 12.08.2022 0.01 First Release
|
||||
* : 31.10.2022 0.02 License notation change.
|
||||
*****************************************************************************/
|
||||
#include "mem_io.h"
|
||||
#include "rcar_def.h"
|
||||
#include "rcar_register.h"
|
||||
#include "swdt.h"
|
||||
#include "gic.h"
|
||||
#include "log.h"
|
||||
#include "ip_control.h"
|
||||
|
||||
void swdt_init(void)
|
||||
{
|
||||
uint32_t sr;
|
||||
uint32_t reg;
|
||||
uint32_t val;
|
||||
uint32_t chk_data;
|
||||
|
||||
/* 1. Clear the TME bit in SWTCSRA to 0 to temporarily stop counting. */
|
||||
reg = mem_read32(SWDT_WTCSRA) & WTCSRA_TME;
|
||||
if (WTCSRA_TME == reg)
|
||||
{
|
||||
mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
|
||||
}
|
||||
|
||||
/* 2.Write the set value in SWTCNT */
|
||||
/* OSCCLK check */
|
||||
reg = mem_read32(RST_MODEMR0);
|
||||
chk_data = reg & CHECK_MD13_MD14;
|
||||
|
||||
val = WTCNT_UPPER_BYTE;
|
||||
|
||||
if (MD14_MD13_TYPE_0 == chk_data)
|
||||
{
|
||||
val |= SWDTCNT_133330HZ;
|
||||
}
|
||||
else if(MD14_MD13_TYPE_1 == chk_data)
|
||||
{
|
||||
val |= SWDTCNT_131570HZ;
|
||||
}
|
||||
else if(MD14_MD13_TYPE_3 == chk_data)
|
||||
{
|
||||
val |= SWDTCNT_131570HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("MODEMR ERROR value = 0x%x\n", chk_data);
|
||||
panic;
|
||||
}
|
||||
|
||||
mem_write32(SWDT_WTCNT, val);
|
||||
|
||||
/* 3. Clear the bit4(WOVF) in SWTCSRA to 0. */
|
||||
mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | WTCSRA_WOVFE | WTCSRA_CKS0_OSCCLK);
|
||||
|
||||
/* 5.Confirm that SWTCSRA.WRFLG becomes 0.*/
|
||||
while (true)
|
||||
{
|
||||
if ((mem_read32(SWDT_WTCSRA) & WTCSRA_WRFLG) == 0U)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* 6. Start the counting by setting the TME bit in SWTCSRA to 1. */
|
||||
sr = mem_read32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
|
||||
|
||||
mem_write32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | WTCSRA_TME));
|
||||
|
||||
}
|
||||
/* End of function swdt_init(void) */
|
||||
|
||||
void swdt_release(void)
|
||||
{
|
||||
|
||||
mem_write32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
|
||||
mem_write32(SWDT_WTCNT, WTCNT_INIT_DATA);
|
||||
}
|
||||
/* End of function swdt_release(void) */
|
||||
|
||||
void swdt_exec(void)
|
||||
{
|
||||
ERROR("System Watchdog Timer overflow.\n");
|
||||
panic;
|
||||
}
|
||||
/* End of function swdt_exec(void) */
|
||||
|
||||
Reference in New Issue
Block a user