add IPL
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157
IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h
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157
IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : rcar register header
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******************************************************************************/
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/******************************************************************************
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* @file rcar_register.h
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* - Version : 0.07
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 02.02.2022 0.01 First Release
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* : 17.02.2022 0.02 Add APMU
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* Support AArch32
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* : 09.05.2022 0.03 Changed to processing for each device
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* : 24.10.2022 0.04 Add supports for HS200/400
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* : 31.10.2022 0.05 License notation change.
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* : 07.11.2022 0.06 Added QOS and RTVRAM related registers.
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* : 21.08.2023 0.07 Add support for V4M.
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*****************************************************************************/
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#ifndef RCAR_REGISTER_H_
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#define RCAR_REGISTER_H_
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#include <stdint.h>
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#define BASE_ADDR_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET */
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#define BASE_ADDR_RPC (0xEE200000U) /* RPC */
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#if (RCAR_LSI == RCAR_S4)
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#define BASE_ADDR_SCIF (0xE6C00000U) /* SCIF */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define BASE_ADDR_SCIF (0xE6E00000U) /* SCIF */
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#endif /* RCAR_LSI == RCAR_S4 */
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#define BASE_ADDR_MMC (0xEE000000U) /* MMC */
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#define BASE_ADDR_HSCIF (0xE6400000U) /* HSCIF */
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#define BASE_AP_CORE_ADDR (0xE6280000U) /* ECM */
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/* Base address offset of each register */
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/* CPGA */
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#define OFFSET_CPGA (0x00150000U)
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/* RESET */
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#define OFFSET_RESET (0x00160000U)
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/* APMU */
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#define OFFSET_APMU (0x00170000U)
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/*RPC*/
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#define OFFSET_RPC (0x00000000U)
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/*SCIF*/
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#if (RCAR_LSI == RCAR_S4)
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#define OFFSET_SCIF3 (0x00050000U)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define OFFSET_SCIF0 (0x00060000U)
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#endif /* RCAR_LSI == RCAR_S4 */
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/* SDHI2/MMC0 */
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#define OFFSET_SDHI (0x00140000U)
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/* HSCIF */
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#define OFFSET_HSCIF0 (0x00140000U)
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/* PFC0 */
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#define OFFSET_PFC0 (0x00050000U)
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/* PFC1 */
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#if (RCAR_LSI == RCAR_S4)
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#define OFFSET_PFC1 (0x00051000U)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define OFFSET_PFC1 (0x00058000U)
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#endif /* RCAR_LSI == RCAR_S4 */
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/* Port Group */
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#define OFFSET_PORTGR (0x00000800U)
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/* CPGWPR */
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#define OFFSET_CPG_CPGWPR (0x00000000U)
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/* SD0CKCR */
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#define OFFSET_CPG_SD0CKCR (0x00000870U)
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/* PLL2CR0 */
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#define OFFSET_CPG_PLL2CR0 (0x00000834U)
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/* PLLECR */
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#define OFFSET_CPG_PLLECR (0x00000820U)
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/* QOS */
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#define ICU_CC (0xE6600000U) /* CC63S,I2C,AXMM,QoS */
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#define ICU_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */
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#define BASE_CCI_ADDR (ICU_CC + ICU_OFFSET_CCI)
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/* RTVRAM */
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#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL)
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#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */
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#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
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#define BASE_RESET_ADDR (BASE_ADDR_PFC + OFFSET_RESET)
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#define BASE_APMU_ADDR (BASE_ADDR_PFC + OFFSET_APMU)
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#define BASE_RPC_ADDR (BASE_ADDR_RPC + OFFSET_RPC)
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#if (RCAR_LSI == RCAR_S4)
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#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF3)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF0)
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#endif /* RCAR_LSI == RCAR_S4 */
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#define BASE_MMC0_ADDR (BASE_ADDR_MMC + OFFSET_SDHI)
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#define BASE_HSCIF_ADDR (BASE_ADDR_HSCIF + OFFSET_HSCIF0)
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#define BASE_PFC0_ADDR (BASE_ADDR_PFC + OFFSET_PFC0)
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#define BASE_PFC1_ADDR (BASE_ADDR_PFC + OFFSET_PFC1)
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#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA)
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#define PFC_GP1_BASE (BASE_PFC0_ADDR + OFFSET_PORTGR)
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#define PFC_GP3_BASE (BASE_PFC1_ADDR + OFFSET_PORTGR)
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#define CPG_CPGWPR (BASE_CPG_ADDR + OFFSET_CPG_CPGWPR)
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#define CPG_PLL2CR0 (BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0)
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#define CPG_PLLECR (BASE_CPG_ADDR + OFFSET_CPG_PLLECR)
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#define CPG_SD0CKCR (BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR)
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#define CPG_FRQCRC0 (BASE_CPG_ADDR + OFFSET_CPG_FRQCRC0 0x0808U)
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#define OFFSET_PFC_DRV0CTRL (0x00000080U)
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#define OFFSET_PFC_DRV1CTRL (0x00000084U)
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#define OFFSET_PFC_DRV2CTRL (0x00000088U)
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#if (RCAR_LSI == RCAR_S4)
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#define PFC_DRVCTRL1_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register0 PortGroup 3
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#define PFC_DRVCTRL2_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL) // R/W 32 POC control register1 PortGroup 3
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define PFC_DRVCTRL0_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL) // R/W 32 POC control register0 PortGroup 3
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#define PFC_DRVCTRL1_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register1 PortGroup 3
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#endif /* RCAR_LSI == RCAR_S4 */
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#define PFC_PMMR(addr) ((addr) & (uintptr_t)0xFFFFF800U) // R/W 32 LSI Multiplexed Pin Setting Mask Register
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#endif /* RCAR_REGISTER_H_ */
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