add IPL
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312
IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h
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312
IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : emmc std header
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******************************************************************************/
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/******************************************************************************
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* @file emmc_std.h
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* - Version : 0.03
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 02.02.2022 0.01 First Release
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* : 24.10.2022 0.02 Add supports for HS200/400
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* : 31.10.2022 0.03 License notation change.
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*****************************************************************************/
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#ifndef EMMC_STD_H__
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#define EMMC_STD_H__
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/* ************************ HEADER (INCLUDE) SECTION *********************** */
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#include "emmc_hal.h"
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#include "emmc_registers.h"
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/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
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/*CSD register Macros */
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#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122))
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#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96))
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/* for sector access */
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#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
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#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U)
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#define EMMC_SECTOR_SIZE (512U)
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#define EMMC_BLOCK_LENGTH (512U)
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#define EMMC_BLOCK_LENGTH_DW (128U)
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/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
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typedef enum
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{
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EMMC_ERR = 0U, /**< unknown error */
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EMMC_SUCCESS , /**< OK */
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EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */
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EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */
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EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */
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EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */
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EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */
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EMMC_ERR_CMD_CRC , /**< command CRC error */
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EMMC_ERR_DATA_CRC , /**< data CRC error */
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EMMC_ERR_PARAM , /**< parameter error */
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EMMC_ERR_RESPONSE , /**< response error */
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EMMC_ERR_RESPONSE_BUSY , /**< response busy error */
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EMMC_ERR_TRANSFER , /**< data transfer error */
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EMMC_ERR_READ_SECTOR , /**< read sector error */
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EMMC_ERR_WRITE_SECTOR , /**< write sector error */
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EMMC_ERR_STATE , /**< state error */
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EMMC_ERR_TIMEOUT , /**< timeout error */
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EMMC_ERR_ILLEGAL_CARD , /**< illegal card */
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EMMC_ERR_CARD_BUSY , /**< Busy state */
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EMMC_ERR_CARD_STATE , /**< card state error */
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EMMC_ERR_SET_TRACE , /**< trace information error */
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EMMC_ERR_FROM_TIMER , /**< Timer error */
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EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */
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EMMC_ERR_CARD_POWER , /**< card power fail */
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EMMC_ERR_ERASE_SECTOR , /**< erase sector error */
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EMMC_ERR_INFO2 , /**< exec cmd error info2 */
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RCAR_ERR /**< Error judged by R-Car register */
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} EMMC_ERROR_CODE;
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/* Error code judged by R-car register or eMMC return*/
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#define EMMC_TUNING_FAIL (0U) /* Fail judged by eMMC return*/
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#define TUNING_SUCCESS (1U) /* Tuning success */
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#define RCAR_TUNING_FAIL (2U) /* Fail judged by R-car register*/
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/* Response */
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/** R1 */
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#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */
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#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
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#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */
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#define EMMC_R1_READY (0x00000100U) /* bit8 */
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#define EMMC_R1_STATE_SHIFT (9U)
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/** R4 */
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#define EMMC_R4_STATUS (0x00008000U)
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/** CSD */
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#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */
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#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */
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#define EMMC_TRANSPEED_MULT_SHIFT (3U)
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/** OCR */
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#define EMMC_HOST_OCR_VALUE (0x40FF8080U)
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#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */
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#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */
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#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U)
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/** EXT_CSD */
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#define EMMC_EXT_CSD_CARD_TYPE (196U)
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#define EMMC_EXT_CSD_PARTITION_CONFIG (179U)
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#define EMMC_EXT_CSD_PWR_CL_DDR_200_360 (253U) /* Power class for 200MHz, DDR at VCC= 3.6V */
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#define EMMC_EXT_CSD_PWR_CL_200_195 (237U) /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */
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#define EMMC_EXT_CSD_PWR_CL_26_195 (201U) /* Power class for 26MHz at 1.95V 1 R */
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#define EMMC_EXT_CSD_PWR_CL_52_195 (200U) /* Power class for 52MHz at 1.95V 1 R */
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#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U)
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#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U)
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#define EMMC_EXT_CSD_CARD_TYPE_200MHZ (0x10U)
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#define EMMC_EXT_CSD_CARD_TYPE_400MHZ (0x40U)
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/** SWITCH (CMD6) argument */
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#define EXTCSD_ACCESS_BYTE (0x03000000U) /* H'03000000 */
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#define BUS_WIDTH_ADD (183U<<16U) /* H'00b70000 */
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#define HS_TIMING_ADD (185U<<16U) /* H'00b90000 */
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#define POW_CLASS_ADD (187U<<16U) /* H'00bb0000 */
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#define BUS_WIDTH_1 (0U<<8U) /* H'00000000 */
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#define BUS_WIDTH_8 (2U<<8U) /* H'00000200 */
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#define BUS_WIDTH_8_DDR (6U<<8U) /* H'00000400 */
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#define HS_TIMING_1 (1U<<8U) /* H'00000100 */
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#define HS_TIMING_HS200 (2U<<8U) /* H'00000200 */
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#define HS_TIMING_HS400 (3U<<8U) /* H'00000300 */
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#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
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#define EMMC_SWITCH_HS200 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200) /**< H'03b90200 */
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#define EMMC_SWITCH_HS400 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400) /**< H'03b90300 */
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#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
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#define EMMC_SWITCH_BUS_WIDTH_8_DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR) /**< H'03b70600 */
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#define EMMC_SWITCH_PARTITION_CONFIG (0x03B30000UL) /**< Partition config = 0x00 */
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/** for st_mmc_base */
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#define EMMC_MAX_RESPONSE_LENGTH (17U)
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#define EMMC_MAX_CID_LENGTH (16U)
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#define EMMC_MAX_CSD_LENGTH (16U)
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#define EMMC_MAX_EXT_CSD_LENGTH (512U)
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/* speed mode */
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#define TIMING_HIGH_SPEED_OFF (0U)
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#define TIMING_HIGH_SPEED (1U)
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#define TIMING_HS200 (2U)
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#define TIMING_HS400 (3U)
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/* MMC Clock Frequency */
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/* 200MHz * 1/x = output clock */
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#define HS400_50MHZ (8U) /* 400MHz * 1/8 = 50MHz */
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#define HS400_200MHZ (2U) /* 400MHz * 1/2 = 200MHz */
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/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
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/* Partition id */
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typedef enum
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{
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PARTITION_ID_USER = 0x0, /**< User Area */
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PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
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PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
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PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
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PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
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PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
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PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
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PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
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PARTITION_ID_MASK = 0x7 /**< [2:0] */
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} EMMC_PARTITION_ID;
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/* card state in R1 response [12:9] */
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typedef enum
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{
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EMMC_R1_STATE_IDLE = 0,
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EMMC_R1_STATE_READY,
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EMMC_R1_STATE_IDENT,
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EMMC_R1_STATE_STBY,
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EMMC_R1_STATE_TRAN,
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EMMC_R1_STATE_DATA,
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EMMC_R1_STATE_RCV,
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EMMC_R1_STATE_PRG,
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EMMC_R1_STATE_DIS,
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EMMC_R1_STATE_BTST,
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EMMC_R1_STATE_SLEP
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} EMMC_R1_STATE;
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typedef enum{
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ESTATE_BEGIN = 0,
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ESTATE_ISSUE_CMD,
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ESTATE_NON_RESP_CMD,
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ESTATE_RCV_RESP,
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ESTATE_RCV_RESPONSE_BUSY,
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ESTATE_CHECK_RESPONSE_COMPLETE,
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ESTATE_DATA_TRANSFER,
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ESTATE_DATA_TRANSFER_COMPLETE,
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ESTATE_ACCESS_END,
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ESTATE_TRANSFER_ERROR,
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ESTATE_ERROR,
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ESTATE_END
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}EMMC_INT_STATE;
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/* eMMC boot driver error information */
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typedef struct
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{
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volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
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volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
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volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */
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volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */
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volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */
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volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */
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} st_error_info;
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/* Command information */
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typedef struct
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{
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HAL_MEMCARD_COMMAND cmd; /**< Command information */
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uint32_t arg; /**< argument */
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HAL_MEMCARD_OPERATION dir; /**< direction */
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uint32_t hw; /**< H/W dependence. SD_CMD register value. */
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} st_command_info;
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/* MMC driver base */
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typedef struct
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{
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st_error_info error_info; /**< error information */
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st_command_info cmd_info; /**< command information */
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/* for data transfer */
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uint32_t *buff_address_virtual; /**< Dest or Src buff */
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uint32_t *buff_address_physical; /**< Dest or Src buff */
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HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */
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uint32_t trans_size; /**< transfer size for this command */
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uint32_t remain_size; /**< remain size for this command */
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uint32_t response_length; /**< response length for this command */
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/* clock */
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uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
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uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
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uint32_t set_freq; /**< Frequency to be set. */
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/* state flag */
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uint32_t card_power_enable; /**< True : Power ON */
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uint32_t clock_enable; /**< True : Clock ON */
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uint32_t initialize; /**< True : initialize complete. */
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uint32_t mount; /**< True : mount complete. */
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uint32_t selected; /**< True : selected card. */
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HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */
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EMMC_R1_STATE current_state; /**< card state */
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volatile uint32_t during_transfer; /**< True : during transfer */
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volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
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volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
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volatile uint32_t force_terminate; /**< force terminate flag */
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volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
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/* timeout */
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uint32_t data_timeout; /**< read and write data timeout.*/
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/* interrupt */
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volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
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volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
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volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
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volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
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/* response */
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uint32_t *response; /**< pointer to buffer for executing command. */
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uint32_t r1_card_status; /**< R1 response data */
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uint32_t r3_ocr; /**< R3 response data */
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uint32_t r4_resp; /**< R4 response data */
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uint32_t r5_resp; /**< R5 response data */
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/* Card registers (4byte align) */
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uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */
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uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */
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uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */
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uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */
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/* SDHI base address */
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uintptr_t base_address;
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} st_mmc_base;
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/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
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/* ************************** FUNCTION PROTOTYPES ************************** */
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/* ********************************* CODE ********************************** */
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/* ******************************** END ************************************ */
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#endif /* EMMC_STD_H__ */
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/* EMMC_STD_H__ */
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