add IPL
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174
IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h
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174
IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : emmc register header
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******************************************************************************/
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/******************************************************************************
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* @file emmc_register.h
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* - Version : 0.04
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 02.02.2022 0.01 First Release
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* : 24.10.2022 0.02 SDIF_MODE register to support HS200/400
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* : 31.10.2022 0.03 License notation change.
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* : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel.
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*****************************************************************************/
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#ifndef EMMC_REGISTERS_H__
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#define EMMC_REGISTERS_H__
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/* ************************ HEADER (INCLUDE) SECTION *********************** */
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#include <rcar_register.h>
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/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
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/* MMC0 channel */
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#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */
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#define SD_CMD (MMC0_SD_BASE + 0x0000U)
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#define SD_ARG (MMC0_SD_BASE + 0x0010U)
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#define SD_STOP (MMC0_SD_BASE + 0x0020U)
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#define SD_SECCNT (MMC0_SD_BASE + 0x0028U)
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#define SD_RSP10 (MMC0_SD_BASE + 0x0030U)
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#define SD_RSP32 (MMC0_SD_BASE + 0x0040U)
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#define SD_RSP54 (MMC0_SD_BASE + 0x0050U)
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#define SD_RSP76 (MMC0_SD_BASE + 0x0060U)
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#define SD_INFO1 (MMC0_SD_BASE + 0x0070U)
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#define SD_INFO2 (MMC0_SD_BASE + 0x0078U)
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#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U)
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#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U)
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#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U)
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#define SD_SIZE (MMC0_SD_BASE + 0x0098U)
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#define SD_OPTION (MMC0_SD_BASE + 0x00A0U)
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#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U)
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#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U)
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#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U)
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#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U)
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#define SOFT_RST (MMC0_SD_BASE + 0x0380U)
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#define HOST_MODE (MMC0_SD_BASE + 0x0390U)
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#define SDIF_MODE (MMC0_SD_BASE + 0x0398U)
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#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U)
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#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U)
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#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U)
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#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U)
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#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U)
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#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U)
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#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U)
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#define SCC_DTCNTL (MMC0_SD_BASE + 0x1000U)
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#define SCC_TAPSET (MMC0_SD_BASE + 0x1008U)
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#define SCC_DT2FF (MMC0_SD_BASE + 0x1010U)
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#define SCC_CKSEL (MMC0_SD_BASE + 0x1018U)
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#define SCC_SMPCMP (MMC0_SD_BASE + 0x1030U)
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#define SCC_TMPPORT2 (MMC0_SD_BASE + 0x1038U)
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/* SD_INFO1 Registers */
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#define SD_INFO1_INFO2 (0x00000004U) /* Access end*/
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#define SD_INFO1_INFO0 (0x00000001U) /* Response end*/
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/* SD_INFO2 Registers */
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#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy*/
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#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable*/
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#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable*/
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#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0*/
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#define SD_INFO2_ALL_ERR (0x0000807FU)
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#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */
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/* DM_INFO1 Registers */
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#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */
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#define DM_CM_INFO_DTRANEND1 (0x00100000U) /* DMAC Channel 1 Transfer End */
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/* DM_INFO2 Registers */
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#define DM_CM_INFO2_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Error */
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#define DM_CM_INFO2_DTRANEND1 (0x00020000U) /* DMAC Channel 1 Error */
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/* SOFT_RST */
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#define SOFT_RST_SDRST (0x00000001U)
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/* SD_CLK_CTRL */
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#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU)
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#define SD_CLK_WRITE_MASK (0x000003FFU)
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/* SD_OPTION */
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#define SD_OPTION_WIDTH (0x00008000U)
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#define SD_OPTION_WIDTH8 (0x00002000U)
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#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U)
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/* MMC Clock Frequency
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* 200MHz * 1/x = output clock
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*/
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#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */
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#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode*/
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#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz*/
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#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz*/
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#define MMC_200MHZ (1U) /* 200MHz * 1/1 = 200 MHz HS200/HS400 mode 200Mhz*/
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#define MMC_FREQ_52MHZ (52000000U)
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#define MMC_FREQ_26MHZ (26000000U)
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#define MMC_FREQ_20MHZ (20000000U)
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/* MMC Clock DIV */
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#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */
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#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
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/* DM_CM_DTRAN_MODE */
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#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream*/
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#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream*/
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#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U)
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/* CC_EXT_MODE */
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#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */
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#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */
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/* DM_CM_INFO_MASK */
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#define DM_CM_INFO_MASK_CLEAR (0xFFEEFEFEU)
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#define DM_CM_INFO_CH0_ENABLE (0x00010001U)
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#define DM_CM_INFO_CH1_ENABLE (0x00100001U)
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/* DM_CM_INFO2_MASK */
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#define DM_CM_INFO2_MASK_CLEAR (0xFFFCFFFEU)
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#define DM_CM_INFO2_CH0_ENABLE (0x00010001U)
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#define DM_CM_INFO2_CH1_ENABLE (0x00020001U)
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/* DM_DTRAN_ADDR */
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#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U)
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/*DM_CM_DTRAN_CTRL */
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#define DM_CM_DTRAN_CTRL_START (0x00000001U)
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/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
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/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
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/* ************************** FUNCTION PROTOTYPES ************************** */
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/* ********************************* CODE ********************************** */
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#endif /* EMMC_REGISTERS_H__ */
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/* ******************************** END ************************************ */
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