add IPL

2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
--- a/IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h
+++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h
@@ -0,0 +1,126 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+ * DESCRIPTION   : Configuration table header
+ ******************************************************************************/
+
+#ifndef CNF_TBL_H_
+#define CNF_TBL_H_
+
+#include <stdint.h>
+
+typedef struct{
+    uint64_t fix;
+    uint64_t be;
+} QOS_SETTING_TABLE;
+
+typedef struct{
+    uint32_t phys_addr; /* Physical address of Region ID registers. */
+    uint32_t value;     /* setting value of Region ID registers. */
+} REGION_ID_SETTING_TABLE;
+
+/* For RAM protection table */
+typedef struct {
+    uint32_t rw_val;
+    uint32_t sec_val;
+}RAM_PROTECTION_VALUE_FORMAT;
+
+typedef struct {
+    uint32_t read_val;
+    uint32_t write_val;
+}RTRAM_PROTECTION_VALUE_FORMAT;
+
+typedef struct {
+    uint32_t addr;
+    RTRAM_PROTECTION_VALUE_FORMAT setting_value;
+}RTRAM_PROTECTION_STRUCTUR;
+
+typedef struct {
+    uint32_t addr;
+    RAM_PROTECTION_VALUE_FORMAT setting_value;
+}SYSTEM_RAM_PROTECTION_STRUCTUR;
+
+typedef struct {
+    uint64_t addr;
+    RAM_PROTECTION_VALUE_FORMAT setting_value;
+}DRAM_PROTECTION_STRUCTUR;
+
+
+#if (RCAR_LSI == RCAR_S4)
+#define QOS_TBL_MAX     (48U)   /* Max setting number of QoS Bank registers. */
+#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
+#define QOS_TBL_MAX     (125U)  /* Max setting number of QoS Bank registers. */
+#endif /* RCAR_LSI == RCAR_S4 */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define RGID_MASTER_MAX (77U)   /* Max number of Region registers. (Master) */
+#define RGID_READ_MAX   (908U)  /* Max number of Region registers. (Read)   */
+#define RGID_WRITE_MAX  (907U)  /* Max number of Region registers. (Write)  */
+#define RGID_SEC_MAX    (957U)  /* Max number of Region registers. (Secure) */
+#define RGID_AXI_MAX    (98U)   /* Max number of Region registers. (Read/Write for AXI-bus)  */
+#elif (RCAR_LSI == RCAR_V4M)
+#define RGID_MASTER_MAX (85U)   /* Max number of Region registers. (Master) */
+#define RGID_READ_MAX   (805U)  /* Max number of Region registers. (Read)   */
+#define RGID_WRITE_MAX  (804U)  /* Max number of Region registers. (Write)  */
+#define RGID_SEC_MAX    (819U)  /* Max number of Region registers. (Secure) */
+#define RGID_AXI_MAX    (90U)   /* Max number of Region registers. (Read/Write for AXI-bus)  */
+#endif /* RCAR_LSI == RCAR_V4H */
+
+#define RAM_PROTECTION_MAX       (16U)   /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */
+#define DRAM_PROTECTION_MAX      (64U)   /* Max number of RAM Protection registers. (SDRAM) */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define IMP_MASTER_MAX  (19U)
+#define IMP_SLAVE_MAX   (38U)
+#endif /* (RCAR_LSI == RCAR_V4H) */
+
+#if (RCAR_LSI == RCAR_V4H)
+#define IPMMU_RGID_MAX  (11U)
+#elif (RCAR_LSI == RCAR_V4M)
+#define IPMMU_RGID_MAX  (10U)
+#endif /* (RCAR_LSI == RCAR_V4H) */
+
+extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX];
+extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX];
+
+extern const REGION_ID_SETTING_TABLE g_rgid_master_tbl[RGID_MASTER_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_read_tbl[RGID_READ_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_write_tbl[RGID_WRITE_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX];
+extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX];
+#if (RCAR_LSI == RCAR_V4H)
+extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX];
+extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX];
+#endif /* (RCAR_LSI == RCAR_V4H) */
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX];
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX];
+extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX];
+
+/* For RAM protection */
+extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX];
+extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX];
+extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX];
+extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX];
+
+#endif /* CNF_TBL_H_ */