add IPL
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304
IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c
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304
IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Power management driver
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******************************************************************************/
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/******************************************************************************
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* @file cpu_on.c
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* - Version : 0.12
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* @brief 1. Boot process of ARM CPU core.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 17.02.2022 0.01 First Release
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* : 25.02.2022 0.02 Changed to boot Cortex-R on Core 0.
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* : 23.03.2022 0.03 Removed unnecessary header file inclusions
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* : 09.05.2022 0.04 Removed unnecessary processing
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* Removed unnecessary cast
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* : 31.10.2022 0.05 License notation change.
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* : 21.08.2023 0.06 Add support for V4M.
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* : 16.11.2023 0.07 Changed not to execute ASPREG setting
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* in case of V4M.
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* : 10.09.2024 0.08 Updated Region ID and RAM protection setting
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* for QNX.
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* : 11.10.2024 0.09 Updated Region ID and RAM protection setting
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* for QNX for V4M.
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* : 09.12.2024 0.10 Updated OTP_MEM_OTPMONITOR60 register to
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* OTP_MEM_OTPMONITOR17 register for V4M.
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* And Improve the adj_ca_variant_freq function.
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* : 19.12.2024 0.11 Add support for booting CR52 core2.
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* : 18.03.2025 0.12 Add INTC initialization process.
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*****************************************************************************/
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#include <stdint.h>
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#include <mem_io.h>
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#include <cpu_on.h>
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#include <rst_register.h>
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#include "access_protection.h"
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#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
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#include <log.h>
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/* ARM */
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#define CA_CORE0_WUP_REQ (0x00000001U)
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#define CA_CORE0_VLD_RVBARP (0x00000001U)
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#define CR_BTMD_RBAR (0x00000000U)
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#define CR_VLD_BARP (0x00000001U << 0U)
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#define CR_BAREN_VALID (0x00000001U << 4U)
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#define CRRST (0x00000000U)
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#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U)
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#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U)
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#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U)
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#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U)
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/* APMU */
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#define APMU_BASE (BASE_APMU_ADDR)
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#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 to 2) */
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#define APMU_CRRSTCTRL(n) (APMU_BASE + ((n) * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */
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#define APMU_CRBARP(n) (APMU_BASE + ((n) * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */
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#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */
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#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */
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#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */
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#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */
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#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U))
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#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U)
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#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U)
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#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0)
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#if (RCAR_LSI == RCAR_V4H)
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#define V4H_5_NI_CA (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
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#define V4H_3_NI_CA (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
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#elif (RCAR_LSI == RCAR_V4M)
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#define V4M_5_NI_CA (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
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#define V4M_3_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
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#define V4M_2_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
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#endif /* RCAR_LSI == RCAR_V4H */
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#define CPG_PLL2CR0_KICK_BIT (0x80000000U)
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#define CPG_PLLECR_PLL2ST_BIT (0x00000200U)
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#if (RCAR_LSI == RCAR_V4M)
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#define CPG_BASE (BASE_CPG_ADDR)
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#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U)
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#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU)
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#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U)
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#define CPG_SRSTCLR5_VAL (0x80000000U)
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#define CPG_SRSTCLR11_VAL (0x00080000U)
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#define CPG_MSTPCR5_VAL (0x80000000U)
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static void intc_init(void);
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#endif /* RCAR_LSI == RCAR_V4M */
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static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr, int n)
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{
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if(RCAR_PWR_TARGET_CR == target)
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{
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/* CR Boot address set */
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mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP));
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mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
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}
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else
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{
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/* CA Boot address set */
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mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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mem_write32(APMU_RVBARPHC0, 0x00000020U); /* CA boot address 0x20_XXXXXXXX */
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#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
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mem_write32(APMU_RVBARPHC0, 0x00000000U);
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#endif
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#else
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mem_write32(APMU_RVBARPHC0, 0x00000000U);
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#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
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}
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}
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/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
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void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id)
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{
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uint32_t res_data;
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if(RCAR_PWR_TARGET_CR == target)
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{
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if (core_id < 0)
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core_id = CORTEX_R_CORE;
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NOTICE("enable CR-52 core %d\n", core_id);
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/* CR Boot address set. */
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arm_cpu_set_address(target, boot_addr, core_id);
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/* CR reset. */
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mem_write32(APMU_CRRSTCTRL(core_id), CRRST);
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}
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else
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{
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#if (RCAR_LSI == RCAR_V4M)
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/* For the initial setting flow of INTC, see Section 15.4.5 in
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* "R-Car Series, V4M Series User's Manual".
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*/
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/* INTC initialize */
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intc_init();
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#endif /* RCAR_LSI == RCAR_V4M */
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/* CA Boot address set. */
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arm_cpu_set_address(target, boot_addr, 0);
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#if (RCAR_LSI == RCAR_V4H)
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/*
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* In case of V4M, doesn't execute following process at Cx 2nd IPL.
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* Because following register setting is needed to execute before C4 power on.
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*/
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/* AP-System core initialize */
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res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U));
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res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
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mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data);
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res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
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res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
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mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
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/* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */
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res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
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res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
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mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
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#endif /* RCAR_LSI == RCAR_V4H */
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/* CA core0 wake up sequence. */
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mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ);
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/* Wait until CA core0 wake up sequence finished. */
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do
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{
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res_data = mem_read32(APMU_PWRCTRLC0);
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}while(CA_CORE0_WUP_REQ & res_data);
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}
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}
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/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
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void adj_ca_variant_freq(void)
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{
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uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
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uint32_t pll2_freq = mem_read32(CPG_PLL2CR0);
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#if (RCAR_LSI == RCAR_V4H)
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/* Set the CPU frequency division ratio according to the type of variant. */
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switch (product)
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{
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case VARIANT_V4H_7:
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/* Default value, do nothing */;
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break;
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case VARIANT_V4H_5:
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pll2_freq = (pll2_freq & ~(0xFFU << 20U));
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pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U));
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break;
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case VARIANT_V4H_3:
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pll2_freq = (pll2_freq & ~(0xFFU << 20U));
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pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U));
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break;
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default:
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; /* Do nothing */
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break;
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}
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if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
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{
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/* Write Division value to FRQCRC0 register */
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mem_write32(CPG_CPGWPR, ~(pll2_freq));
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mem_write32(CPG_PLL2CR0, pll2_freq);
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mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
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mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
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while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
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{
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;
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}
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}
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#elif (RCAR_LSI == RCAR_V4M)
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/* Set the CPU frequency division ratio according to the type of variant. */
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switch (product)
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{
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case VARIANT_V4M_7:
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/* Default value, do nothing */;
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break;
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case VARIANT_V4M_5:
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pll2_freq = (pll2_freq & ~(0xFFU << 20U));
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pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U));
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break;
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case VARIANT_V4M_3:
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pll2_freq = (pll2_freq & ~(0xFFU << 20U));
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pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U));
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break;
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case VARIANT_V4M_2:
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pll2_freq = (pll2_freq & ~(0xFFU << 20U));
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pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U));
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break;
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default:
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; /* Do nothing */
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break;
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}
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if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
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{
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/* Write Division value to FRQCRC0 register */
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mem_write32(CPG_CPGWPR, ~(pll2_freq));
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mem_write32(CPG_PLL2CR0, pll2_freq);
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mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
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mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
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while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
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{
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;
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}
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}
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#endif /* RCAR_LSI == RCAR_V4H */
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}
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/* End of function adj_cpu_variant_freq(void) */
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#if (RCAR_LSI == RCAR_V4M)
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static void intc_init(void)
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{
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uint32_t reg;
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mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL));
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mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL);
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mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL));
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mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL);
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mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL));
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reg = mem_read32(CPG_MSTPCR5);
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reg |= CPG_MSTPCR5_VAL;
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mem_write32(CPG_MSTPCR5, reg);
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}
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/* End of function intc_init(void) */
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#endif /* RCAR_LSI == RCAR_V4M */
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