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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
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192
IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader.ld Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader linker directive
******************************************************************************/
DEFAULTS {
//Memory
remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000)
remap_size = 1M //RT-SRAM size
rt_sram_addr = 0xEB200000 //RT-SRAM address
local_ram_addr = 0xfede0000 //LRAM address
local_ram_size = 128K //LRAM size
// Size
//No override area
stack_size = 16K //ICUMX Loader stack size
sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K)
bss_size = 16K
// Configuration Table
qosbw_table_size = 4K
qoswt_table_size = 4K
rgid_m_table_size = 1K
rgid_r_table_size = 8K
rgid_w_table_size = 8K
rgid_sec_table_size = 8K
rgid_axi_table_size = 1K
rgid_gid_table_size = 1K //include .data section
configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size
// ICUMX Loader
ipl_top_addr = 0xEB210000
ipl_size = 128K //ICUMX Loader size
vector_table_size = 2K //vector table size
ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size)
// Address
// ICUMX Loader
vector_table_address_offset = ipl_top_addr - rt_sram_addr
code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset
code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size)
// No override area
stack_addr_offset = remap_size - stack_size
sa9_addr_offset = 0x30000
bss_addr_offset = sa9_addr_offset - bss_size
// Configuration Table
configuration_table_address_offset = vector_table_address_offset + vector_table_size
configuration_table_address = code_fetch_remap_vector_table + vector_table_size
qosbw_table_address = configuration_table_address
qoswt_table_address = qosbw_table_address + qosbw_table_size
rgid_m_table_address = qoswt_table_address + qoswt_table_size
rgid_r_table_address = rgid_m_table_address + rgid_m_table_size
rgid_w_table_address = rgid_r_table_address + rgid_r_table_size
rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size
rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size
rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size
// Offset
qosbw_table_address_offset = vector_table_address_offset + vector_table_size
qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size
rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size
rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size
rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size
rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size
rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size
rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size
ipl_rom_address_offset = configuration_table_address_offset + configuration_size
}
MEMORY
{
vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP)
qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW)
qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT)
rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI)
rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID)
ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size
// Physical address
phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM)
phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW)
phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT)
phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI))
phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID))
phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM)
// No override area
sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert
stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack
bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area
local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size // Local RAM
}
//
// Program layout for starting in ROM, copying data to RAM,
// and continuing to execute out of ROM.
//
SECTIONS
{
//
// ROM SECTIONS(Remap)
//
// Place .text into fast_memory. Fail if it does not fit.
.reset ALIGN(4) : > vector_table
.EIINTTBL_ICU ALIGN(512) : > .
.qosbw_tbl ALIGN(4) : > qosbw_table
.qoswt_tbl ALIGN(4) : > qoswt_table
.rgid_m_tbl ALIGN(4) : > rgid_m_table
.rgid_r_tbl ALIGN(4) : > rgid_r_table
.rgid_w_tbl ALIGN(4) : > rgid_w_table
.rgid_sec_tbl ALIGN(4) : > rgid_sec_table
.rgid_axi_tbl ALIGN(4) : > rgid_axi_table
.rgid_gid_tbl ALIGN(4) : > rgid_gid_table
.data ALIGN(4) : > .
.text ALIGN(4) : > ipl_rom
.RE_CR.text ALIGN(4) : > .
.rosdata ALIGN(4) : > .
.rodata ALIGN(4) : > .
.secinfo ALIGN(4) : > .
.rom_end ALIGN(4) : > .
.canary ALIGN(4) : > bss
.bss ALIGN(4) : > .
// ROM mirror SECTIONS(RT-SRAM)
_start = ipl_top_addr;
.ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table
.ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > .
.ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table
.ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table
.ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table
.ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table
.ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table
.ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table
.ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table
.ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table
.ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > .
.ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom
.ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > .
.ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > .
.ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > .
.ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > .
.cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary.
//
// RAM SECTIONS
//
.top_stack : > stack
.RT.stack ALIGN(4) PAD(stack_size) ABS : > .
.end_stack : > .
.top.local.ram : > local_ram
.sdata ALIGN(4) : > .
.tdata ALIGN(4) : > .
.sdabase ALIGN(4) : > .
.end.local.ram : > .
.sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load
}

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader linker directive
******************************************************************************/
DEFAULTS {
//Memory
remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000)
remap_size = 1M //RT-SRAM size
rt_sram_addr = 0xEB200000 //RT-SRAM address
local_ram_addr = 0xfede0000 //LRAM address
local_ram_size = 128K //LRAM size
// Size
//No override area
stack_size = 16K //ICUMX Loader stack size
bootrom_work_size = 2K
sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K)
bss_size = 16K
// Configuration Table
qosbw_table_size = 4K
qoswt_table_size = 4K
rgid_m_table_size = 1K
rgid_r_table_size = 8K
rgid_w_table_size = 8K
rgid_sec_table_size = 8K
rgid_axi_table_size = 1K
rgid_gid_table_size = 1K //include .data section
configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size
// ICUMX Loader
ipl_top_addr = 0xEB210000
ipl_size = 128K //ICUMX Loader size
vector_table_size = 2K //vector table size
ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size)
// Address
// ICUMX Loader
vector_table_address_offset = ipl_top_addr - rt_sram_addr
code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset
code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size)
// No override area
stack_addr_offset = 110K // stack top address : 0xFEDFB800 (This is in Local RAM)
sa9_addr_offset = 0x30000
bss_addr_offset = sa9_addr_offset - bss_size
// Configuration Table
configuration_table_address_offset = vector_table_address_offset + vector_table_size
configuration_table_address = code_fetch_remap_vector_table + vector_table_size
qosbw_table_address = configuration_table_address
qoswt_table_address = qosbw_table_address + qosbw_table_size
rgid_m_table_address = qoswt_table_address + qoswt_table_size
rgid_r_table_address = rgid_m_table_address + rgid_m_table_size
rgid_w_table_address = rgid_r_table_address + rgid_r_table_size
rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size
rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size
rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size
// Offset
qosbw_table_address_offset = vector_table_address_offset + vector_table_size
qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size
rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size
rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size
rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size
rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size
rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size
rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size
ipl_rom_address_offset = configuration_table_address_offset + configuration_size
}
MEMORY
{
vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP)
qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW)
qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT)
rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI)
rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID)
ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size
// Physical address
phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM)
phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW)
phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT)
phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master))
phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read))
phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write))
phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure))
phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI))
phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID))
phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM)
// No override area
sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert
stack : ORIGIN = local_ram_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack (This is in Local RAM)
bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area
local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size - bootrom_work_size // Local RAM
bootrom_work : ORIGIN = local_ram_addr + stack_addr_offset + stack_size, LENGTH = bootrom_work_size // BootROM work area
}
//
// Program layout for starting in ROM, copying data to RAM,
// and continuing to execute out of ROM.
//
SECTIONS
{
//
// ROM SECTIONS(Remap)
//
// Place .text into fast_memory. Fail if it does not fit.
.reset ALIGN(4) : > vector_table
.EIINTTBL_ICU ALIGN(512) : > .
.qosbw_tbl ALIGN(4) : > qosbw_table
.qoswt_tbl ALIGN(4) : > qoswt_table
.rgid_m_tbl ALIGN(4) : > rgid_m_table
.rgid_r_tbl ALIGN(4) : > rgid_r_table
.rgid_w_tbl ALIGN(4) : > rgid_w_table
.rgid_sec_tbl ALIGN(4) : > rgid_sec_table
.rgid_axi_tbl ALIGN(4) : > rgid_axi_table
.rgid_gid_tbl ALIGN(4) : > rgid_gid_table
.data ALIGN(4) : > .
.text ALIGN(4) : > ipl_rom
.RE_CR.text ALIGN(4) : > .
.rosdata ALIGN(4) : > .
.rodata ALIGN(4) : > .
.secinfo ALIGN(4) : > .
.rom_end ALIGN(4) : > .
.canary ALIGN(4) : > bss
.bss ALIGN(4) : > .
// ROM mirror SECTIONS(RT-SRAM)
_start = ipl_top_addr;
.ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table
.ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > .
.ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table
.ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table
.ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table
.ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table
.ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table
.ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table
.ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table
.ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table
.ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > .
.ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom
.ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > .
.ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > .
.ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > .
.ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > .
.cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary.
//
// RAM SECTIONS
//
.top.local.ram : > local_ram
.sdata ALIGN(4) : > .
.tdata ALIGN(4) : > .
.sdabase ALIGN(4) : > .
.top_stack : > stack
.RT.stack ALIGN(4) PAD(stack_size) ABS : > .
.end_stack : > .
.used_by_bootrom ALIGN(4) PAD(bootrom_work_size) ABS : > bootrom_work // 0xFEDFF800 - 0xFEDFFFFF is prohibited writing
.end.local.ram : > .
.sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load
}

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader.S Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader start code
******************************************************************************/
.global code_start
.global _loader_main
.global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */
.global ___ghs_set_stack_chk_guard
BOOTROM_CODE_START_ADDRESS .set 0x01104000 /* Boot ROM start address */
BOOTROM_CODE_END_ADDRESS .set 0x0112CFFC /* Boot ROM end address */
SICREMAP_WINDOW_AREA_START_ADDRESS .set 0xFC000000 /* Remap 0 start address */
SICREMAP_WINDOW_AREA_END_ADDRESS .set 0xFEBFFFFC /* SIC area end address */
ICU_REGISTER_AREA_START_ADDRESS .set 0xFEDE0000 /* ICUMXB register area start address */
ICU_REGISTER_AREA_END_ADDRESS .set 0xFFFEFFFC /* ICUMXB register area end address */
MPAT_SX_SR_ENABLE .set 0x000000E8 /* SV mode Read/Execution enable */
MPAT_SW_SR_ENABLE .set 0x000000D8 /* SV mode Read/Writer enable */
MPRC_E3_TO_E0_ENABLE .set 0x0000000F /* E0,E1,E2,E3 enable */
MPM_SVP_MPE_ENABLE .set 0x00000003 /* SV mode protect enable, MPU enable */
MPAT_ALL_DISABLE .set 0x00000040
MPM_ALL_DISABLE .set 0x00000000
.section ".reset", "ax"
.align 2
code_start:
/* ; initialize registers */
mov r0, r1
mov r0, r2
mov r0, r3
mov r0, r4
mov r0, r5
mov r0, r6
mov r0, r7
mov r0, r8
mov r0, r9
mov r0, r10
mov r0, r11
mov r0, r12
mov r0, r13
mov r0, r14
mov r0, r15
mov r0, r16
mov r0, r17
mov r0, r18
mov r0, r19
mov r0, r20
mov r0, r21
mov r0, r22
mov r0, r23
mov r0, r24
mov r0, r25
mov r0, r26
mov r0, r27
mov r0, r28
mov r0, r29
ldsr r0, 0, 0
ldsr r0, 16, 0
/* set global pointer *
mov ___ghsbegin_sdabase, gp
/* set stack pointer */
mov ___ghsend_RT_stack, sp
/* MPU Disable */
stsr 0, r6 ,5
andi 0xFFFE, r6, r6
ldsr r6, 0, 5
SYNCM
/* MPU setting */
mov BOOTROM_CODE_START_ADDRESS, r12 /* MPLA0 */
ldsr r12, 0, 6
mov BOOTROM_CODE_END_ADDRESS, r12 /* MPUA0 */
ldsr r12, 1, 6
mov ___ghsbegin_reset, r12 /* MPLA1 */
ldsr r12, 4, 6
mov ___ghsend_rom_end, r12 /* MPUA1 */
ldsr r12, 5, 6
mov SICREMAP_WINDOW_AREA_START_ADDRESS, r12 /* MPLA2 */
ldsr r12, 8, 6
mov SICREMAP_WINDOW_AREA_END_ADDRESS, r12 /* MPUA2 */
ldsr r12, 9, 6
mov ICU_REGISTER_AREA_START_ADDRESS, r12 /* MPLA3 */
ldsr r12, 12, 6
mov ICU_REGISTER_AREA_END_ADDRESS, r12 /* MPUA3 */
ldsr r12, 13, 6
mov MPAT_SX_SR_ENABLE, r12 /* MPAT0 */
ldsr r12, 2, 6
mov MPAT_SX_SR_ENABLE, r12 /* MPAT1 */
ldsr r12, 6, 6
mov MPAT_SW_SR_ENABLE, r12 /* MPAT2 */
ldsr r12, 10, 6
mov MPAT_SW_SR_ENABLE, r12 /* MPAT3 */
ldsr r12, 14, 6
mov MPRC_E3_TO_E0_ENABLE, r12 /* MPRC */
ldsr r12, 1, 5
mov MPM_SVP_MPE_ENABLE, r12 /* MPM */
ldsr r12, 0, 5
SYNCM
/* BSS clear */
mov ___ghsbegin_bss, r6
mov ___ghsend_bss, r7
mov r0, r1
loop_clear:
st.dw r0, 0[r6]
addi 8, r6, r6
cmp r7, r6
bl loop_clear
/* Set canary before jump another function. */
/* Don't call functions before calling __ghs_set_stack_chk_guard. */
jarl ___ghs_set_stack_chk_guard, lp
mov _loader_main, r2
jarl [r2], lp
/* Release MPU setting */
mov MPM_ALL_DISABLE, r12
ldsr r12, 0, 5 /* MPM */
ldsr zero, 1, 5 /* MPRC */
mov MPAT_ALL_DISABLE, r12
ldsr r12, 2, 6 /* MPAT0 */
ldsr r12, 6, 6 /* MPAT1 */
ldsr r12, 10, 6 /* MPAT2 */
ldsr r12, 14, 6 /* MPAT3 */
ldsr zero, 0, 6 /* MPLA0 */
ldsr zero, 1, 6 /* MPUA0 */
ldsr zero, 4, 6 /* MPLA1 */
ldsr zero, 5, 6 /* MPUA1 */
ldsr zero, 8, 6 /* MPLA2 */
ldsr zero, 9, 6 /* MPUA2 */
ldsr zero, 12, 6 /* MPLA3 */
ldsr zero, 13, 6 /* MPUA3 */
SYNCM
jmp [r10]
nop
halt
.section ".padding"
.align 4

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_common.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main common function
******************************************************************************/
/******************************************************************************
* @file loader_main_common.c
* - Version : 0.04
* @brief 1.Output boot message.
* 2.Judge boot mode.
* 3.Set BL31 parameter.
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 02.04.2022 0.01 First Release
* : 04.04.2023 0.02 Removed stdio.h.
* : 21.08.2023 0.03 Add support for V4M.
* : 19.09.2023 0.04 Add log output for build option LSI.
*****************************************************************************/
#include <stdint.h>
#include <stddef.h> /* NULL pointer */
#include <mem_io.h>
#include <loader_main_common.h>
#include <rcar_def.h>
#include <rst_register.h>
#include <rom_api.h>
#include <log.h>
#include <remap.h>
#include <cpg.h>
#include <fcpr.h>
#include <access_protection.h>
#include <gpio.h>
#define RST_MODEMR0_MD5 (0x00000020U)
/* Define for Work Around of APMU */
#define CL0GRP3_BIT (1U << 3)
#define CL1GRP3_BIT (1U << 7)
#define RTGRP3_BIT (1U << 19)
#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
static void judge_bootmode(uint32_t lcs);
/* global variable */
uint32_t is_verify = SECURE_BOOT;
static void judge_bootmode(uint32_t lcs)
{
uint32_t md;
/* LCS Status check */
if((lcs != LCS_CM)
&& (lcs != LCS_DM)
&& (lcs != LCS_SD)
&& (lcs != LCS_SE)
&& (lcs != LCS_FA))
{
ERROR("LCS state error."
"LCS = 0x%x", lcs);
panic;
}
md = (mem_read32(RST_MODEMR0) & RST_MODEMR0_MD5) >> 5U;
if (lcs == LCS_SE)
{
/* LCS=SE => Secure boot */
is_verify = SECURE_BOOT;
}
else if ((lcs != LCS_SD) && (md == 0U))
{
/* LCS=CM/DM/FA and MD5=0 => Secure boot */
is_verify = SECURE_BOOT;
}
else
{
/* LCS=SD or MD5=1 => Normal boot */
is_verify = NORMAL_BOOT;
}
if (NORMAL_BOOT != is_verify)
{
NOTICE("Secure boot(ICUMX)\n");
}
else
{
NOTICE("Normal boot(ICUMX)\n");
}
}
/* End of function judge_bootmode(uint32_t lcs) */
void print_boot_msg(void)
{
uint32_t lcs = 0U; /* store LCS state */
uint32_t lcs_size = sizeof(lcs);
uint32_t prr;
uint32_t reg; /* store register value */
uint32_t ret; /* store return value */
__attribute__((__unused__)) const char *str;
__attribute__((__unused__)) const char *product_s4 = "S4";
__attribute__((__unused__)) const char *product_v4h = "V4H";
__attribute__((__unused__)) const char *product_v4m = "V4M";
__attribute__((__unused__)) const char *unknown = "unknown";
__attribute__((__unused__)) const char *boot_hyper80_160= "HyperFlash";
__attribute__((__unused__)) const char *boot_serial40 = "Serial Flash";
__attribute__((__unused__)) const char *boot_qspi80_160 = "Octal SPI Flash";
__attribute__((__unused__)) const char *boot_emmc50x8 = "eMMC(50MHz x8)";
const char *lcs_name[8U] = {
[LCS_CM] = "CM",
[LCS_DM] = "DM",
[LCS_SD] = "SD",
[LCS_SE] = "SE",
[LCS_FA] = "FA",
};
NOTICE("ICUMX Loader Rev.%s\n", IPL_VERSION);
NOTICE("LSI=%d (Build Option : S4=0, V4H=1, V4M=2)\n", RCAR_LSI);
NOTICE("%s\n", build_message);
#if (BOOT_TIME_CHECK != 0)
gpio_N1305(2);
#endif
/* Get PRR */
prr = mem_read32(PRR);
prr &= (PRR_PRODUCT_MASK | PRR_MAJOR_MASK | PRR_MINOR_MASK);
switch (prr & PRR_PRODUCT_MASK)
{
case PRR_PRODUCT_S4:
{
str = product_s4;
break;
}
case PRR_PRODUCT_V4H:
{
str = product_v4h;
break;
}
case PRR_PRODUCT_V4M:
{
str = product_v4m;
break;
}
default:
{
str = unknown;
break;
}
}
NOTICE("PRR is R-Car %s Ver%d.%d\n", str,
((prr & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET,
(prr & PRR_MINOR_MASK));
reg = mem_read32(RST_MODEMR0);
reg &= RST_MODEMR0_BOOT_DEV_MASK;
switch (reg)
{
case RST_MODEMR0_BOOT_DEV_HYPERFLASH160:
case RST_MODEMR0_BOOT_DEV_HYPERFLASH80:
{
str = boot_hyper80_160;
break;
}
case RST_MODEMR0_BOOT_DEV_SERIAL_FLASH40:
case RST_MODEMR0_BOOT_DEV_SERIAL_FLASH:
{
str = boot_serial40;
break;
}
case RST_MODEMR0_BOOT_DEV_QSPI_FLASH80:
{
str = boot_qspi80_160;
break;
}
case RST_MODEMR0_BOOT_DEV_EMMC_50X8:
{
str = boot_emmc50x8;
break;
}
default:
{
str = unknown;
break;
}
}
NOTICE("Boot device is %s(0x%x)\n", str, reg);
#if (QSPI_DDR_MODE==1)
NOTICE("Change QSPI DDR Transfer mode\n");
#endif
/* Get LCS state */
ret = call_ROM_GetLcs(&lcs, lcs_size);
str = unknown;
if (ret == ROMAPI_OK)
{
if (NULL != lcs_name[lcs])
{
str = lcs_name[lcs];
}
}
NOTICE("LCM state is %s\n", str);
/* If PRR is S4 Ver.1.0 */
if ((PRR_PRODUCT_S4 == (prr & PRR_PRODUCT_MASK)) && (0U == (prr & PRR_CUT_MASK)))
{
set_sicremap_s4v10(); /* downgrade SICREMAP setting. */
is_verify = NORMAL_BOOT;/* S4 Ver.1.0 is Normal Boot only. */
}
else
{
/* LCS judgement for secure boot */
judge_bootmode(lcs);
}
#if (SET_FCPR_PARAM == FCPR_ENABLE)
NOTICE("Data Compression Enable\n");
NOTICE("Start address = 0x%08x End address = 0x%08x\n", COMPRESSION_START_ADDR, COMPRESSION_END_ADDR);
#endif
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
NOTICE("Access protection Enable\n");
#endif
}
/* End of function print_boot_msg(void) */
/* Work Around setting for APMU */
void wa_setting_apmu(void)
{
uint32_t apmu_tmp;
/* Work Around setting for D0_ACCENR-DOMAIN3_ACCENR */
apmu_tmp = mem_read32(APMU_D0_ACCENR);
apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU;
apmu_reg_write(APMU_D0_ACCENR, apmu_tmp);
apmu_tmp = mem_read32(APMU_D1_ACCENR);
apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU;
apmu_reg_write(APMU_D1_ACCENR, apmu_tmp);
apmu_tmp = mem_read32(APMU_D2_ACCENR);
apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU;
apmu_reg_write(APMU_D2_ACCENR, apmu_tmp);
apmu_tmp = mem_read32(APMU_D3_ACCENR);
apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU;
apmu_reg_write(APMU_D3_ACCENR, apmu_tmp);
}
/* End of function wa_setting_apmu(void) */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main function
******************************************************************************/
/******************************************************************************
* @file loader_main.c
* - Version : 0.15
* @brief 1. IP initialization.
* 2. DMA transfer the binary image from Flash to RAM.
* 3. Authentication of the transferred image.
* 4. Boot CR and CA core.
* 5. Release of used resources.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* Add process to call rpc_release function.
* : 30.09.2021 0.03 Support of eMMC boot.
* : 15.10.2021 0.04 Modified the MCU boot sequence.
* remove include of Flash/eMMC.
* : 03.12.2021 0.05 Add RT-VRAM extend mode.
* : CA IPL boot support
* : 06.01.2022 0.06 Support for two-stage boot of G4MH
* : Add the Reset mask release process for RWDT.
* : Add exception handling for ICUMX_WDTA.
* : 20.01.2022 0.07 Capture DDR rev.0.02rc11
* Add ICUMX name unification.
* : 28.02.2022 0.08 Modify the process of setting the parameters
* used by BL31 in IPL.
* : 14.04.2022 0.09 Fixed Set SDCLK to 200MHz.
* : 23.05.2022 0.10 Integration of S4 and V4H
* Renamed from loader_main.c to loader_main_s4.c.
* : 04.07.2022 0.11 Change loading Control Domain process to
* calling load_main_for_mcu() function.
* : 05.08.2022 0.12 Add authentication of software minimum
* version table.
* : 30.09.2022 0.13 Modify pre-process pranch in load_main_for_mcu
* function.
* Modify authentication process of software
* minimum version.
* : 12.01.2023 0.14 Modified argument to fixed
* when calls smoni_set_param() function.
* Modified processing sequence for Access
* protection.
* : 04.04.2023 0.15 Removed stdio.h.
*****************************************************************************/
#include <stdint.h>
#include <loader_main.h>
#include <loader_main_common.h>
#include <cpu_on.h>
#include <rst_register.h>
#include <image_load.h>
#include <ip_control.h>
#include <qos.h>
#include <remap.h>
#include <remap_register.h>
#include <rom_api.h>
#include <mem_io.h>
#include <log.h>
#include <wdt.h>
#include <micro_wait.h>
#include <mcu_register.h>
#include <rtvram.h>
#include <ram_def.h>
#include <access_protection.h>
#include <cpu_on_for_mcu.h>
#include <loader_main_mcu.h>
/* Provided code */
#include "../ip/ddr/boot_init_dram.h"
# if (ECC_ENABLE == 1)
#include "../ip/ddr/s4/lpddr4x/ecc_enable_s4.h"
# endif
#define CA_IPL (0U)
#define BL31 (1U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
#define WDTRSTCR_PASSWORD (0xA55A0000U)
/* flag of set BL31 parameter*/
#define CA_APP_SET_PARAM_ENABLE (1U)
/* Calculation set address for BL31 parameter */
#define SMONI_IPL_PARAM_OFFSET (0x00022200U)
#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U)
#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U)
#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U)
/* KIND BOOT flag*/
#define BL31_COLD_BOOT (0x0000000000000000U)
#define BL31_WARM_BOOT (0x0000000000000001U)
#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU)
/* Program top address of Secure Monitor(BL31), OP-TEE and u-boot. */
#define SMONI_PHYS_TOP_ADDR (0x46400000U)
#define OPTEE_PHYS_TOP_ADDR (0x44100000U)
#define UBOOT_PHYS_TOP_ADDR (0x50000000U)
/* struct */
typedef struct{
uint8_t uctype;
uint8_t ucversion;
uint16_t ussize;
uint32_t uiattr;
uint32_t psecmonimageinfo_low;
uint32_t psecmonimageinfo_high;
uint32_t psecoptepinfo_low;
uint32_t psecoptepinfo_high;
uint32_t psecoptimageinfo_low;
uint32_t psecoptimageinfo_high;
uint32_t pnonsecepinfo_low;
uint32_t pnonsecepinfo_high;
uint32_t pnonsecimageinfo_low;
uint32_t pnonsecimageinfo_high;
}st_smoni_iplparams_t;
typedef struct{
uint8_t uctype;
uint8_t ucversion;
uint16_t ussize;
uint32_t uiattr;
uint32_t ulpc_low;
uint32_t ulpc_high;
uint32_t ulspsr_low;
uint32_t ulspsr_high;
uint32_t ularg0_low;
uint32_t ularg0_high;
uint32_t ularg1_low;
uint32_t ularg1_high;
uint32_t ularg2_low;
uint32_t ularg2_high;
uint32_t ularg3_low;
uint32_t ularg3_high;
uint32_t ularg4_low;
uint32_t ularg4_high;
uint32_t ularg5_low;
uint32_t ularg5_high;
uint32_t ularg6_low;
uint32_t ularg6_high;
uint32_t ularg7_low;
uint32_t ularg7_high;
}st_smoni_entrypointinfo_t;
static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify);
static void smoni_set_param(uint32_t smoni_entry_point,
uint32_t tee_entry_point,
uint32_t uboot_entry_point);
static void load_main_for_mcu(const LOAD_INFO *li);
#if ((CR_SECURE_DEBUG == SECURE_DEBUG_ENABLE) || (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER))
#define HOTPLUG_MAGIC_NUM (0x853F912EU)
#else
#define HOTPLUG_MAGIC_NUM (0x00000000U)
#endif
__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U,
0x00000000U, HOTPLUG_MAGIC_NUM};
uint32_t loader_main(void)
{
uint32_t reg; /* store register value */
int32_t result; /* store result of ddr_init() */
uint32_t is_verify = SECURE_BOOT;
uint32_t boot_ca_id;
uint32_t auth_count = 0U;
__attribute__((__unused__)) uint32_t loop = 0U;
__attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */
LOAD_INFO li[MAX_PLACED] = {0U};
/*****************************************************************************
* Initialize Hardware
*****************************************************************************/
/* IP initialize */
ip_init();
/* Unmask the detection of RWDT overflow */
reg = mem_read32(RST_WDTRSTCR);
reg &= ~WDTRSTCR_RWDT_RSTMSK;
reg |= WDTRSTCR_PASSWORD;
mem_write32(RST_WDTRSTCR, reg);
# if (ECC_ENABLE == 1)
/*****************************************************************************
* ECC and EDC Initialize
*****************************************************************************/
ecc_rtsram_enable();
edc_axi_enable();
edc_vram_enable();
#endif
/*****************************************************************************
* Work Around for APMU
*****************************************************************************/
wa_setting_apmu();
/*****************************************************************************
* Output boot message
*****************************************************************************/
is_verify =print_boot_msg();
/*****************************************************************************
* Setting Access protection
*****************************************************************************/
/* Region ID access protection */
rgid_protection();
ram_protection();
/* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */
set_master_rgid_4_tfr_mod();
/*****************************************************************************
* Load Certficate from QSPI
*****************************************************************************/
/* Load content certificate */
ca_load_num = load_content_cert();
/* Get load information */
load_init(li);
/*****************************************************************************
* Authenticate Software minimum version table
*****************************************************************************/
auth_min_ver_tbl(is_verify, li);
/*****************************************************************************
* Load Control Domain
*****************************************************************************/
load_main_for_mcu(li, is_verify);
/*****************************************************************************
* DDR Initialization
*****************************************************************************/
/* DDR initialize */
result = InitDram();
if (INITDRAM_OK != result)
{
ERROR("Failed to DRAM initialize (%d).\n", result);
panic;
}
#if (ECC_ENABLE == 1)
/* ECC Protection */
enable_ecc();
#endif /* ECC_ENABLE */
/* QoS configuration */
qos_init();
/* RT-VRAM Extend mode */
rtvram_extendmode();
/*****************************************************************************
* Load RTOS from Flash
*****************************************************************************/
/* Start loading RTOS image from Flash into SDRAM */
load_image(&li[RTOS_ID]);
/* finish loading RTOS */
load_end();
/*****************************************************************************
* Load Cx IPL from Flash
*****************************************************************************/
#if (CA_LOAD_TYPE == CA_IPL)
/* Start loading Cx IPL image from Flash into SDRAM */
load_image(&li[CA_PROGRAM_ID]);
/* Authenticate of RTOS */
rom_secureboot(is_verify, &li[RTOS_ID]);
/* boot CR */
arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr);
/* The CA image to boot is CA IPL. */
boot_ca_id = CA_PROGRAM_ID;
/* finish loading Cx IPL */
load_end();
#elif (CA_LOAD_TYPE == BL31)
/* Authenticate of RTOS */
rom_secureboot(is_verify, &li[RTOS_ID]);
/* boot CR */
arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr);
/* The CA image to boot is CA prgram#1. */
boot_ca_id = CA_OPTIONAL_ID;
/*****************************************************************************
* Load CA Program#1--#8 from Flash
*****************************************************************************/
/* Start loading CA Program#n image from Flash into SDRAM */
for (loop = 0U; loop < ca_load_num; loop++)
{
/* Loading start */
load_image(&li[boot_ca_id + loop]);
/* Authenticate of CA Program#n-1 */
if (loop != 0U)
{
rom_secureboot(is_verify, &li[boot_ca_id + loop - 1U]);
auth_count++;
}
/* finish loading CA Program#n */
load_end();
}
#endif /* (CA_LOAD_TYPE == CA_IPL) */
/*****************************************************************************
* Load Secure Firmware from Flash
*****************************************************************************/
/* Start loading Secure FW image from Flash into SDRAM */
load_image(&li[SECURE_FW_ID]);
/* Authenticate of Cx IPL or CA Program#n */
rom_secureboot(is_verify, &li[boot_ca_id + auth_count]);
/* Set Secure Monitor parameter */
smoni_set_param(SMONI_PHYS_TOP_ADDR, /* BL31 */
OPTEE_PHYS_TOP_ADDR, /* OP-TEE */
UBOOT_PHYS_TOP_ADDR); /* U-Boot */
/* boot CA */
arm_cpu_on(RCAR_PWR_TARGET_CA, li[boot_ca_id].boot_addr);
/* finish loading Secure Firmware */
load_end();
/* load_secure data(for ICUMXB) */
load_securedata(SECURE_FW_ID);
/* Authenticate of Secure Firmware */
rom_secureboot(is_verify, &li[SECURE_FW_ID]);
/* finish loading secure data */
load_end();
/* Finally Protection setting */
ram_protection_final();
rgid_protection_final();
#if (ECC_ENABLE == 1)
/* Notice the ecc enable */
NOTICE("Enabled ECC and EDC for RT-SRAM, AXI, VRAM, SDRAM. \n");
# endif
NOTICE("Load finish.\n");
ip_release();
return remap_get_remap_addr(li[SECURE_FW_ID].boot_addr);
}
/* End of function loader_main(void) */
static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify)
{
#if (BOOT_MCU != 0U)
mcu_load_main(li, is_verify);
#endif /* (BOOT_MCU != 0U) */
}
/* End of function load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify) */
static void smoni_set_param(uint32_t smoni_entry_point,
uint32_t tee_entry_point,
uint32_t uboot_entry_point)
{
#if (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE)
uint32_t mapped_addr;
st_smoni_iplparams_t *smoni_ipl_param;
st_smoni_entrypointinfo_t *smoni_ep_info;
st_smoni_entrypointinfo_t *optee_ep_info;
remap_register(smoni_entry_point, &mapped_addr);
/* set struct address */
smoni_ipl_param = (st_smoni_iplparams_t *)
(mapped_addr + SMONI_IPL_PARAM_OFFSET);
smoni_ep_info = (st_smoni_entrypointinfo_t *)
(mapped_addr + SMONI_EP_INFO_OFFSET);
optee_ep_info = (st_smoni_entrypointinfo_t *)
(mapped_addr + OPTEE_EP_INFO_OFFSET);
/* set parameter */
smoni_ipl_param->uctype = 0x03U;
smoni_ipl_param->ucversion = 0x01U;
smoni_ipl_param->ussize = 0x0030U;
smoni_ipl_param->uiattr = 0x00000000U;
smoni_ipl_param->psecmonimageinfo_low = 0x00000000U;
smoni_ipl_param->psecmonimageinfo_high = 0x00000000U;
smoni_ipl_param->psecoptepinfo_low = 0x00000000U;
smoni_ipl_param->psecoptepinfo_high = 0x00000000U;
smoni_ipl_param->psecoptimageinfo_low = 0x00000000U;
smoni_ipl_param->psecoptimageinfo_high = 0x00000000U;
smoni_ipl_param->pnonsecepinfo_low =
remap_get_phys_addr((uint32_t)smoni_ep_info);
smoni_ipl_param->pnonsecepinfo_high = 0x00000000U;
smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U;
smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U;
smoni_ep_info->uctype = 0x01U;
smoni_ep_info->ucversion = 0x01U;
smoni_ep_info->ussize = 0x0058U; /* structure size */
smoni_ep_info->uiattr = 0x00000001U; /* SECURE */
smoni_ep_info->ulpc_low = uboot_entry_point;
smoni_ep_info->ulpc_high = 0x00000000U;
/* SPSR_EL3.E[9] = b1 (BigEndian) *
* .A[8] = b1 (DataAbort MASK) *
* .I[7] = b1 (IRQ MASK) *
* .F[6] = b1 (FIQ MASK) *
* .M[4] = b0 (AArcch64) *
* .M[3:1] = b0101 (EL1h) */
smoni_ep_info->ulspsr_low = 0x000003C5U;
smoni_ep_info->ulspsr_high = 0x00000000U;
smoni_ep_info->ularg0_low = 0x00000000U;
smoni_ep_info->ularg0_high = 0x00000000U;
smoni_ep_info->ularg1_low = 0x00000000U;
smoni_ep_info->ularg1_high = 0x00000000U;
smoni_ep_info->ularg2_low = 0x00000000U;
smoni_ep_info->ularg2_high = 0x00000000U;
smoni_ep_info->ularg3_low = 0x00000000U;
smoni_ep_info->ularg3_high = 0x00000000U;
smoni_ep_info->ularg4_low = 0x00000000U;
smoni_ep_info->ularg4_high = 0x00000000U;
smoni_ep_info->ularg5_low = 0x00000000U;
smoni_ep_info->ularg5_high = 0x00000000U;
smoni_ep_info->ularg6_low = 0x00000000U;
smoni_ep_info->ularg6_high = 0x00000000U;
smoni_ep_info->ularg7_low = 0x00000000U;
smoni_ep_info->ularg7_high = 0x00000000U;
optee_ep_info->uctype = 0x01U;
optee_ep_info->ucversion = 0x02U;
optee_ep_info->ussize = 0x0058U;
optee_ep_info->uiattr = 0x00000008U;
optee_ep_info->ulpc_low = tee_entry_point;
optee_ep_info->ulpc_high = 0x00000000U;
optee_ep_info->ulspsr_low = 0x000003C5U;
optee_ep_info->ulspsr_high = 0x00000000U;
optee_ep_info->ularg0_low = 0x00000000U;
optee_ep_info->ularg0_high = 0x00000000U;
optee_ep_info->ularg1_low = 0x00000000U;
optee_ep_info->ularg1_high = 0x00000000U;
optee_ep_info->ularg2_low = 0x00000000U;
optee_ep_info->ularg2_high = 0x00000000U;
optee_ep_info->ularg3_low = 0x00000000U;
optee_ep_info->ularg3_high = 0x00000000U;
optee_ep_info->ularg4_low = 0x00000000U;
optee_ep_info->ularg4_high = 0x00000000U;
optee_ep_info->ularg5_low = 0x00000000U;
optee_ep_info->ularg5_high = 0x00000000U;
optee_ep_info->ularg6_low = 0x00000000U;
optee_ep_info->ularg6_high = 0x00000000U;
optee_ep_info->ularg7_low = 0x00000000U;
optee_ep_info->ularg7_high = 0x00000000U;
mapped_addr += BL31_KIND_BOOT_ADDR;
mem_write32((mapped_addr), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU));
mem_write32(((mapped_addr) + 0x4U),
(uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU));
remap_unregister(mapped_addr);
#endif /* (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE) */
}
/* End of function smoni_set_param(uint32_t smoni_entry_point) */

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4h.c Normal file
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@@ -0,0 +1,496 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main function for V4H
******************************************************************************/
/******************************************************************************
* @file loader_main.c
* - Version : 0.14
* @brief 1. IP initialization.
* 2. DMA transfer the binary image from Flash to RAM.
* 3. Authentication of the transferred image.
* 4. Boot CR and CA core.
* 5. Release of used resources.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* Add process to call rpc_release function.
* : 30.09.2021 0.03 Support of eMMC boot.
* : (30.11.2021 0.04) Support boot sequence of V4H.
* : 03.12.2021 0.05 Add RT-VRAM extend mode.
* : 23.05.2022 0.06 Integration of S4 and V4H
* Renamed from loader_main.c to loader_main_v4h.c.
* : 05.08.2022 0.07 Add authentication of software minimum
* version table.
* : 30.09.2022 0.08 Modify authentication process of software
* minimum version.
* : 20.01.2023 0.09 Add W/A OTLINT-5556: increased latency
* : 17.04.2023 0.10 Add setting for V4H v2.x leak current reduce
* Removed stdio.h.
* Add certificate authentication functions to be
* execute before image transfer.
* : 15.05.2023 0.11 Change the jump address of secure firmware from
* on SIC remap area to CF remap area.
* : 13.06.2024 0.12 Updated ECM register setting in wa_for_v4h2
* function.
* : 27.12.2024 0.13 Change the location of ECC and EDC
* initialization function.
* : 07.04.2025 0.14 Added ecm_init_setting function calling.
*****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <loader_main.h>
#include <loader_main_common.h>
#include <cpu_on.h>
#include <image_load.h>
#include <ip_control.h>
#include <qos.h>
#include <rcar_def.h>
#include <remap.h>
#include <remap_register.h>
#include <rom_api.h>
#include <mem_io.h>
#include <log.h>
#include <wdt.h>
#include <micro_wait.h>
#include <rtvram.h>
#include <ram_def.h>
#include <access_protection.h>
#include "rcar_def.h"
#if (ECM_ERROR_ENABLE == 1)
#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h"
#endif /* ECM_ERROR_ENABLE == 1 */
/* Provided code */
#include "../ip/ddr/boot_init_dram.h"
#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h"
#include <cpg_register.h>
#include <san.h>
#include <gpio.h>
/* Time analysis */
#include <scmt.h>
#include <scmt_checkpoint.h>
#if (0 == (MEASURE_TIME))
#define store_time_checkpoint(x,y)
#define print_time_checkpoints(x)
#endif
#include <android_ab.h>
#define ICISTP_BASE (BASE_ICISTP_ADDR)
#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U)
#define EDC_BASE (BASE_ECM_ADDR)
#define EDCSTRT20 (EDC_BASE + 0x80C0U)
#define TIDSTRT20 (EDC_BASE + 0x81C0U)
/* SYSC register */
#define SYSC_BASE (BASE_SYSC_ADDR)
#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */
#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */
#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */
#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */
/* Power Domain Register */
#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */
#define SYSC_PDR42 (0x0A80U) /* A2CN0 */
#define SYSC_PDR43 (0x0AC0U) /* A3IR */
#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */
#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41))
#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42))
#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43))
#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */
#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41))
#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42))
#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43))
#define PDR_MAX (3U) /* Number of PDR's to be set */
#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */
#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */
#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */
#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */
#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */
#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */
#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */
#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */
#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */
#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */
#define RGID_SET_RGID_FIN_FLG_VAL (0x64U)
#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER)
#define HOTPLUG_MAGIC_NUM (0x853F912EU)
#else
#define HOTPLUG_MAGIC_NUM (0x00000000U)
#endif
__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U,
0x00000000U, HOTPLUG_MAGIC_NUM};
/* Prototype functions */
#include <san.h>
static void wa_for_v4h2(void);
static void set_leak_current_reduce_for_v4h2x(void);
uint32_t loader_main(void)
{
uint32_t boot_ca_id;
uint32_t auth_count = 0U;
uint32_t boot_cpu;
uint32_t tmp;
__attribute__((__unused__)) uint32_t loop = 0U;
__attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */
LOAD_INFO li[MAX_PLACED] = {0U};
#if (1 == (MEASURE_TIME))
scmt_module_start();
store_time_checkpoint("loader_main", 0);
#endif
#if (SAN_ENABLE == 1)
/* Appendix A Sequence of Activation
step (5) Stop RWDT and System WDT */
rwdt_init(0);
swdt_init(0);
#endif
/*****************************************************************************
* Initialize Hardware
*****************************************************************************/
/* IP initialize, step(6) of Sequence of Activation? */
ip_init();
#if (ECM_ERROR_ENABLE == 1)
ecm_init_setting();
#endif /* ECM_ERROR_ENABLE == 1 */
/*****************************************************************************
* Work Around for APMU
*****************************************************************************/
wa_setting_apmu();
/*****************************************************************************
* Output boot message
*****************************************************************************/
print_boot_msg();
/*****************************************************************************
* WA for V4H ver2.0
*****************************************************************************/
uint32_t Prr_Cut;
Prr_Cut = mem_read32(PRR) & PRR_CUT_MASK;
if (Prr_Cut >= PRR_PRODUCT_20)
{
/* IPL setting for V4H v2.x leak current reduce */
set_leak_current_reduce_for_v4h2x();
wa_for_v4h2();
}
/* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */
tmp = mem_read32(BASE_APMU_ADDR + 0x68U);
tmp = tmp & ~(1 << 29);
mem_write32((BASE_APMU_ADDR + 0x68U), tmp);
#if (ECM_ENABLE == 1)
/*****************************************************************************
* ECC and EDC Initialize
*****************************************************************************/
edc_axi_enable();
edc_vram_enable();
#endif
#if (SAN_ENABLE == 1)
/* step(7) Initial Checks */
SM_6_3_1();
SM_6_3_2();
SM_5_3_6();
SM_5_1();
SM_6_23();
SM_4_21();
SM_5_1_6();
SM_5_2_6();
SM_6_2();
SM_6_11();
SM_6_14_6();
SM_6_22();
SM_6_24_2();
SM_6_24_3();
SM_6_29();
SM_6_30();
PMIC_SM_27A();
PMIC_SM_27B();
PMIC_SM_27C();
PMIC_SM_27D();
/* step(8) start the timers for Periodical checks */
check_SoC_Activation();
/* step(9) send the first WDT message */
PMIC_SM_12_wdt();
#endif
/*****************************************************************************
* Setting Access protection
*****************************************************************************/
/* Region ID access protection */
rgid_protection();
ram_protection();
/* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */
set_master_rgid_4_tfr_mod();
/*****************************************************************************
* Clear ECM Status Bits
*****************************************************************************/
/* Check the V4H is v1.0 */
if(Prr_Cut == PRR_PRODUCT_10)
{
clear_ecm_st_axi();
}
store_time_checkpoint("init_done", 0);
/*****************************************************************************
* Load Certficate from QSPI
*****************************************************************************/
int slot;
slot = ab_select_slot();
#ifndef STRICT_AB_BOOTING
#warning "STRICT_AB_BOOTING is not defined, using default slot selection"
if (slot < 0) {
ERROR("Failed to select slot: %d, using default slot\n", slot);
slot = 0;
} else
#endif
NOTICE("slot: %d\n", slot);
/* Load content certificate */
ca_load_num = load_content_cert(slot);
store_time_checkpoint("load_cert_done",
CONTENT_CERT_INFO_SIZE + ca_load_num*CONTENT_CERT_SIZE);
/* Get load information */
load_init(li, slot);
/* verify the each content certs before Image load */
preload_verify_cntcert(li);
/*****************************************************************************
* Authenticate Software minimum version table
*****************************************************************************/
auth_min_ver_tbl(li);
store_time_checkpoint("verify_cert_done", 0);
/*****************************************************************************
* Load Cx IPL from Flash
*****************************************************************************/
/* Start loading Cx IPL image from Flash into SDRAM */
load_image(&li[CA_PROGRAM_ID]);
/* The CA image to boot is CA IPL. */
boot_ca_id = CA_PROGRAM_ID;
/* boot CPU is CR */
boot_cpu = RCAR_PWR_TARGET_CR;
/* finish loading Cx IPL */
load_end();
store_time_checkpoint("load_Cx_IPL_done", li[CA_PROGRAM_ID].image_size);
#if (BOOT_TIME_CHECK != 0)
gpio_N1305(2);
#endif
/* Set V4H_SDRDES_1V8(GP1_23) to high before optee start */
gpio_V4H_SERDES_1V8_en(1);
/*****************************************************************************
* Load Secure Firmware from Flash
*****************************************************************************/
/* Start loading Secure FW image from Flash into SDRAM */
load_image(&li[SECURE_FW_ID]);
store_time_checkpoint("load_Secure_FW_start (DMA-background)", li[SECURE_FW_ID].image_size);
/* Authenticate of CA Program#n */
rom_secureboot(&li[boot_ca_id + auth_count]);
store_time_checkpoint("verify_Cx_IPL_done", 0);
/* SystemRAM has an undefined initial value, clear the address of
* the SystemRAM that is going to store set finish flag of RGID. */
mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU);
/* Before Boot CPU, Set the division ratio for CPU operating frequency */
adj_cr_variant_freq();
/* boot CA */
arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr);
store_time_checkpoint("start_Cx_IPL_done", 0);
/* finish loading Secure Firmware */
load_end();
store_time_checkpoint("load_Secure_FW_done", 0);
/* load_secure data(for ICUMXB) */
load_securedata(SECURE_FW_ID, slot);
store_time_checkpoint("load_Secure_Data_start (DMA-background)", SECUREDATA_SIZE);
/* Authenticate of Secure Firmware */
rom_secureboot(&li[SECURE_FW_ID]);
store_time_checkpoint("verify_Secure_FW_done", 0);
/* finish loading secure data */
load_end();
store_time_checkpoint("load_Secure_Data_done", 0);
#if (BOOT_TIME_CHECK != 0)
gpio_N1305(2);
#endif
/* Finally Protection setting */
rgid_protection_final();
/* set RGID setting finish flag.
* because polling from CX 2nd IPL. */
mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL);
#if (ECM_ENABLE == 1)
/* Notice the ecc enable */
NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n");
#endif
NOTICE("Load finish.\n");
// ip_release();
store_time_checkpoint("done (Jumping to [SECURE_FW_ID].boot_addr)", 0);
print_time_checkpoints();
return get_cfremap_addr(li[SECURE_FW_ID].boot_addr);
}
/* End of function loader_main(void) */
void clear_ecm_st_axi(void)
{
mem_write32(ICISTPSTPER000,0x30U);
mem_write32(EDCSTRT20, 0x10U);
mem_write32(TIDSTRT20, 0x12U);
}/* End of function clear_ecm_st_axi(void) */
static void wa_for_v4h2(void)
{
uint32_t tmp;
/* 1. Release of pseudo power shutdown */
/* Process moved to function set_leak_current_reduce_for_v4h2x(). */
/* 2. Reset ON for A2CN0 and Reset OFF for A2CN0 */
tmp = mem_read32(BASE_CPG_ADDR + 0x2C00U); /* Software Reset Register 0 (SRCR0) */
tmp = tmp | (0x1U << 23U);
mem_write32(CPG_CPGWPR, ~tmp);
mem_write32((BASE_CPG_ADDR + 0x2C00U),tmp);
tmp = mem_read32(BASE_CPG_ADDR + 0x2C80U); /* Software Reset Clearing Register 0 (SRSTCLR0) */
tmp = tmp | (0x1U << 23U);
mem_write32(CPG_CPGWPR, ~tmp);
mem_write32((BASE_CPG_ADDR + 0x2C80U),tmp);
/* Unlock the ECM register protect. */
mem_write32(ECMWPCNTR, 0xACCE0001);
/* 3. ECM Enable */
tmp = mem_read32(BASE_ECM_ADDR + 0x50018U); /* ECM Error Control Register 6 (ECMERRCTLR6) */
tmp = tmp | (0xfU << 24U);
mem_write32((BASE_ECM_ADDR + 0x50018U),tmp);
/* Lock the ECM register protect. */
mem_write32(ECMWPCNTR, 0xACCE0000U);
}/* End of function wa_for_v4h2(void) */
static void set_leak_current_reduce_for_v4h2x(void)
{
uint32_t reg;
const uint32_t pdrsr_tbl[PDR_MAX] = { /* SYSC PDRSR register table */
SYSC_PDRSR43, /* A3IR */
SYSC_PDRSR42, /* A2CN0 */
SYSC_PDRSR41 /* A1CNN0 */
};
const uint32_t pdroncr_tbl[PDR_MAX] = { /* SYSC PDRONCR register table */
SYSC_PDRONCR43, /* A3IR */
SYSC_PDRONCR42, /* A2CN0 */
SYSC_PDRONCR41 /* A1CNN0 */
};
/* Power ON / OFF process complete interrupt enable for PDR41-PDR43 */
reg = mem_read32(SYSC_SYSCIER1);
reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43);
mem_write32(SYSC_SYSCIER1, reg);
INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1));
/* MASK complete interrupt request to INTC for PDR41-PDR43 */
reg = mem_read32(SYSC_SYSCIMR1);
reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43);
mem_write32(SYSC_SYSCIMR1, reg);
INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1));
for(uint32_t loop = 0U; loop < PDR_MAX; loop++)
{
/* Check PDRn Power on state */
reg = mem_read32(pdrsr_tbl[loop]);
INFO("PDRSR(0x%08x) = %08x\n",pdrsr_tbl[loop],reg);
reg &= SYSC_PDRSR_PWR_MASK;
/* Only when the Power state of PDRn is OFF, the Power On Request is processed */
if((reg == SYSC_PDRSR_PWROFF) == true)
{
/* Wait until SYSC is in Not busy status */
do{
/* Get SYSC processing Power ON / OFF status */
reg = mem_read32(SYSC_SYSCSR);
INFO("SYSCSR(0x%08x) = %08x\n", SYSC_SYSCSR, reg);
reg &= SYSCSR_BUSY_MASK;
} while((reg == SYSCSR_NOT_BUSY) != true);
/* PDRn Power ON request */
mem_write32(pdroncr_tbl[loop], SYSC_PDRONCR_PWRON);
INFO("PDRONCRn(0x%08x) = %08x\n",pdroncr_tbl[loop],mem_read32(pdroncr_tbl[loop]));
/* Power ON process complete interrupt status for PDR41-PDR43 */
do{
reg = mem_read32(SYSC_SYSCISCR1);
INFO("SYSCISCR1(0x%08x) = %08x\n", SYSC_SYSCISCR1, reg);
reg &= (SYSC_BIT_PDR43 >> loop); /* loop = 0:PDR43 1:PDR42 2:PDR41 */
} while((reg !=SYSC_PDR_PWR_PROC) != true);
/* Clear Power ON process complete interrupt status for PDR41-PDR43 */
mem_write32(SYSC_SYSCISCR1, reg);
INFO("SYSCISCR1(0x%08x) = %08x\n",SYSC_SYSCISCR1,mem_read32(SYSC_SYSCISCR1));
}
}
/* Power ON / OFF process complete interrupt disable for PDR41-PDR43 */
reg = mem_read32(SYSC_SYSCIER1);
reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43);
mem_write32(SYSC_SYSCIER1, reg);
INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1));
/* MASK complete interrupt request to INTC for PDR41-PDR43 */
reg = mem_read32(SYSC_SYSCIMR1);
reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43);
mem_write32(SYSC_SYSCIMR1, reg);
INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1));
}

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main function for V4M
******************************************************************************/
/******************************************************************************
* @file loader_main_v4m.c
* - Version : 0.04
* @brief 1. IP initialization.
* 2. DMA transfer the binary image from Flash to RAM.
* 3. Authentication of the transferred image.
* 4. Boot CR and CA core.
* 5. Release of used resources.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
* : 14.11.2023 0.02 Fixed file header path of ECC.
* : 16.11.2023 0.03 Added avs_low_power_mode_setting function
* calling.
* : 07.04.2025 0.04 Added ecm_init_setting function calling.
*****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <loader_main.h>
#include <loader_main_common.h>
#include <cpu_on.h>
#include <image_load.h>
#include <ip_control.h>
#include <qos.h>
#include <rcar_def.h>
#include <remap.h>
#include <remap_register.h>
#include <rom_api.h>
#include <mem_io.h>
#include <log.h>
#include <wdt.h>
#include <micro_wait.h>
#include <rtvram.h>
#include <ram_def.h>
#include <access_protection.h>
#include <avs.h>
#include "rcar_def.h"
#if (ECM_ERROR_ENABLE == 1)
#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h"
#endif /* ECM_ERROR_ENABLE == 1 */
/* Provided code */
#include "../ip/ddr/boot_init_dram.h"
#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h"
#include <cpg_register.h>
#define ICISTP_BASE (BASE_ICISTP_ADDR)
#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U)
#define EDC_BASE (BASE_ECM_ADDR)
#define EDCSTRT20 (EDC_BASE + 0x80C0U)
#define TIDSTRT20 (EDC_BASE + 0x81C0U)
/* SYSC register */
#define SYSC_BASE (BASE_SYSC_ADDR)
#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */
#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */
#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */
#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */
/* Power Domain Register */
#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */
#define SYSC_PDR42 (0x0A80U) /* A2CN0 */
#define SYSC_PDR43 (0x0AC0U) /* A3IR */
#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */
#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41))
#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42))
#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43))
#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */
#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41))
#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42))
#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43))
#define PDR_MAX (3U) /* Number of PDR's to be set */
#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */
#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */
#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */
#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */
#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */
#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */
#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */
#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */
#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */
#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */
#define RGID_SET_RGID_FIN_FLG_VAL (0x64U)
#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER)
#define HOTPLUG_MAGIC_NUM (0x853F912EU)
#else
#define HOTPLUG_MAGIC_NUM (0x00000000U)
#endif
__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U,
0x00000000U, HOTPLUG_MAGIC_NUM};
uint32_t loader_main(void)
{
uint32_t boot_ca_id;
uint32_t auth_count = 0U;
uint32_t boot_cpu;
uint32_t tmp;
__attribute__((__unused__)) uint32_t loop = 0U;
__attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */
LOAD_INFO li[MAX_PLACED] = {0U};
/*****************************************************************************
* Initialize Hardware
*****************************************************************************/
/* IP initialize */
ip_init();
#if (ECM_ERROR_ENABLE == 1)
ecm_init_setting();
#endif /* ECM_ERROR_ENABLE == 1 */
#if (ECM_ENABLE == 1)
/*****************************************************************************
* ECC and EDC Initialize
*****************************************************************************/
edc_axi_enable();
edc_vram_enable();
#endif
/*****************************************************************************
* Work Around for APMU
*****************************************************************************/
wa_setting_apmu();
/*****************************************************************************
* Output boot message
*****************************************************************************/
print_boot_msg();
/*****************************************************************************
* Low Power Mode setting for V4M
*****************************************************************************/
avs_low_power_mode_setting();
/*****************************************************************************
* WA for V4M
*****************************************************************************/
/* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */
tmp = mem_read32(BASE_APMU_ADDR + 0x68U);
tmp = tmp & ~(1U << 29U);
mem_write32((BASE_APMU_ADDR + 0x68U), tmp);
/*****************************************************************************
* Setting Access protection
*****************************************************************************/
/* Region ID access protection */
rgid_protection();
ram_protection();
/* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */
set_master_rgid_4_tfr_mod();
/*****************************************************************************
* Load Certficate from QSPI
*****************************************************************************/
/* Load content certificate */
ca_load_num = load_content_cert();
/* Get load information */
load_init(li);
/* verify the each content certs before Image load */
preload_verify_cntcert(li);
/*****************************************************************************
* Authenticate Software minimum version table
*****************************************************************************/
auth_min_ver_tbl(li);
/*****************************************************************************
* Load Cx IPL from Flash
*****************************************************************************/
/* Start loading Cx IPL image from Flash into SDRAM */
load_image(&li[CA_PROGRAM_ID]);
/* The CA image to boot is CA IPL. */
boot_ca_id = CA_PROGRAM_ID;
/* boot CPU is CR */
boot_cpu = RCAR_PWR_TARGET_CR;
/* finish loading Cx IPL */
load_end();
/*****************************************************************************
* Load Secure Firmware from Flash
*****************************************************************************/
/* Start loading Secure FW image from Flash into SDRAM */
load_image(&li[SECURE_FW_ID]);
/* Authenticate of CA Program#n */
rom_secureboot(&li[boot_ca_id + auth_count]);
/* SystemRAM has an undefined initial value, clear the address of
* the SystemRAM that is going to store set finish flag of RGID. */
mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU);
/* Before Boot CPU, Set the division ratio for CPU operating frequency */
adj_cr_variant_freq();
/* boot CA */
arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr);
/* finish loading Secure Firmware */
load_end();
/* load_secure data(for ICUMXB) */
load_securedata(SECURE_FW_ID);
/* Authenticate of Secure Firmware */
rom_secureboot(&li[SECURE_FW_ID]);
/* finish loading secure data */
load_end();
/* Finally Protection setting */
rgid_protection_final();
/* set RGID setting finish flag.
* because polling from CX 2nd IPL. */
mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL);
#if (ECM_ENABLE == 1)
/* Notice the ecc enable */
NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n");
#endif
NOTICE("Load finish.\n");
ip_release();
return get_cfremap_addr(li[SECURE_FW_ID].boot_addr);
}
/* End of function loader_main(void) */