add IPL
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218
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.c
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218
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.c
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2015-2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : DMA driver
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******************************************************************************/
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/******************************************************************************
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* @file dma.c
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* - Version : 0.05
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* @brief RT-DMAC driver.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 15.10.2021 0.01 First Release
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* : 10.02.2022 0.02 Add dma_start_xbyte function.
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* : 18.03.2022 0.03 Modify to read modify write when write to
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* : register.
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* : 29.03.2022 0.04 Modify magic number to definition.
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* : 09.11.2022 0.05 License notation change.
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*****************************************************************************/
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#include <stdint.h>
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#include <stddef.h>
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#include <mem_io.h>
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#include <rpc_register.h>
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#include <cpg_register.h>
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#include <rpc.h>
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#include <wdt.h>
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#include <log.h>
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/*
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* from flash_writer's reg_rcar.h
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*/
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/* RT-DMA Control */
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#define RTDMACTL_BASE (BASE_RTDMACTL_ADDR)
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#define RTDMAC_RDMOR (RTDMACTL_BASE + 0x0060U) /* R/W 16 DMA operation register (for channels 0 to 15) */
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/* RT-DMAC0(for RPC) */
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#define RTDMAC_BASE (BASE_RTDMA0_ADDR)
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#define RTDMAC_RDMSEC (RTDMAC_BASE + 0x00B0U) /* R/W 32 DMA secure control register (for channels 0 to 15) */
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#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x0000U + (0x80U * (x))) /* R/W 32 DMA source address register_0 */
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#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x0004U + (0x80U * (x))) /* R/W 32 DMA destination address register_0 */
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#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x0008U + (0x80U * (x))) /* R/W 32 DMA transfer count register_0 */
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#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x000CU + (0x80U * (x))) /* R/W 32 DMA channel control register_0 */
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#include "dma2.h"
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#define RDMOR_INITIAL (0x0301U)
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#define DMACH (0U)
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#define RDMTCR_CNT_SHIFT (6U)
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#define RDMCHCR_TRN_MODE (0x00105409U)
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#define RDMCHCR_TRN_MODE_SRC_FIX (0x00104409U)
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#define RDMCHCR_TRN_MODE_1BYTE (0x00005401U)
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#define RDMCHCR_TE_BIT (0x00000002U)
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#define TE_FLAG (0x00000000U)
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#define RDMCHCR_CAE_BIT (0x80000000U)
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#define RDMCHCR_CAE_BIT_NOERROR (0x00000000U)
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#define RDMCHCR_CAIE_BIT (0x40000000U)
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#define RDMCHCR_DPM_BIT (0x30000000U)
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#define RDMCHCR_RPT_BIT (0x0F000000U)
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#define RDMCHCR_WAIT_BIT (0x00800000U)
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#define RDMCHCR_DPB_BIT (0x00400000U)
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#define RDMCHCR_DSE_BIT (0x00080000U)
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#define RDMCHCR_DSIE_BIT (0x00040000U)
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#define RDMCHCR_DM_BIT (0x0000C000U)
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#define RDMCHCR_SM_BIT (0x00003000U)
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#define RDMCHCR_RS_BIT (0x00000F00U)
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#define RDMCHCR_TS_BIT (0x00300018U)
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#define RDMCHCR_IE_BIT (0x00000004U)
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#define RDMCHCR_TE_BIT (0x00000002U)
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#define RDMCHCR_DE_BIT (0x00000001U)
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#define RDMCHCR_CONF_MASK (RDMCHCR_TS_BIT | RDMCHCR_DM_BIT | RDMCHCR_SM_BIT \
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| RDMCHCR_RS_BIT | RDMCHCR_DE_BIT)
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#define RDMCHCR_DESCRIPTOR_CONF_MASK (RDMCHCR_DPM_BIT | RDMCHCR_RPT_BIT | RDMCHCR_WAIT_BIT | RDMCHCR_DPB_BIT)
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#define RDMCHCR_INTERRUPT_MASK (RDMCHCR_CAIE_BIT | RDMCHCR_DSIE_BIT | RDMCHCR_IE_BIT)
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#define RDMCHCR_FLAG_MASK (RDMCHCR_CAE_BIT | RDMCHCR_DSE_BIT | RDMCHCR_TE_BIT)
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#define RDMCHCR_ALL_BIT_MASK (RDMCHCR_CONF_MASK | RDMCHCR_DESCRIPTOR_CONF_MASK \
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| RDMCHCR_INTERRUPT_MASK | RDMCHCR_FLAG_MASK)
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#define CMNSR_TEND (0x00000001U)
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#define RDMTCR_UPPER_MASK (0xFF000000U)
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/* fraction mask for 64-byte units */
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#define FRACTION_MASK_64_BYTE (0x0000003FU)
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/* fraction mask for 256-byte units */
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#define FRACTION_MASK_256_BYTE (0x000000FFU)
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void dma2_init(void)
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{
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uint32_t reg;
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/* DMA transfer disabled */
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reg = mem_read32(RTDMAC_RDMCHCR(DMACH));
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reg &= ~(RDMCHCR_ALL_BIT_MASK);
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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/* DMA operation */
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mem_write16(RTDMAC_RDMOR, RDMOR_INITIAL);
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/* DMA secure control register */
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reg = mem_read32(RTDMAC_RDMSEC);
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reg |= ((uint32_t)1U << DMACH);
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mem_write32(RTDMAC_RDMSEC, reg);
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}
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/* End of function dma_init */
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void dma2_start(uint32_t dst, uint32_t src, uint32_t len, uint32_t mode)
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{
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uint32_t reg;
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if (((dst & FRACTION_MASK_64_BYTE) != 0U) || ((src & FRACTION_MASK_64_BYTE) != 0U))
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{
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/* dst or src are not 64-bit alignment. */
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ERROR("not 64-bit alignment in DMA(2) transfer\n");
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while(1)
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{
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; /* panic */
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}
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}
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/* round up 256 byte alignment */
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len += FRACTION_MASK_256_BYTE;
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len &= (~(uint32_t)(FRACTION_MASK_256_BYTE));
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/* DMA destination address */
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mem_write32(RTDMAC_RDMDAR(DMACH), dst);
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/* DMA source address */
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mem_write32(RTDMAC_RDMSAR(DMACH), src);
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/* DMA 64bytes-unit transfer count */
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mem_write32(RTDMAC_RDMTCR(DMACH), ((len >> RDMTCR_CNT_SHIFT) & (~RDMTCR_UPPER_MASK)));
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/* DMA channel control */
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reg = mem_read32(RTDMAC_RDMCHCR(DMACH));
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if (mode == DMA_MODE_SRC_FIX)
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{
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reg |= RDMCHCR_TRN_MODE_SRC_FIX;
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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}
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else
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{
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reg |= RDMCHCR_TRN_MODE;
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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}
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}
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/* End of function dma_start */
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void dma2_start_xbyte(uint32_t dst, uint32_t src, uint32_t len, uint32_t trns_unit)
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{
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uint32_t reg;
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/* DMA destination address */
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mem_write32(RTDMAC_RDMDAR(DMACH), dst);
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/* DMA source address */
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mem_write32(RTDMAC_RDMSAR(DMACH), src);
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/* DMA transfer count */
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mem_write32(RTDMAC_RDMTCR(DMACH), ((len >> trns_unit) & (~RDMTCR_UPPER_MASK)));
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/* DMA channel control */
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reg = mem_read32(RTDMAC_RDMCHCR(DMACH));
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if (trns_unit == TRANS_UNIT_1BYTE)
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{
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/* DMA channel control (transfer unit is 1 byte)*/
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reg |= RDMCHCR_TRN_MODE_1BYTE;
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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}
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if (trns_unit == TRANS_UNIT_64BYTES)
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{
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/* DMA channel control (transfer unit is 64 bytes) */
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reg |= RDMCHCR_TRN_MODE;
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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}
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}
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/* End of function dma_start_byte */
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void dma2_end(void)
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{
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uint32_t reg;
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/* Check end of DMA transfer. */
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do
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{
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wdt_restart();
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/* Check error of DMA transfer */
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if ((mem_read32(RTDMAC_RDMCHCR(DMACH)) & RDMCHCR_CAE_BIT) != RDMCHCR_CAE_BIT_NOERROR)
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{
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ERROR("DMA(2) - Channel Address Error\n");
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while(1)
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{
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; /* panic */
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}
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}
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}
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while ((mem_read32(RTDMAC_RDMCHCR(DMACH)) & RDMCHCR_TE_BIT) == TE_FLAG);
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/* DMA transfer disabled */
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reg = mem_read32(RTDMAC_RDMCHCR(DMACH));
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reg &= ~(RDMCHCR_ALL_BIT_MASK);
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mem_write32(RTDMAC_RDMCHCR(DMACH), reg);
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rpc_end_state_check();
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}
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/* End of function dma_end */
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