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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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16
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h Normal file
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/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved.
*/
#ifndef __BOOT_INIT_DRAM_
#define __BOOT_INIT_DRAM_
extern int32_t InitDram(void);
#define INITDRAM_OK (0)
#define INITDRAM_NG (0xffffffff)
#define INITDRAM_ERR_I (0xffffffff)
#define INITDRAM_ERR_O (0xfffffffe)
#define INITDRAM_ERR_T (0xfffffff0)
#endif /* __BOOT_INIT_DRAM_*/

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/ddr.mk Normal file
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#
# Copyright (c) 2015-2022, Renesas Electronics Corporation All rights reserved.
#
OBJ_FILE += ip/ddr/s4/lpddr4x/boot_init_dram.o
OBJ_FILE += ip/ddr/dram_sub_func.o

17
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c Normal file
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/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation All rights reserved.
*/
#include <stdint.h>
#include "dram_sub_func.h"
void dram_get_boot_status(uint32_t *status)
{
*status = DRAM_BOOT_STATUS_COLD;
}
int32_t dram_update_boot_status(uint32_t status)
{
int32_t ret = 0;
return ret;
}

16
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h Normal file
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/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved.
*/
#ifndef DRAM_SUB_FUNC_H_
#define DRAM_SUB_FUNC_H_
#define DRAM_BOOT_STATUS_COLD (0U)
#define DRAM_BOOT_STATUS_WARM (1U)
#define DRAM_UPDATE_STATUS_ERR (-1)
void dram_get_boot_status(uint32_t *status);
int32_t dram_update_boot_status(uint32_t status);
#endif /* DRAM_SUB_FUNC_H_ */

2243
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c Normal file
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254
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c Normal file
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/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DRAM Param setting
******************************************************************************/
#define JS2_DERATE 0
#define DBSC_REFINT 1920 /* Average periodic refresh interval/Average Refresh Interval [ns] */
#define DBSC_REFINTS 0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
#define REWT_TRAINING_INTERVAL 20000 /* Periodic-WriteDQ Training Interval [us] */
/*******************************************************************************
* NUMBER OF BOARD CONFIGRATION
* PLEASE DEFINE
******************************************************************************/
#define BOARDNUM 3 /* Add User platform BOARD */
/*******************************************************************************
* PLEASE SET board number or board judge function
******************************************************************************/
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t _board_judge(void);
static uint32_t boardcnf_get_brd_type(void) {
return _board_judge();
}
#else /* BOARD_JUDGE_AUTO */
static uint32_t boardcnf_get_brd_type(void) {
return (0);
}
#endif /* BOARD_JUDGE_AUTO */
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
struct _boardcnf_ch {
/*
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
0xff...NO_MEMORY
*/
uint8_t ddr_density[CS_CNT];
/* SoC caX([5][4][3][2][1][0]) -> MEM caY: */
uint32_t ca_swap;
/* SoC dqsX([3][2][1][0]) -> MEM dqsY: */
uint16_t dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
uint32_t dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
uint8_t dm_swap[SLICE_CNT];
};
struct _boardcnf {
/* ch in use */
uint16_t phyvalid;
/* Read vref (SoC) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_r;
/* Write vref (MR14) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_w;
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_ca;
struct _boardcnf_ch ch[2];
};
static const struct _boardcnf boardcnfs[BOARDNUM] = {
/*
* boardcnf[0] RENESAS S4 Spider (16Gbit 2rank)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x243510U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x21706345, 0x23510746 },
/* dm_swap[] */ { 0x08, 0x08 }
},
/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x345210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x30124675, 0x53126047 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
},
/*
* boardcnf[1] RENESAS S4-N Spider (16Gbit 2rank)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x243510U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x21705634, 0x23516048 },
/* dm_swap[] */ { 0x08, 0x07 }
},
/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x345201U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x03124675, 0x35126047 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
},
/*
* boardcnf[2] RENESAS S4(2ch)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ {
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x00543210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x76543210, 0x76543210 },
/* dm_swap[] */ { 0x08, 0x08 }
},
/* ch[1] */ {
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x00543210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x76543210, 0x76543210 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
}
};
/*******************************************************************************
* EXTAL CLOCK DEFINITION
* PLEASE DEFINE HOW TO JUDGE BORAD CLK
******************************************************************************/
/*
* RENESAS SPIDER BOARD EXAMPLE
* judge by md14/md13
*
* 16.00MHz CLK,DIV= 48,3 (md14,md13==0,0)
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
* 40.00MHz CLK,DIV=120,3 (md14,md13==1,1)
*/
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) {
uint32_t md;
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3;
switch(md) {
case 0x0 : *clk = 48; *div = 3; break; /* 48 / 3 = 16.00MHz */
case 0x1 : *clk = 60; *div = 3; break; /* 60 / 3 = 20.00MHz */
/* case 0x2 : *clk = 75; *div = 3; break; */ /* Not supported */
case 0x3 : *clk =120; *div = 3; break; /* 120 / 3 = 40.00MHz */
}
(void)brd;
}
/*******************************************************************************
* DDR MBPS TARGET
* PLEASE DEFINE HOW TO JUDGE DDR BPS
******************************************************************************/
/*
DDRxxxx (judge by md17) : Mbps
SSCG enable / disable for PLL1 (judge by md37/md36)
*/
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) {
uint32_t md;
uint32_t sscg;
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x01U;
sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U;
switch(sscg) {
case 0x0 :
switch(md) {
case 0x0 : *mbps = 3200; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x1 :
switch(md) {
case 0x0 : *mbps = 3120; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x2 :
switch(md) {
case 0x0 : *mbps = 3040; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x3 :
switch(md) {
case 0x0 : *mbps = 3000; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
}
(void)brd;
}
#ifdef BOARD_JUDGE_AUTO
/*******************************************************************************
* SAMPLE board detect function
******************************************************************************/
static uint32_t _board_judge(void) {
uint32_t brd;
brd = 0; /* spider (16Gbit 2rank)*/
return brd;
}
#endif

73
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h Normal file
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/*******************************************************************************
* File Name : boot_init_dram_config.h
* Version : 1.0
* Description : This file containing structure definitions for board settings
******************************************************************************/
/*****************************************************************************
* History : Please refer the readme.txt
*
******************************************************************************/
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* © 2020-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_CONFIG
#define BOOT_INIT_DRAM_CONFIG
#include <stdint.h>
#include "boot_init_dram_regdef.h"
/*******************************************************************************
* DRAM Param setting
* this parameter is depending on the user
******************************************************************************/
#define JS2_DERATE 0
#define BOARDNUM 5
#define USE_BOARD 0
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
struct board_cfg_t
{
uint32_t phyvalid;
uint32_t vref_r;
uint32_t vref_w;
uint32_t vref_ca;
uint32_t ddr_density[CH_CNT][CS_CNT];
uint32_t ca_swap[CH_CNT];
uint32_t dqs_swap[CH_CNT];
uint32_t dq_swap[CH_CNT][SLICE_CNT];
uint32_t dm_swap[CH_CNT][SLICE_CNT];
};
void judge_board_clk_freq(uint32_t* board_clk, uint32_t* board_clkdiv, uint32_t* board_clkdiva);
void judge_ddr_ope_freq(uint32_t* ddr_mbps, uint32_t* ddr_mbpsdiv);
void judge_bus_clk_freq(uint32_t* bus_mbps, uint32_t* bus_mbpsdiv, const uint32_t* board_clk, const uint32_t* board_clkdiv);
extern const struct board_cfg_t board_cfg[BOARDNUM];
#endif /* BOOT_INIT_DRAM_CONFIG */

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h Normal file
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/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.30rc7"
#define DRAM_CH_CNT 0x02
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 3 - 10 - 1), 3, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_Z0CKKSCR (CPG_BASE + 0x08A8U)
#define CPG_Z1CKKSCR (CPG_BASE + 0x08ACU)
#define CPG_SRST4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */
#define PRR_PRODUCT_12 (0x00000002U) /* ver 1.2 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_BASE (BASE_DBSC_ADDR)
#else
#define DBSC_BASE (0xE6790000U)
#endif
#define DBSC_DBSYSCONF0 (DBSC_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_BASE + 0x0004U)
#define DBSC_DBSYSCONF1A (DBSC_BASE + 0x0008U)
#define DBSC_DBSYSCONF2 (DBSC_BASE + 0x000CU)
#define DBSC_DBPHYCONF0 (DBSC_BASE + 0x0010U)
#define DBSC_DBSYSCONF2A (DBSC_BASE + 0x0014U)
#define DBSC_DBKIND (DBSC_BASE + 0x0020U)
#define DBSC_DBKINDA (DBSC_BASE + 0x0024U)
#define DBSC_DBMEMCONF(ch, cs) (DBSC_BASE + 0x0030U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs)
#define DBSC_DBMEMCONF_0_0 (DBSC_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch, cs) (DBSC_BASE + 0x0070U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs)
#define DBSC_DBMEMCONF_0_0A (DBSC_BASE + 0x0070U)
#define DBSC_DBMEMCONF_0_1A (DBSC_BASE + 0x0074U)
#define DBSC_DBMEMCONF_0_2A (DBSC_BASE + 0x0078U)
#define DBSC_DBMEMCONF_0_3A (DBSC_BASE + 0x007CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_BASE + 0x0080U)
#define DBSC_DBMEMCONF_1_1A (DBSC_BASE + 0x0084U)
#define DBSC_DBMEMCONF_1_2A (DBSC_BASE + 0x0088U)
#define DBSC_DBMEMCONF_1_3A (DBSC_BASE + 0x008CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_BASE + 0x0090U)
#define DBSC_DBMEMCONF_2_1A (DBSC_BASE + 0x0094U)
#define DBSC_DBMEMCONF_2_2A (DBSC_BASE + 0x0098U)
#define DBSC_DBMEMCONF_2_3A (DBSC_BASE + 0x009CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_BASE + 0x00A0U)
#define DBSC_DBMEMCONF_3_1A (DBSC_BASE + 0x00A4U)
#define DBSC_DBMEMCONF_3_2A (DBSC_BASE + 0x00A8U)
#define DBSC_DBMEMCONF_3_3A (DBSC_BASE + 0x00ACU)
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_BASE + 0x0108U)
#define DBSC_DBACEN (DBSC_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_BASE + 0x0304U)
#define DBSC_DBTR3 (DBSC_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_BASE + 0x0368U)
#define DBSC_DBBL (DBSC_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_BASE + 0x0404U)
#define DBSC_DBRFCNF1 (DBSC_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_BASE + 0x052CU)
#define DBSC_DBDFISTAT(ch) (DBSC_BASE + 0x0600U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBDFISTAT_0 (DBSC_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_BASE + 0x0604U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBDFICNT_0 (DBSC_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_BASE + 0x06C4U)
#define DBSC_DBPDCNT2(ch) (DBSC_BASE + 0x0618U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDCNT2_0 (DBSC_BASE + 0x0618U)
#define DBSC_DBPDCNT2_1 (DBSC_BASE + 0x0658U)
#define DBSC_DBPDCNT2_2 (DBSC_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_BASE + 0x06D8U)
#define DBSC_DBPDCNT3(ch) (DBSC_BASE + 0x061CU + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDCNT3_0 (DBSC_BASE + 0x061CU)
#define DBSC_DBPDCNT3_1 (DBSC_BASE + 0x065CU)
#define DBSC_DBPDCNT3_2 (DBSC_BASE + 0x069CU)
#define DBSC_DBPDCNT3_3 (DBSC_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_BASE + 0x0620U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDLK_0 (DBSC_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_BASE + 0x0624U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDRGA_0 (DBSC_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_BASE + 0x0628U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDRGD_0 (DBSC_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_BASE + 0x06E8U)
#define DBSC_DBPDSTAT(ch) (DBSC_BASE + 0x0630U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDSTAT_0 (DBSC_BASE + 0x0630U)
#define DBSC_DBPDSTAT_1 (DBSC_BASE + 0x0670U)
#define DBSC_DBPDSTAT_2 (DBSC_BASE + 0x06B0U)
#define DBSC_DBPDSTAT_3 (DBSC_BASE + 0x06F0U)
#define DBSC_DBPDSTAT1(ch) (DBSC_BASE + 0x0634U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBBUS0CNF0 (DBSC_BASE + 0x0800U)
#define DBSC_DBBUS0CNF1 (DBSC_BASE + 0x0804U)
#define DBSC_DBBCAMDIS (DBSC_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)

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/*******************************************************************************
* Copyright (c) 2022-2023 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_s4.c
* - Version : 0.02
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 09.08.2022 0.01 First Release
* : 04.04.2023 0.02 Removed stdio.h and string.h.
*****************************************************************************/
#include <stdint.h>
static void ecm_unlock(void);
static void ecm_write(uint32_t adr, uint32_t val);
static void ecm_lock(void);
#include "boot_init_dram_regdef.h"
#include "ecc_enable_s4.h"
static void ecm_unlock(void)
{
uint32_t tmp_adr;
tmp_adr = ((0xACCEU << 16U) | (ECMWPCNTR & 0xffffU));
mem_write32(ECMWACNTR, tmp_adr);
mem_write32(ECMWPCNTR, 0xACCE0001);
}
static void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
static void ecm_lock(void)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (ECMWACNTR & 0xffffU)));
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
void enable_ecc(void)
{
NOTICE("ECC for DRAM is enable.\n");
uint32_t ecm_tmp;
/* Unlock the access protect for DBSC registers */
mem_write32(DBSC_DBSYSCNT0, 0x00001234U);
mem_write32(DBSC_DBSYSCNT0A, 0x00001234U);
/* (A) Initialization for DRAM */
mmio_write_32(DBSC_DBACEN, 0x00000000U);
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and ECMERRFATALR registers to inform
the control domain of the fatal error. */
ecm_tmp = mem_read32(ECMERRTGTR0);
ecm_tmp &= ~(0x3U);
ecm_write(ECMERRTGTR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRCTLR0);
ecm_tmp |= 0x3U;
ecm_write(ECMERRCTLR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRFATALR0);
ecm_tmp |= 0x3U;
ecm_write(ECMERRFATALR0, ecm_tmp);
/* (B) Setting ECC protection area */
/* Set the bottom row address of the ECC protection area */
mem_write32(DBFSDRAMECCAREA00, ECC_PROT_SIZE0);
mem_write32(DBFSDRAMECCAREA01, ECC_PROT_SIZE1);
/* (2) Initialization for DRAM connected to DBSCCORE */
/* Specify RANK0 as the initialization target */
ecm_tmp = mem_read32(DBFSCONF00A);
ecm_tmp = 0x0U;
mem_write32(DBFSCONF00A, ecm_tmp);
/* Set the start and end row address of the initialization area */
mem_write32(DBFSCONF01A, START_ECC_INIT_AREA0);
mem_write32(DBFSCONF05A, END_ECC_INIT_AREA0);
/* Set 0x1 to start initialization */
ecm_tmp = mem_read32(DBFSCTRL01A);
ecm_tmp |= 0x01U;
mem_write32(DBFSCTRL01A, ecm_tmp);
/* Wait until to DRAM initialization is complete */
NOTICE("DRAM rank 0 is initializing.......\n");
do
{
ecm_tmp = mem_read32(DBFSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* If DRAM is connected to RANK1, Initialize RANK1 */
/* Specify RANK0 as the initialization target */
ecm_tmp = mem_read32(DBFSCONF00A);
ecm_tmp |= 0x1U;
mem_write32(DBFSCONF00A, ecm_tmp);
/* Set the start and end row address of the initialization area */
mem_write32(DBFSCONF01A, START_ECC_INIT_AREA1);
mem_write32(DBFSCONF05A, END_ECC_INIT_AREA1);
/* Set 0x1 to start initialization */
ecm_tmp = mem_read32(DBFSCTRL01A);
ecm_tmp |= 0x01U;
mem_write32(DBFSCTRL01A, ecm_tmp);
/* Wait until to DRAM initialization is complete */
NOTICE("DRAM rank 1 is initializing.......\n");
do
{
ecm_tmp = mem_read32(DBFSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* (C) Setting ECC protection enable */
ecm_tmp = mem_read32(DBFSCONFAXI0);
ecm_tmp |= (0x3 << 8U);
mem_write32(DBFSCONFAXI0, ecm_tmp);
/* (D) System RAM initialization */
/* Wait for initialization of System RAM */
NOTICE("System RAM is initializing.......\n");
do
{
;
} while ((mem_read32(DBFSSTAT00A) & 0x1U) != 0x1U);
/* (E) Setting for ECC error interrupt */
/* (1) Set the ECC error interrupt for read data. */
mem_write32(DBFSINTENB02A, 0xFF00U);
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
ecm_tmp = mem_read32(DBFSINTENB02A);
ecm_tmp |= (0xFFU << 24U);
mem_write32(DBFSINTENB02A, ecm_tmp);
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
mem_write32(DBFSINTENB04A, 0xFFFFU);
/* Lock the ECM registers */
ecm_lock();
/* Enable the write protect of ECM registers */
mmio_write_32(DBSC_DBACEN, 0x00000001U);
/* Enable the access protect for DBSC registers */
mem_write32(DBSC_DBSYSCNT0, 0x00000000U);
mem_write32(DBSC_DBSYSCNT0A, 0x00000000U);
}
void ecc_rtsram_enable(void)
{
uint32_t ecc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and
ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 2-bit error) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 29U) ;
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 29U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 19 of ECMERRTGTR7 to 0 and bit 19 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 2-bit error (for ICUMX)) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 19U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 19U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 29 and 19 of ECMERRFATALR7 to 1. (Notification of fatal error) */
ecc_tmp = mem_read32(ECMERRFATALR7);
ecc_tmp |= ((1U << 29U) | (1U << 19U));
ecm_write(ECMERRFATALR7, ecc_tmp);
/* (2) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers to
notify the correctable error to software. */
/* Set bit 30 of ECMERRTGTR7 to 1 and bit 30 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 1-bit error) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 30U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 30U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 20 of ECMERRTGTR7 to 1 and bit 20 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 1-bit error (for ICUMX)) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 20U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 20U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR
and ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 10 - bit 6 of ECMERRTGTR7 to all 0 and bit 10 - bit 6 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1fU << 6U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1fU << 6U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 23 - bit 16 of ECMERRTGTR39 to all 0 and bit 23 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0xffU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0xffU << 6U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
/* Set bit 10 - bit 6 of ECMERRFATALR7 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR7);
edc_tmp |= (0x1fU << 6U);
ecm_write(ECMERRFATALR7, edc_tmp);
/* Set bit 23 - bit 16 of ECMERRFATALR39 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR39);
edc_tmp |= (0xffU << 16U);
ecm_write(ECMERRFATALR39, edc_tmp);
/* Set bit 26 of ECMERRFATALR1 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRFATALR1, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and
ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 19, 18 of ECMERRFATALR17 to 1. (Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR17);
edc_tmp |= (0x3U << 18U);
ecm_write(ECMERRFATALR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
ecm_write(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}

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/*******************************************************************************
* Copyright (c) 2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
#if(__RH850__)
#include "mem_io.h"
#include "log.h"
#define ECM_BASE (BASE_ECC_ADDR)
#define DBSC_BASE (BASE_DBSC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define ECM_BASE (0xE6250000U)
#define DBSC_BASE (0xE6790000U)
#endif/* __RH850__ */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void enable_ecc(void);
void ecc_rtsram_enable(void);
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DBSC_DBACEN (DBSC_BASE + 0x0200U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define ECMERRFATALR0 (ECM_BASE + 0x0600U)
#define ECMERRFATALR1 (ECM_BASE + 0x0600U + 0x4U * 1U)
#define ECMERRFATALR7 (ECM_BASE + 0x0600U + 0x4U * 7U)
#define ECMERRFATALR17 (ECM_BASE + 0x0600U + 0x4U * 17U)
#define ECMERRFATALR39 (ECM_BASE + 0x0600U + 0x4U * 39U)
#define DBFSCONF00A (DBSC_BASE + 0x7640U)
#define DBFSCONF01A (DBSC_BASE + 0x7644U)
#define DBFSCONF05A (DBSC_BASE + 0x7654U)
#define DBFSCTRL01A (DBSC_BASE + 0x7604U)
#define DBFSSTAT01A (DBSC_BASE + 0x7684U)
#define DBFSSTAT00A (DBSC_BASE + 0x7680U)
#define DBFSINTENB02A (DBSC_BASE + 0x7088U)
#define DBFSINTENB04A (DBSC_BASE + 0x7090U)
#define DBFSDRAMECCAREA00 (DBSC_BASE + 0x7450U)
#define DBFSDRAMECCAREA01 (DBSC_BASE + 0x7454U)
#define DBFSCONFAXI0 (DBSC_BASE + 0x7400U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 */
#define ECC_PROT_SIZE0 (0x2000U)
#define ECC_PROT_SIZE1 (0x2000U)
/* Start and End row address of ECC Protection area for rank0 */
#define START_ECC_INIT_AREA0 (0x00000000U)
#define END_ECC_INIT_AREA0 (0x00001FFFU)
/* Start and End row address of ECC Protection area for rank1 */
#define START_ECC_INIT_AREA1 (0x00000000U)
#define END_ECC_INIT_AREA1 (0x00001FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

615
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h Normal file
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@@ -0,0 +1,615 @@
/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#define DDR_PHY_SLICE_REGSET_OFS_S4 0x1000
#define DDR_PHY_ADR_V_REGSET_OFS_S4 0x1200
#define DDR_PHY_ADR_G_REGSET_OFS_S4 0x1300
#define DDR_PI_REGSET_OFS_S4 0x0800
#define DDR_PHY_SLICE_REGSET_SIZE_S4 0x100
#define DDR_PHY_ADR_V_REGSET_SIZE_S4 0x80
#define DDR_PHY_ADR_G_REGSET_SIZE_S4 0x100
#define DDR_PI_REGSET_SIZE_S4 0x100
#define DDR_PHY_SLICE_REGSET_NUM_S4 140
#define DDR_PHY_ADR_V_REGSET_NUM_S4 54
#define DDR_PHY_ADR_G_REGSET_NUM_S4 143
#define DDR_PI_REGSET_NUM_S4 223
static const uint32_t DDR_PHY_SLICE_REGSET_S4[DDR_PHY_SLICE_REGSET_NUM_S4] = {
/*1000*/ 0x000004F0,
/*1001*/ 0x00000000,
/*1002*/ 0x00030200,
/*1003*/ 0x00000000,
/*1004*/ 0x00000000,
/*1005*/ 0x01030000,
/*1006*/ 0x00010000,
/*1007*/ 0x01030004,
/*1008*/ 0x00000000,
/*1009*/ 0x00000000,
/*100a*/ 0x00000000,
/*100b*/ 0x01000001,
/*100c*/ 0x00000200,
/*100d*/ 0x000800C0,
/*100e*/ 0x06010190,
/*100f*/ 0x00030030,
/*1010*/ 0x00000000,
/*1011*/ 0x00000000,
/*1012*/ 0x55555A3C,
/*1013*/ 0x00005555,
/*1014*/ 0x0000B5B5,
/*1015*/ 0x00004A4A,
/*1016*/ 0x00005656,
/*1017*/ 0x0000A9A9,
/*1018*/ 0x0000A9A9,
/*1019*/ 0x0000B5B5,
/*101a*/ 0x00000000,
/*101b*/ 0x00000000,
/*101c*/ 0x2A000000,
/*101d*/ 0x00000808,
/*101e*/ 0x04000000,
/*101f*/ 0x00000408,
/*1020*/ 0x10600000,
/*1021*/ 0x0C008006,
/*1022*/ 0x00000000,
/*1023*/ 0x00000000,
/*1024*/ 0x55AA55AA,
/*1025*/ 0x33CC33CC,
/*1026*/ 0x0FF00FF0,
/*1027*/ 0x0F0FF0F0,
/*1028*/ 0x00008E38,
/*1029*/ 0x01000100,
/*102a*/ 0x00800180,
/*102b*/ 0x00000001,
/*102c*/ 0x00000000,
/*102d*/ 0x00000000,
/*102e*/ 0x00000000,
/*102f*/ 0x00000000,
/*1030*/ 0x00000000,
/*1031*/ 0x00000000,
/*1032*/ 0x00000000,
/*1033*/ 0x00000000,
/*1034*/ 0x00000000,
/*1035*/ 0x00000000,
/*1036*/ 0x00000000,
/*1037*/ 0x00000000,
/*1038*/ 0x00000000,
/*1039*/ 0x00000000,
/*103a*/ 0x00000000,
/*103b*/ 0x00000000,
/*103c*/ 0x00000000,
/*103d*/ 0x00000000,
/*103e*/ 0x00000000,
/*103f*/ 0x00000000,
/*1040*/ 0x00000000,
/*1041*/ 0x00000000,
/*1042*/ 0x00000104,
/*1043*/ 0x00000120,
/*1044*/ 0x00000000,
/*1045*/ 0x00000000,
/*1046*/ 0x00000000,
/*1047*/ 0x00000000,
/*1048*/ 0x00000000,
/*1049*/ 0x00000000,
/*104a*/ 0x00000000,
/*104b*/ 0x00000000,
/*104c*/ 0x07FF0000,
/*104d*/ 0x00800800,
/*104e*/ 0x00081020,
/*104f*/ 0x04010000,
/*1050*/ 0x00000000,
/*1051*/ 0x00000000,
/*1052*/ 0x00000000,
/*1053*/ 0x00000000,
/*1054*/ 0x01CC0C01,
/*1055*/ 0x2003CC0C,
/*1056*/ 0x20000139,
/*1057*/ 0x07FF0200,
/*1058*/ 0x0100DD01,
/*1059*/ 0x00000103,
/*105a*/ 0x00000000,
/*105b*/ 0x00000000,
/*105c*/ 0x00060000,
/*105d*/ 0x00A000A0,
/*105e*/ 0x00A000A0,
/*105f*/ 0x00A000A0,
/*1060*/ 0x00A000A0,
/*1061*/ 0x000500A0,
/*1062*/ 0x51517042,
/*1063*/ 0x31C08000,
/*1064*/ 0x09AD0064,
/*1065*/ 0x00C0C001,
/*1066*/ 0x0E0C0101,
/*1067*/ 0x10001000,
/*1068*/ 0x0C073E42,
/*1069*/ 0x0F0C3708,
/*106a*/ 0x01C00190,
/*106b*/ 0x04000420,
/*106c*/ 0x00000322,
/*106d*/ 0x0A0000D0,
/*106e*/ 0x00030200,
/*106f*/ 0x02800000,
/*1070*/ 0x80800000,
/*1071*/ 0x000E0010,
/*1072*/ 0x76543210,
/*1073*/ 0x00000008,
/*1074*/ 0x02800280,
/*1075*/ 0x02800280,
/*1076*/ 0x02800280,
/*1077*/ 0x02800280,
/*1078*/ 0x00000280,
/*1079*/ 0x0000A000,
/*107a*/ 0x00A000A0,
/*107b*/ 0x00A000A0,
/*107c*/ 0x00A000A0,
/*107d*/ 0x00A000A0,
/*107e*/ 0x00A000A0,
/*107f*/ 0x00A000A0,
/*1080*/ 0x00A000A0,
/*1081*/ 0x00A000A0,
/*1082*/ 0x01C200A0,
/*1083*/ 0x01A00005,
/*1084*/ 0x00000000,
/*1085*/ 0x00000000,
/*1086*/ 0x00080200,
/*1087*/ 0x00000000,
/*1088*/ 0x20202020,
/*1089*/ 0x20202020,
/*108a*/ 0x01012020,
/*108b*/ 0x00000000
};
static const uint32_t DDR_PHY_ADR_V_REGSET_S4[DDR_PHY_ADR_V_REGSET_NUM_S4] = {
/*1200*/ 0x00000000,
/*1201*/ 0x00000000,
/*1202*/ 0x00000000,
/*1203*/ 0x00000000,
/*1204*/ 0x00000000,
/*1205*/ 0x00000100,
/*1206*/ 0x00000200,
/*1207*/ 0x00000000,
/*1208*/ 0x00000000,
/*1209*/ 0x00000000,
/*120a*/ 0x00000000,
/*120b*/ 0x00800200,
/*120c*/ 0x00000080,
/*120d*/ 0x00DCBA98,
/*120e*/ 0x01000000,
/*120f*/ 0x00200003,
/*1210*/ 0x00000000,
/*1211*/ 0x00000000,
/*1212*/ 0x00000000,
/*1213*/ 0x00000000,
/*1214*/ 0x00000000,
/*1215*/ 0x00000000,
/*1216*/ 0x00000000,
/*1217*/ 0x0000002A,
/*1218*/ 0x00000015,
/*1219*/ 0x00000015,
/*121a*/ 0x0000002A,
/*121b*/ 0x00000033,
/*121c*/ 0x0000000C,
/*121d*/ 0x0000000C,
/*121e*/ 0x00000033,
/*121f*/ 0x00543210,
/*1220*/ 0x003F0000,
/*1221*/ 0x0000013F,
/*1222*/ 0x20202003,
/*1223*/ 0x00202020,
/*1224*/ 0x20008008,
/*1225*/ 0x00000810,
/*1226*/ 0x00000F00,
/*1227*/ 0x00000000,
/*1228*/ 0x00000000,
/*1229*/ 0x00000000,
/*122a*/ 0x000605CC,
/*122b*/ 0x00030000,
/*122c*/ 0x00000300,
/*122d*/ 0x00000300,
/*122e*/ 0x00000300,
/*122f*/ 0x00000300,
/*1230*/ 0x00000300,
/*1231*/ 0x42080010,
/*1232*/ 0x0000803E,
/*1233*/ 0x00000008,
/*1234*/ 0x01000001,
/*1235*/ 0x00008000
};
static const uint32_t DDR_PHY_ADR_G_REGSET_S4[DDR_PHY_ADR_G_REGSET_NUM_S4] = {
/*1300*/ 0x00000000,
/*1301*/ 0x00000100,
/*1302*/ 0x00000000,
/*1303*/ 0x00000000,
/*1304*/ 0x00050000,
/*1305*/ 0x04000000,
/*1306*/ 0x00000020,
/*1307*/ 0x00000000,
/*1308*/ 0x00000000,
/*1309*/ 0x00000000,
/*130a*/ 0x00000000,
/*130b*/ 0x00002001,
/*130c*/ 0x00004003,
/*130d*/ 0x00010028,
/*130e*/ 0x01010100,
/*130f*/ 0x00800800,
/*1310*/ 0x08102000,
/*1311*/ 0x00000000,
/*1312*/ 0x00000000,
/*1313*/ 0x00010E06,
/*1314*/ 0x00000000,
/*1315*/ 0x00000000,
/*1316*/ 0x00000000,
/*1317*/ 0x00000000,
/*1318*/ 0x00040000,
/*1319*/ 0x00000000,
/*131a*/ 0x00000000,
/*131b*/ 0x00000064,
/*131c*/ 0x00000000,
/*131d*/ 0x00000100,
/*131e*/ 0x00000200,
/*131f*/ 0x80012000,
/*1320*/ 0x00041B42,
/*1321*/ 0x05000000,
/*1322*/ 0x00000000,
/*1323*/ 0x00000000,
/*1324*/ 0x00000000,
/*1325*/ 0x01000000,
/*1326*/ 0x01070501,
/*1327*/ 0x00000054,
/*1328*/ 0x00004410,
/*1329*/ 0x00004410,
/*132a*/ 0x00004410,
/*132b*/ 0x00004410,
/*132c*/ 0x00004410,
/*132d*/ 0x00004410,
/*132e*/ 0x00004410,
/*132f*/ 0x00004410,
/*1330*/ 0x00004410,
/*1331*/ 0x00000000,
/*1332*/ 0x00000000,
/*1333*/ 0x00000000,
/*1334*/ 0x00060000,
/*1335*/ 0x00000000,
/*1336*/ 0x00000090,
/*1337*/ 0x0000A25A,
/*1338*/ 0x00000008,
/*1339*/ 0x00000000,
/*133a*/ 0x00000000,
/*133b*/ 0x00000000,
/*133c*/ 0x00000000,
/*133d*/ 0x00000000,
/*133e*/ 0x03000000,
/*133f*/ 0x00000000,
/*1340*/ 0x00000000,
/*1341*/ 0x00000000,
/*1342*/ 0x04102000,
/*1343*/ 0x00041020,
/*1344*/ 0x00C98C98,
/*1345*/ 0x3F400000,
/*1346*/ 0x3F3F1F3F,
/*1347*/ 0x0000001F,
/*1348*/ 0x00000000,
/*1349*/ 0x00000000,
/*134a*/ 0x00000000,
/*134b*/ 0x00010000,
/*134c*/ 0x00000000,
/*134d*/ 0x00000000,
/*134e*/ 0x00000000,
/*134f*/ 0x00000100,
/*1350*/ 0x00000000,
/*1351*/ 0x00000000,
/*1352*/ 0x00040700,
/*1353*/ 0x00000000,
/*1354*/ 0x00000000,
/*1355*/ 0x00000000,
/*1356*/ 0x00000002,
/*1357*/ 0x00000100,
/*1358*/ 0x00000000,
/*1359*/ 0x00000000,
/*135a*/ 0x00001F00,
/*135b*/ 0x00000000,
/*135c*/ 0x00000000,
/*135d*/ 0x00080000,
/*135e*/ 0x000007FF,
/*135f*/ 0x00000000,
/*1360*/ 0x00000000,
/*1361*/ 0x00000000,
/*1362*/ 0x00000000,
/*1363*/ 0x00000000,
/*1364*/ 0x000FFFFF,
/*1365*/ 0x000FFFFF,
/*1366*/ 0x0000FFFF,
/*1367*/ 0xFFFFFFF0,
/*1368*/ 0x030FFFFF,
/*1369*/ 0x01FFFFFF,
/*136a*/ 0x0000FFFF,
/*136b*/ 0x00000000,
/*136c*/ 0x00000000,
/*136d*/ 0x00000000,
/*136e*/ 0x00000000,
/*136f*/ 0x00000000,
/*1370*/ 0x00000006,
/*1371*/ 0x00000000,
/*1372*/ 0x00001142,
/*1373*/ 0x08010600,
/*1374*/ 0x00000080,
/*1375*/ 0x03000300,
/*1376*/ 0x03000300,
/*1377*/ 0x00000300,
/*1378*/ 0x00000300,
/*1379*/ 0x00000300,
/*137a*/ 0x00000300,
/*137b*/ 0x00000005,
/*137c*/ 0x0004BFCC,
/*137d*/ 0x0000010C,
/*137e*/ 0x0000027F,
/*137f*/ 0x00000000,
/*1380*/ 0x0000027F,
/*1381*/ 0x00000000,
/*1382*/ 0x00127F00,
/*1383*/ 0x0089FF00,
/*1384*/ 0x00827FCC,
/*1385*/ 0x00000000,
/*1386*/ 0x00127F80,
/*1387*/ 0x01980000,
/*1388*/ 0x00127F80,
/*1389*/ 0x01980000,
/*138a*/ 0x00127F00,
/*138b*/ 0x01980000,
/*138c*/ 0x00127F00,
/*138d*/ 0x01980000,
/*138e*/ 0x20040006
};
static const uint32_t DDR_PI_REGSET_S4[DDR_PI_REGSET_NUM_S4] = {
/*0800*/ 0x00000B00,
/*0801*/ 0x00000000,
/*0802*/ 0x00000000,
/*0803*/ 0x00000101,
/*0804*/ 0x00640000,
/*0805*/ 0x00000001,
/*0806*/ 0x00000000,
/*0807*/ 0x00000000,
/*0808*/ 0x00000000,
/*0809*/ 0x00000000,
/*080a*/ 0x00000003,
/*080b*/ 0x00010100,
/*080c*/ 0x08000003,
/*080d*/ 0x00000103,
/*080e*/ 0x00000000,
/*080f*/ 0x00000000,
/*0810*/ 0x00000000,
/*0811*/ 0x00000000,
/*0812*/ 0x00000000,
/*0813*/ 0x00000000,
/*0814*/ 0x0A000000,
/*0815*/ 0x00000028,
/*0816*/ 0x00000100,
/*0817*/ 0x00320003,
/*0818*/ 0x00000000,
/*0819*/ 0x00000000,
/*081a*/ 0x01010102,
/*081b*/ 0x00000000,
/*081c*/ 0x55555A3C,
/*081d*/ 0x00000055,
/*081e*/ 0x000000B5,
/*081f*/ 0x0000004A,
/*0820*/ 0x00000056,
/*0821*/ 0x000000A9,
/*0822*/ 0x000000A9,
/*0823*/ 0x000000B5,
/*0824*/ 0x01000000,
/*0825*/ 0x00010000,
/*0826*/ 0x00030300,
/*0827*/ 0x0000001A,
/*0828*/ 0x000007D0,
/*0829*/ 0x00000300,
/*082a*/ 0x00000000,
/*082b*/ 0x00000000,
/*082c*/ 0x01080000,
/*082d*/ 0x00010101,
/*082e*/ 0x00000000,
/*082f*/ 0x00030000,
/*0830*/ 0x03000100,
/*0831*/ 0x00000017,
/*0832*/ 0x00000000,
/*0833*/ 0x00000000,
/*0834*/ 0x00000000,
/*0835*/ 0x0A0A140A,
/*0836*/ 0x10020300,
/*0837*/ 0x00020805,
/*0838*/ 0x00000404,
/*0839*/ 0x00000000,
/*083a*/ 0x00000000,
/*083b*/ 0x01000101,
/*083c*/ 0x00020203,
/*083d*/ 0x00340000,
/*083e*/ 0x00000000,
/*083f*/ 0x00000000,
/*0840*/ 0x01000000,
/*0841*/ 0x00000000,
/*0842*/ 0x00000800,
/*0843*/ 0x00020002,
/*0844*/ 0x00010001,
/*0845*/ 0x00010000,
/*0846*/ 0x00020002,
/*0847*/ 0x00000002,
/*0848*/ 0x00000000,
/*0849*/ 0x00000000,
/*084a*/ 0x00000000,
/*084b*/ 0x00000000,
/*084c*/ 0x00000000,
/*084d*/ 0x00000000,
/*084e*/ 0x00000000,
/*084f*/ 0x00000000,
/*0850*/ 0x00100400,
/*0851*/ 0x08010100,
/*0852*/ 0x08000000,
/*0853*/ 0x00000100,
/*0854*/ 0x00000000,
/*0855*/ 0x0000AA00,
/*0856*/ 0x00000000,
/*0857*/ 0x00010000,
/*0858*/ 0x00000000,
/*0859*/ 0x00000000,
/*085a*/ 0x00000000,
/*085b*/ 0x00000000,
/*085c*/ 0x00000000,
/*085d*/ 0x00000000,
/*085e*/ 0x00000000,
/*085f*/ 0x00000000,
/*0860*/ 0x00000000,
/*0861*/ 0x00000000,
/*0862*/ 0x00000000,
/*0863*/ 0x00000000,
/*0864*/ 0x00000000,
/*0865*/ 0x00000000,
/*0866*/ 0x00000000,
/*0867*/ 0x00000000,
/*0868*/ 0x00000000,
/*0869*/ 0x00000000,
/*086a*/ 0x00000000,
/*086b*/ 0x00000000,
/*086c*/ 0x00000000,
/*086d*/ 0x00000000,
/*086e*/ 0x00000000,
/*086f*/ 0x00000000,
/*0870*/ 0x00000000,
/*0871*/ 0x00000000,
/*0872*/ 0x00000000,
/*0873*/ 0x00000000,
/*0874*/ 0x00000000,
/*0875*/ 0x00000000,
/*0876*/ 0x00000000,
/*0877*/ 0x00000002,
/*0878*/ 0x01010001,
/*0879*/ 0x00010200,
/*087a*/ 0x04000103,
/*087b*/ 0x01050001,
/*087c*/ 0x00010600,
/*087d*/ 0x00000107,
/*087e*/ 0x00000000,
/*087f*/ 0x00000000,
/*0880*/ 0x00000100,
/*0881*/ 0x00000000,
/*0882*/ 0x00000000,
/*0883*/ 0x00000000,
/*0884*/ 0x00040100,
/*0885*/ 0x00000000,
/*0886*/ 0x00000000,
/*0887*/ 0x01000000,
/*0888*/ 0x00002B2B,
/*0889*/ 0x00000034,
/*088a*/ 0x0000006C,
/*088b*/ 0x120C046C,
/*088c*/ 0x00481248,
/*088d*/ 0x00000006,
/*088e*/ 0x00000046,
/*088f*/ 0x00000256,
/*0890*/ 0x00002073,
/*0891*/ 0x00000256,
/*0892*/ 0x04002073,
/*0893*/ 0x00000404,
/*0894*/ 0x00002A00,
/*0895*/ 0x002A002A,
/*0896*/ 0x01000100,
/*0897*/ 0x00000100,
/*0898*/ 0x00000000,
/*0899*/ 0x00000000,
/*089a*/ 0x00010000,
/*089b*/ 0x00010100,
/*089c*/ 0x00010100,
/*089d*/ 0x15040100,
/*089e*/ 0x0E0E0215,
/*089f*/ 0x00040402,
/*08a0*/ 0x000C0034,
/*08a1*/ 0x00210049,
/*08a2*/ 0x00210049,
/*08a3*/ 0x01000001,
/*08a4*/ 0x00040005,
/*08a5*/ 0x00040216,
/*08a6*/ 0x01000216,
/*08a7*/ 0x00060006,
/*08a8*/ 0x02170100,
/*08a9*/ 0x01000217,
/*08aa*/ 0x02170217,
/*08ab*/ 0x11111111,
/*08ac*/ 0x00001111,
/*08ad*/ 0x0A070600,
/*08ae*/ 0x1F130A0D,
/*08af*/ 0x1F130A14,
/*08b0*/ 0x0000C014,
/*08b1*/ 0x00C01000,
/*08b2*/ 0x00C01000,
/*08b3*/ 0x00021000,
/*08b4*/ 0x00240005,
/*08b5*/ 0x00240216,
/*08b6*/ 0x003E0216,
/*08b7*/ 0x1609003A,
/*08b8*/ 0x00000007,
/*08b9*/ 0x003A003E,
/*08ba*/ 0x00071609,
/*08bb*/ 0x00003E00,
/*08bc*/ 0x1609003A,
/*08bd*/ 0x08000007,
/*08be*/ 0x04010404,
/*08bf*/ 0x01030277,
/*08c0*/ 0x0A0A0320,
/*08c1*/ 0x18272D10,
/*08c2*/ 0x5A752F28,
/*08c3*/ 0x1E202008,
/*08c4*/ 0x272D1016,
/*08c5*/ 0x752F2818,
/*08c6*/ 0x2020085A,
/*08c7*/ 0x0000161E,
/*08c8*/ 0x0000008C,
/*08c9*/ 0x00000578,
/*08ca*/ 0x000040E6,
/*08cb*/ 0x000288FC,
/*08cc*/ 0x000040E6,
/*08cd*/ 0x000288FC,
/*08ce*/ 0x02660006,
/*08cf*/ 0x04040266,
/*08d0*/ 0xC83CC804,
/*08d1*/ 0x0000003C,
/*08d2*/ 0x00040000,
/*08d3*/ 0x0F1166F1,
/*08d4*/ 0x3F740006,
/*08d5*/ 0x0F1166F1,
/*08d6*/ 0x3F740006,
/*08d7*/ 0x0F1166F1,
/*08d8*/ 0x00040006,
/*08d9*/ 0x0F1166F1,
/*08da*/ 0x3F74002E,
/*08db*/ 0x0F1166F1,
/*08dc*/ 0x3F74002E,
/*08dd*/ 0x0F1166F1,
/*08de*/ 0x0000002E
};

302
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h Normal file
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@@ -0,0 +1,302 @@
/*******************************************************************************
* Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.08rc7"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U)
#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U)
#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U)
#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU)
#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U)
#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#else
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU)
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U)
#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U)
#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U)
#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU)
#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U)
#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U)
#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U)
#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU)
#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U)
#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U)
#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U)
#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU)
#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U)
#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U)
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U)
#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U)
#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U)
#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U)
#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU)
#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U)
#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U)
#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U)
#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU)
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U)
#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U)
#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU)
#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U)
#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U)
#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U)
#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U)
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U)
#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U)
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U)
#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U)
#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U)
#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U)
#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U)
#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U)
#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U)
#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U)
#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U)
#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U)
#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U)
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x))
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y))

220
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c Normal file
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@@ -0,0 +1,220 @@
/*******************************************************************************
* Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4h.c
* - Version : 0.06
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 09.08.2022 0.01 First Release
* : 22.03.2023 0.02 Added AXI Timeout setting
* : 04.04.2023 0.03 Removed stdio.h and string.h.
* : 24.08.2023 0.04 Removed enable_ecc function.
* : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 07.04.2025 0.06 Remove unused functions.
*****************************************************************************/
#include <stdint.h>
#include <cnf_tbl.h>
#include <remap.h>
#include <wdt.h>
#if (ECM_ENABLE == 1)
#include "ecc_enable_v4h.h"
#include "v4h/lpddr5/boot_init_dram_regdef.h"
#include "ecm_enable_v4h.h"
#define AXI_SICREMAP_NUM (5U)
#define RGID_BASE1 (0xFE600000U)
#define RGID_BASE2 (0xE7A00000U)
#define RGID_BASE3 (0xEB800000U)
#define RGID_BASE4 (0xFD800000U)
#define RGID_BASE5 (0xFEA00000U)
#define FDT_COUNTER_MASK (0x0000FFFFU)
static void axi_timeout_setting(void);
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x3FFU << 2U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x3FFU << 2U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0x1FFFU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0x1FFFU << 16U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
axi_timeout_setting();
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 30U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 30U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 29U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 29U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
mem_write32(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
static void axi_timeout_setting(void)
{
uint32_t reg;
uint32_t loop;
REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
};
/* Register of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr);
}
/* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */
for (loop = 0U; loop < FDT_REG_MAX; loop++)
{
reg = mem_read32(g_fdt_tbl[loop].reg_addr);
reg &= ~(FDT_COUNTER_MASK);
reg |= g_fdt_tbl[loop].value;
mem_write32(g_fdt_tbl[loop].reg_addr, reg);
INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value);
}
for(loop = 0U; loop < INTEN_REG_MAX; loop++)
{
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value);
INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value);
}
/* Unregister of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_unregister(axi_remap_tbl[loop].rmp_addr);
}
wdt_restart();
}
#endif /* ECM_ENABLE == 1 */

123
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h Normal file
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/*******************************************************************************
* Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
/* DBSC registers */
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U)
#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U)
#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0x1000U)
#define ECC_PROT_SIZE01 (0x1000U)
#define ECC_PROT_SIZE10 (0x1000U)
#define ECC_PROT_SIZE11 (0x1000U)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x00000FFFU)
#define END_ECC_INIT_AREA10 (0x00000FFFU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x00000FFFU)
#define END_ECC_INIT_AREA11 (0x00000FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4h.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4h.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
#include "ecc_enable_v4h.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define TYPE1_ECM_REG_MAX (13U)
#define TYPE2_ECM_REG_MAX (22U)
#define TYPE3_ECM_CTLREG_MAX (1U)
#define TYPE3_ECM_TGTREG_MAX (2U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
[2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */
[3] = {0xFD85001CU, 0x0C000000U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
/* Skip ECMERRCTLR16 setting */
[4] = {0xFD850044U, 0x2D000000U}, /* ECMERRCTLR17 */
[5] = {0xFD850048U, 0x0EC0003FU}, /* ECMERRCTLR18 */
[6] = {0xFD85004CU, 0x00FFFF08U}, /* ECMERRCTLR19 */
[7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */
[8] = {0xFD850054U, 0x9F800000U}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
[9] = {0xFD85008CU, 0x300003C0U}, /* ECMERRCTLR35 */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
[10] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
[11] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */
[12] = {0xFD8500A8U, 0x00040020U}, /* ECMERRCTLR42 */
};
const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
[2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */
[3] = {0xFD85021CU, 0x0C000000U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
/* Skip ECMERRTGTR16 setting */
[4] = {0xFD850244U, 0x2D000000U}, /* ECMERRTGTR17 */
[5] = {0xFD850248U, 0x0EC0003FU}, /* ECMERRTGTR18 */
[6] = {0xFD85024CU, 0x00FFFF08U}, /* ECMERRTGTR19 */
[7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */
[8] = {0xFD850254U, 0x9F800000U}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
[9] = {0xFD85028CU, 0x300003C0U}, /* ECMERRTGTR35 */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
[10] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
[11] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */
[12] = {0xFD8502A8U, 0x00040020U}, /* ECMERRTGTR42 */
};
const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x4000000FU}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0x1C004000U}, /* ECMERRCTLR1 */
[2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xFD850014U, 0xC1FFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */
[7] = {0xFD85001CU, 0x00803481U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */
[9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */
[10] = {0xFD850048U, 0x003C1FC0U}, /* ECMERRCTLR18 */
[11] = {0xFD85004CU, 0xFF0000F0U}, /* ECMERRCTLR19 */
[12] = {0xFD850050U, 0x02222220U}, /* ECMERRCTLR20 */
[13] = {0xFD850054U, 0x0061BE0FU}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */
[15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[16] = {0xFD85008CU, 0xC3F00C00U}, /* ECMERRCTLR35 */
[17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
[19] = {0xFD8500A0U, 0x000067FEU}, /* ECMERRCTLR40 */
[20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */
[21] = {0xFD8500A8U, 0x00800400U}, /* ECMERRCTLR42 */
};
const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x4000000FU}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0x1C004000U}, /* ECMERRTGTR1 */
[2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xFD850214U, 0xC1FFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */
[7] = {0xFD85021CU, 0x00803481U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */
[9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */
[10] = {0xFD850248U, 0x003C1FC0U}, /* ECMERRTGTR18 */
[11] = {0xFD85024CU, 0xFF0000F0U}, /* ECMERRTGTR19 */
[12] = {0xFD850250U, 0x02222220U}, /* ECMERRTGTR20 */
[13] = {0xFD850254U, 0x0061BE0FU}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */
[15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[16] = {0xFD85028CU, 0xC3F00C00U}, /* ECMERRTGTR35 */
[17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
[19] = {0xFD8502A0U, 0x000067FEU}, /* ECMERRTGTR40 */
[20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */
[21] = {0xFD8502A8U, 0x00800400U}, /* ECMERRTGTR42 */
};
const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = {
/* Skip ECMERRCTLR0 setting */
/* Skip ECMERRCTLR1 setting */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
/* Skip ECMERRCTLR6 setting */
/* Skip ECMERRCTLR7 setting */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[0] = {0xFD850040U, 0x3FFFC000U}, /* ECMERRCTLR16 */
/* Skip ECMERRCTLR17 setting */
/* Skip ECMERRCTLR18 setting */
/* Skip ECMERRCTLR19 setting */
/* Skip ECMERRCTLR20 setting */
/* Skip ECMERRCTLR21 setting */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
/* Skip ECMERRCTLR35 setting */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
/* Skip ECMERRCTLR38 setting */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
/* Skip ECMERRCTLR41 setting */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = {
[0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */
/* Skip ECMERRTGTR1 setting */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
/* Skip ECMERRTGTR6 setting */
/* Skip ECMERRTGTR7 setting */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[1] = {0xFD850240U, 0x3FFFC000U}, /* ECMERRTGTR16 */
/* Skip ECMERRTGTR17 setting */
/* Skip ECMERRTGTR18 setting */
/* Skip ECMERRTGTR19 setting */
/* Skip ECMERRTGTR20 setting */
/* Skip ECMERRTGTR21 setting */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
/* Skip ECMERRTGTR35 setting */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
/* Skip ECMERRTGTR38 setting */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
/* Skip ECMERRTGTR41 setting */
/* Skip ECMERRTGTR42 setting */
};
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n");
/* For the initial setting flow for Type-1, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.2.5 : (1)
* Section 4.1.4.5 : (1)
* Section 4.12.1.5 : (1)
* Section 4.13.1.5 : (1)
* Section 4.14.5 : (1)
* Section 4.16.5 : (1)
* Section 4.18.5 : (1)
* Section 4.2.7.5 : (1)
* Section 4.2.9.5 : (1)
* Section 4.23.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.14.5 : (1)
* Section 4.3.19.5 : (1)
* Section 4.3.21.5 : (1)
* Section 4.4.14.5 : (1)
* Section 4.4.16.5 : (3)
* Section 4.4.18.5 : (1)
* Section 4.4.20.5 : (1)
* Section 4.4.3.5 : (1)
* Section 4.4.4.5 : (1)
* Section 4.4.6.5 : (1)
* Section 4.4.7.5 : (1)
* Section 4.4.9.5 : (1)
* Section 4.5.1.5 : (1)
* Section 4.7.1.5 : (1)
* Section 4.7.10.5 : (1)
* Section 4.7.3.5 : (1)
* Section 4.7.4.5 : (1)
* Section 4.7.7.5 : (1)
* Section 4.7.8.5 : (1)
* Section 5.6.5 : (1)
* Section 5.8.1.5 : (1)
*/
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type1_tbl[loop].value);
ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr),
ecmerrctlr_type1_tbl[loop].value);
}
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type1_tbl[loop].value);
ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr),
ecmerrtgtr_type1_tbl[loop].value);
}
/* For the initial setting flow for Type-2, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.1.5 : (1)
* Section 4.12.2.5 : (1)
* Section 4.12.3.5 : (1)
* Section 4.15.5 : (1)
* Section 4.16.5 : (1)
* Section 4.2.1.5 : (1)
* Section 4.2.10.5 : (1)
* Section 4.2.12.5 : (1)
* Section 4.2.2.5 : (1)
* Section 4.2.4.5 : (1)
* Section 4.2.8.5 : (1)
* Section 4.3.1.5 : (1)
* Section 4.3.10.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.13.5 : (1)
* Section 4.3.15.5 : (1)
* Section 4.3.16.5 : (1)
* Section 4.3.2.5 : (1)
* Section 4.3.5.5 : (1)
* Section 4.3.7.5 : (1)
* Section 4.3.8.5 : (1)
* Section 4.4.10.5 : (1)
* Section 4.4.12.5 : (8)
* Section 4.4.13.5 : (1)
* Section 4.4.15.5 : (1)
* Section 4.4.2.5 : (1)
* Section 4.5.3.5 : (1)
* Section 4.6.5 : (1)
* Section 4.7.2.5 : (1)
* Section 5.11.5 : (1)
* Section 5.12.5 : (1)
* Section 5.13.5 : (1)
* Section 5.4.5 : (1)
* Section 5.8.2.5 : (1)
*/
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type2_tbl[loop].value);
ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr),
ecmerrctlr_type2_tbl[loop].value);
}
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type2_tbl[loop].value);
ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr),
ecmerrtgtr_type2_tbl[loop].value);
}
/* For the initial setting flow for Type-3, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.19.1.5 : (3)
* Section 6.2.5 : (12)
*/
for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type3_tbl[loop].value);
ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr),
ecmerrctlr_type3_tbl[loop].value);
}
for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type3_tbl[loop].value);
ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr),
ecmerrtgtr_type3_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_init_setting(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

42
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE_V4H
#define ECM_ENABLE_V4H
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE_V4H */

302
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h Normal file
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/*******************************************************************************
* Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.08rc7"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U)
#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U)
#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U)
#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU)
#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U)
#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#else
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU)
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U)
#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U)
#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U)
#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU)
#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U)
#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U)
#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U)
#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU)
#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U)
#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U)
#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U)
#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU)
#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U)
#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U)
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U)
#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U)
#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U)
#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U)
#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU)
#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U)
#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U)
#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U)
#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU)
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U)
#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U)
#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU)
#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U)
#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U)
#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U)
#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U)
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U)
#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U)
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U)
#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U)
#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U)
#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U)
#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U)
#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U)
#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U)
#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U)
#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U)
#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U)
#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U)
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x))
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y))

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/*******************************************************************************
* Copyright (c) 2023-2024 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4m.c
* - Version : 0.03
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
* : 13.06.2024 0.02 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 07.04.2025 0.06 Remove unused functions.
*****************************************************************************/
#include <stdint.h>
#include <cnf_tbl.h>
#include <remap.h>
#include <wdt.h>
#if (ECM_ENABLE == 1)
#include "ecc_enable_v4m.h"
#include "v4m/lpddr5/boot_init_dram_regdef.h"
#include "ecm_enable_v4m.h"
#define AXI_SICREMAP_NUM (5U)
#define RGID_BASE1 (0xFE600000U)
#define RGID_BASE2 (0xE7A00000U)
#define RGID_BASE3 (0xEB800000U)
#define RGID_BASE4 (0xFD800000U)
#define RGID_BASE5 (0xFEA00000U)
#define FDT_COUNTER_MASK (0x0000FFFFU)
static void axi_timeout_setting(void);
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x3FFU << 2U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x3FFU << 2U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0x1FFFU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0x1FFFU << 16U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
axi_timeout_setting();
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 30U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 30U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 29U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 29U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
mem_write32(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
static void axi_timeout_setting(void)
{
uint32_t reg;
uint32_t loop;
REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
};
/* Register of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr);
}
/* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */
for (loop = 0U; loop < FDT_REG_MAX; loop++)
{
reg = mem_read32(g_fdt_tbl[loop].reg_addr);
reg &= ~(FDT_COUNTER_MASK);
reg |= g_fdt_tbl[loop].value;
mem_write32(g_fdt_tbl[loop].reg_addr, reg);
INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value);
}
for(loop = 0U; loop < INTEN_REG_MAX; loop++)
{
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value);
INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value);
}
/* Unregister of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_unregister(axi_remap_tbl[loop].rmp_addr);
}
wdt_restart();
}
#endif /* ECM_ENABLE == 1 */

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/*******************************************************************************
* Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
/* DBSC registers */
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U)
#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U)
#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0x1000U)
#define ECC_PROT_SIZE01 (0x1000U)
#define ECC_PROT_SIZE10 (0x1000U)
#define ECC_PROT_SIZE11 (0x1000U)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x00000FFFU)
#define END_ECC_INIT_AREA10 (0x00000FFFU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x00000FFFU)
#define END_ECC_INIT_AREA11 (0x00000FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

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/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4m.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4m.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
#include "ecc_enable_v4m.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define TYPE1_ECM_REG_MAX (14U)
#define TYPE2_ECM_REG_MAX (21U)
#define TYPE3_ECM_CTLREG_MAX (1U)
#define TYPE3_ECM_TGTREG_MAX (2U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
[2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */
[3] = {0xFD85001CU, 0x08000000U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
/* Skip ECMERRCTLR16 setting */
[4] = {0xFD850044U, 0x2D001000U}, /* ECMERRCTLR17 */
[5] = {0xFD850048U, 0x0CC001FFU}, /* ECMERRCTLR18 */
[6] = {0xFD85004CU, 0xFFF80000U}, /* ECMERRCTLR19 */
[7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */
[8] = {0xFD850054U, 0x9F000000U}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[9] = {0xFD850080U, 0x10000000U}, /* ECMERRCTLR32 */
[10] = {0xFD850084U, 0x10000000U}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[11] = {0xFD85008CU, 0x20002280U}, /* ECMERRCTLR35 */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
[12] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
[13] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
[2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */
[3] = {0xFD85021CU, 0x08000000U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
/* Skip ECMERRTGTR16 setting */
[4] = {0xFD850244U, 0x2D001000U}, /* ECMERRTGTR17 */
[5] = {0xFD850248U, 0x0CC001FFU}, /* ECMERRTGTR18 */
[6] = {0xFD85024CU, 0xFFF80000U}, /* ECMERRTGTR19 */
[7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */
[8] = {0xFD850254U, 0x9F000000U}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[9] = {0xFD850280U, 0x10000000U}, /* ECMERRTGTR32 */
[10] = {0xFD850284U, 0x10000000U}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[11] = {0xFD85028CU, 0x20002280U}, /* ECMERRTGTR35 */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
[12] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
[13] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */
/* Skip ECMERRTGTR42 setting */
};
const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x40000003U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0x04004000U}, /* ECMERRCTLR1 */
[2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xFD850014U, 0x81FFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */
[7] = {0xFD85001CU, 0x00801481U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */
[9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */
[10] = {0xFD850048U, 0x00341600U}, /* ECMERRCTLR18 */
[11] = {0xFD85004CU, 0x0007FF30U}, /* ECMERRCTLR19 */
[12] = {0xFD850050U, 0x02200220U}, /* ECMERRCTLR20 */
[13] = {0xFD850054U, 0x0061820FU}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */
[15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[16] = {0xFD85008CU, 0x83B00800U}, /* ECMERRCTLR35 */
[17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
[19] = {0xFD8500A0U, 0x0000601EU}, /* ECMERRCTLR40 */
[20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x40000003U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0x04004000U}, /* ECMERRTGTR1 */
[2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xFD850214U, 0x81FFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */
[7] = {0xFD85021CU, 0x00801481U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */
[9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */
[10] = {0xFD850248U, 0x00341600U}, /* ECMERRTGTR18 */
[11] = {0xFD85024CU, 0x0007FF30U}, /* ECMERRTGTR19 */
[12] = {0xFD850250U, 0x02200220U}, /* ECMERRTGTR20 */
[13] = {0xFD850254U, 0x0061820FU}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */
[15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[16] = {0xFD85028CU, 0x83B00800U}, /* ECMERRTGTR35 */
[17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
[19] = {0xFD8502A0U, 0x0000601EU}, /* ECMERRTGTR40 */
[20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */
/* Skip ECMERRTGTR42 setting */
};
const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = {
/* Skip ECMERRCTLR0 setting */
/* Skip ECMERRCTLR1 setting */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
/* Skip ECMERRCTLR6 setting */
/* Skip ECMERRCTLR7 setting */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[0] = {0xFD850040U, 0x33F00000U}, /* ECMERRCTLR16 */
/* Skip ECMERRCTLR17 setting */
/* Skip ECMERRCTLR18 setting */
/* Skip ECMERRCTLR19 setting */
/* Skip ECMERRCTLR20 setting */
/* Skip ECMERRCTLR21 setting */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
/* Skip ECMERRCTLR35 setting */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
/* Skip ECMERRCTLR38 setting */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
/* Skip ECMERRCTLR41 setting */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = {
[0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */
/* Skip ECMERRTGTR1 setting */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
/* Skip ECMERRTGTR6 setting */
/* Skip ECMERRTGTR7 setting */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[1] = {0xFD850240U, 0x33F00000U}, /* ECMERRTGTR16 */
/* Skip ECMERRTGTR17 setting */
/* Skip ECMERRTGTR18 setting */
/* Skip ECMERRTGTR19 setting */
/* Skip ECMERRTGTR20 setting */
/* Skip ECMERRTGTR21 setting */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
/* Skip ECMERRTGTR35 setting */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
/* Skip ECMERRTGTR38 setting */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
/* Skip ECMERRTGTR41 setting */
/* Skip ECMERRTGTR42 setting */
};
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n");
/* For the initial setting flow for Type-1, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.2.5 : (1)
* Section 4.1.4.5 : (1)
* Section 4.12.1.5 : (1)
* Section 4.14.5 : (1)
* Section 4.2.7.5 : (1)
* Section 4.2.9.5 : (1)
* Section 4.23.5 : (1)
* Section 4.25.5 : (1)
* Section 4.3.14.5 : (1)
* Section 4.3.19.5 : (1)
* Section 4.3.21.5 : (1)
* Section 4.4.16.5 : (1)
* Section 4.4.18.5 : (1)
* Section 4.4.20.5 : (1)
* Section 4.4.3.5 : (1)
* Section 4.4.4.5 : (1)
* Section 4.4.6.5 : (1)
* Section 4.4.7.5 : (1)
* Section 4.4.9.5 : (1)
* Section 4.5.1.5 : (1)
* Section 4.7.1.5 : (1)
* Section 4.7.10.5 : (1)
* Section 4.7.3.5 : (1)
* Section 4.7.4.5 : (1)
* Section 4.7.7.5 : (1)
* Section 4.7.8.5 : (1)
* Section 5.8.1.5 : (1)
*/
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-1 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type1_tbl[loop].value);
ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr),
ecmerrctlr_type1_tbl[loop].value);
}
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-1 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type1_tbl[loop].value);
ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr),
ecmerrtgtr_type1_tbl[loop].value);
}
/* For the initial setting flow for Type-2, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.1.5 : (1)
* Section 4.12.2.5 : (1)
* Section 4.12.3.5 : (1)
* Section 4.15.5 : (1)
* Section 4.16.5 : (1)
* Section 4.18.5 : (1)
* Section 4.2.1.5 : (1)
* Section 4.2.10.5 : (1)
* Section 4.2.12.5 : (1)
* Section 4.2.2.5 : (1)
* Section 4.2.4.5 : (1)
* Section 4.2.8.5 : (1)
* Section 4.3.1.5 : (1)
* Section 4.3.10.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.13.5 : (1)
* Section 4.3.15.5 : (1)
* Section 4.3.16.5 : (1)
* Section 4.3.2.5 : (1)
* Section 4.3.5.5 : (1)
* Section 4.3.7.5 : (1)
* Section 4.3.8.5 : (1)
* Section 4.4.10.5 : (1)
* Section 4.4.12.5 : (6)
* Section 4.4.13.5 : (1)
* Section 4.4.14.5 : (1)
* Section 4.4.15.5 : (1)
* Section 4.4.2.5 : (1)
* Section 4.5.3.5 : (1)
* Section 4.6.5 : (1)
* Section 4.7.2.5 : (1)
* Section 5.11.5 : (1)
* Section 5.12.5 : (1)
* Section 5.13.5 : (1)
* Section 5.4.5 : (1)
* Section 5.6.5 : (1)
* Section 5.8.2.5 : (1)
*/
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type2_tbl[loop].value);
ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr),
ecmerrctlr_type2_tbl[loop].value);
}
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type2_tbl[loop].value);
ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr),
ecmerrtgtr_type2_tbl[loop].value);
}
/* For the initial setting flow for Type-3, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.19.1.5 : (3)
* Section 6.2.5 : (12)
*/
for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type3_tbl[loop].value);
ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr),
ecmerrctlr_type3_tbl[loop].value);
}
for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type3_tbl[loop].value);
ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr),
ecmerrtgtr_type3_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_init_setting(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

47
IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h Normal file
View File

@@ -0,0 +1,47 @@
/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE_V4M
#define ECM_ENABLE_V4M
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE_V4M */