add IPL
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237
IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c
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237
IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Power management driver
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******************************************************************************/
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/******************************************************************************
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* @file cpu_on.c
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* - Version : 0.09
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* @brief Boot process of ARM CPU core.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 28.07.2021 0.01 First Release
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* : 03.09.2021 0.02 Modify macro definition name.
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* : 08.09.2021 0.03 Removed the reset process of BOOT_CTRL and
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* OPBT_CTRL register.
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* : 06.01.2022 0.04 Static analysis support
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* : 23.05.2022 0.05 Integration of S4 and V4H
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* : 21.06.2022 0.06 Remove functions for MCU.
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* : 21.08.2023 0.07 Add support for V4M.
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* : 17.11.2023 0.08 Move a part of definitions to cpu_on.h.
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* : 09.12.2024 0.09 Update OTP_MEM_OTPMONITOR60 register to
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* OTP_MEM_OTPMONITOR17 register for V4M.
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* And Improve the adj_cr_variant_freq function.
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*****************************************************************************/
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#include <stdint.h>
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#include <types.h>
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#include <mem_io.h>
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#include <cpu_on.h>
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#include <cpg.h>
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#include <cpg_register.h>
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#include <ap_system_core_register.h>
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#include <inline_asm.h>
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/* ARM */
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#define CA_CORE0_WUP_REQ (0x00000001U)
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#define CA_CORE0_VLD_RVBARP (0x00000001U)
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#define CR_VLD_BARP (0x00000001U << 0U)
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#define CR_BAREN_VALID (0x00000001U << 4U)
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#define CRRST_BIT (0x00000001U)
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#if (RCAR_LSI == RCAR_V4H)
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#define V4H_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
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#define V4H_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
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#define V4H_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
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#elif (RCAR_LSI == RCAR_V4M)
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#define V4M_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
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#define V4M_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
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#define V4M_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
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#define V4M_2_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
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# endif /* RCAR_LSI == RCAR_V4H */
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#define CPG_PLL6CR0_KICK_BIT (0x80000000U)
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#define CPG_PLLECR_PLL6ST_BIT (0x00008000U)
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#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U)
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static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
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static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
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{
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if(RCAR_PWR_TARGET_CR == target)
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{
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/* CR Boot address set */
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mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP));
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mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
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}
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else if(RCAR_PWR_TARGET_CA == target)
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{
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/* CA Boot address set */
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mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
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mem_write32(APMU_RVBARPHC0, 0x00000000U);
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}
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else
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{
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/* No Process */
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}
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}
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/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
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void arm_cpu_on(uint32_t target, uint32_t boot_addr)
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{
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uint32_t res_data;
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if(RCAR_PWR_TARGET_CR == target)
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{
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/* CR Boot address set. */
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arm_cpu_set_address(target, boot_addr);
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synci();
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/* CR reset. */
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res_data = mem_read32(APMU_CRRSTCTRL);
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res_data &= ~(CRRST_BIT);
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mem_write32(APMU_CRRSTCTRL, res_data);
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}
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else if(RCAR_PWR_TARGET_CA == target)
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{
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/* CA Boot address set. */
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arm_cpu_set_address(target, boot_addr);
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/* AP-System core initialize */
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res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U));
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res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
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mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data);
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res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
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res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
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mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
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#if (RCAR_LSI == RCAR_V4H)
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res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
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res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
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mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
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#endif /* RCAR_LSI == RCAR_V4H */
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synci();
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/* CA core0 wake up sequence. */
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res_data = mem_read32(APMU_PWRCTRLC0);
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res_data |= CA_CORE0_WUP_REQ;
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mem_write32(APMU_PWRCTRLC0, res_data);
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/* Wait until CA core0 wake up sequence finished. */
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do
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{
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res_data = mem_read32(APMU_PWRCTRLC0);
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}while(FALSE != (CA_CORE0_WUP_REQ & res_data));
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}
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else
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{
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/* No Process */
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}
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}
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/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
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void adj_cr_variant_freq(void)
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{
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uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
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uint32_t pll6_freq = mem_read32(CPG_PLL6CR0);
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#if (RCAR_LSI == RCAR_V4H)
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/* Set the CPU frequency division ratio according to the type of variant. */
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switch (product)
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{
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case VARIANT_V4H_7:
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/* Default value, do nothing */;
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break;
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case VARIANT_V4H_5:
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pll6_freq = (pll6_freq & ~(0xFFU << 20U));
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pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U));
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break;
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case VARIANT_V4H_3:
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pll6_freq = (pll6_freq & ~(0xFFU << 20U));
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pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U));
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break;
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default:
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; /* Do nothing */
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break;
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}
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if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
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{
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/* Write Division value to FRQCRC0 register */
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mem_write32(CPG_CPGWPR, ~(pll6_freq));
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mem_write32(CPG_PLL6CR0, pll6_freq);
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mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
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mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
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while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
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{
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;
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}
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}
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#elif (RCAR_LSI == RCAR_V4M)
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/* Set the CPU frequency division ratio according to the type of variant. */
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switch (product)
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{
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case VARIANT_V4M_7:
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/* Default value, do nothing */;
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break;
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case VARIANT_V4M_5:
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pll6_freq = (pll6_freq & ~(0xFFU << 20U));
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pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U));
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break;
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case VARIANT_V4M_3:
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pll6_freq = (pll6_freq & ~(0xFFU << 20U));
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pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U));
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break;
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case VARIANT_V4M_2:
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pll6_freq = (pll6_freq & ~(0xFFU << 20U));
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pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U));
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break;
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default:
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; /* Do nothing */
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break;
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}
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if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
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{
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/* Write Division value to FRQCRC0 register */
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mem_write32(CPG_CPGWPR, ~(pll6_freq));
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mem_write32(CPG_PLL6CR0, pll6_freq);
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mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
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mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
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while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
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{
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;
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}
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}
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#endif /* RCAR_LSI == RCAR_V4H */
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}
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/* End of function adj_cpu_variant_freq(void) */
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