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woody
2025-12-24 17:21:08 +09:00
parent a96323de19
commit 96dc62d8dc
2302 changed files with 455822 additions and 0 deletions
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0
IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/crc32.c Normal file
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IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/log.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver
******************************************************************************/
/******************************************************************************
* @file log.c
* - Version : 0.03
* @brief Log driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 06.01.2022 0.02 Static analysis support
* : 04,04,2023 0.03 Fixed to not use the standard input/output
* library when LOG_LEVEL=0.
*****************************************************************************/
#include <stdint.h>
#include <log.h>
#include <scif.h>
#if LOG_LEVEL >= LOG_ERROR
#include <stdarg.h>
#define VSPRINTF_OK (0)
void local_printf(const char *fmt, ...)
{
va_list ap;
static char s_buffer[1024];
int32_t num;
uint32_t loop;
/* Convert all arguments to one string */
va_start(ap, fmt);
num = vsprintf(s_buffer, fmt, ap);
va_end(ap);
/* String output */
if (VSPRINTF_OK <= num)
{
for (loop = 0U; loop < num; loop++)
{
(void)console_putc((uint8_t)s_buffer[loop]);
/* If the outputted character is LF, output CR */
if (s_buffer[loop] == 0x0A) /* \n */
{
(void)console_putc((uint8_t)'\r');
}
}
}
else
{
while(1)
{
/* loop due to error detection. */
}
}
}
/* End of function local_printf(const char *fmt, ...) */
#endif
void panic_printf(const char *str)
{
const uint8_t *p = (const uint8_t *)str;
/* Output one character at a time until the data in the argument is null-terminated string. */
while(*p != (uint8_t)'\0')
{
(void)console_putc(*p);
p++;
}
/* output character is CR and LF */
(void)console_putc((uint8_t)'\r');
(void)console_putc((uint8_t)'\n');
}
/* End of function panic_printf(const char *str) */

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IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/scif.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver
******************************************************************************/
/******************************************************************************
* @file scif.c
* - Version : 0.08
* @brief 1. Initial setting of SCIF.
* 2. Initial setting of HSCIF.
* 3. Log output function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify the timing of MODEMR judgement.
* : 15.10.2021 0.03 Modify register access to read modify write.
* : 03.12.2021 0.04 Fix incorrect configuration process.
* : 06.01.2022 0.05 Static analysis support
* : 23.05.2022 0.06 Integration of S4 and V4H
* : 20.12.2022 0.07 Modify writing bit size to SCBRR register.
* : 21.08.2023 0.08 Add support for V4M.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <cpg.h>
#include <pfc.h>
#include <scif.h>
#include <mem_io.h>
#include <micro_wait.h>
#include <rst_register.h>
/* Define */
#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U)
#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U)
#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN)
#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U)
#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U)
#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U)
#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN)
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCSMR_CHR (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCSMR_PE (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSMR_STOP (uint16_t)((uint16_t)1U << 3U)
#define SCIF_SCSMR_CKS (uint16_t)((uint16_t)3U << 0U)
#define SCIF_SCSMR_INIT_DATA ~((uint16_t)(SCIF_SCSMR_CHR | SCIF_SCSMR_PE | SCIF_SCSMR_STOP | SCIF_SCSMR_CKS))
/* Pclk(66MHz)/1, 115.2kbps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 921.6kbps*/
/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */
#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 1.8432Mbps*/
/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */
#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U)
#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U)
#define HSCIF_HSSRR_SRCYC (uint16_t)(0x1FU << 0U)
#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */
#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8)
#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U)
#define HSCIF_CKS_CKS (uint16_t)(1U << 15U)
#define HSCIF_CKS_XIN (uint16_t)(1U << 14U)
#define HSCIF_CKS_SC_CLK_EXT ~((uint16_t)(HSCIF_CKS_CKS | HSCIF_CKS_XIN))
/* module start setting value */
#if (RCAR_LSI == RCAR_S4)
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 4U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 2U)
#endif /* RCAR_LSI == RCAR_S4 */
/* Pin function setting value */
#if (RCAR_LSI == RCAR_S4)
#define GPSR_TX ((uint32_t)1U << 3U) /* HTX0 / TX3 */
#define GPSR_RX ((uint32_t)1U << 2U) /* HRX0 / RX3 */
#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */
#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */
#define POC_TX_33V ((uint32_t)1U << 3U) /* HTX0 / TX3 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 2U) /* HRX0 / RX3 3.3V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX/TX) */
#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */
#define PFC_IPSR_HSCIF_VAL (uint32_t)(0x00000000U) /* HSCIF0 RX/TX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 0U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 0U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00000001U) /* Mask value of IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_VAL (uint32_t)(1U << 0U) /* IPSR (External Clock) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define GPSR_TX ((uint32_t)1U << 12U) /* HTX0 / TX0 */
#define GPSR_RX ((uint32_t)1U << 16U) /* HRX0 / RX0 */
#define IPSR_RX_VAL ((uint32_t)1U << 0U) /* RX0 */
#define IPSR_TX_VAL ((uint32_t)1U << 16U) /* TX0 */
#define POC_TX_33V ((uint32_t)1U << 12U) /* HTX0 / TX0 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 16U) /* HRX0 / RX0 3.3V setting value */
#define POC_TX_18V ((uint32_t)0U << 12U) /* HTX0 / TX0 1.8V setting value */
#define POC_RX_18V ((uint32_t)0U << 16U) /* HRX0 / RX0 1.8V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 0U) /* IPSR bit[3:0] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 16U) /* IPSR bit[19:16] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK1 (uint32_t)(IPSR_TX_MASK) /* Mask value of IPSR (SCIF0/HSCIF0 TX) */
#define PFC_IPSR_SCIF_VAL1 (uint32_t)(IPSR_TX_VAL) /* SCIF0 TX */
#define PFC_IPSR_SCIF_MASK2 (uint32_t)(IPSR_RX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX) */
#define PFC_IPSR_SCIF_VAL2 (uint32_t)(IPSR_RX_VAL) /* SCIF0 RX */
#define PFC_IPSR_HSCIF_VAL1 (uint32_t)(0x00000000U) /* HSCIF0 TX */
#define PFC_IPSR_HSCIF_VAL2 (uint32_t)(0x00000000U) /* HSCIF0 RX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 4U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 4U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00020000U) /* Mask value of IPSR (External Clock) */
#endif /* RCAR_LSI == RCAR_S4 */
static void (*rcar_putc)(uint8_t outchar);
static void scif_module_start(uint32_t modemr);
static void scif_pfc_init(uint32_t modemr);
static void scif_console_init(uint32_t modemr);
static void scif_console_putc(uint8_t outchar);
static void hscif_console_putc(uint8_t outchar);
static void scif_module_start(uint32_t modemr)
{
uint32_t reg;
if(modemr == MODEMR_SCIF_DLMODE)
{
reg = mem_read32(CPG_MSTPSR7D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_SCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_SCIF);
cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg);
}
}
else
{
reg = mem_read32(CPG_MSTPSR5D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_HSCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_HSCIF);
cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg);
}
}
}
/* End of function scif_module_start(void) */
static void scif_pfc_init(uint32_t modemr)
{
uint32_t reg;
#if (RCAR_LSI == RCAR_S4)
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set RX / TX of SCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_SCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR0_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR0_RW, reg);
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set TX of SCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_SCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set RX of SCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_SCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP2SR1_RW, reg);
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR1_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR1_RW, reg);
#endif /* RCAR_LSI == RCAR_S4 */
}
/* End of function scif_pfc_init(void) */
static void scif_console_init(uint32_t modemr)
{
uint16_t reg;
switch(modemr)
{
case MODEMR_HSCIF_DLMODE_3000000:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* external clock, SC_CLK pin used for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* 24MHz / (3000000 * 8) = 1 */
mem_write16(HSCIF_DL, HSCIF_DL_DIV1);
reg = mem_read16(HSCIF_CKS);
reg &= HSCIF_CKS_SC_CLK_EXT;
mem_write16(HSCIF_CKS, reg);
/* Sampling rate 8 */
reg = mem_read16(HSCIF_HSSRR);
reg &= ~(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC);
reg |= HSCIF_HSSRR_VAL;
mem_write16(HSCIF_HSSRR, reg);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_1843200:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 1843200bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_921600:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 921600bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_SCIF_DLMODE:
default:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(SCIF_SCFCR, reg);
/* clear ORER bit */
mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(SCIF_SCSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(SCIF_SCSMR, reg);
/* Baud rate 115200bps*/
mem_write8(SCIF_SCBRR, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(SCIF_SCFCR, reg);
/* enable TE, RE; SC_CLK=no output */
reg = mem_read16(SCIF_SCSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(SCIF_SCSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = scif_console_putc;
break;
}
}
}
/* End of function scif_console_init(void) */
#define _MODE31 (BASE_RTSRAM_ADDR + 0x0002FFF0)
#define _MODE_115200 0x00115200
void scif_init(void)
{
uint32_t modemr;
#ifdef FORCE_115200 /* force to serial speed to 115200 bps */
/* Gen4_ICUMX_loader(0xEB22FFF0) at RT-VRAM */
modemr = MODEMR_SCIF_DLMODE;
mem_write32(_MODE31, _MODE_115200);
#else
modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U);
modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
#endif
scif_module_start(modemr);
scif_pfc_init(modemr);
scif_console_init(modemr);
}
/* End of function scif_init(void) */
void console_putc(uint8_t outchar)
{
rcar_putc(outchar);
}
/* End of function console_putc(void) */
static void scif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function scif_console_putc(uint8_t outchar) */
static void hscif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */
reg = mem_read16(HSCIF_HSFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(HSCIF_HSFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function hscif_console_putc(uint8_t outchar) */

126
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#include <stdint.h>
#include <stddef.h> /* NULL pointer */
#include <stdio.h>
#include "scmt.h"
#include "scmt_config.h"
#include "scmt_checkpoint.h"
#if PRINT_INFO
#include <rst_register.h> /* Access to mode pin register */
#include <mem_io.h> /* Access to mode pin register */
#endif /* PRINT_INFO */
#define xstr(a) str(a)
#define str(a) #a
/* Structure to hold the log data. */
typedef struct {
uint32_t counter; /* Value of SCMT counter */
char * note; /* String is stored as pointer! Pointer must be valid during runtime! */
uint32_t data; /* Arbitrary data to add to log */
} checkpoint_t;
checkpoint_t time_checkpoints[TIME_CHECKPOINTS_MAX];
/* If SCMT has a start value other than zero, we'll keep two slots free to inform the user about the offset within the print function */
#if (SCMT_START_VALUE == 0)
uint32_t time_checkpoints_index = 0;
#else
uint32_t time_checkpoints_index = 2;
#endif
/* Store a checkpoint: Fetch current counter value and store it together with a pointer to a static string as well as arbitrary data */
void store_time_checkpoint(char * note, uint32_t data)
{
if (time_checkpoints_index < TIME_CHECKPOINTS_MAX) {
time_checkpoints[time_checkpoints_index].counter = scmt_module_read();
time_checkpoints[time_checkpoints_index].note = note;
time_checkpoints[time_checkpoints_index].data = data;
}
time_checkpoints_index++;
}
#if (0 == (MEASURE_TIME_NOPRINT))
/* Print checkpoints */
void print_time_checkpoints(void)
{
uint32_t i;
{PRINTFN(MODULE"=================\r\n");}
#if PRINT_INFO
/* First, provide some information about the environment */
{PRINTFN(MODULE"MODEMR[1:0]: 0x%x 0x%x\r\n", mem_read32(RST_MODEMR1), mem_read32(RST_MODEMR0) );}
{PRINTFN(MODULE"Timer: '" xstr(TIMER_FUNC) "'\r\n");}
{PRINTFN(MODULE"- freq: %.3f kHz\r\n", (TIMER_FREQ)/1000.0f);}
{PRINTFN(MODULE"- resolution: 1 tick = %.4f ms\r\n", 1000.0/(TIMER_FREQ));}
#endif /* PRINT_INFO */
/* In case of unsufficient storage for checkpoints, inform about it */
if (time_checkpoints_index >= TIME_CHECKPOINTS_MAX) {
{PRINTFN(MODULE"Internal number of checkpoints exceeded reserved space: %i of %i\r\n", time_checkpoints_index, TIME_CHECKPOINTS_MAX);}
}
/* In case of non-zero SCMT start value, inform about it */
#if (SCMT_START_VALUE != 0)
time_checkpoints[0].counter = 0;
time_checkpoints[0].note = "Reset Release!";
time_checkpoints[1].counter = SCMT_START_VALUE;
time_checkpoints[1].note = "Timer started here with manual offset relative to reset release!";
#endif
/* Print log in CSV style */
{PRINTFN(MODULE"CSV; timer_ticks; total_time[ms]; delta_time[ms]; data; comment\r\n" );}
for (i=0; i<time_checkpoints_index; i++) {
/* Some projects don't have float handling activated in the compiler.
In this case you have to calculate the times later in the spreadsheets */
#if PRINT_FLOAT
float ms = time_checkpoints[i].counter*1000.0/(TIMER_FREQ);
float ms_delta = 0.0;
if (i>0) {
ms_delta = ms - time_checkpoints[i-1].counter*1000.0/(TIMER_FREQ);
}
// ==> "E:ICUMX:CP: 364; 2.77; 2.77; 0; init_done"
{PRINTFN(MODULE"CP; %u; %f; %f; %u; %s\r\n", time_checkpoints[i].counter, ms, ms_delta, time_checkpoints[i].data, time_checkpoints[i].note );}
#else
{PRINTFN(MODULE"CP; %u; --; --; %u; %s\r\n", time_checkpoints[i].counter, time_checkpoints[i].data, time_checkpoints[i].note );}
#endif
}
/* Timer verification.
Sample calculation:
SCIF is running with 921600 Baud. 8N1 => 0.0108 ms / bit.
Sending 20 characters should take 28 timer ticks of SCMT
As SCIF has a 16-stage FIFO, send at least 16 characters before start of measurements */
#if 0 != TIMER_TEST_VS_BAUD
{
uint32_t start = 0, stop = 0;
const char teststr[] = "ExecutingTimerTestExecutingTimerTestExecutingTimerTest!\r\n"; /* 57 characters */
const float charrate = (TIMER_TEST_VS_BAUD)/10.0; /* 8N1: 10 cycles per character */
const float expected_ms = sizeof(teststr)*1000.0/(charrate);
float measured_ms;
{PRINTFN(MODULE"=================\r\n");}
{PRINTFN(MODULE"FillingFifoForTimerTestFillingFifoForTimerTest - ");}
start = (TIMER_FUNC)();
{local_printf(teststr);}
stop = (TIMER_FUNC)();
measured_ms = (stop-start)*1000.0/(TIMER_FREQ);
{PRINTFN(MODULE"(Printing the test took %5i ticks / %7.2f ms / expected: %7.2f ms - %s)\r\n", stop-start, measured_ms, expected_ms, ((measured_ms/expected_ms < 1.3) && (measured_ms/expected_ms > 0.9))?"OK":"ERROR");}
}
#endif /* TIMER_TEST_VS_BAUD */
{PRINTFN(MODULE"=================\r\n");}
}
#else //(MEASURE_TIME_NOPRINT) == 0
void print_time_checkpoints(void) {}
#endif //(MEASURE_TIME_NOPRINT) == 0

109
IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/micro_wait.c Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver
******************************************************************************/
/******************************************************************************
* @file micro_wait.c
* - Version : 0.03
* @brief Wait of micro second
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 15.10.2021 0.02 modify register access to read modify write.
* : 03.12.2021 0.03 fix incorrect configuration process.
*****************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
#include <mem_io.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (0xFFFEEA14U)
#define INTCR_RF ((uint16_t)1U << 12U)
#define INTCR_RF_NO_REQ ((uint16_t)0U << 12U)
#define OSTM0_BASE (0xFFFEE000U)
#define OSTM0CMP (OSTM0_BASE)
#define OSTM0TS (OSTM0_BASE + 0x0014U)
#define OSTM0TT (OSTM0_BASE + 0x0018U)
#define OSTM0CTL (OSTM0_BASE + 0x0020U)
#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */
#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */
#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */
void micro_wait(uint32_t count_us)
{
uint32_t val;
uint16_t reg16;
uint8_t reg8;
if (count_us != 0U)
{
/* When the timer count is an argument that exceeds 0xFFFFFFFF */
if(MAX_MICRO_WAIT < count_us)
{
count_us = MAX_MICRO_WAIT;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
/* timer start */
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
mem_write32(OSTM0CMP, val);
reg8 = mem_read8(OSTM0CTL);
reg8 |= OSTM0CTL_MD10;
mem_write8(OSTM0CTL, reg8);
reg8 = mem_read8(OSTM0TS);
reg8 |= OSTM0TS_TS;
mem_write8(OSTM0TS, reg8);
while (1)
{
reg16 = mem_read16(INTICUOSTM0);
if ((reg16 & (INTCR_RF)) != INTCR_RF_NO_REQ)
{
/* timer stop */
reg16 = (reg16 & (uint16_t)(~(INTCR_RF)));
mem_write16(INTICUOSTM0, reg16);
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
break;
}
}
}
}
/* End of function micro_wait(uint32_t count_us) */

108
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#include <stdint.h>
#include <mem_io.h>
#include <scmt.h>
#include <scmt_config.h>
#include <scmt_register.h>
#if SCMT_DEBUG
#include <log.h>
#endif /* SCMT_DEBUG */
#if SCMT_TOGGLE_GPIO
#include <pfc.h>
void gpio_set(void)
{
/* V4H: SCL3_V::Pin AK5::GP8_06
GPIO Group 8 Base: H’E606 8000
INOUTSELn +0x184 (set pin to output mode)
OUTDTn +0x188 (set pin output value)
*/
pfc_reg_write(PFC_INOUTSEL8_RW, 1<<6); /* Set GP8_06 to output mode */
pfc_reg_write(PFC_OUTDT8_RW, 1<<6); /* Set GP8_06 to 'high' */
}
static int gpio_reset_cnt = 3;
void gpio_clear(void)
{
if (gpio_reset_cnt>0) {
gpio_reset_cnt--;
}
else
{
pfc_reg_write(PFC_OUTDT8_RW, 0); /* Set GP8_06 to 'low' */
}
}
#endif /* SCMT_TOGGLE_GPIO */
void scmt_module_start(void)
{
/* For boot time measurement, signal start of SCMT by GPIO pin toggle */
#if SCMT_TOGGLE_GPIO
gpio_set();
#endif /* SCMT_TOGGLE_GPIO */
/* If you have issues with the code getting stuck or reading zero from the timer,
you can debug the init seqence with SCMT_DEBUG.
Just make sure that printing debug data is already possible. */
#if SCMT_DEBUG
PRINTFN("SCMT A\n");
#endif /* SCMT_DEBUG */
#if SCMT_INIT
mem_write32(SCMT_CMSCNT,(SCMT_START_VALUE)); /* Set counter value to zero */
#endif /* SCMT_INIT */
#if SCMT_DEBUG
PRINTFN("SCMT B: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) );
#endif /* SCMT_DEBUG */
#if SCMT_INIT
mem_write32(SCMT_CMSCOR,0xffffffff); /* Set compare value to maximum, we use it as 32-bit counter only */
#endif /* SCMT_INIT */
#if SCMT_DEBUG
PRINTFN("SCMT C: SCMT_CMSCOR (0x%x) = 0x%x\n", SCMT_CMSCOR, mem_read32(SCMT_CMSCOR) );
#endif /* SCMT_DEBUG */
#if SCMT_INIT
while(mem_read16(SCMT_CMSCSR)&(1<<13)); /* Wait for write clearance */
#endif /* SCMT_INIT */
#if SCMT_DEBUG
PRINTFN("SCMT D: SCMT_CMSCSR (0x%x) = 0x%x\n", SCMT_CMSCSR, mem_read16(SCMT_CMSCSR) );
#endif /* SCMT_DEBUG */
#if SCMT_INIT
mem_write16(SCMT_CMSSTR,1<<5); /* Start counter */
#endif /* SCMT_INIT */
#if SCMT_DEBUG
PRINTFN("SCMT E: SCMT_CMSSTR (0x%x) = 0x%x\n", SCMT_CMSSTR, mem_read16(SCMT_CMSSTR) );
PRINTFN("SCMT F: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) );
PRINTFN("SCMT G: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) );
PRINTFN("SCMT H: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) );
PRINTFN("SCMT I: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) );
#endif /* SCMT_DEBUG */
}
uint32_t scmt_module_read(void)
{
uint32_t last = 0, current = 0;
/* For boot time measurement, signal start of SCMT by GPIO pin toggle, reset after some time */
#if SCMT_TOGGLE_GPIO
gpio_clear();
#endif /* SCMT_TOGGLE_GPIO */
/* From UM:
When CMSCNT is read during the counter operation, the read value may be wrong because of an asynchronous clock between counter and bus-interface.
For exact value, read this register continuously, until same values are read from this register. */
current = mem_read32(SCMT_CMSCNT);
do {
last = current;
current = mem_read32(SCMT_CMSCNT);
} while (last != current);
return current;
}
/* NOT SAFE FOR OVERLFOWS */
void scmt_wait_ticks(uint32_t ticks)
{
uint32_t start = scmt_module_read();
uint32_t stop = start + ticks;
while (stop > scmt_module_read()) { /* NOP */ };
}