141 lines
5.1 KiB
Plaintext
141 lines
5.1 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX8MQ(ARM, Cortex-A53) on IMX8MQ-EVK Board QSPI FLASH Program script
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; @Description:
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; The N25Q256 is on the QSPIA_SS0_B
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;
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; SRAM: 0x900000
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; QuadSPI(controller) Base: 0x30BB0000
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; FLASH APB BASE ADDRESS: 0x08000000
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;
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; @Keywords: Flash SPI QuadSPI
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; @Author: jjeong
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; @Board: IMX8MQ-EVK
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; @Chip: IMX8MQ*
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: imx8m-qspi.cmm 12049 2023-04-20 12:32:16Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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&QSPI_BASE=0x30BB0000
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&QSPI_AMBA_BASE=0x08000000
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RESet
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SYStem.RESet
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SYStem.CPU IMX8MQ
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SYStem.JtagClock CTCK 10MHz
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SYStem.Option ResBreak OFF
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SYStem.Option WaitIDCODE 1.5s
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Trace.DISable
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CORE.ASSIGN 1.
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SYStem.Up
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// CCM_TARGET_ROOTn : Address: 3038_0000h base + 8000h offset + (128d x i), where i=0d to 124d
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// i=87. QSPI_CLK_ROOT
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Data.Set A:0x303842F8 %LE %Long 0x3 ;CCM_CCGR47_CLEAR, clock gating register CCM_CCGR47
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Data.Set A:(0x30388000+0x2B80) %LE %Long 0x11000002 ; (SYSTEM_PLL1_DIV2)/2 = 40Mhz
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Data.Set A:0x303842F4 %LE %Long 0x3 ;CCM_CCGR47_SET, clock gating register CCM_CCGR47
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Data.Set AMD:0x303300F4 %LE %Long 0x1 ; IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, ALT1_QSPI_A_SCLK
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Data.Set AMD:0x303300F8 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B), ALT1_QSPI_A_SS0_B
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Data.Set AMD:0x303300FC %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B), ALT1_QSPI_A_SS1_B
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Data.Set AMD:0x30330100 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B), ALT1_QSPI_B_SS0_B
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Data.Set AMD:0x30330104 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B), ALT1_QSPI_B_SS1_B
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Data.Set AMD:0x30330108 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE), ALT1_QSPI_B_SCLK
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Data.Set AMD:0x3033010C %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00), ALT1_QSPI_A_DATA0
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Data.Set AMD:0x30330110 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01), ALT1_QSPI_A_DATA1
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Data.Set AMD:0x30330114 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02), ALT1_QSPI_A_DATA2
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Data.Set AMD:0x30330118 %LE %Long 0x1 ; (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03), ALT1_QSPI_A_DATA3
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//qspi controller
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Data.Set A:(&QSPI_BASE) %Long 0x0F400C
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Data.Set A:(&QSPI_BASE+0x30) %Long 0x0
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Data.Set A:(&QSPI_BASE+0x180) %Long (&QSPI_AMBA_BASE+0x04000000) ; Serial Flash A1 Top Address(QuadSPIx_SFA1AD)
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Data.Set A:(&QSPI_BASE+0x184) %Long (&QSPI_AMBA_BASE+0x08000000) ; Serial Flash A2 Top Address(QuadSPIx_SFA2AD)
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Data.Set A:(&QSPI_BASE+0x188) %Long (&QSPI_AMBA_BASE+0x0C000000) ; Serial Flash B1Top Address (QuadSPIx_SFB1AD)
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Data.Set A:(&QSPI_BASE+0x18C) %Long (&QSPI_AMBA_BASE+0x10000000) ; Serial Flash B2Top Address (QuadSPIx_SFB2AD)
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Data.Set A:(&QSPI_BASE+0x10) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x14) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x18) %Long 0x0E
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Data.Set A:(&QSPI_BASE+0x1C) %Long 0x80002000 ;QuadSPI_BUF3CR
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Data.Set A:(&QSPI_BASE+0x100) %Long &QSPI_AMBA_BASE ;QuadSPI_SFAR
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Data.Set A:(&QSPI_BASE+0x160) %Long 0xFFFFFFFF ;clear the Flag Register
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//QSPI AHB(A:0x08000000) read configuration
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//3byte read at &QSPI_AMBA_BASE
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D.S A:(&QSPI_BASE+0x310) %Long (0x08180400|0x3) ;default
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D.S A:(&QSPI_BASE+0x314) %Long 0x24001C08
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D.S A:(&QSPI_BASE+0x318) %Long 0x0 ;STOP
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//4byte read for spansion flash memory
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;D.S A:(&QSPI_BASE+0x310) %Long (0x08200400|0x13) ;ADDR(32bits) 0 & CMD(0x13)
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;D.S A:(&QSPI_BASE+0x314) %Long 0x24001C08 ;JMP_ON_CS(inst 0)& READ(8bytes)
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;D.S A:(&QSPI_BASE+0x318) %Long 0x0 ;STOP
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Data.Set A:(&QSPI_BASE) %Long 0x0F000C
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//FLASH READ ID TEST
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GOSUB READ_ID_TEST
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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Break.RESet
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FLASH.RESet
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FLASH.Create &QSPI_AMBA_BASE++0x01ffffff 0x10000 TARGET Byte
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FLASH.TARGET 0x900000 0x902000 0x1000 &pdd/flash/byte/snor_imx8.bin
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FLASH.List
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DIALOG.YESNO "Program flash memory?"
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LOCAL &progflash
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ENTRY &progflash
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IF &progflash
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(
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FLASH.ReProgram.ALL
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Data.LOAD.auto *
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;Data.LOAD.Binary * 0x08000000
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FLASH.ReProgram.off
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)
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ENDDO
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READ_ID_TEST:
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&cmd=0x9F; read ID JEDEC Manufacture ID and JEDEC CFI
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&temp=Data.Long(A:&QSPI_BASE)
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Data.Set A:&QSPI_BASE %Long (&temp|0x0c00) //clear Tx/Rx buffer
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Data.Set A:(&QSPI_BASE+0x300) %LE %Long 0x5AF05AF0 ; LUTKEY
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Data.Set A:(&QSPI_BASE+0x304) %LE %Long 0x2 ; LCKCR
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//0. read id
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Data.Set A:(&QSPI_BASE+0x360) %LE %Long (0x1c040400)|&cmd ; LUT0, SEQID0
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Data.Set A:(&QSPI_BASE+0x364) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x368) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x36C) %LE %Long 0x0
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Data.Set A:(&QSPI_BASE+0x100) %Long &QSPI_AMBA_BASE ; SFAR , FLASH BASE ADDRESS
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// assert Read id command
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Data.Set A:(&QSPI_BASE+0x008) %Long (0x5<<24.) ; (5.<<24.)
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WAIT 100.ms
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&temp=Data.Long(A:&QSPI_BASE)
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Data.Set A:&QSPI_BASE %Long (&temp|0x0800) //clear Tx buffer
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PRINT "1st 0x" Data.Long(A:(&QSPI_BASE+0x200))&0xFF " (Manufacturer)"
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PRINT "2nd 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>8.)&0xFF " (Device ID)"
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PRINT "3rd 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>16.)&0xFF
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PRINT "4th 0x" (Data.Long(A:(&QSPI_BASE+0x200))>>24.)&0xFF
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RETURN
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