447 lines
18 KiB
Plaintext
447 lines
18 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX8MN Specific Menu
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; @Props: Released
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; @Author: JAM, KWI, DAB
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; @Changelog: 2019-05-21 JAM
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; 2021-04-09 KWI
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; 2022-01-26 DAB
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A53, Cortex-M7
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; @Chip: IMX8MNQ, IMX8MNQ-CM7
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx8mn.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA53")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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if (CORENAME()=="CORTEXM7F")
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(
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popup "[:chip]Core Registers (Cortex-M7F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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menuitem "AIPSTZ" "per , ""AIPSTZ (AHB to IP Bridge Trust Zone)"""
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menuitem "APBH" "per , ""APBH (AHB-to-APBH Bridge with DMA)"""
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menuitem "ASRC" "per , ""ASRC"""
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menuitem "BCH" "per , ""BCH (62BIT Correcting ECC Accelrator)"""
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menuitem "CCM" "per , ""CCM (Clock Controller Module)"""
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menuitem "CCM_ANALOG" "per , ""CCM_ANALOG"""
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menuitem "DDRC" "per , ""DDRC (DDR Controller)"""
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popup "DWC_DDRPHYA_ANIB"
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(
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menuitem "DWC_DDRPHYA_ANIB0" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB0"""
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menuitem "DWC_DDRPHYA_ANIB1" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB1"""
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menuitem "DWC_DDRPHYA_ANIB2" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB2"""
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menuitem "DWC_DDRPHYA_ANIB3" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB3"""
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menuitem "DWC_DDRPHYA_ANIB4" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB4"""
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menuitem "DWC_DDRPHYA_ANIB5" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB5"""
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menuitem "DWC_DDRPHYA_ANIB6" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB6"""
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menuitem "DWC_DDRPHYA_ANIB7" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB7"""
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menuitem "DWC_DDRPHYA_ANIB8" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB8"""
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menuitem "DWC_DDRPHYA_ANIB9" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB9"""
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)
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menuitem "DWC_DDRPHYA_APBONLY0" "per , ""DWC_DDRPHYA_APBONLY"""
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popup "DWC_DDRPHYA_DBYTE"
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(
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menuitem "DWC_DDRPHYA_DBYTE0" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE0"""
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menuitem "DWC_DDRPHYA_DBYTE1" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE1"""
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menuitem "DWC_DDRPHYA_DBYTE2" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE2"""
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menuitem "DWC_DDRPHYA_DBYTE3" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE3"""
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)
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menuitem "DWC_DDRPHYA_DRTUB0" "per , ""DWC_DDRPHYA_DRTUB"""
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menuitem "DWC_DDRPHYA_INITENG0" "per , ""DWC_DDRPHYA_INITENG"""
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menuitem "DWC_DDRPHYA_MASTER0" "per , ""DWC_DDRPHYA_MASTER"""
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popup "ECSPI (Enhanced Configurable SPI)"
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(
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menuitem "ECSPI1" "per , ""ECSPI (Enhanced Configurable SPI),ECSPI1"""
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menuitem "ECSPI2" "per , ""ECSPI (Enhanced Configurable SPI),ECSPI2"""
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menuitem "ECSPI3" "per , ""ECSPI (Enhanced Configurable SPI),ECSPI3"""
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)
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menuitem "ENET" "per , ""ENET (Ethernet MAC)"""
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menuitem "FLEXSPI" "per , ""FLEXSPI (FlexSPI)"""
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menuitem "GPC" "per , ""GPC"""
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menuitem "GPC_PGC" "per , ""GPC_PGC"""
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popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
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(
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menuitem "GPIO1" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO1"""
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menuitem "GPIO2" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO2"""
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menuitem "GPIO3" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO3"""
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menuitem "GPIO4" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO4"""
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menuitem "GPIO5" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO5"""
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)
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menuitem "GPMI" "per , ""GPMI (General Purpose Media Interface)"""
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popup "GPT (General Purpose Timer)"
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(
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menuitem "GPT1" "per , ""GPT (General Purpose Timer),GPT1"""
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menuitem "GPT2" "per , ""GPT (General Purpose Timer),GPT2"""
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menuitem "GPT3" "per , ""GPT (General Purpose Timer),GPT3"""
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menuitem "GPT4" "per , ""GPT (General Purpose Timer),GPT4"""
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menuitem "GPT5" "per , ""GPT (General Purpose Timer),GPT5"""
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menuitem "GPT6" "per , ""GPT (General Purpose Timer),GPT6"""
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)
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popup "I2C (Inter-Integrated Circuit)"
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(
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menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
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menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2"""
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menuitem "I2C3" "per , ""I2C (Inter-Integrated Circuit),I2C3"""
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menuitem "I2C4" "per , ""I2C (Inter-Integrated Circuit),I2C4"""
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)
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popup "I2S (Inter-Integrated Sound Bus Controller)"
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(
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menuitem "I2S2" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S2"""
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menuitem "I2S3" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S3"""
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menuitem "I2S5" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S5"""
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menuitem "I2S6" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S6"""
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menuitem "I2S7" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S7"""
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)
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menuitem "IOMUXC" "per , ""IOMUXC (IOMUX Controller)"""
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menuitem "IOMUXC_GPR" "per , ""IOMUXC_GPR (IOMUX Controller General Purpose Registers)"""
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menuitem "ISI" "per , ""ISI (ISI Memory Map)"""
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menuitem "LCDIF" "per , ""LCDIF (LCD Interface)"""
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menuitem "MIPI_CSI" "per , ""MIPI_CSI (MIPI CSI Host Controller)"""
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menuitem "MIPI_DSI" "per , ""MIPI_DSI (MIPI DSI Host Controller)"""
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menuitem "MUB" "per , ""MUB (Messaging Unit Processor B-side)"""
|
|
menuitem "OCOTP" "per , ""OCOTP (OCOTP Register Reference Index)"""
|
|
menuitem "PDM" "per , ""PDM (Pulse Density Modulation (Digital Microphone) Interface)"""
|
|
popup "PWM (Pulse-Width Modulator)"
|
|
(
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|
menuitem "PWM1" "per , ""PWM (Pulse-Width Modulator),PWM1"""
|
|
menuitem "PWM2" "per , ""PWM (Pulse-Width Modulator),PWM2"""
|
|
menuitem "PWM3" "per , ""PWM (Pulse-Width Modulator),PWM3"""
|
|
menuitem "PWM4" "per , ""PWM (Pulse-Width Modulator),PWM4"""
|
|
)
|
|
menuitem "RDC" "per , ""RDC"""
|
|
popup "RDC_SEMAPHORE (Resources Domain Controller Semaphore)"
|
|
(
|
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menuitem "RDC_SEMAPHORE1" "per , ""RDC_SEMAPHORE (Resources Domain Controller Semaphore),RDC_SEMAPHORE1"""
|
|
menuitem "RDC_SEMAPHORE2" "per , ""RDC_SEMAPHORE (Resources Domain Controller Semaphore),RDC_SEMAPHORE2"""
|
|
)
|
|
popup "SDMAARM (Smart Direct Memory Access - Arm Platform)"
|
|
(
|
|
menuitem "SDMAARM1" "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM1"""
|
|
menuitem "SDMAARM2" "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM2"""
|
|
menuitem "SDMAARM3" "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM3"""
|
|
)
|
|
menuitem "SEMA4" "per , ""SEMA4 (Semaphore)"""
|
|
menuitem "SNVS" "per , ""SVNS (Secure Non-Volatile Storage)"""
|
|
popup "SPBA (Shared Peripheral Bus Arbiter)"
|
|
(
|
|
menuitem "SPBA1" "per , ""SPBA (Shared Peripheral Bus Arbiter),SPBA1"""
|
|
menuitem "SPBA2" "per , ""SPBA (Shared Peripheral Bus Arbiter),SPBA2"""
|
|
)
|
|
popup "SPDIF (Sony/Philips Digital Interface)"
|
|
(
|
|
menuitem "SPDIF1" "per , ""SPDIF (Sony/Philips Digital Interface),SPDIF1"""
|
|
menuitem "SPDIF2" "per , ""SPDIF (Sony/Philips Digital Interface),SPDIF2"""
|
|
)
|
|
menuitem "SRC" "per , ""SRC (System Reset Controller)"""
|
|
menuitem "TMU" "per , ""TMU (Thermal Monitoring Unit)"""
|
|
popup "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
(
|
|
menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
|
|
menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
|
|
menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
|
|
menuitem "UART4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART4"""
|
|
)
|
|
menuitem "USB" "per , ""USB (Universal Serial Bus)"""
|
|
menuitem "USBNC" "per , ""USBNC (Universal Serial Bus)"""
|
|
popup "USDHC (Ultra Secured Digital Host Controller)"
|
|
(
|
|
menuitem "USDHC1" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC1"""
|
|
menuitem "USDHC2" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC2"""
|
|
menuitem "USDHC3" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC3"""
|
|
)
|
|
popup "WDOG (Watchdog Timer Unit)"
|
|
(
|
|
menuitem "WDOG1" "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
|
|
menuitem "WDOG2" "per , ""WDOG (Watchdog Timer Unit),WDOG2"""
|
|
menuitem "WDOG3" "per , ""WDOG (Watchdog Timer Unit),WDOG3"""
|
|
)
|
|
menuitem "XTALOSC" "per , ""XTALOSC"""
|
|
)
|
|
)
|