; --------------------------------------------------------------------------------
; @Title: IMX8MN Specific Menu
; @Props: Released
; @Author: JAM, KWI, DAB
; @Changelog: 2019-05-21 JAM
;             2021-04-09 KWI
;             2022-01-26 DAB
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-A53, Cortex-M7
; @Chip: IMX8MNQ, IMX8MNQ-CM7
; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menimx8mn.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXA53")
(
popup "[:chip]Core Registers (Cortex-A53)"
(
menuitem "[:chip]ID Registers[AArch64]"                                     "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"                 "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                        "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"                  "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                       "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]"       "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                  "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                             "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch64]"                     "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]"                                     "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"                 "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                        "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"                  "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                       "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]"       "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                  "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                             "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch32]"                     "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)"                            "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
)
)
if (CORENAME()=="CORTEXM7F")
(
popup "[:chip]Core Registers (Cortex-M7F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M7F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
menuitem "AIPSTZ"                   "per , ""AIPSTZ (AHB to IP Bridge Trust Zone)"""
menuitem "APBH"                     "per , ""APBH (AHB-to-APBH Bridge with DMA)"""
menuitem "ASRC"                     "per , ""ASRC"""
menuitem "BCH"                      "per , ""BCH (62BIT Correcting ECC Accelrator)"""
menuitem "CCM"                      "per , ""CCM (Clock Controller Module)"""
menuitem "CCM_ANALOG"               "per , ""CCM_ANALOG"""
menuitem "DDRC"                     "per , ""DDRC (DDR Controller)"""
popup "DWC_DDRPHYA_ANIB"
(
menuitem "DWC_DDRPHYA_ANIB0"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB0"""
menuitem "DWC_DDRPHYA_ANIB1"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB1"""
menuitem "DWC_DDRPHYA_ANIB2"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB2"""
menuitem "DWC_DDRPHYA_ANIB3"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB3"""
menuitem "DWC_DDRPHYA_ANIB4"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB4"""
menuitem "DWC_DDRPHYA_ANIB5"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB5"""
menuitem "DWC_DDRPHYA_ANIB6"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB6"""
menuitem "DWC_DDRPHYA_ANIB7"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB7"""
menuitem "DWC_DDRPHYA_ANIB8"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB8"""
menuitem "DWC_DDRPHYA_ANIB9"    "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB9"""
)
menuitem "DWC_DDRPHYA_APBONLY0"     "per , ""DWC_DDRPHYA_APBONLY"""
popup "DWC_DDRPHYA_DBYTE"
(
menuitem "DWC_DDRPHYA_DBYTE0"   "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE0"""
menuitem "DWC_DDRPHYA_DBYTE1"   "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE1"""
menuitem "DWC_DDRPHYA_DBYTE2"   "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE2"""
menuitem "DWC_DDRPHYA_DBYTE3"   "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE3"""
)
menuitem "DWC_DDRPHYA_DRTUB0"       "per , ""DWC_DDRPHYA_DRTUB"""
menuitem "DWC_DDRPHYA_INITENG0"     "per , ""DWC_DDRPHYA_INITENG"""
menuitem "DWC_DDRPHYA_MASTER0"      "per , ""DWC_DDRPHYA_MASTER"""
popup "ECSPI (Enhanced Configurable SPI)"
(
menuitem "ECSPI1"               "per , ""ECSPI (Enhanced Configurable SPI),ECSPI1"""
menuitem "ECSPI2"               "per , ""ECSPI (Enhanced Configurable SPI),ECSPI2"""
menuitem "ECSPI3"               "per , ""ECSPI (Enhanced Configurable SPI),ECSPI3"""
)
menuitem "ENET"                     "per , ""ENET (Ethernet MAC)"""
menuitem "FLEXSPI"                  "per , ""FLEXSPI (FlexSPI)"""
menuitem "GPC"                      "per , ""GPC"""
menuitem "GPC_PGC"                  "per , ""GPC_PGC"""
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
(
menuitem "GPIO1"                "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO1"""
menuitem "GPIO2"                "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO2"""
menuitem "GPIO3"                "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO3"""
menuitem "GPIO4"                "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO4"""
menuitem "GPIO5"                "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO5"""
)
menuitem "GPMI"                     "per , ""GPMI (General Purpose Media Interface)"""
popup "GPT (General Purpose Timer)"
(
menuitem "GPT1"                 "per , ""GPT (General Purpose Timer),GPT1"""
menuitem "GPT2"                 "per , ""GPT (General Purpose Timer),GPT2"""
menuitem "GPT3"                 "per , ""GPT (General Purpose Timer),GPT3"""
menuitem "GPT4"                 "per , ""GPT (General Purpose Timer),GPT4"""
menuitem "GPT5"                 "per , ""GPT (General Purpose Timer),GPT5"""
menuitem "GPT6"                 "per , ""GPT (General Purpose Timer),GPT6"""
)
popup "I2C (Inter-Integrated Circuit)"
(
menuitem "I2C1"                 "per , ""I2C (Inter-Integrated Circuit),I2C1"""
menuitem "I2C2"                 "per , ""I2C (Inter-Integrated Circuit),I2C2"""
menuitem "I2C3"                 "per , ""I2C (Inter-Integrated Circuit),I2C3"""
menuitem "I2C4"                 "per , ""I2C (Inter-Integrated Circuit),I2C4"""
)
popup "I2S (Inter-Integrated Sound Bus Controller)"
(
menuitem "I2S2"                 "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S2"""
menuitem "I2S3"                 "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S3"""
menuitem "I2S5"                 "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S5"""
menuitem "I2S6"                 "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S6"""
menuitem "I2S7"                 "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S7"""
)
menuitem "IOMUXC"                   "per , ""IOMUXC (IOMUX Controller)"""
menuitem "IOMUXC_GPR"               "per , ""IOMUXC_GPR (IOMUX Controller General Purpose Registers)"""
menuitem "ISI"                      "per , ""ISI (ISI Memory Map)"""
menuitem "LCDIF"                    "per , ""LCDIF (LCD Interface)"""
menuitem "MIPI_CSI"                 "per , ""MIPI_CSI (MIPI CSI Host Controller)"""
menuitem "MIPI_DSI"                 "per , ""MIPI_DSI (MIPI DSI Host Controller)"""
menuitem "MUB"                      "per , ""MUB (Messaging Unit Processor B-side)"""
menuitem "OCOTP"                    "per , ""OCOTP (OCOTP Register Reference Index)"""
menuitem "PDM"                      "per , ""PDM (Pulse Density Modulation (Digital Microphone) Interface)"""
popup "PWM (Pulse-Width Modulator)"
(
menuitem "PWM1"                 "per , ""PWM (Pulse-Width Modulator),PWM1"""
menuitem "PWM2"                 "per , ""PWM (Pulse-Width Modulator),PWM2"""
menuitem "PWM3"                 "per , ""PWM (Pulse-Width Modulator),PWM3"""
menuitem "PWM4"                 "per , ""PWM (Pulse-Width Modulator),PWM4"""
)
menuitem "RDC"                      "per , ""RDC"""
popup "RDC_SEMAPHORE (Resources Domain Controller Semaphore)"
(
menuitem "RDC_SEMAPHORE1"       "per , ""RDC_SEMAPHORE (Resources Domain Controller Semaphore),RDC_SEMAPHORE1"""
menuitem "RDC_SEMAPHORE2"       "per , ""RDC_SEMAPHORE (Resources Domain Controller Semaphore),RDC_SEMAPHORE2"""
)
popup "SDMAARM (Smart Direct Memory Access - Arm Platform)"
(
menuitem "SDMAARM1"             "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM1"""
menuitem "SDMAARM2"             "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM2"""
menuitem "SDMAARM3"             "per , ""SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM3"""
)
menuitem "SEMA4"                    "per , ""SEMA4 (Semaphore)"""
menuitem "SNVS"                     "per , ""SVNS (Secure Non-Volatile Storage)"""
popup "SPBA (Shared Peripheral Bus Arbiter)"
(
menuitem "SPBA1"                "per , ""SPBA (Shared Peripheral Bus Arbiter),SPBA1"""
menuitem "SPBA2"                "per , ""SPBA (Shared Peripheral Bus Arbiter),SPBA2"""
)
popup "SPDIF (Sony/Philips Digital Interface)"
(
menuitem "SPDIF1"               "per , ""SPDIF (Sony/Philips Digital Interface),SPDIF1"""
menuitem "SPDIF2"               "per , ""SPDIF (Sony/Philips Digital Interface),SPDIF2"""
)
menuitem "SRC"                      "per , ""SRC (System Reset Controller)"""
menuitem "TMU"                      "per , ""TMU (Thermal Monitoring Unit)"""
popup "UART (Universal Asynchronous Receiver/Transmitter)"
(
menuitem "UART1"                "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
menuitem "UART2"                "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
menuitem "UART3"                "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
menuitem "UART4"                "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART4"""
)
menuitem "USB"                      "per , ""USB (Universal Serial Bus)"""
menuitem "USBNC"                    "per , ""USBNC (Universal Serial Bus)"""
popup "USDHC (Ultra Secured Digital Host Controller)"
(
menuitem "USDHC1"               "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC1"""
menuitem "USDHC2"               "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC2"""
menuitem "USDHC3"               "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC3"""
)
popup "WDOG (Watchdog Timer Unit)"
(
menuitem "WDOG1"                "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
menuitem "WDOG2"                "per , ""WDOG (Watchdog Timer Unit),WDOG2"""
menuitem "WDOG3"                "per , ""WDOG (Watchdog Timer Unit),WDOG3"""
)
menuitem "XTALOSC"                  "per , ""XTALOSC"""
)
)